coreboot-gerrit October 2020

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Change in coreboot[master]: drivers/ipmi: Add uid parameter to struct drivers_ipmi_config
by Furquan Shaikh (Code Review) 09 Nov '20

09 Nov '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40705 ) Change subject: drivers/ipmi: Add uid parameter to struct drivers_ipmi_config ...................................................................... drivers/ipmi: Add uid parameter to struct drivers_ipmi_config This change adds uid parameter to drivers_ipmi_config that can be used by ipmi_ssdt() to store the uid value to be used by ipmi_write_acpi_tables. This allows to remove the requirement in ipmi_ssdt() to update dev->command. This is being done in preparation to make the struct device * parameter to fill_ssdt as const. Change-Id: Ieb41771c75aae902191bba5d220796e6c343f8e0 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/drivers/ipmi/chip.h M src/drivers/ipmi/ipmi_kcs_ops.c M src/drivers/net/r8168.c 3 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/40705/1 diff --git a/src/drivers/ipmi/chip.h b/src/drivers/ipmi/chip.h index 4e9641b..ede9af6 100644 --- a/src/drivers/ipmi/chip.h +++ b/src/drivers/ipmi/chip.h @@ -23,6 +23,7 @@ * Will be used if wait_for_bmc is true. */ u16 bmc_boot_timeout; + unsigned int uid; /* Auto-filled by ipmi_ssdt() */ }; #endif /* _IMPI_CHIP_H_ */ diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 043616a..349abbc 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -212,7 +212,7 @@ acpi_create_ipmi(dev, spmi, (ipmi_revision_major << 8) | (ipmi_revision_minor << 4), &addr, IPMI_INTERFACE_KCS, gpe_interrupt, apic_interrupt, - dev->command); + conf->uid); acpi_add_table(rsdp, spmi); @@ -236,14 +236,14 @@ conf = dev->chip_info; /* Use command to pass UID to ipmi_write_acpi_tables */ - dev->command = uid_cnt++; + conf->uid = uid_cnt++; /* write SPMI device */ acpigen_write_scope(scope); acpigen_write_device("SPMI"); acpigen_write_name_string("_HID", "IPI0001"); acpigen_write_name_unicode("_STR", "IPMI_KCS"); - acpigen_write_name_byte("_UID", dev->command); + acpigen_write_name_byte("_UID", conf->uid); acpigen_write_STA(0xf); acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index c547f17..b904586 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -306,7 +306,7 @@ #if CONFIG(HAVE_ACPI_TABLES) #define R8168_ACPI_HID "R8168" -static void r8168_net_fill_ssdt(struct device *dev) +static void r8168_net_fill_ssdt(const struct device *dev) { struct drivers_net_config *config = dev->chip_info; const char *path = acpi_device_path(dev->bus->dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/40705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb41771c75aae902191bba5d220796e6c343f8e0 Gerrit-Change-Number: 40705 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Introduce HP Sure Start and the method to bypass it
by Iru Cai (vimacs) (Code Review) 09 Nov '20

09 Nov '20

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45577 to review the following change. Change subject: Documentation: Introduce HP Sure Start and the method to bypass it ...................................................................... Documentation: Introduce HP Sure Start and the method to bypass it Change-Id: Id198afdaa13b4c361e1b77a56d5a2436ed1c4c86 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A Documentation/mainboard/hp/hp_sure_start.md M Documentation/mainboard/index.md 2 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45577/1 diff --git a/Documentation/mainboard/hp/hp_sure_start.md b/Documentation/mainboard/hp/hp_sure_start.md new file mode 100644 index 0000000..d1f3f67 --- /dev/null +++ b/Documentation/mainboard/hp/hp_sure_start.md @@ -0,0 +1,57 @@ +# HP Sure Start + +According to the [HP Sure Start Technical Whitepaper], HP Sure Start is a chipset +and processor independent firmware intrusion detection and automatic repair system. +It is implemented in HP notebooks since 2013, and desktops since 2015. + +This document talks about some mechanism of HP Sure Start on some machines, and +the method to bypass it. + +## Laptops with SMSC MEC1322 embedded controller + +Haswell EliteBook, ZBook and ProBook 600 series use SMSC MEC1322 embedded controller. +The EC firmware implements HP Sure Start. A Haswell EliteBook has two flash chips. +According to the strings in the EC firmware, the 16MB flash chip that stores the +BIOS firmware is called the *system flash*, and the 2MB flash chip that stores part +of the system flash content is called the *private flash*. + +The private flash is connected to the EC, and is not accessible by the OS. +It contains the following: + +- HP Sure Start policy header (starting with the string "POLI") +- A copy of the Intel Flash Descriptor +- A copy of the GbE firmware +- Machine Unique Data (MUD) +- Hashes of the IFD, GbE firmware and MUD, the hash algorithm is unknown +- A copy of the bootblock, UEFI PEI stage, and microcode + +If the IFD of the system flash does not match the hash in the private flash, for example, +modifying the IFD with ``ifdtool -u`` or ``me_cleaner -S``, the EC will recover the IFD. + +If the content of the private flash is lost. The EC firmware will still copy the IFD, +bootblock and PEI to the private flash. However, the IFD is not protected after that. + +HP Sure Start also verifies bootblock, PEI, and microcode without using the private flash. +EC firmware reads them from an absolute address of the system flash chip, which is +hardcoded in the EC firmware. It looks like this verification is done with a digital +signature. If the PEI volume is modified, EC firmware will recover it using the copy +in the private flash. If the private flash has no valid copies of the PEI volume, and +the PEI volume is modified, the machine will refuse to boot with the CapsLock LED blinking. + +## Bypassing HP Sure Start + +First search the mainboard for the flash chips. If there are two flash chips, +the smaller one may be the private flash. + +For Intel boards, try to modify the IFD with ``ifdtool -u``, power on and shut down +the machine, then read the flash again. If the IFD is not modified, it is likely to +be recovered from the private flash. Find the private flash and erase it, then the IFD +can be modified. + +To bypass the bootblock and PEI verification, we can modify the IFD to make the +BIOS region not overlap with the protected region. Since the EC firmware is usually +located at the high address of the flash chip (and in the protected region), +we can leave it untouched, and do not need to extract the EC firmware to put it in +the coreboot image. + +[HP Sure Start Technical Whitepaper]: http://h10032.www1.hp.com/ctg/Manual/c05163901 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 0eefee8..335eae2 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -61,6 +61,7 @@ ### EliteBook series - [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md) +- [HP Sure Start](hp/hp_sure_start.md) - [EliteBook 2560p](hp/2560p.md) - [EliteBook 8760w](hp/8760w.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/45577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id198afdaa13b4c361e1b77a56d5a2436ed1c4c86 Gerrit-Change-Number: 45577 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: soc/nvidia/tegra124/include/soc/clk_rst.h: Remove extra tab
by HAOUAS Elyes (Code Review) 09 Nov '20

09 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46328 ) Change subject: soc/nvidia/tegra124/include/soc/clk_rst.h: Remove extra tab ...................................................................... soc/nvidia/tegra124/include/soc/clk_rst.h: Remove extra tab Change-Id: I0c606fd129c200446744f7a67ae63fec6d8e1684 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/nvidia/tegra124/include/soc/clk_rst.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/46328/1 diff --git a/src/soc/nvidia/tegra124/include/soc/clk_rst.h b/src/soc/nvidia/tegra124/include/soc/clk_rst.h index 0b0e025..cfddd10 100644 --- a/src/soc/nvidia/tegra124/include/soc/clk_rst.h +++ b/src/soc/nvidia/tegra124/include/soc/clk_rst.h @@ -257,7 +257,7 @@ u32 spare_reg0; /* _SPARE_REG0, 0x55c */ u32 _rsv32[4]; /* 0x560-0x56c */ u32 plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */ - u32 _rsv32_1[7]; /* 0x574-58c */ + u32 _rsv32_1[7]; /* 0x574-58c */ u32 plldp_base; /* _PLLDP_BASE, 0x590 */ u32 plldp_misc; /* _PLLDP_MISC, 0x594 */ u32 plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c606fd129c200446744f7a67ae63fec6d8e1684 Gerrit-Change-Number: 46328 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: cpu/intel/model_206ax: Get CPU frequencies for SMBIOS type 4
by Michał Żygowski (Code Review) 09 Nov '20

09 Nov '20

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47058 ) Change subject: cpu/intel/model_206ax: Get CPU frequencies for SMBIOS type 4 ...................................................................... cpu/intel/model_206ax: Get CPU frequencies for SMBIOS type 4 Calculate the frequencies based on the appropriate MSRs adn pass them to SMBIOS tables generator. Ivybridge microarchitecture does not yet implement CPUID 16H leaf to obtain the required frequencies. TEST=Intel Core i7-3770, TianoCore UEFI payload displays the CPU frequency correctly equal 3.4GHz in Boot Manager Menu, dmidecode shows correct frequencies according to Intel ARK, 3.4Ghz base and 3.9GHz turbo Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Iefbae6111d39107eacac7e61654311646c6981eb --- M src/cpu/intel/model_206ax/model_206ax_init.c 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47058/1 diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 7fb412c..2afbfee 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -18,6 +18,7 @@ #include "chip.h" #include <cpu/intel/smm_reloc.h> #include <cpu/intel/common/common.h> +#include <smbios.h> /* * List of supported C-states in this processor @@ -360,6 +361,25 @@ ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); } +unsigned int smbios_cpu_get_max_speed_mhz(void) +{ + msr_t msr; + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + return (msr.lo & 0xff) * SANDYBRIDGE_BCLK; +} + +unsigned int smbios_cpu_get_current_speed_mhz(void) +{ + msr_t msr; + msr = rdmsr(MSR_PLATFORM_INFO); + return ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK; +} + +unsigned int smbios_processor_external_clock(void) +{ + return SANDYBRIDGE_BCLK; +} + static void configure_mca(void) { msr_t msr; -- To view, visit https://review.coreboot.org/c/coreboot/+/47058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefbae6111d39107eacac7e61654311646c6981eb Gerrit-Change-Number: 47058 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: mb/emulation/q35: Define pm_acpi_smi_cmd_port
by Arthur Heymans (Code Review) 09 Nov '20

09 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45814 ) Change subject: mb/emulation/q35: Define pm_acpi_smi_cmd_port ...................................................................... mb/emulation/q35: Define pm_acpi_smi_cmd_port The X86 Qemu targets use the AMD64 SMM save state, but unlike most AMD CPU's the PM ACPI SMI port is not configurable and uses the Intel default APM_CNT, 0xb2 port. This will be used by the common save state handler. Change-Id: Ifee9476f628a2df710fb4340ce6a19b008df1033 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/emulation/qemu-q35/Makefile.inc A src/mainboard/emulation/qemu-q35/smi.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/45814/1 diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index e142d4d..59c61c4 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -14,3 +14,5 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smi.c \ No newline at end of file diff --git a/src/mainboard/emulation/qemu-q35/smi.c b/src/mainboard/emulation/qemu-q35/smi.c new file mode 100644 index 0000000..5d8d482 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/smi.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/smm.h> + +/* The X86 qemu target uses AMD64 save states but the APM port is not configurable. */ +uint16_t pm_acpi_smi_cmd_port(void) +{ + return APM_CNT; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifee9476f628a2df710fb4340ce6a19b008df1033 Gerrit-Change-Number: 45814 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/amd/*/smi.h: Move the pm_acpi_smi_cmd_port function declaration
by Arthur Heymans (Code Review) 09 Nov '20

09 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45813 ) Change subject: soc/amd/*/smi.h: Move the pm_acpi_smi_cmd_port function declaration ...................................................................... soc/amd/*/smi.h: Move the pm_acpi_smi_cmd_port function declaration This prototype will be used outside of soc/amd. Change-Id: Icc69cf8a910764b27edf64f0f527b8f6a9013121 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/cpu/x86/smm.h M src/soc/amd/picasso/include/soc/smi.h M src/soc/amd/picasso/smi_util.c M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/amd/stoneyridge/smi_util.c 5 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/45813/1 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 1073d03..6cf6f82 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -197,5 +197,8 @@ /* Return the SMM save state revision. The revision can be fetched from the smm savestate which is always at the same offset downward from the top of the save state. */ uint32_t smm_revision(void); +/* Returns the PM ACPI SMI port. On Intel systems this typically not configurable (APM_CNT, 0xb2). + On AMD systems it is sometimes configurable. */ +uint16_t pm_acpi_smi_cmd_port(void); #endif /* CPU_X86_SMM_H */ diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index a629fc5..ee47676 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -213,7 +213,6 @@ uint8_t level; /* Edge or Level, smi_sci_dir */ }; -uint16_t pm_acpi_smi_cmd_port(void); void configure_smi(uint8_t smi_num, uint8_t mode); void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void configure_scimap(const struct sci_source *sci); diff --git a/src/soc/amd/picasso/smi_util.c b/src/soc/amd/picasso/smi_util.c index 2c5085b..2fbc8e2 100644 --- a/src/soc/amd/picasso/smi_util.c +++ b/src/soc/amd/picasso/smi_util.c @@ -5,6 +5,7 @@ */ #include <console/console.h> +#include <cpu/x86/smm.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <amdblocks/acpimmio.h> diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index f7cacea..15bba0f 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -211,7 +211,6 @@ uint8_t level; /* Edge or Level, smi_sci_dir */ }; -uint16_t pm_acpi_smi_cmd_port(void); void configure_smi(uint8_t smi_num, uint8_t mode); void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void configure_scimap(const struct sci_source *sci); diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c index 2c5085b..2fbc8e2 100644 --- a/src/soc/amd/stoneyridge/smi_util.c +++ b/src/soc/amd/stoneyridge/smi_util.c @@ -5,6 +5,7 @@ */ #include <console/console.h> +#include <cpu/x86/smm.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <amdblocks/acpimmio.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc69cf8a910764b27edf64f0f527b8f6a9013121 Gerrit-Change-Number: 45813 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: [WIP] SMM save states
by Arthur Heymans (Code Review) 09 Nov '20

09 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44323 ) Change subject: [WIP] SMM save states ...................................................................... [WIP] SMM save states Change-Id: I4a31d05c09065543424a9010ac434dde0dfb5836 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/smm/Makefile.inc A src/cpu/intel/smm/em64t101_save_state.c M src/cpu/x86/smm/Makefile.inc A src/cpu/x86/smm/save_state.c M src/cpu/x86/smm/smm.ld A src/include/cpu/x86/save_state.h M src/lib/program.ld M src/southbridge/intel/i82801ix/smihandler.c 8 files changed, 210 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/44323/1 diff --git a/src/cpu/intel/smm/Makefile.inc b/src/cpu/intel/smm/Makefile.inc index a49b796..df73ae7 100644 --- a/src/cpu/intel/smm/Makefile.inc +++ b/src/cpu/intel/smm/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm_reloc.c +smm-y += em64t101_save_state.c diff --git a/src/cpu/intel/smm/em64t101_save_state.c b/src/cpu/intel/smm/em64t101_save_state.c new file mode 100644 index 0000000..404906b --- /dev/null +++ b/src/cpu/intel/smm/em64t101_save_state.c @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <string.h> +#include <cpu/x86/save_state.h> +#include <cpu/intel/em64t101_save_state.h> + +static void *em64t101_get_reg_base(const enum cpu_reg reg, const int node) +{ + const em64t101_smm_state_save_area_t *save_state = (const em64t101_smm_state_save_area_t *)smm_get_save_state(node); + + switch (reg) { + case RAX: + return (void *)&save_state->rax; + case RBX: + return (void *)&save_state->rbx; + case RCX: + return (void *)&save_state->rcx; + case RDX: + return (void *)&save_state->rdx; + } + + return NULL; +} + +enum get_set { + GET, + SET +}; + +static int em64t101_get_set(const enum get_set op_type, const enum cpu_reg reg, + const int node, void *in_out, const uint8_t length) +{ + + void *reg_base = em64t101_get_reg_base(reg, node); + + if (!reg_base) + return -1; + + switch (length) { + case 1: + case 2: + case 4: + case 8: + switch (op_type) { + case GET: + memcpy(in_out, reg_base, length); + return 0; + case SET: + memcpy(reg_base, in_out, length); + } + } + + return -1; +} + +static int em64t101_get_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length) +{ + return em64t101_get_set(GET, reg, node, out, length); +} + +static int em64t101_set_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length) +{ + return em64t101_get_set(SET, reg, node, in, length); +} + +static int em64t101_apmc_node(u8 cmd) +{ + em64t101_smm_state_save_area_t *state; + int node; + + for (node = 0; node < CONFIG_MAX_CPUS; node++) { + state = smm_get_save_state(node); + + /* Check for Synchronous IO (bit0 == 1) */ + if (!(state->io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4 == 0) */ + if (state->io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + + /* Check AX against the requested command */ + if ((state->rax & 0xff) != cmd) + continue; + + return node; + } + + return -1; +} + +static const uint32_t revisions[] = { + 0x00030101, + SMM_REV_INVALID, +}; + +static const struct smm_save_state_ops ops __smm_save_state_ops = { + .revision_table = revisions, + .get_reg = em64t101_get_reg, + .set_reg = em64t101_set_reg, + .apmc_node = em64t101_apmc_node, +}; diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index bbd96c6..2b3e073 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -28,6 +28,8 @@ ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual endif +smm-y += save_state.c + ifeq ($(CONFIG_SMM_TSEG),y) ramstage-y += tseg_region.c diff --git a/src/cpu/x86/smm/save_state.c b/src/cpu/x86/smm/save_state.c new file mode 100644 index 0000000..7c757e3 --- /dev/null +++ b/src/cpu/x86/smm/save_state.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/smm.h> +#include <cpu/x86/save_state.h> + +static struct smm_save_state_ops *save_state; + +/* Returns -1 on failure, 0 on success */ +static int init_save_state(void) +{ + const uint32_t revision = smm_revision(); + struct smm_save_state_ops *ops; + static bool initialized = false; + + if (initialized) + return 0; + + for (ops = _smm_save_state_ops; ops < _esmm_save_state_ops; ops++) { + const uint32_t *rev; + for (rev = ops->revision_table; *rev != SMM_REV_INVALID; rev++) + if (*rev == revision) { + save_state = ops; + initialized = true; + return 0; + } + } + + return -1; +} + +int get_apmc_node(u8 cmd) +{ + if (init_save_state()) + return -1; + + return save_state->apmc_node(cmd); +} + +int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length) +{ + if (init_save_state()) + return -1; + + return save_state->get_reg(reg, node, out, length); +} diff --git a/src/cpu/x86/smm/smm.ld b/src/cpu/x86/smm/smm.ld index 2f46975..39afee4 100644 --- a/src/cpu/x86/smm/smm.ld +++ b/src/cpu/x86/smm/smm.ld @@ -25,6 +25,11 @@ /* C read-only data of the SMM handler */ . = ALIGN(16); + + _smm_save_state_ops = .; + KEEP(*(.rodata.smm_ops)); + _esmm_save_state_ops = .; + *(.rodata) *(.rodata.*) diff --git a/src/include/cpu/x86/save_state.h b/src/include/cpu/x86/save_state.h new file mode 100644 index 0000000..b97890b --- /dev/null +++ b/src/include/cpu/x86/save_state.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __CPU_X86_SAVE_STATE_H__ +#define __CPU_X86_SAVE_STATE_H__ + +#include <stdint.h> + +#if ENV_SMM +#define __smm_save_state_ops __attribute__((used, __section__(".rodata.smm_ops"))) +#else +#define __smm_save_state_ops __attribute__((unused)) +#endif + +enum cpu_reg { + RAX, + RBX, + RCX, + RDX +}; + +#define SMM_REV_INVALID 0xffffffff + +struct smm_save_state_ops { + const uint32_t *revision_table; + /* Accessors for CPU registers in the SMM save state + Returns -1 on failure, 0 on success */ + int (*get_reg)(const enum cpu_reg reg, const int node, void *out, const uint8_t length); + int(*set_reg)(const enum cpu_reg reg, const int node, void *in, const uint8_t length); + /* Returns -1 on failure, the node on which the 'cmd' was send on success */ + int(*apmc_node)(u8 cmd); +}; + +/** start of compile time generated pci driver array */ +extern struct smm_save_state_ops _smm_save_state_ops[]; +/** end of compile time generated pci driver array */ +extern struct smm_save_state_ops _esmm_save_state_ops[]; + +int get_apmc_node(u8 cmd); +int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length); + +#endif /* __CPU_X86_SAVE_STATE_H__ */ diff --git a/src/lib/program.ld b/src/lib/program.ld index 88a3126..1894ae0 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -44,6 +44,13 @@ _ecpu_drivers = .; #endif +#if ENV_SMM || ENV_RMODULE + . = ALIGN(ARCH_POINTER_ALIGN_SIZE); + _smm_save_state_ops = .; + KEEP(*(.rodata.smm_ops)); + _esmm_save_state_ops = .; +#endif + . = ALIGN(ARCH_POINTER_ALIGN_SIZE); *(.rodata); *(.rodata.*); diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 699f51f..9b37f05 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -3,6 +3,7 @@ #include <types.h> #include <console/console.h> #include <cpu/x86/smm.h> +#include <cpu/x86/save_state.h> #include <device/pci_def.h> #include <southbridge/intel/common/pmutil.h> #include "i82801ix.h" @@ -31,6 +32,8 @@ return 1; /* IO trap handled */ } + get_apmc_node(5); + /* Not handled */ return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a31d05c09065543424a9010ac434dde0dfb5836 Gerrit-Change-Number: 44323 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: cpu/x86/smm/smm.ld: Assert that CONFIG_MAX_CPUS <= 4
by Arthur Heymans (Code Review) 09 Nov '20

09 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44322 ) Change subject: cpu/x86/smm/smm.ld: Assert that CONFIG_MAX_CPUS <= 4 ...................................................................... cpu/x86/smm/smm.ld: Assert that CONFIG_MAX_CPUS <= 4 The SMM_ASEG code only supports up to 4 CPUs, so assert this at buildtime. Change-Id: I8ec803cd1b76f17f4dccd5c573179d542d54c277 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smm.ld 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/44322/1 diff --git a/src/cpu/x86/smm/smm.ld b/src/cpu/x86/smm/smm.ld index af5968d..2f46975 100644 --- a/src/cpu/x86/smm/smm.ld +++ b/src/cpu/x86/smm/smm.ld @@ -2,6 +2,9 @@ /* Maximum number of CPUs/cores */ CPUS = 4; + +_ = ASSERT(CPUS > CONFIG_MAX_CPUS, "The ASEG SMM code only supports up to 4 CPUS"); + ENTRY(smm_handler_start); SECTIONS -- To view, visit https://review.coreboot.org/c/coreboot/+/44322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ec803cd1b76f17f4dccd5c573179d542d54c277 Gerrit-Change-Number: 44322 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: cpu/x86/smm/smihandler.c: Simplify smm revision handling
by Arthur Heymans (Code Review) 09 Nov '20

09 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45471 ) Change subject: cpu/x86/smm/smihandler.c: Simplify smm revision handling ...................................................................... cpu/x86/smm/smihandler.c: Simplify smm revision handling The ASEG smihandler bails out if an unsupported SMM save state revision is detected. Now we have code to find the SMM save state depending on the SMM save state revision so reuse this to do the same. This also increases the loglevel when bailing out of SMM due to unsupported SMM save state revision from BIOS_DEBUG to BIOS_WARNING, given that the system likely still boots but won't have a functioning smihandler. Change-Id: I57198f0c85c0f7a1fa363d3bd236c3d41b68d2f0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smihandler.c 1 file changed, 3 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45471/1 diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 077fa8d..dea4cf3 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -14,23 +14,6 @@ #include <spi-generic.h> #endif -typedef enum { - AMD64, - EM64T100, - EM64T101, - LEGACY -} save_state_type_t; - -typedef struct { - save_state_type_t type; - union { - amd64_smm_state_save_area_t *amd64_state_save; - em64t100_smm_state_save_area_t *em64t100_state_save; - em64t101_smm_state_save_area_t *em64t101_state_save; - legacy_smm_state_save_area_t *legacy_state_save; - }; -} smm_state_save_area_t; - static int do_driver_init = 1; typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; @@ -162,9 +145,6 @@ void smi_handler(void) { unsigned int node; - const uint32_t smm_rev = smm_revision(); - smm_state_save_area_t state_save; - u32 smm_base = SMM_BASE; /* ASEG */ /* Are we ok to execute the handler? */ if (!smi_obtain_lock()) { @@ -190,36 +170,9 @@ printk(BIOS_SPEW, "\nSMI# #%d\n", node); - switch (smm_rev) { - case 0x00030002: - case 0x00030007: - state_save.type = LEGACY; - state_save.legacy_state_save = - smm_save_state(smm_base, - SMM_LEGACY_ARCH_OFFSET, node); - break; - case 0x00030100: - state_save.type = EM64T100; - state_save.em64t100_state_save = - smm_save_state(smm_base, - SMM_EM64T100_ARCH_OFFSET, node); - break; - case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */ - state_save.type = EM64T101; - state_save.em64t101_state_save = - smm_save_state(smm_base, - SMM_EM64T101_ARCH_OFFSET, node); - break; - case 0x00020064: - case 0x00030064: - state_save.type = AMD64; - state_save.amd64_state_save = - smm_save_state(smm_base, - SMM_AMD64_ARCH_OFFSET, node); - break; - default: - printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_rev); - printk(BIOS_DEBUG, "SMI# not supported on your CPU\n"); + if (smm_get_save_state(node) == NULL) { + printk(BIOS_WARNING, "smm_revision: 0x%08x\n", smm_revision()); + printk(BIOS_WARNING, "SMI# not supported on your CPU\n"); /* Don't release lock, so no further SMI will happen, * if we don't handle it anyways. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57198f0c85c0f7a1fa363d3bd236c3d41b68d2f0 Gerrit-Change-Number: 45471 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: mb/purism/librem_cml: Add baseboard and Librem Mini v2 board
by Matt DeVillier (Code Review) 09 Nov '20

09 Nov '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46984 ) Change subject: mb/purism/librem_cml: Add baseboard and Librem Mini v2 board ...................................................................... mb/purism/librem_cml: Add baseboard and Librem Mini v2 board Add new Cometlake-U baseboard, and Librem Mini v2 variant. The Mini v2 is the same board as the v1, except for the SoC change from Whiskeylake-U to Cometlake-U. Documentation has been updated accordingly. Change-Id: I856bb914941211cfbec4fed871ba2a5a038e23c3 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- A Documentation/mainboard/purism/librem_mini_v2.md A src/mainboard/purism/librem_cml/Kconfig A src/mainboard/purism/librem_cml/Kconfig.name A src/mainboard/purism/librem_cml/Makefile.inc A src/mainboard/purism/librem_cml/acpi/mainboard.asl A src/mainboard/purism/librem_cml/board_info.txt A src/mainboard/purism/librem_cml/dsdt.asl A src/mainboard/purism/librem_cml/ramstage.c A src/mainboard/purism/librem_cml/romstage.c A src/mainboard/purism/librem_cml/variants/librem_mini/board_info.txt A src/mainboard/purism/librem_cml/variants/librem_mini/data.vbt A src/mainboard/purism/librem_cml/variants/librem_mini/devicetree.cb A src/mainboard/purism/librem_cml/variants/librem_mini/gpio.c A src/mainboard/purism/librem_cml/variants/librem_mini/hda_verb.c A src/mainboard/purism/librem_cml/variants/librem_mini/include/variant/gpio.h A src/mainboard/purism/librem_cml/variants/librem_mini/include/variant/variant.h A src/mainboard/purism/librem_cml/variants/librem_mini/variant.c 17 files changed, 1,352 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/46984/1 diff --git a/Documentation/mainboard/purism/librem_mini_v2.md b/Documentation/mainboard/purism/librem_mini_v2.md new file mode 100644 index 0000000..81ae9a5 --- /dev/null +++ b/Documentation/mainboard/purism/librem_mini_v2.md @@ -0,0 +1,123 @@ +# Purism Librem Mini v2 + +This page describes how to run coreboot on the [Purism Librem Mini v2]. + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Core i7-10510U | ++------------------+--------------------------------------------------+ +| PCH | Comet Point LP Premium (Cometlake-U) | ++------------------+--------------------------------------------------+ +| Super I/O, EC | ITE IT8528E | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine (CSME 14.x) | ++------------------+--------------------------------------------------+ +``` + +![](librem_mini.jpg) +![](librem_mini_flash.jpg) + +## Required proprietary blobs + +To build a minimal working coreboot image some blobs are required (assuming +only the BIOS region is being modified). + +```eval_rst ++-----------------+---------------------------------+---------------------+ +| Binary file | Apply | Required / Optional | ++=================+=================================+=====================+ +| FSP-M, FSP-S | Intel Firmware Support Package | Required | ++-----------------+---------------------------------+---------------------+ +| microcode | CPU microcode | Required | ++-----------------+---------------------------------+---------------------+ +| vgabios | VGA Option ROM | Optional | ++-----------------+---------------------------------+---------------------+ +``` + +FSP-M and FSP-S are obtained after splitting the Comet Lake FSP binary (done +automatically by the coreboot build system and included into the image) from +the `3rdparty/fsp` submodule. + +Microcode updates are automatically included into the coreboot image by the build +system from the `3rdparty/intel-microcode` submodule. Official Purism release +images may include newer microcode, which is instead pulled from Purism's +[purism-blobs] repository. + +VGA Option ROM is not required to boot, but if one needs graphics in pre-OS +stage, it should be included (if not using FSP/GOP display init). It can +be extracted via cbfstool from the existing board firmware or pulled from +the [purism-blobs] repository. + +## Intel Management Engine + +The Librem Mini v2 uses version 14.x of the Intel Management Engine (ME) / +Converged Security Engine (CSE). The ME/CSE is disabled using the High +Assurance Platform (HAP) bit, which puts the ME into a disabled state +after platform bring-up (BUP) and disables all PCI/HECI interfaces. +This can be verified via the coreboot cbmem utility: +`sudo ./cbmem -1 | grep 'ME:'` +provided coreboot has been modified to output the ME status even when +the PCI device is not visible/active (as it is in Purism's release builds). + +## Flashing coreboot + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. The first build +supporting the chipset is flashrom v1.2-107-gb1f858f. Firmware an be +easily flashed with internal programmer (either BIOS region or full image). + +### External programming + +The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip, +and has a diode attached to the VCC line for in-system programming. +This chip is located on the bottom side of the board under the CPU heatsink, +in line with the front USB 2.0 ports. + +One has to remove all screws (in order): + + * 2 top cover screws + * 4 screws securing the mainboard to the chassis + * 4 screws securing the heatsink/fan assembly to the mainboard (under the SODIMMs) + +The m.2 SSD will need to be removed if the Wi-Fi antenna are connected to +an internal Wi-Fi/BT module. Use a SOIC-8 chip clip to program the chip. +Specifically, it's a Winbond W25Q128JV (3.3V) - [datasheet][W25Q128JV]. + +The EC firmware is stored on a separate SOIC-8 chip (a Winbond W25Q80DV), +but is not protected by a diode and therefore cannot be read/written to without +desoldering it from the mainboard. + +## Known issues + + * SeaBIOS can be finicky with detecting USB devices + * Mode switching with VGA option ROM display init can be slow and sometimes hang + * Some SATA devices on the 2.5" interface can have issues operating at 6Gbps, + despite the HSIO PHY settings being set optimally. These devices may show + errors in dmesg and drop down to 3Gbps, but should not fail to boot. + The same issue is present on the AMI vendor firmware. + +## Working + + * External displays via HDMI/DislpayPort with VGA option ROM or FSP/GOP init + (no libgfxinit support yet) + * SeaBIOS (1.14), Tianocore (CorebootPayloadpkg), Heads (Purism downstream) payloads + * Ethernet, m.2 2230 Wi-Fi + * System firmware updates via flashrom + * PCIe NVMe + * m.2 and SATA III + * Audio via front 3.5mm jack, HDMI, and DisplayPort + * SMBus (reading SPD from DIMMs) + * Initialization with CML FSP 2.0 + * S3 Suspend/Resume + * Booting PureOS 10.x, Debian 11.x, Qubes 4.1.0-alpha1, Linux Mint 20, Windows 10 2004 + +## Not working / untested + + * ITE IT8528E Super IO functions + + +[Purism Librem Mini v2]: https://puri.sm/products/librem-mini/ +[purism-blobs]: https://source.puri.sm/coreboot/purism-blobs +[W25Q128JV]: https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.p… +[flashrom]: https://flashrom.org/Flashrom diff --git a/src/mainboard/purism/librem_cml/Kconfig b/src/mainboard/purism/librem_cml/Kconfig new file mode 100644 index 0000000..0d70300 --- /dev/null +++ b/src/mainboard/purism/librem_cml/Kconfig @@ -0,0 +1,69 @@ +config BOARD_PURISM_BASEBOARD_LIBREM_CML + def_bool n + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_GENERIC_CBFS_SERIAL + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select NO_UART_ON_SUPERIO + select SOC_INTEL_COMETLAKE_1 + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SPD_READ_BY_WORD + select USE_LEGACY_8254_TIMER + +if BOARD_PURISM_BASEBOARD_LIBREM_CML + +config MAINBOARD_DIR + string + default "purism/librem_cml" + +config MAINBOARD_FAMILY + string + default "Librem Mini" if BOARD_PURISM_LIBREM_MINI_V2 + +config MAINBOARD_PART_NUMBER + string + default "Librem Mini v2" if BOARD_PURISM_LIBREM_MINI_V2 + +config VARIANT_DIR + string + default "librem_mini" if BOARD_PURISM_LIBREM_MINI_V2 + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config CBFS_SIZE + hex + default 0xA00000 + +config MAX_CPUS + int + default 8 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config VGA_BIOS_ID + string + default "8086,9b41" + +config PXE_ROM_ID + string + default "10ec,8168" + +config NO_POST + bool + default y + +config CONSOLE_SERIAL + bool + default n +endif diff --git a/src/mainboard/purism/librem_cml/Kconfig.name b/src/mainboard/purism/librem_cml/Kconfig.name new file mode 100644 index 0000000..726aee9 --- /dev/null +++ b/src/mainboard/purism/librem_cml/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_PURISM_LIBREM_MINI_V2 + bool "Librem Mini v2" + select BOARD_PURISM_BASEBOARD_LIBREM_CML diff --git a/src/mainboard/purism/librem_cml/Makefile.inc b/src/mainboard/purism/librem_cml/Makefile.inc new file mode 100644 index 0000000..8e3b5a6 --- /dev/null +++ b/src/mainboard/purism/librem_cml/Makefile.inc @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +romstage-y += variants/$(VARIANT_DIR)/variant.c + +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += ramstage.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/purism/librem_cml/acpi/mainboard.asl b/src/mainboard/purism/librem_cml/acpi/mainboard.asl new file mode 100644 index 0000000..999030d --- /dev/null +++ b/src/mainboard/purism/librem_cml/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.LPCB) { + + Device (AC) + { + Name (_HID, "ACPI0003") + Name (_PCL, Package () { LPCB }) + Name (ACFG, One) + + Method (_PSR, 0, NotSerialized) + { + Return (ACFG) + } + } +} diff --git a/src/mainboard/purism/librem_cml/board_info.txt b/src/mainboard/purism/librem_cml/board_info.txt new file mode 100644 index 0000000..8283cee --- /dev/null +++ b/src/mainboard/purism/librem_cml/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Purism +Board name: Librem CometLake baseboard +Category: misc +Release year: 2020 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/purism/librem_cml/dsdt.asl b/src/mainboard/purism/librem_cml/dsdt.asl new file mode 100644 index 0000000..6545a6e --- /dev/null +++ b/src/mainboard/purism/librem_cml/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/purism/librem_cml/ramstage.c b/src/mainboard/purism/librem_cml/ramstage.c new file mode 100644 index 0000000..56ed1b7 --- /dev/null +++ b/src/mainboard/purism/librem_cml/ramstage.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> +#include <variant/gpio.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + size_t num_gpios; + const struct pad_config *gpio_table = variant_gpio_table(&num_gpios); + cnl_configure_pads(gpio_table, num_gpios); +} diff --git a/src/mainboard/purism/librem_cml/romstage.c b/src/mainboard/purism/librem_cml/romstage.c new file mode 100644 index 0000000..af8b473 --- /dev/null +++ b/src/mainboard/purism/librem_cml/romstage.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> +#include <variant/variant.h> + +static const struct cnl_mb_cfg memcfg = { + /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa0}, + }, + .spd[1] = {.read_type = NOT_EXISTING}, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa4}, + }, + .spd[3] = {.read_type = NOT_EXISTING}, + + /* + * Rcomp resistor values. These values represent the resistance in + * ohms of the three rcomp resistors attached to the DDR_COMP_0, + * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + */ + .rcomp_resistor = { 121, 81, 100 }, + + /* + * Rcomp target values. These will typically be the following + * values for Cannon Lake : { 80, 40, 40, 40, 30 } + */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* + * Indicates whether memory is interleaved. + * Set to 1 for an interleaved design, + * set to 0 for non-interleaved design. + */ + .dq_pins_interleaved = 1, + + /* + * VREF_CA configuration. + * Set to 0 VREF_CA goes to both CH_A and CH_B, + * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, + * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. + */ + .vref_ca_config = 2, + + /* Early Command Training */ + .ect = 0, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + cannonlake_memcfg_init(mem_cfg, &memcfg); + + variant_memory_init_params(mem_cfg); +} diff --git a/src/mainboard/purism/librem_cml/variants/librem_mini/board_info.txt b/src/mainboard/purism/librem_cml/variants/librem_mini/board_info.txt new file mode 100644 index 0000000..de22500 --- /dev/null +++ b/src/mainboard/purism/librem_cml/variants/librem_mini/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Purism +Board name: Librem Mini v2 +Category: desktop +Release year: 2020 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/purism/librem_cml/variants/librem_mini/data.vbt b/src/mainboard/purism/librem_cml/variants/librem_mini/data.vbt new file mode 100644 index 0000000..b538209 --- /dev/null +++ b/src/mainboard/purism/librem_cml/variants/librem_mini/data.vbt Binary files differ diff --git a/src/mainboard/purism/librem_cml/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cml/variants/librem_mini/devicetree.cb new file mode 100644 index 0000000..5f49508 --- /dev/null +++ b/src/mainboard/purism/librem_cml/variants/librem_mini/devicetree.cb @@ -0,0 +1,170 @@ +chip soc/intel/cannonlake + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + +# ACPI (soc/intel/cannonlake/acpi.c) + # PM Timer Disabled + register "PmTimerDisabled" = "1" + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 51, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) + register "SaGv" = "SaGv_Enabled" + register "enable_c6dram" = "1" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + + # All SRCCLKREQ pins mapped directly + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + + # Set all SRCCLKREQ pins as free-use + register "PcieClkSrcUsage[0]" = "0x80" + register "PcieClkSrcUsage[1]" = "0x80" + register "PcieClkSrcUsage[2]" = "0x80" + register "PcieClkSrcUsage[3]" = "0x80" + register "PcieClkSrcUsage[4]" = "0x80" + register "PcieClkSrcUsage[5]" = "0x80" + + # Misc + register "satapwroptimize" = "1" + + # Power + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "2" # 500ms + register "PchPmSlpAMinAssert" = "4" # 2s + + # Thermal + register "tcc_offset" = "10" + +# PM Util (soc/intel/cannonlake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "PMC_GPP_C" + register "gpe0_dw1" = "PMC_GPP_D" + register "gpe0_dw2" = "PMC_GPP_E" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on # SA Thermal device + register "Device4Enable" = "1" + end + device pci 08.0 on end # Gaussian Mixture Model + device pci 12.0 on end # Thermal Subsystem + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port rear lower + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port rear upper + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port front right lower + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port front right upper + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port front left lower + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port front left upper + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port front + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Type-A ports front center (2) + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port rear lower + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port rear upper + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port front lower + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port front upper + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port front + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # RAM memory + device pci 14.3 off end # CNVi wifi + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on # SATA + register "SataMode" = "Sata_AHCI" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[2]" = "1" + end + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 on # PCI Express Port 8 + device pci 00.0 on end # x1 (WLAN) + register "PcieRpSlotImplemented[7]" = "1" + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" + chip drivers/wifi/generic + device pci 00.0 on end + end + end + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 on # PCI Express Port 10 + device pci 00.0 on end # x1 (LAN #2) + register "PcieRpSlotImplemented[9]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "0" + end + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on # PCI Express Port 13 + device pci 00.0 on end # x4 M.2/M 2280 + register "PcieRpSlotImplemented[12]" = "1" + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + end + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 on # Intel HDA + register "PchHdaAudioLinkHda" = "1" + end + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/purism/librem_cml/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cml/variants/librem_mini/gpio.c new file mode 100644 index 0000000..001ef43 --- /dev/null +++ b/src/mainboard/purism/librem_cml/variants/librem_mini/gpio.c @@ -0,0 +1,783 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <variant/gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - RCIN# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + + /* GPP_A1 - LAD0 */ + /* DW0: 0x44000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + + /* GPP_A2 - LAD1 */ + /* DW0: 0x44000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + + /* GPP_A3 - LAD2 */ + /* DW0: 0x44000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + + /* GPP_A4 - LAD3 */ + /* DW0: 0x44000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + + /* GPP_A5 - LFRAME# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + + /* GPP_A6 - SERIRQ */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + + /* GPP_A7 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + + /* GPP_A8 - CLKRUN# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + + /* GPP_A9 - CLKOUT_LPC0 */ + /* DW0: 0x44000700, DW1: 0x00001000 */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + + /* GPP_A10 - CLKOUT_LPC1 */ + /* DW0: 0x44000700, DW1: 0x00001000 */ + PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), + + /* GPP_A11 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A11, 1, PLTRST), + + /* GPP_A12 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A12, 1, PLTRST), + + /* GPP_A13 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + + /* GPP_A14 - SUS_STAT# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + + /* GPP_A15 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A15, 1, PLTRST), + + /* GPP_A16 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00003000 */ + PAD_CFG_TERM_GPO(GPP_A16, 1, UP_20K, PLTRST), + + /* GPP_A17 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A17, 1, PLTRST), + + /* GPP_A18 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_A18, UP_20K), + + /* GPP_A19 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_A19, UP_20K), + + /* GPP_A20 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_A20, UP_20K), + + /* GPP_A21 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_A21, UP_20K), + + /* GPP_A22 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_A22, UP_20K), + + /* GPP_A23 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_A23, UP_20K), + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - Reserved */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + + /* GPP_B1 - Reserved */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* GPP_B2 - VRALERT# */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), + + /* GPP_B3 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B3, 1, PLTRST), + + /* GPP_B4 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), + + /* GPP_B5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_B5, NONE), + + /* GPP_B6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_B6, NONE), + + /* GPP_B7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_B7, NONE), + + /* GPP_B8 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_B8, NONE), + + /* GPP_B9 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_B9, NONE), + + /* GPP_B10 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_B10, NONE), + + /* GPP_B11 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B11, 1, PLTRST), + + /* GPP_B12 - SLP_S0# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* GPP_B13 - PLTRST# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* GPP_B14 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B14, 1, PLTRST), + + /* GPP_B15 - GPIO */ + /* DW0: 0x80000201, DW1: 0x00003000 */ + PAD_CFG_TERM_GPO(GPP_B15, 1, UP_20K, PLTRST), + + /* GPP_B16 - GSPI0_CLK */ + /* DW0: 0x84000601, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B16, NONE, PLTRST, NF1), + + /* GPP_B17 - GSPI0_MISO */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + + /* GPP_B18 - GSPI0_MOSI */ + /* DW0: 0x84000601, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B18, NONE, PLTRST, NF1), + + /* GPP_B19 - GSPI1_CS0# */ + /* DW0: 0x84000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B19, NONE, PLTRST, NF1), + + /* GPP_B20 - GSPI1_CLK */ + /* DW0: 0x84000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B20, NONE, PLTRST, NF1), + + /* GPP_B21 - GSPI1_MISO */ + /* DW0: 0x84000402, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B21, NONE, PLTRST, NF1), + + /* GPP_B22 - GSPI1_MOSI */ + /* DW0: 0x84000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B22, NONE, PLTRST, NF1), + + /* GPP_B23 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B23, 1, DEEP), + + /* ------- GPIO Group GPP_G ------- */ + + /* GPP_G0 - GPIO */ + /* DW0: 0x04000200, DW1: 0x00001000 */ + PAD_CFG_TERM_GPO(GPP_G0, 0, DN_20K, PWROK), + + /* GPP_G1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_G1, NONE), + + /* GPP_G2 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_G2, NONE), + + /* GPP_G3 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_G3, NONE), + + /* GPP_G4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_G4, NONE), + + /* GPP_G5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_G5, UP_20K), + + /* GPP_G6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_G6, NONE), + + /* GPP_G7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00001000 */ + PAD_NC(GPP_G7, DN_20K), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D0 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D0, NONE), + + /* GPP_D1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D1, NONE), + + /* GPP_D2 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D2, NONE), + + /* GPP_D3 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D3, NONE), + + /* GPP_D4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D4, NONE), + + /* GPP_D5 - ISH_I2C0_SDA */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + + /* GPP_D6 - ISH_I2C0_SCL */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + + /* GPP_D7 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D7, 1, PLTRST), + + /* GPP_D8 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D8, 1, PLTRST), + + /* GPP_D9 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D9, 1, PLTRST), + + /* GPP_D10 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D10, 1, PLTRST), + + /* GPP_D11 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00003000 */ + PAD_CFG_TERM_GPO(GPP_D11, 1, UP_20K, DEEP), + + /* GPP_D12 - GPIO */ + /* DW0: 0x42100102, DW1: 0x00003000 */ + PAD_CFG_GPI_APIC(GPP_D12, UP_20K, DEEP, EDGE_SINGLE, NONE), + + /* GPP_D13 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D13, NONE), + + /* GPP_D14 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + + /* GPP_D15 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), + + /* GPP_D16 - GPIO */ + /* DW0: 0x04000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D16, 0, RSMRST), + + /* GPP_D17 - DMIC_CLK1 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + + /* GPP_D18 - DMIC_DATA1 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + + /* GPP_D19 - DMIC_CLK0 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + + /* GPP_D20 - DMIC_DATA0 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + + /* GPP_D21 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D21, NONE), + + /* GPP_D22 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D22, NONE), + + /* GPP_D23 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F0 - GPIO */ + /* DW0: 0x00000301, DW1: 0x00000000 */ + PAD_NC(GPP_F0, NONE), + + /* GPP_F1 - GPIO */ + /* DW0: 0x04000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F1, 0, RSMRST), + + /* GPP_F2 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00003000 */ + PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST), + + /* GPP_F3 - GPIO */ + /* DW0: 0x84000300, DW1: 0x00003000 */ + PAD_NC(GPP_F3, UP_20K), + + /* GPP_F4 - CNV_BRI_DT */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1), + + /* GPP_F5 - CNV_BRI_RSP */ + /* DW0: 0x44000702, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), + + /* GPP_F6 - CNV_RGI_DT */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1), + + /* GPP_F7 - CNV_RGI_RSP */ + /* DW0: 0x44000702, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), + + /* GPP_F8 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F8, NONE), + + /* GPP_F9 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F9, NONE), + + /* GPP_F10 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + + /* GPP_F11 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F11, NONE), + + /* GPP_F12 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F12, NONE), + + /* GPP_F13 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F13, NONE), + + /* GPP_F14 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F14, NONE), + + /* GPP_F15 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F15, NONE), + + /* GPP_F16 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F16, NONE), + + /* GPP_F17 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F17, NONE), + + /* GPP_F18 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F18, NONE), + + /* GPP_F19 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F19, NONE), + + /* GPP_F20 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F20, NONE), + + /* GPP_F21 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F21, NONE), + + /* GPP_F22 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_F22, NONE), + + /* GPP_F23 - A4WP_PRESENT */ + /* DW0: 0x44000700, DW1: 0x00001000 */ + PAD_CFG_NF(GPP_F23, DN_20K, DEEP, NF1), + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_H0, UP_20K), + + /* GPP_H1 - CNV_RF_RESET# */ + /* DW0: 0x44000f00, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3), + + /* GPP_H2 - MODEM_CLKREQ */ + /* DW0: 0x44000f00, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3), + + /* GPP_H3 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003000 */ + PAD_NC(GPP_H3, UP_20K), + + /* GPP_H4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_H4, NONE), + + /* GPP_H5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_H5, NONE), + + /* GPP_H6 - I2C3_SDA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + + /* GPP_H7 - I2C3_SCL */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + + /* GPP_H8 - I2C4_SDA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + + /* GPP_H9 - I2C4_SCL */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + + /* GPP_H10 - I2C5_SDA */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1), + + /* GPP_H11 - I2C5_SCL */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF1), + + /* GPP_H12 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H12, 1, PLTRST), + + /* GPP_H13 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H13, 1, PLTRST), + + /* GPP_H14 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H14, 1, PLTRST), + + /* GPP_H15 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H15, 1, PLTRST), + + /* GPP_H16 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_H16, NONE), + + /* GPP_H17 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H17, 0, DEEP), + + /* GPP_H18 - CPU_C10_GATE# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /* GPP_H19 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H19, 1, PLTRST), + + /* GPP_H20 - GPIO */ + /* DW0: 0x84000300, DW1: 0x00000000 */ + PAD_NC(GPP_H20, NONE), + + /* GPP_H21 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H21, 0, DEEP), + + /* GPP_H22 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H22, 1, PLTRST), + + /* GPP_H23 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H23, 0, DEEP), + + /* ------- GPIO Group GPD ------- */ + + /* GPD0 - BATLOW# */ + /* DW0: 0x04000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), + + /* GPD1 - ACPRESENT */ + /* DW0: 0x04000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1), + + /* GPD2 - LAN_WAKE# */ + /* DW0: 0x04000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPD2, NATIVE, RSMRST, NF1), + + /* GPD3 - PRWBTN# */ + /* DW0: 0x04000702, DW1: 0x00003000 */ + PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), + + /* GPD4 - SLP_S3# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), + + /* GPD5 - SLP_S4# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), + + /* GPD6 - SLP_A# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), + + /* GPD7 - GPIO */ + /* DW0: 0x04000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPD7, 0, RSMRST), + + /* GPD8 - SUSCLK */ + /* DW0: 0x04000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), + + /* GPD9 - SLP_WLAN# */ + /* DW0: 0x04000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), + + /* GPD10 - SLP_S5# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), + + /* GPD11 - LANPHYPC */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + + /* GPP_C1 - SMBDATA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_C2 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C2, 1, DEEP), + + /* GPP_C3 - SML0CLK */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + + /* GPP_C4 - SML0DATA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + + /* GPP_C5 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + + /* GPP_C6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C6, NONE), + + /* GPP_C7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C7, NONE), + + /* GPP_C8 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C8, 1, PLTRST), + + /* GPP_C9 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C9, 1, PLTRST), + + /* GPP_C10 - GPIO */ + /* DW0: 0x84000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C10, 0, PLTRST), + + /* GPP_C11 - GPIO */ + /* DW0: 0x40100103, DW1: 0x00000000 */ + PAD_CFG_GPI_APIC(GPP_C11, NONE, DEEP, LEVEL, NONE), + + /* GPP_C12 - UART1_RXD */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1), + + /* GPP_C13 - UART1_TXD */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + + /* GPP_C14 - UART1_RTS# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + + /* GPP_C15 - UART1_CTS# */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C15, NONE, PLTRST, NF1), + + /* GPP_C16 - I2C0_SDA */ + /* DW0: 0x84000402, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), + + /* GPP_C17 - I2C0_SCL */ + /* DW0: 0x84000402, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), + + /* GPP_C18 - I2C1_SDA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + + /* GPP_C19 - I2C1_SCL */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + + /* GPP_C20 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C20, NONE), + + /* GPP_C21 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C21, NONE), + + /* GPP_C22 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C22, 1, PLTRST), + + /* GPP_C23 - GPIO */ + /* DW0: 0x40100102, DW1: 0x00001000 */ + PAD_CFG_GPI_APIC(GPP_C23, DN_20K, DEEP, LEVEL, NONE), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E0 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_E0, NONE), + + /* GPP_E1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_E1, NONE), + + /* GPP_E2 - SATAXPCIE2 */ + /* DW0: 0x84000502, DW1: 0x00003000 */ + PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1), + + /* GPP_E3 - GPIO */ + /* DW0: 0x82040102, DW1: 0x00000000 */ + PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE), + + /* GPP_E4 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E4, 1, PLTRST), + + /* GPP_E5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_E5, NONE), + + /* GPP_E6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_E6, NONE), + + /* GPP_E7 - GPIO */ + /* DW0: 0x82000102, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, EDGE_SINGLE, ACPI), + + /* GPP_E8 - SATALED# */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + + /* GPP_E9 - RESERVED */ + /* DW0: 0x44001700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF5), + + /* GPP_E10 - RESERVED */ + /* DW0: 0x44001700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF5), + + /* GPP_E11 - USB2_OC2# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + + /* GPP_E12 - USB2_OC3# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + /* GPP_E13 - DDPB_HPD0 */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + + /* GPP_E14 - DDPC_HPD1 */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* GPP_E15 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E15, 1, PLTRST), + + /* GPP_E16 - GPIO */ + /* DW0: 0x80880102, DW1: 0x00003000 */ + PAD_CFG_GPI_SCI(GPP_E16, UP_20K, PLTRST, LEVEL, INVERT), + + /* GPP_E17 - EDP_HPD */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + + /* GPP_E18 - DPPB_CTRLCLK */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + + /* GPP_E19 - DPPB_CTRLDATA */ + /* DW0: 0x44000602, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + + /* GPP_E20 - DPPC_CTRLCLK */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + + /* GPP_E21 - DPPC_CTRLDATA */ + /* DW0: 0x44000602, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + + /* GPP_E22 - DPPD_CTRLCLK */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E22, NONE, PLTRST, NF1), + + /* GPP_E23 - DPPD_CTRLDATA */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E23, NONE, PLTRST, NF1), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/purism/librem_cml/variants/librem_mini/hda_verb.c b/src/mainboard/purism/librem_cml/variants/librem_mini/hda_verb.c new file mode 100644 index 0000000..c3daf3c --- /dev/null +++ b/src/mainboard/purism/librem_cml/variants/librem_mini/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor/Device ID: Realtek ALC293 */ + 0x10ec0000, /* Subsystem ID */ + 11, /* Number of entries */ + + AZALIA_SUBVENDOR(0, 0x10ec0000), + AZALIA_PIN_CFG(0, 0x12, 0x40000000), + AZALIA_PIN_CFG(0, 0x15, 0x01214010), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19130), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40422201), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + 0x8086280b, /* Codec Vendor/Device ID: Intel CannonPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/purism/librem_cml/variants/librem_mini/include/variant/gpio.h b/src/mainboard/purism/librem_cml/variants/librem_mini/include/variant/gpio.h new file mode 100644 index 0000000..9094b04 --- /dev/null +++ b/src/mainboard/purism/librem_cml/variants/librem_mini/include/variant/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +const struct pad_config *variant_gpio_table(size_t *num); + +#endif diff --git a/src/mainboard/purism/librem_cml/variants/librem_mini/include/variant/variant.h b/src/mainboard/purism/librem_cml/variants/librem_mini/include/variant/variant.h new file mode 100644 index 0000000..ee104c8 --- /dev/null +++ b/src/mainboard/purism/librem_cml/variants/librem_mini/include/variant/variant.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_H +#define VARIANT_H + +#include <soc/romstage.h> + +void variant_memory_init_params(FSP_M_CONFIG *mem_cfg); + +#endif diff --git a/src/mainboard/purism/librem_cml/variants/librem_mini/variant.c b/src/mainboard/purism/librem_cml/variants/librem_mini/variant.c new file mode 100644 index 0000000..aaea8a4 --- /dev/null +++ b/src/mainboard/purism/librem_cml/variants/librem_mini/variant.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <variant/variant.h> + +void variant_memory_init_params(FSP_M_CONFIG *mem_cfg) +{ + /* Enable and set SATA HSIO adjustments for ports 0 and 2 */ + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 2; + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[2] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I856bb914941211cfbec4fed871ba2a5a038e23c3 Gerrit-Change-Number: 46984 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020