coreboot-gerrit October 2020

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Change in coreboot[master]: Documentation/releases: Add ASan to 4.13 relnotes
by Harshit Sharma (Code Review) 11 Nov '20

11 Nov '20

Harshit Sharma has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45118 ) Change subject: Documentation/releases: Add ASan to 4.13 relnotes ...................................................................... Documentation/releases: Add ASan to 4.13 relnotes Change-Id: I2953729c69dfcfa8b34192b3e1623fdfad87ca3a Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com> --- M Documentation/releases/coreboot-4.13-relnotes.md 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/45118/1 diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md index dcc8bf4..388d291 100644 --- a/Documentation/releases/coreboot-4.13-relnotes.md +++ b/Documentation/releases/coreboot-4.13-relnotes.md @@ -49,4 +49,13 @@ CPU threads as possible limited only by SMRAM space and not by 64K. By default this loader version is disabled. Please see cpu/x86/Kconfig for more info. +### Address Sanitizer + +coreboot now has an in-built Address Sanitizer, a runtime memory debugger +designed to find out-of-bounds access and use-after-scope bugs. It is made +available on all x86 platforms in ramstage and on QEMU i440fx, Intel Apollo +Lake, and Haswell in romstage. Further, it can be enabled in romstage on other +x86 platforms as well. Refer [ASan documentation](../technotes/asan.md) for +more info. + ### Add significant changes here -- To view, visit https://review.coreboot.org/c/coreboot/+/45118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2953729c69dfcfa8b34192b3e1623fdfad87ca3a Gerrit-Change-Number: 45118 Gerrit-PatchSet: 1 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint/sata.c: Simplify RMW operations
by Angel Pons (Code Review) 11 Nov '20

11 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47030 ) Change subject: sb/intel/lynxpoint/sata.c: Simplify RMW operations ...................................................................... sb/intel/lynxpoint/sata.c: Simplify RMW operations Introduce the `sir_unset_and_set_mask` helper and update the one PCI read-modify-write operation that is somehow not reproducible. Change-Id: I30ad6ef8ad97ee0a8dc2297fba5bbbfe24f00f1c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/sata.c 1 file changed, 13 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/47030/1 diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index d0aaa99..4174e1f 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -25,10 +25,17 @@ pci_write_config32(dev, SATA_SIRD, value); } +static inline void sir_unset_and_set_mask(struct device *dev, int idx, u32 unset, u32 set) +{ + pci_write_config32(dev, SATA_SIRI, idx); + + const u32 value = pci_read_config32(dev, SATA_SIRD) & ~unset; + pci_write_config32(dev, SATA_SIRD, value | set); +} + static void sata_init(struct device *dev) { u32 reg32; - u16 reg16; u32 *abar; @@ -70,10 +77,7 @@ pci_write_config32(dev, IDE_CONFIG, reg32); /* for AHCI, Port Enable is managed in memory mapped space */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= 0x8000 | config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); + pci_update_config16(dev, 0x92, ~0x3f, 0x8000 | config->sata_port_map); udelay(2); /* Setup register 98h */ @@ -174,25 +178,16 @@ sir_write(dev, 0x64, 0x883c9001); /* Step 2: SIR 68h[15:0] = 880Ah */ - reg32 = sir_read(dev, 0x68); - reg32 &= 0xffff0000; - reg32 |= 0x880a; - sir_write(dev, 0x68, reg32); + sir_unset_and_set_mask(dev, 0x68, 0xffff, 0x880a); /* Step 3: SIR 60h[3] = 1 */ - reg32 = sir_read(dev, 0x60); - reg32 |= (1 << 3); - sir_write(dev, 0x60, reg32); + sir_unset_and_set_mask(dev, 0x60, 0, 1 << 3); /* Step 4: SIR 60h[0] = 1 */ - reg32 = sir_read(dev, 0x60); - reg32 |= (1 << 0); - sir_write(dev, 0x60, reg32); + sir_unset_and_set_mask(dev, 0x60, 0, 1 << 0); /* Step 5: SIR 60h[1] = 1 */ - reg32 = sir_read(dev, 0x60); - reg32 |= (1 << 1); - sir_write(dev, 0x60, reg32); + sir_unset_and_set_mask(dev, 0x60, 0, 1 << 1); /* Clock Gating */ sir_write(dev, 0x70, 0x3f00bf1f); -- To view, visit https://review.coreboot.org/c/coreboot/+/47030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ad6ef8ad97ee0a8dc2297fba5bbbfe24f00f1c Gerrit-Change-Number: 47030 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: mt8192/mcupm.c: use load_blob_file to load the blob file
by Yidi Lin (Code Review) 11 Nov '20

11 Nov '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46931 ) Change subject: mt8192/mcupm.c: use load_blob_file to load the blob file ...................................................................... mt8192/mcupm.c: use load_blob_file to load the blob file Use load_blob_file to load the blob file. TEST=1. emerge-asurada coreboot chromeos-bootimage; 2. See following log during booting. load_blob_file: Load mcupm.bin in 35 msecs, size 115668 bytes 3. Test suspend/resume by: a. suspend (on DUT): echo mem > /sys/power/stat b. resume (on host): dut-control power_state:on Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I871cb3486ddf1346cf1aad16057192aa769918db --- M src/soc/mediatek/mt8192/mcupm.c 1 file changed, 4 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46931/1 diff --git a/src/soc/mediatek/mt8192/mcupm.c b/src/soc/mediatek/mt8192/mcupm.c index 9391b05..df4111f 100644 --- a/src/soc/mediatek/mt8192/mcupm.c +++ b/src/soc/mediatek/mt8192/mcupm.c @@ -1,31 +1,22 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/barrier.h> -#include <cbfs.h> #include <console/console.h> #include <device/mmio.h> #include <soc/mcupm.h> -#include <string.h> +#include <soc/mtlib_common.h> #define ABNORMALBOOT_REG (0x0C55FAA0) -#define BUF_SIZE (128 * KiB) -static uint8_t mcupm_bin[BUF_SIZE] __aligned(8); +#define MCUPM_BLOB_FILE "mcupm.bin" void mcupm_init(void) { - const char *file_name = "mcupm.bin"; - size_t fw_size = cbfs_boot_load_file(file_name, - mcupm_bin, - sizeof(mcupm_bin), - CBFS_TYPE_RAW); - - if (fw_size == 0) - die("MCUPM file :mcupm.bin not found."); + if (load_blob_file(MCUPM_BLOB_FILE, MCUPM_SRAM_BASE)) + die("MCUPM file :%s not found.", MCUPM_BLOB_FILE); write32(&mt8192_mcupm->sw_rstn, 0x0); /* Clear abnormal boot register */ write32((void *)ABNORMALBOOT_REG, 0x0); - memcpy((void *)MCUPM_SRAM_BASE, mcupm_bin, fw_size); /* Memory barrier to ensure that all fw code is loaded * before we release the reset pin. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I871cb3486ddf1346cf1aad16057192aa769918db Gerrit-Change-Number: 46931 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: DO-NOT-SUBMIT: ignore changes under 3rdparty folder
by Yidi Lin (Code Review) 11 Nov '20

11 Nov '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46412 ) Change subject: DO-NOT-SUBMIT: ignore changes under 3rdparty folder ...................................................................... DO-NOT-SUBMIT: ignore changes under 3rdparty folder Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I1651e27f2875647d9cd1b50c6520c7c8c74f2488 --- M .gitmodules M 3rdparty/amd_blobs M 3rdparty/blobs M 3rdparty/intel-microcode M 3rdparty/qc_blobs 5 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/46412/1 diff --git a/.gitmodules b/.gitmodules index 4350a2c..626bf52 100644 --- a/.gitmodules +++ b/.gitmodules @@ -2,7 +2,7 @@ path = 3rdparty/blobs url = ../blobs.git update = none - ignore = dirty + ignore = all [submodule "util/nvidia-cbootimage"] path = util/nvidia/cbootimage url = ../nvidia-cbootimage.git @@ -25,7 +25,7 @@ path = 3rdparty/fsp url = ../fsp.git update = none - ignore = dirty + ignore = all [submodule "opensbi"] path = 3rdparty/opensbi url = ../opensbi.git @@ -33,7 +33,7 @@ path = 3rdparty/intel-microcode url = ../intel-microcode.git update = none - ignore = dirty + ignore = all [submodule "3rdparty/ffs"] path = 3rdparty/ffs url = ../ffs.git @@ -41,7 +41,7 @@ path = 3rdparty/amd_blobs url = ../amd_blobs update = none - ignore = dirty + ignore = all [submodule "3rdparty/cmocka"] path = 3rdparty/cmocka url = ../cmocka.git @@ -50,7 +50,7 @@ path = 3rdparty/qc_blobs url = ../qc_blobs.git update = none - ignore = dirty + ignore = all [submodule "3rdparty/intel-sec-tools"] path = 3rdparty/intel-sec-tools url = ../9esec-security-tooling.git diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index e393a88..335f577 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit e393a885c89f8ee3f05242a9e42578c60931b49d +Subproject commit 335f577697f7d27353a84b8a156a67a1dbad255f diff --git a/3rdparty/blobs b/3rdparty/blobs index 1aff9c3..96ae35c 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 1aff9c32eb15fc0e9da2f389f9b77e06d6fd3a21 +Subproject commit 96ae35c462d903d6940d982e61bea697103b7af6 diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 0e4288f..ee319ae 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 0e4288f81f806620c65f70ee2bcf94b69d574096 +Subproject commit ee319ae7bc59e88b60142f40a9ec1b46656de4db diff --git a/3rdparty/qc_blobs b/3rdparty/qc_blobs index 6b7fe49..11b212c 160000 --- a/3rdparty/qc_blobs +++ b/3rdparty/qc_blobs @@ -1 +1 @@ -Subproject commit 6b7fe498eb782b8f9758f28dd53bb0697be0d0b0 +Subproject commit 11b212c273b930885d1bee0b00a223a73628c852 -- To view, visit https://review.coreboot.org/c/coreboot/+/46412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1651e27f2875647d9cd1b50c6520c7c8c74f2488 Gerrit-Change-Number: 46412 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: HACK sdm845: Drag in all of the binary blobs
by T.Michael Turney (Code Review) 11 Nov '20

11 Nov '20

Hello T Michael Turney, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32450 to review the following change. Change subject: HACK sdm845: Drag in all of the binary blobs ...................................................................... HACK sdm845: Drag in all of the binary blobs This patch is a hack until licensing issues are resolved. There is a lot of ugliness in the Makefile.inc to allow build-bot to accept this patch without having access to the binary blobs required to run on Napali hardware. Change-Id: Ia7bd9fdc7295364c63366a6efe9a5c92db9b5b1a Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M src/soc/qualcomm/sdm845/Makefile.inc 1 file changed, 104 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/32450/1 diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc index 34064a1..8c64a2f 100644 --- a/src/soc/qualcomm/sdm845/Makefile.inc +++ b/src/soc/qualcomm/sdm845/Makefile.inc @@ -73,13 +73,117 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/sdm845/include CPPFLAGS_common += -Isrc/soc/qualcomm/common/include +SDM845_BLOB := $(top)/3rdparty/blobs/soc/qualcomm/sdm845 + BL31_MAKEARGS += PLAT=sdm845 ifeq ($(CONFIG_QC_SDI_ENABLE),y) BL31_MAKEARGS += DEBUG=1 endif +################################################################################ +ifeq ($(CONFIG_QC_SDI_ENABLE),y) +QCSDI_FILE := $(SDM845_BLOB)/QcSdi.elf +qcsdi_file := $(shell ls $(QCSDI_FILE)) +ifneq (,$(findstring $(QCSDI_FILE),$(qcsdi_file))) + QCSDI_CBFS := $(CONFIG_CBFS_PREFIX)/qcsdi + $(QCSDI_CBFS)-file := $(QCSDI_FILE) + $(QCSDI_CBFS)-type := stage + $(QCSDI_CBFS)-compression := none + cbfs-files-y += $(QCSDI_CBFS) +endif +endif + +################################################################################ +QCLIB_FILE := $(SDM845_BLOB)/QcLib.elf +qclib_file := $(shell ls $(QCLIB_FILE)) +ifneq (,$(findstring $(QCLIB_FILE),$(qclib_file))) + QCLIB_CBFS := $(CONFIG_CBFS_PREFIX)/qclib + $(QCLIB_CBFS)-file := $(QCLIB_FILE) + $(QCLIB_CBFS)-type := stage + $(QCLIB_CBFS)-compression := none + cbfs-files-y += $(QCLIB_CBFS) +endif + +################################################################################ +PMIC_FILE := $(SDM845_BLOB)/Pmic.bin +pmic_file := $(shell ls $(PMIC_FILE)) +ifneq (,$(findstring $(PMIC_FILE),$(pmic_file))) + PMIC_CBFS := $(CONFIG_CBFS_PREFIX)/pmiccfg + $(PMIC_CBFS)-file := $(PMIC_FILE) + $(PMIC_CBFS)-type := raw + $(PMIC_CBFS)-compression := none + cbfs-files-y += $(PMIC_CBFS) +endif + +################################################################################ +DCB_FILE := $(SDM845_BLOB)/6000_0200_1_dcb.bin +dcb_file := $(shell ls $(DCB_FILE)) +ifneq (,$(findstring $(DCB_FILE),$(dcb_file))) + DCB_CBFS := $(CONFIG_CBFS_PREFIX)/dcb + $(DCB_CBFS)-file := $(DCB_FILE) + $(DCB_CBFS)-type := raw + $(DCB_CBFS)-compression := none + cbfs-files-y += $(DCB_CBFS) +endif + +################################################################################ +AOP_FILE := $(SDM845_BLOB)/aop.mbn +aop_file := $(shell ls $(AOP_FILE)) +ifneq (,$(findstring $(AOP_FILE),$(aop_file))) + AOP_CBFS := $(CONFIG_CBFS_PREFIX)/aop + $(AOP_CBFS)-file := $(AOP_FILE) + $(AOP_CBFS)-type := payload + $(AOP_CBFS)-compression := $(CBFS_COMPRESS_FLAG) + cbfs-files-y += $(AOP_CBFS) +endif + +################################################################################ +UART_FW_FILE := $(SDM845_BLOB)/uart_fw.bin +uart_fw_file := $(shell ls $(UART_FW_FILE)) +ifneq (,$(findstring $(UART_FW_FILE),$(uart_fw_file))) + UART_FW_CBFS := $(CONFIG_CBFS_PREFIX)/uart_fw + $(UART_FW_CBFS)-file := $(UART_FW_FILE) + $(UART_FW_CBFS)-type := raw + $(UART_FW_CBFS)-compression := none + cbfs-files-y += $(UART_FW_CBFS) +endif + +################################################################################ +SPI_FW_FILE := $(SDM845_BLOB)/spi_fw.bin +spi_fw_file := $(shell ls $(SPI_FW_FILE)) +ifneq (,$(findstring $(SPI_FW_FILE),$(spi_fw_file))) + SPI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/spi_fw + $(SPI_FW_CBFS)-file := $(SPI_FW_FILE) + $(SPI_FW_CBFS)-type := raw + $(SPI_FW_CBFS)-compression := none + cbfs-files-y += $(SPI_FW_CBFS) +endif + +################################################################################ +I2C_FW_FILE := $(SDM845_BLOB)/i2c_fw.bin +i2c_fw_file := $(shell ls $(I2C_FW_FILE)) +ifneq (,$(findstring $(I2C_FW_FILE),$(i2c_fw_file))) + I2C_FW_CBFS := $(CONFIG_CBFS_PREFIX)/i2c_fw + $(I2C_FW_CBFS)-file := $(I2C_FW_FILE) + $(I2C_FW_CBFS)-type := raw + $(I2C_FW_CBFS)-compression := none + cbfs-files-y += $(I2C_FW_CBFS) +endif + +################################################################################ +QC_SEC_FILE := $(SDM845_BLOB)/qc_sec.mbn +qc_sec_file := $(shell ls $(QC_SEC_FILE)) +ifneq (,$(findstring $(QC_SEC_FILE),$(qc_sec_file))) +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.elf + @util/qualcomm/createxbl.py -f $(objcbfs)/bootblock.elf \ + -x $(QC_SEC_FILE) -o $(objcbfs)/merged_bb_qcsec.mbn \ + -a 64 -d 64 -c 64 + @util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \ + $(objcbfs)/bootblock.bin +else $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf "Generating: $(subst $(obj)/,,$(@))\n" cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin +endif endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7bd9fdc7295364c63366a6efe9a5c92db9b5b1a Gerrit-Change-Number: 32450 Gerrit-PatchSet: 1 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: sb/intel/lynxpoint/sata: Always use AHCI mode
by Angel Pons (Code Review) 11 Nov '20

11 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47022 ) Change subject: sb/intel/lynxpoint/sata: Always use AHCI mode ...................................................................... sb/intel/lynxpoint/sata: Always use AHCI mode The other two modes are not used by any mainboard, and the code seems to be copied from older southbridges. As the code looks incorrect, drop it. Change-Id: I374546279a85cead1aea13e0952bbfd6f643a75b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/devicetree.cb M src/mainboard/asrock/h81m-hds/devicetree.cb M src/mainboard/google/beltino/devicetree.cb M src/mainboard/google/slippy/devicetree.cb M src/mainboard/intel/baskingridge/devicetree.cb M src/mainboard/lenovo/t440p/devicetree.cb M src/mainboard/supermicro/x10slm-f/devicetree.cb M src/southbridge/intel/lynxpoint/chip.h M src/southbridge/intel/lynxpoint/sata.c 9 files changed, 79 insertions(+), 177 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/47022/1 diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb index e7dfa74..43a65f8 100644 --- a/src/mainboard/asrock/b85m_pro4/devicetree.cb +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -20,7 +20,6 @@ chip southbridge/intel/lynxpoint register "gen1_dec" = "0x000c0291" # Super I/O HWM - register "sata_ahci" = "1" register "sata_port_map" = "0x3f" device pci 14.0 on end # xHCI controller diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index cf73e39..7b08af9 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -28,7 +28,6 @@ end chip southbridge/intel/lynxpoint - register "sata_ahci" = "1" register "sata_port_map" = "0x33" register "gen1_dec" = "0x00000295" # Super I/O HWM diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index f9a56d7..8c54f6a 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -37,8 +37,6 @@ register "gpe0_en_3" = "0x00000000" register "gpe0_en_4" = "0x00000000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" register "sata_devslp_disable" = "0x1" diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 043ead6..382e83c 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -44,8 +44,6 @@ register "gpe0_en_3" = "0x00000000" register "gpe0_en_4" = "0x00000000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" register "sio_acpi_mode" = "1" diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index 6d2342e..37cff88 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -33,8 +33,6 @@ register "alt_gp_smi_en" = "0x0000" register "gpe0_en_1" = "0x4000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3f" # SuperIO range is 0x700-0x73f diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index 33ff903..7264df1 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -31,7 +31,6 @@ register "gen4_dec" = "0x000c06a1" register "gpi13_routing" = "2" register "gpi1_routing" = "2" - register "sata_ahci" = "1" # 0(HDD), 1(M.2), 5(ODD) register "sata_port_map" = "0x23" device pci 14.0 on end # xHCI Controller diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm-f/devicetree.cb index 3a0dfbe..6cd3ab7 100644 --- a/src/mainboard/supermicro/x10slm-f/devicetree.cb +++ b/src/mainboard/supermicro/x10slm-f/devicetree.cb @@ -19,7 +19,6 @@ device pci 03.0 off end # Mini-HD audio chip southbridge/intel/lynxpoint - register "sata_ahci" = "1" register "sata_port_map" = "0x3f" register "gen1_dec" = "0x00000295" # Super I/O HWM diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index 40d0460..89bbb1c 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -38,9 +38,7 @@ uint32_t gpe0_en_4; uint32_t alt_gp_smi_en; - /* IDE configuration */ - uint32_t ide_legacy_combined; - uint32_t sata_ahci; + /* SATA configuration */ uint8_t sata_port_map; uint32_t sata_port0_gen3_tx; uint32_t sata_port1_gen3_tx; diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 510440b..d0aaa99 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -29,6 +29,9 @@ { u32 reg32; u16 reg16; + + u32 *abar; + /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -45,170 +48,87 @@ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); + printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); - /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0); + /* Set Interrupt Line */ + /* Interrupt Pin is set by D31IP.PIP */ + pci_write_config8(dev, INTR_LN, 0x0a); - /* And without AHCI BAR no memory decoding */ - pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY); + /* Set timings */ + pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | + IDE_PPE0 | IDE_IE0 | IDE_TIME0); + pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config8(dev, 0x09, 0x80); + /* Sync DMA */ + pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); + pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); + /* Set IDE I/O Configuration */ + reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; + pci_write_config32(dev, IDE_CONFIG, reg32); - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); + /* for AHCI, Port Enable is managed in memory mapped space */ + reg16 = pci_read_config16(dev, 0x92); + reg16 &= ~0x3f; + reg16 |= 0x8000 | config->sata_port_map; + pci_write_config16(dev, 0x92, reg16); + udelay(2); - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); - - /* Port enable */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); - - /* SATA Initialization register */ - pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); - } else if (config->sata_ahci) { - u32 *abar; - - printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); - - /* Set Interrupt Line */ - /* Interrupt Pin is set by D31IP.PIP */ - pci_write_config8(dev, INTR_LN, 0x0a); - - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); - - /* for AHCI, Port Enable is managed in memory mapped space */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= 0x8000 | config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); - udelay(2); - - /* Setup register 98h */ - reg32 = pci_read_config16(dev, 0x98); - reg32 |= 1 << 19; /* BWG step 6 */ - reg32 |= 1 << 22; /* BWG step 5 */ - reg32 &= ~(0x3f << 7); - reg32 |= 0x04 << 7; /* BWG step 7 */ - reg32 |= 1 << 20; /* BWG step 8 */ - reg32 &= ~(0x03 << 5); - reg32 |= 1 << 5; /* BWG step 9 */ - reg32 |= 1 << 18; /* BWG step 10 */ - reg32 |= 1 << 29; /* BWG step 11 */ - if (pch_is_lp()) { - reg32 &= ~((1 << 31) | (1 << 30)); - reg32 |= 1 << 23; - reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ - } - pci_write_config32(dev, 0x98, reg32); - - /* Setup register 9Ch: Disable alternate ID and BWG step 12 */ - pci_write_config16(dev, 0x9c, 1 << 5); - - /* SATA Initialization register */ - reg32 = 0x183; - reg32 |= (config->sata_port_map ^ 0x3f) << 24; - reg32 |= (config->sata_devslp_mux & 1) << 15; - pci_write_config32(dev, 0x94, reg32); - - /* Initialize AHCI memory-mapped space */ - abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS - reg32 &= ~0x00020060; // clear SXS+EMS+PMS - if (pch_is_lp()) - reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY - write32(abar + 0x00, reg32); - /* PI (Ports implemented) */ - write32(abar + 0x03, config->sata_port_map); - (void)read32(abar + 0x03); /* Read back 1 */ - (void)read32(abar + 0x03); /* Read back 2 */ - /* CAP2 (HBA Capabilities Extended)*/ - reg32 = read32(abar + 0x09); - /* Enable DEVSLP */ - if (pch_is_lp()) { - if (config->sata_devslp_disable) - reg32 &= ~(1 << 3); - else - reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); - } else { - reg32 &= ~0x00000002; - } - write32(abar + 0x09, reg32); - } else { - printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); - - /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0); - - /* And without AHCI BAR no memory decoding */ - pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY); - - /* - * Native mode capable on both primary and secondary (0xa) - * or'ed with enabled (0x50) = 0xf - * - * FIXME: Does not match the code. - */ - pci_write_config8(dev, 0x09, 0x8f); - - /* Set Interrupt Line */ - /* Interrupt Pin is set by D31IP.PIP */ - pci_write_config8(dev, INTR_LN, 0xff); - - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_SITRE | IDE_ISP_3_CLOCKS | - IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); - - /* Port enable */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); - - /* SATA Initialization register */ - pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183); + /* Setup register 98h */ + reg32 = pci_read_config16(dev, 0x98); + reg32 |= 1 << 19; /* BWG step 6 */ + reg32 |= 1 << 22; /* BWG step 5 */ + reg32 &= ~(0x3f << 7); + reg32 |= 0x04 << 7; /* BWG step 7 */ + reg32 |= 1 << 20; /* BWG step 8 */ + reg32 &= ~(0x03 << 5); + reg32 |= 1 << 5; /* BWG step 9 */ + reg32 |= 1 << 18; /* BWG step 10 */ + reg32 |= 1 << 29; /* BWG step 11 */ + if (pch_is_lp()) { + reg32 &= ~((1 << 31) | (1 << 30)); + reg32 |= 1 << 23; + reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ } + pci_write_config32(dev, 0x98, reg32); + + /* Setup register 9Ch: Disable alternate ID and BWG step 12 */ + pci_write_config16(dev, 0x9c, 1 << 5); + + /* SATA Initialization register */ + reg32 = 0x183; + reg32 |= (config->sata_port_map ^ 0x3f) << 24; + reg32 |= (config->sata_devslp_mux & 1) << 15; + pci_write_config32(dev, 0x94, reg32); + + /* Initialize AHCI memory-mapped space */ + abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "ABAR: %p\n", abar); + /* CAP (HBA Capabilities) : enable power management */ + reg32 = read32(abar + 0x00); + reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS + reg32 &= ~0x00020060; // clear SXS+EMS+PMS + if (pch_is_lp()) + reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY + write32(abar + 0x00, reg32); + /* PI (Ports implemented) */ + write32(abar + 0x03, config->sata_port_map); + (void)read32(abar + 0x03); /* Read back 1 */ + (void)read32(abar + 0x03); /* Read back 2 */ + /* CAP2 (HBA Capabilities Extended)*/ + reg32 = read32(abar + 0x09); + /* Enable DEVSLP */ + if (pch_is_lp()) { + if (config->sata_devslp_disable) + reg32 &= ~(1 << 3); + else + reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); + } else { + reg32 &= ~0x00000002; + } + write32(abar + 0x09, reg32); /* Set Gen3 Transmitter settings if needed */ if (config->sata_port0_gen3_tx) @@ -291,7 +211,6 @@ { /* Get the chip configuration */ config_t *config = dev->chip_info; - u16 map = 0; if (!config) return; @@ -300,12 +219,7 @@ * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ - if (config->sata_ahci) - map = 0x0060; - - map |= (config->sata_port_map ^ 0x3f) << 8; - - pci_write_config16(dev, 0x90, map); + pci_write_config16(dev, 0x90, 0x0060 | (config->sata_port_map ^ 0x3f) << 8); } static struct device_operations sata_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/47022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I374546279a85cead1aea13e0952bbfd6f643a75b Gerrit-Change-Number: 47022 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/google/volteer: Disable Precision Time Management for NVMe
by Duncan Laurie (Code Review) 10 Nov '20

10 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46857 ) Change subject: mb/google/volteer: Disable Precision Time Management for NVMe ...................................................................... mb/google/volteer: Disable Precision Time Management for NVMe In order for runtime D3 support on NVMe it has been found that Prevision Time Management needs to be disabled for the PCIe root port 9. BUG=b:16099644 TEST=test RTD3 on NVMe on reworked volteer and delbin device Change-Id: Ie77494214bee136a65b5a343da310b9b320ba5b4 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/46857/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 2a62505..f47e29a 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -83,6 +83,7 @@ register "PcieRpLtrEnable[8]" = "1" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" + register "PciePtmDisable[8]" = "1" # Enable Optane PCIE 11 using clk 0 register "PcieRpEnable[10]" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/46857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie77494214bee136a65b5a343da310b9b320ba5b4 Gerrit-Change-Number: 46857 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: soc/intel/common/smbus: Add CannonPoint-H device
by Tim Crawford (Code Review) 10 Nov '20

10 Nov '20

Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46300 ) Change subject: soc/intel/common/smbus: Add CannonPoint-H device ...................................................................... soc/intel/common/smbus: Add CannonPoint-H device SMBus is required for initialization of the TAS5825M smart amp present on some Clevo laptops. Change-Id: I9fd425b199c17d11c49add504c645d9aa1aae122 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/soc/intel/common/block/smbus/smbus.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/46300/1 diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index ac8fefb..aa7ad2f 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -76,6 +76,7 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNL_SMBUS, + PCI_DEVICE_ID_INTEL_CNP_H_SMBUS, PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS, PCI_DEVICE_ID_INTEL_SPT_H_SMBUS, PCI_DEVICE_ID_INTEL_LWB_SMBUS_SUPER, -- To view, visit https://review.coreboot.org/c/coreboot/+/46300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fd425b199c17d11c49add504c645d9aa1aae122 Gerrit-Change-Number: 46300 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: tests: Add lib/edid-test test case
by Name of user not set (Code Review) 10 Nov '20

10 Nov '20

Name of user not set #1003143 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46817 ) Change subject: tests: Add lib/edid-test test case ...................................................................... tests: Add lib/edid-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I796e660eebc4d2c3c32207bd3a6ee44aaffeb325 --- A tests/include/lib/edid-test.h M tests/lib/Makefile.inc A tests/lib/edid-test.c M tests/stubs/console.c 4 files changed, 1,373 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/46817/1 diff --git a/tests/include/lib/edid-test.h b/tests/include/lib/edid-test.h new file mode 100644 index 0000000..073905d --- /dev/null +++ b/tests/include/lib/edid-test.h @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdlib.h> +#include <commonlib/bsd/helpers.h> + + +struct edid_raw { + uint8_t header[8]; + + /* Display product identification */ + uint16_t manufacturer_id; + uint16_t product_code; + uint32_t serial_number; + uint8_t manufacture_week; + uint8_t manufacture_year; + + /* EDID version information */ + uint8_t edid_version; + uint8_t edid_revision; + + /* Basic display parameters */ + uint8_t video_input_type; + uint8_t horizontal_size; /* [cm] */ + uint8_t vertical_size; /* [cm] */ + uint8_t display_gamma; + uint8_t supported_features; + + /* Color space definition */ + uint8_t color_characteristics[10]; + + /* Timing information */ + uint8_t established_supported_timings[2]; + uint8_t manufacturers_reserved_timing; + uint8_t standard_timings_supported[16]; + uint8_t descriptor_block_1[18]; + uint8_t descriptor_block_2[18]; + uint8_t descriptor_block_3[18]; + uint8_t descriptor_block_4[18]; + + /* Number of optional 128-byte extension blocks */ + uint8_t extension_flag; + + uint8_t checksum; +} __packed; + +_Static_assert(sizeof(struct edid_raw) == 128); + +#define EDID_HEADER_RAW { 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00 } +#define EDID_HEADER_INVALID_RAW { 0, 0, 0, 0, 0, 0, 0, 0 } + +#define EDID_MANUFACTURER_ID 0xcb55 +#define EDID_MANUFACTURER_NAME "UNK" +#define EDID_PRODUCT_CODE 0x1234 +#define EDID_SERIAL_NUMBER 0x56789ABC +#define EDID_MANUFACTURE_WEEK 23u +#define EDID_MANUFACTURE_NO_WEEK 0u +#define EDID_MANUFACTURE_YEAR (2015u - 1990u) + +/* Video Input Definition for Analog Video Signal Interface */ +#define EDID_ANALOG_VSI (0u << 7) +#define EDID_SIGNAL_LEVEL_0 0u +#define EDID_SIGNAL_LEVEL_1 (1u << 5) +#define EDID_SIGNAL_LEVEL_2 (2u << 5) +#define EDID_SIGNAL_LEVEL_3 (3u << 5) +#define EDID_VIDEO_SETUP_BLANK_EQ_BLACK 0u +#define EDID_VIDEO_SETUP_BLANK_TO_BLACK (1u << 4) +#define EDID_SEPARATE_SYNC_H_AND_V(v) ((v != 0 ? 0x1 : 0x0) << 3) +#define EDID_COMPOSITE_SYNC_H(v) ((v != 0 ? 0x1 : 0x0) << 2) +#define EDID_COMPOSITE_SYNC_ON_GREEN(v) ((v != 0 ? 0x1 : 0x0) << 1) +#define EDID_SERRATION_VSYNC(v) (v != 0 ? 0x1 : 0x0) + +/* Video Input Definition for Digital Video Signal Interface */ +#define EDID_DIGITAL_VSI (1u << 7) +#define EDID_COLOR_BIT_DEPTH_UNDEFINED 0u +#define EDID_COLOR_BIT_DEPTH_6B (1u << 4) +#define EDID_COLOR_BIT_DEPTH_8B (2u << 4) +#define EDID_COLOR_BIT_DEPTH_10B (3u << 4) +#define EDID_COLOR_BIT_DEPTH_12B (4u << 4) +#define EDID_COLOR_BIT_DEPTH_14B (5u << 4) +#define EDID_COLOR_BIT_DEPTH_16B (6u << 4) +#define EDID_INTERFACE_UNDEFINED 0u +#define EDID_INTERFACE_DVI 1u +#define EDID_INTERFACE_HDMI_A 2u +#define EDID_INTERFACE_HDMI_B 3u +#define EDID_INTERFACE_MDDI 4u +#define EDID_INTERFACE_DP 5u + +/* BEGIN Supported features */ +#define EDID_STANDBY_MODE(v) ((v != 0 ? 0x1 : 0x0) << 7) +#define EDID_SUSPEND_MODE(v) ((v != 0 ? 0x1 : 0x0) << 6) +#define EDID_ACTIVE_OFF(v) ((v != 0 ? 0x1 : 0x0) << 5) +/* For analog interface */ +#define EDID_COLOR_TYPE_MONO 0u +#define EDID_COLOR_TYPE_RGB (1u << 3) +#define EDID_COLOR_TYPE_NON_RGB (2u << 3) +#define EDID_COLOR_TYPE_UNDEFINED (3u << 3) +/* For digital interface */ +#define EDID_COLOR_FORMAT_RGB444 0u +#define EDID_COLOR_FORMAT_RGB444_YCRCB444 (1u << 3) +#define EDID_COLOR_FORMAT_RGB444_YCRCB422 (2u << 3) +#define EDID_COLOR_FORMAT_RGB444_YCRCB422_YCRCB422 (3u << 3) + +#define EDID_SRGB_SUPPORTED(v) (((v) == 0 ? 0u : 1u) << 2) +#define EDID_PREFERRED_TIMING_EXTENDED_INFO (1u << 1) +#define EDID_PREFERRED_TIMING_NO_EXTENDED_INFO 0u +#define EDID_DISPLAY_FREQUENCY_CONTINUOUS 1u +#define EDID_DISPLAY_FREQUENCY_NON_CONTINUOUS 0u +/* END Supported features */ + +/* Red X 0.640 */ +#define EDID_COLOR_R_X 0x25 +/* Red Y 0.330 */ +#define EDID_COLOR_R_Y 0x152 +/* Green X 0.300 */ +#define EDID_COLOR_G_X 0x13a +/* Green Y 0.600 */ +#define EDID_COLOR_G_Y 0x267 +/* Blue X 0.150 */ +#define EDID_COLOR_B_X 0x9a +/* Blue Y 0.060 */ +#define EDID_COLOR_B_Y 0x3e +/* White X 0.3125 */ +#define EDID_COLOR_W_X 0xa +/* White Y 0.3291 */ +#define EDID_COLOR_W_Y 0x22a + +/* 1 and 0 bits of each color */ +#define EDID_COLOR_R_X10_Y10 (((EDID_COLOR_R_X & 0x3) << 2) | (EDID_COLOR_R_Y & 0x3)) +#define EDID_COLOR_G_X10_Y10 (((EDID_COLOR_G_X & 0x3) << 2) | (EDID_COLOR_G_Y & 0x3)) +#define EDID_COLOR_B_X10_Y10 (((EDID_COLOR_B_X & 0x3) << 2) | (EDID_COLOR_B_Y & 0x3)) +#define EDID_COLOR_W_X10_Y10 (((EDID_COLOR_W_X & 0x3) << 2) | (EDID_COLOR_W_Y & 0x3)) + +/* Concatenated 0 and 1 bits of each color. To be put + * as first and second byte of color characteristic. */ +#define EDID_COLOR_RG_XY ((EDID_COLOR_R_X10_Y10 << 4) | EDID_COLOR_G_X10_Y10) +#define EDID_COLOR_BW_XY ((EDID_COLOR_B_X10_Y10 << 4) | EDID_COLOR_W_X10_Y10) + +/* Bits 9 through 2 of each color */ +#define EDID_COLOR_R_X92 (EDID_COLOR_R_X >> 2) +#define EDID_COLOR_R_Y92 (EDID_COLOR_R_Y >> 2) +#define EDID_COLOR_G_X92 (EDID_COLOR_G_X >> 2) +#define EDID_COLOR_G_Y92 (EDID_COLOR_G_Y >> 2) +#define EDID_COLOR_B_X92 (EDID_COLOR_B_X >> 2) +#define EDID_COLOR_B_Y92 (EDID_COLOR_B_Y >> 2) +#define EDID_COLOR_W_X92 (EDID_COLOR_W_X >> 2) +#define EDID_COLOR_W_Y92 (EDID_COLOR_W_Y >> 2) + +#define EDID_ESTABLISHED_TIMINGS_1_800x600_60Hz 1u +#define EDID_ESTABLISHED_TIMINGS_1_800x600_56Hz (1u << 1) +#define EDID_ESTABLISHED_TIMINGS_1_640x480_75Hz (1u << 2) +#define EDID_ESTABLISHED_TIMINGS_1_640x480_72Hz (1u << 3) +#define EDID_ESTABLISHED_TIMINGS_1_640x480_67Hz (1u << 4) +#define EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz (1u << 5) +#define EDID_ESTABLISHED_TIMINGS_1_720x400_88Hz (1u << 6) +#define EDID_ESTABLISHED_TIMINGS_1_720x400_70Hz (1u << 7) + +#define EDID_ESTABLISHED_TIMINGS_2_1280x1024_75Hz 1u +#define EDID_ESTABLISHED_TIMINGS_2_1024x768_75Hz (1u << 1) +#define EDID_ESTABLISHED_TIMINGS_2_1024x768_70Hz (1u << 2) +#define EDID_ESTABLISHED_TIMINGS_2_1024x768_60Hz (1u << 3) +#define EDID_ESTABLISHED_TIMINGS_2_1024x768_80HzI (1u << 4) +#define EDID_ESTABLISHED_TIMINGS_2_832x624_75Hz (1u << 5) +#define EDID_ESTABLISHED_TIMINGS_2_800x600_75Hz (1u << 6) +#define EDID_ESTABLISHED_TIMINGS_2_800x600_72Hz (1u << 7) + +#define EDID_MANUFACTURERS_TIMINGS_1152x870_75Hz (1u << 7) + +#define EDID_HORIZONTAL_ACCESSIBLE_PIXELS(px) (((px) / 8 - 31) & 0xFF) +#define EDID_ASPECT_RATIO_16_10 0u +#define EDID_ASPECT_RATIO_4_3 (1u << 6) +#define EDID_ASPECT_RATIO_5_4 (2u << 6) +#define EDID_ASPECT_RATIO_16_9 (3u << 6) +#define EDID_FIELD_REFRESH_RATE(hz) (((hz) - 60) & 0x1f) + +#define EDID_PIXEL_CLOCK(v) (((v) / 10000) & 0xFFFF) + +#define EDID_RAW_DEFAULT_PARAMS .header = EDID_HEADER_RAW, \ + .edid_version = 1, \ + .edid_revision = 4, \ + .manufacturer_id = EDID_MANUFACTURER_ID, \ + .product_code = EDID_PRODUCT_CODE, \ + .serial_number = EDID_SERIAL_NUMBER, \ + .manufacture_week = EDID_MANUFACTURE_NO_WEEK, \ + .manufacture_year = EDID_MANUFACTURE_YEAR, \ + .color_characteristics = { \ + EDID_COLOR_RG_XY, \ + EDID_COLOR_BW_XY, \ + EDID_COLOR_R_X92, \ + EDID_COLOR_R_Y92, \ + EDID_COLOR_G_X92, \ + EDID_COLOR_G_Y92, \ + EDID_COLOR_B_X92, \ + EDID_COLOR_B_Y92, \ + EDID_COLOR_W_X92, \ + EDID_COLOR_W_Y92, \ + } diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 3062bca..e3b1bb8 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -4,6 +4,7 @@ tests-y += b64_decode-test tests-y += hexstrtobin-test tests-y += imd-test +tests-y += edid-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -17,4 +18,8 @@ imd-test-srcs += tests/lib/imd-test.c imd-test-srcs += tests/stubs/console.c -imd-test-srcs += src/lib/imd.c \ No newline at end of file +imd-test-srcs += src/lib/imd.c +edid-test-srcs += tests/lib/edid-test.c +edid-test-srcs += src/lib/edid.c +edid-test-srcs += tests/stubs/console.c + diff --git a/tests/lib/edid-test.c b/tests/lib/edid-test.c new file mode 100644 index 0000000..5f320d3 --- /dev/null +++ b/tests/lib/edid-test.c @@ -0,0 +1,1155 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdlib.h> +#include <tests/test.h> +#include <edid.h> +#include <assert.h> +#include <string.h> +#include <lib/edid-test.h> + + +static uint8_t get_raw_edid_checksum(const unsigned char *x) +{ + unsigned char sum = 0; + int i; + for (i = 0; i < 127; ++i) + sum += x[i]; + + return 256 - sum; +} + +static void edid_raw_calc_checksum(struct edid_raw *raw) +{ + raw->checksum = get_raw_edid_checksum((const unsigned char *)raw); +} + +static void test_decode_edid_no_edid(void **state) +{ + assert_int_equal(EDID_ABSENT, decode_edid(NULL, 0, NULL)); +} + +static void test_decode_edid_invalid_header(void **state) +{ + struct edid_raw raw = { + .header = EDID_HEADER_INVALID_RAW + }; + raw.checksum = get_raw_edid_checksum((const unsigned char *)&raw); + + assert_int_equal(EDID_ABSENT, decode_edid((unsigned char *)&raw, sizeof(raw), NULL)); +} + +static void test_decode_edid_frame_1(void **state) +{ + struct edid out; + struct edid_raw raw = { + EDID_RAW_DEFAULT_PARAMS, + .video_input_type = EDID_ANALOG_VSI + | EDID_SIGNAL_LEVEL_0 + | EDID_VIDEO_SETUP_BLANK_EQ_BLACK + | EDID_SEPARATE_SYNC_H_AND_V(1) + | EDID_COMPOSITE_SYNC_H(1) + | EDID_COMPOSITE_SYNC_ON_GREEN(1) + | EDID_SERRATION_VSYNC(1), + .horizontal_size = 43, /* [cm] */ + .vertical_size = 32, /* [cm] */ + .display_gamma = 120, /* 220% */ + .supported_features = EDID_STANDBY_MODE(0) + | EDID_SUSPEND_MODE(0) + | EDID_ACTIVE_OFF(1) + | EDID_COLOR_FORMAT_RGB444 + | EDID_SRGB_SUPPORTED(0) + | EDID_PREFERRED_TIMING_EXTENDED_INFO + | EDID_DISPLAY_FREQUENCY_CONTINUOUS, + .established_supported_timings = { + [0] = EDID_ESTABLISHED_TIMINGS_1_720x400_70Hz + | EDID_ESTABLISHED_TIMINGS_1_720x400_88Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_67Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_72Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_75Hz + | EDID_ESTABLISHED_TIMINGS_1_800x600_56Hz + | EDID_ESTABLISHED_TIMINGS_1_800x600_60Hz, + [1] = EDID_ESTABLISHED_TIMINGS_2_800x600_72Hz + | EDID_ESTABLISHED_TIMINGS_2_800x600_75Hz + | EDID_ESTABLISHED_TIMINGS_2_832x624_75Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_80HzI + | EDID_ESTABLISHED_TIMINGS_2_1024x768_60Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_70Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_75Hz + | EDID_ESTABLISHED_TIMINGS_2_1280x1024_75Hz, + }, + .manufacturers_reserved_timing = EDID_MANUFACTURERS_TIMINGS_1152x870_75Hz, + .standard_timings_supported = { + [0] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1600), + [1] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85), + + [2] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1600), + [3] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(75), + + [4] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1600), + [5] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(70), + + [6] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1600), + [7] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(65), + + [8] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280), + [9] = EDID_ASPECT_RATIO_5_4 | EDID_FIELD_REFRESH_RATE(85), + + [10] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280), + [11] = EDID_ASPECT_RATIO_5_4 | EDID_FIELD_REFRESH_RATE(60), + + [12] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1024), + [13] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85), + + [14] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(800), + [15] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85), + }, + .descriptor_block_1 = { + [0] = EDID_PIXEL_CLOCK(162000000u) & 0xFF, + [1] = (EDID_PIXEL_CLOCK(162000000u) >> 8) & 0xFF, + + /* + * Horizontal Addressable Video is 1600px + * Horizontal Blanking is 560px + */ + [2] = 0x40, [3] = 0x30, [4] = 0x62, + + /* + * Vertical Addressable Video is 1200 lines + * Vertical Blanking is 50 lines + */ + [5] = 0xB0, [6] = 0x32, [7] = 0x40, + + [8] = 64u, /* Horizontal Front Porch in pixels */ + [9] = 192u, /* Horizontal Pulse Sync Width in pixels */ + [10] = 0x13, /* Vertical Front Porch is 1 line */ + [11] = 0x00, /* Vertical Sync Pulse Width is 3 lines */ + + /* + * Horizontal Addressable Image Size is 427mm + * Vertical Addressable Image Size is 320mm + */ + [12] = 0xAB, [13] = 0x40, [14] = 0x11, + + [15] = 0x00, /* Horizontal border size is 0px*/ + [16] = 0x00, /* Vertical Border Size is 0px */ + + /* + * Timing is Non-Interlaced Video, + * Stereo Video is not supported, + * Digital separate syncs are requires. + * */ + [17] = 0x1E, + }, + .descriptor_block_2 = { + /* Display Range Limits Block Tag */ + [0] = 0, [1] = 0, [2] = 0, [3] = 0xFD, + + [4] = 0, /* Horizontal and Vertical Rate Offsets are zero */ + [5] = 50u, /* Minimum Vertical Freq is 50Hz */ + [6] = 90u, /* Maximum Vertical Freq is 90Hz */ + + [7] = 30u, /* Minimum Horizontal Freq is 30kHz */ + [8] = 110u, /* Maximum Horizontal Freq is 110kHz */ + [9] = 23u, /* Maximum Pixel Clock Freq i 230MHz */ + [10] = 0x4, /* Begin CVT Support Info */ + [11] = 0x11, /* Compatible with CVT Version 1.1 */ + [12] = 0, /* Maimum Pixel Clock Freq remains at 230MHz */ + [13] = 200, /* Maximum Active Pixels per Pile is 1600 */ + [14] = 0x90, /* Supported aspect ratios: 4:3, 5:4 */ + + /* Preferred Aspect Ratio is 4:3, Standard CVT Blanking is supported */ + [15] = 0, + [16] = 0x50, /* H. & V. Stretch are supported and Shrinks are not */ + [17] = 60u, /* Preferred Refresh Rate is 60Hz */ + }, + .descriptor_block_3 = { + /* Established Timings III Block Tag */ + [0] = 0, [1] = 0, [2] = 0, [3] = 0xF7, [4] = 0, + + [5] = 10u, /* VESA DMT Standard Version #10 */ + /* + * 640x350@85Hz, + * 640x400@85Hz, + * 720x400@85Hz, + * 640x480@85Hz, + * 800x600@85Hz, + * 1024x768@85Hz, + * 1152x864@75Hz + */ + [6] = 0x7F, + + /* + * 1280x960@60Hz, + * 1280x960@85Hz, + * 1280x1024@60Hz, + * 1280x1024@85Hz + */ + [7] = 0x0F, + + /* + * 1400x1050@60Hz (Normal Blanking), + * 1400x1050@75Hz are supported. + */ + [8] = 0x03, + + /* + * 1400x1050@85Hz, + * 1600x1200@60Hz, + * 1600x1200@65Hz, + * 1600x1200@70Hz are supported. + */ + [9] = 0x87, + + /* + * 1600x1200@75Hz, + * 1600x1200@85Hz are supported. + */ + [10] = 0xC0, + + /* 1920 timings not supported */ + [11] = 0x0, + + [12 ... 17] = 0, + }, + .descriptor_block_4 = { + /* Display Product Name Block Tag */ + [0] = 0, [1] = 0, [2] = 0, [3] = 0xFC, [4] = 0, + + /* Product name */ + [5] = 'A', + [6] = 'B', + [7] = 'C', + [8] = ' ', + [9] = 'L', + [10] = 'C', + [11] = 'D', + [12] = '2', + [13] = '1', + [14] = '\n', + [15] = ' ', + [16] = ' ', + [17] = ' ', + }, + .extension_flag = 0x0, /* No extensions */ + }; + + edid_raw_calc_checksum(&raw); + + /* Only checking if frame is present. Don't care if is conformant. + * In real-life situations frames often are not 100% conformant, + * but are at least correct when it comes to key data fields. */ + assert_int_not_equal(EDID_ABSENT, + decode_edid((unsigned char *)&raw, + sizeof(struct edid_raw), + &out)); + + assert_int_equal(32, out.framebuffer_bits_per_pixel); + assert_int_equal(0, out.panel_bits_per_color); + assert_int_equal(0, out.panel_bits_per_pixel); + assert_int_equal(0, out.link_clock); + assert_int_equal(1600, out.x_resolution); + assert_int_equal(1200, out.y_resolution); + assert_int_equal(6400, out.bytes_per_line); + assert_int_equal(0, out.hdmi_monitor_detected); + assert_int_equal(0, strnlen(out.ascii_string, ARRAY_SIZE(out.ascii_string))); + assert_string_equal(out.manufacturer_name, EDID_MANUFACTURER_NAME); + + /* Mode */ + assert_null(out.mode.name); + assert_int_equal(162000, out.mode.pixel_clock); + assert_int_equal(1, out.mode.lvds_dual_channel); + assert_int_equal(0, out.mode.refresh); + assert_int_equal(1600, out.mode.ha); + assert_int_equal(560, out.mode.hbl); + assert_int_equal(64, out.mode.hso); + assert_int_equal(192, out.mode.hspw); + assert_int_equal(0, out.mode.hborder); + assert_int_equal(1200, out.mode.va); + assert_int_equal(50, out.mode.vbl); + assert_int_equal(1, out.mode.vso); + assert_int_equal(0, out.mode.vborder); + assert_int_equal(43, out.mode.phsync); + assert_int_equal(43, out.mode.pvsync); + assert_int_equal(0, out.mode.x_mm); + assert_int_equal(0, out.mode.y_mm); + + assert_int_equal(1, out.mode_is_supported[EDID_MODE_640x480_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_720x480_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_1280x720_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_1920x1080_60Hz]); +} + +static void test_decode_edid_frame_2(void **state) +{ + struct edid out; + unsigned char raw_data[128 * 2]; /* Frame with one extension */ + struct edid_raw raw = { + EDID_RAW_DEFAULT_PARAMS, + .video_input_type = EDID_DIGITAL_VSI + | EDID_INTERFACE_HDMI_A + | EDID_COLOR_BIT_DEPTH_8B, + .horizontal_size = 16, /* Aspect ratio 16:9 in landscape */ + .vertical_size = 0, /* Landscape flag */ + .display_gamma = 120, /* 220% */ + .supported_features = EDID_STANDBY_MODE(0) + | EDID_SUSPEND_MODE(0) + | EDID_ACTIVE_OFF(0) + | EDID_COLOR_FORMAT_RGB444_YCRCB422_YCRCB422 + | EDID_SRGB_SUPPORTED(1) + | EDID_PREFERRED_TIMING_EXTENDED_INFO + | EDID_DISPLAY_FREQUENCY_NON_CONTINUOUS, + + .established_supported_timings = { + [0] = EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz, + [1] = 0, + }, + .manufacturers_reserved_timing = 0, + .standard_timings_supported = { [0 ... 15] = 0, }, + .descriptor_block_1 = { + [0] = EDID_PIXEL_CLOCK(148500000u) & 0xFF, + [1] = (EDID_PIXEL_CLOCK(148500000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1920px + * Horizontal Blanking is 280px + */ + [2] = 0x80, [3] = 0x18, [4] = 0x71, + + /* Vertical Addressable Video is 1080 lines + * Vertical Blanking is 45 lines + */ + [5] = 0x38, [6] = 0x2D, [7] = 0x40, + + [8] = 88u, /* Horizontal Front Porch in pixels */ + [9] = 44u, /* Horizontal Pulse Sync Width in pixels */ + [10] = 4u, /* Vertical Front Porch is 4 lines */ + [11] = 5u, /* Vertical Sync Pulse Width is 5 lines */ + + /* Horizontal Addressable Image Size is 1039mm + * Vertical Addressable Image Size is 584mm + */ + [12] = 0x0F, [13] = 0x48, [14] = 0x42, + + [15] = 0x00, /* Horizontal border size is 0px*/ + [16] = 0x00, /* Vertical Border Size is 0px */ + + /* Timing is Non-Interlaced Video, + * Stereo Video is not supported, + * Digital separate and syncs are requires. + */ + [17] = 0x1E, + }, + .descriptor_block_2 = { + [0] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, + [1] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1920px + * Horizontal Blanking is 280px + */ + [2] = 0x80, [3] = 0x18, [4] = 0x71, + + /* Vertical Addressable Video is 540 lines + * Vertical Blanking is 22 lines + */ + [5] = 0x1C, [6] = 0x16, [7] = 0x20, + + [8] = 88u, /* Horizontal Front Porch in pixels */ + [9] = 44u, /* Horizontal Pulse Sync Width in pixels */ + [10] = 0x25, /* Vertical Front Porch is 2 lines */ + [11] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + + /* Horizontal Addressable Image Size is 1039mm + * Vertical Addressable Image Size is 584mm + */ + [12] = 0x0F, [13] = 0x48, [14] = 0x42, + + [15] = 0x00, /* Horizontal border size is 0px*/ + [16] = 0x00, /* Vertical Border Size is 0px */ + + /* Timing is Interlaced Video, + * Stereo Video is not supported, + * Digital separate and syncs are requires. + */ + [17] = 0x9E, + }, + .descriptor_block_3 = { + [0] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, + [1] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1280px + * Horizontal Blanking is 370px + */ + [2] = 0x00, [3] = 0x72, [4] = 0x51, + + /* Vertical Addressable Video is 720 lines + * Vertical Blanking is 30 lines + */ + [5] = 0xD0, [6] = 0x1E, [7] = 0x20, + + [8] = 110u, /* Horizontal Front Porch in pixels */ + [9] = 40u, /* Horizontal Pulse Sync Width in pixels */ + [10] = 0x55u, /* Vertical Front Porch is 5 lines */ + [11] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + + /* Horizontal Addressable Image Size is 1039mm + * Vertical Addressable Image Size is 584mm + */ + [12] = 0x0F, [13] = 0x48, [14] = 0x42, + + [15] = 0x00, /* Horizontal border size is 0px*/ + [16] = 0x00, /* Vertical Border Size is 0px */ + + /* Timing is Non-Interlaced Video, + * Stereo Video is not supported, + * Digital separate syncs are requires. + */ + [17] = 0x1E, + }, + .descriptor_block_4 = { + /* Display Product Name Block Tag */ + [0] = 0, [1] = 0, [2] = 0, [3] = 0xFC, [4] = 0, + + /* Product name */ + [5] = 'A', + [6] = 'B', + [7] = 'C', + [8] = ' ', + [9] = 'L', + [10] = 'C', + [11] = 'D', + [12] = '4', + [13] = '7', + [14] = 'w', + [15] = '\n', + [16] = ' ', + [17] = ' ', + }, + .extension_flag = 0x0, /* No extensions */ + }; + + edid_raw_calc_checksum(&raw); + + memcpy(raw_data, &raw, sizeof(raw)); + + unsigned char ext[128] = { + [0] = 0x02, /* CEA 861 Extension Block Tag Code */ + [1] = 0x03, /* CEA 861 Block Version */ + + [2] = 0x18, /* Detail Timing Descriptors start 0x18 bytes from here */ + + /* Underscan is not supported + * Basic Audio is supported + * YCbCr 4:4:4 & YCbCr 4:2:2 are supported + * Number of native formats: 2 + */ + [3] = 0x72, + + /* Video Data Block Tag Code is 2 + * Number of Short Video Descriptor Bytes i 7 + */ + [4] = 0x47, + + /* 1920x1080p 59.94/60 Hz 16 : 9 AR (CEA Format #16) + * is a supported Native Format. */ + [5] = 0x90, + + /* 1920x1080i 59.94/60 Hz 16 : 9 AR (CEA Format #5) + * is a supported Native Format. */ + [6] = 0x85, + + /* 1280x720p 59.94/60 Hz 16 : 9 AR (CEA Format #4) is a supported format. */ + [7] = 0x04, + + /* 720x480p 59.94/60 Hz 16 : 9 AR (CEA Format #3) is a supported format. */ + [8] = 0x03, + + /* 720x480p 59.94/60 Hz 4 : 3 AR (CEA Format #2) is a supported format. */ + [9] = 0x02, + + /* 720x480i 59.94/60 Hz 16 : 9 AR (CEA Format #7) is a supported format. */ + [10] = 0x07, + + /* 720x480i 59.94/60 Hz 4 : 3 AR (CEA Format #6) is a supported format. */ + [11] = 0x06, + + /* Audio Data Block Tag Code is 1. + * Number of Short Audio Descriptor Bytes is 3. + */ + [12] = 0x23, + + /* Audio Format Tag Code is 1 --- LPCM is supported. + * Maximum number of audio channels is 2 + */ + [13] = 0x09, + + /* Supported Sampling Frequencies include: 48kHz; 44.1kHz & 32kHz. */ + [14] = 0x07, + + /* Supported Sampling Bit Rates include: 24 bit; 20 bit & 16 bit. */ + [15] = 0x07, + + /* Speaker Allocation Block Tag Code is 4. + * Number of Speaker Allocation + * Descriptor Bytes is 3. + */ + [16] = 0x83, + + /* Speaker Allocation is Front-Left & Front-Right */ + [17] = 0x01, + + /* Reserved */ + [18 ... 19] = 0, + + /* Vendor Specific Data Block Tag Code is 3. + * Number of Vendor Specific Data Bytes is 5. + */ + [20] = 0x65, + + /* 24bit IEEE registration Identifier is 0x000C03 */ + [21] = 0x03, [22] = 0x0C, [23] = 0x00, + + /* Vendor Specific Data is 0x10000 */ + [24] = 0x01, [25] = 0x00, + + /* Descriptor Block 5 [18 Bytes] */ + + [26] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, + [27] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 720px. + * Horizontal Blanking is 138 px. + */ + [28] = 0xD0, [29] = 0x8A, [30] = 0x20, + + /* Vertical Addressable Video is 480 lines. + * Vertical Blanking is 45 lines. + */ + [31] = 0xE0, [32] = 0x2D, [33] = 0x10, + + [34] = 16u, /* Horizontal Front Porch in pixels */ + [35] = 62u, /* Horizontal Sync Pulse Width in pixels */ + [36] = 0x96, /* Vertical Front Porch is 9 lines */ + [37] = 0x00, /* Vertical Sync Pulse Width is 6 lines */ + + /* Displayed Image Aspect Ratio is 16:9 */ + [38] = 16u, [39] = 9u, [40] = 0u, + + /* Horizontal and Vertical Border Size is 0 px */ + [41] = 0u, [42] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [43] = 0x18, + + /* Descriptor Block 6 [18 Bytes] */ + + [44] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, + [45] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 720px. + * Horizontal Blanking is 138 px. + */ + [46] = 0xD0, [47] = 0x8A, [48] = 0x20, + + /* Vertical Addressable Video is 480 lines. + * Vertical Blanking is 45 lines. + */ + [49] = 0xE0, [50] = 0x2D, [51] = 0x10, + + [52] = 16u, /* Horizontal Front Porch in pixels */ + [53] = 62u, /* Horizontal Sync Pulse Width in pixels */ + [54] = 0x96, /* Vertical Front Porch is 9 lines */ + [55] = 0x00, /* Vertical Sync Pulse Width is 6 lines */ + + /* Displayed Image Aspect Ratio is 4:3 */ + [56] = 4u, [57] = 3u, [58] = 0u, + + /* Horizontal and Vertical Border Size is 0 px */ + [59] = 0u, [60] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [61] = 0x18, + + /* Descriptor Block 7 [18 Bytes] */ + + [62] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, + [63] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1440px. + * Horizontal Blanking is 276 px. + */ + [64] = 0xA0, [65] = 0x14, [66] = 0x51, + + /* Vertical Addressable Video is 240 lines. + * Vertical Blanking is 23 lines. + */ + [67] = 0xF0, [68] = 0x16, [69] = 0x00, + + [70] = 38u, /* Horizontal Front Porch in pixels */ + [71] = 124u, /* Horizontal Sync Pulse Width in pixels */ + [72] = 0x43, /* Vertical Front Porch is 9 lines */ + [73] = 0x00, /* Vertical Sync Pulse Width is 6 lines */ + + /* Displayed Image Aspect Ratio is 16:9 */ + [74] = 16u, [75] = 9u, [76] = 0u, + + /* Horizontal and Vertical Border Size is 0 px */ + [77] = 0u, [78] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [79] = 0x98, + + /* Descriptor Block 8 [18 Bytes] */ + + [80] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, + [81] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1440px. + * Horizontal Blanking is 276 px. + */ + [82] = 0xA0, [83] = 0x14, [84] = 0x51, + + /* Vertical Addressable Video is 240 lines. + * Vertical Blanking is 23 lines. + */ + [85] = 0xF0, [86] = 0x16, [87] = 0x00, + + [88] = 38u, /* Horizontal Front Porch in pixels */ + [89] = 124u, /* Horizontal Sync Pulse Width in pixels */ + [90] = 0x43, /* Vertical Front Porch is 9 lines */ + [91] = 0x00, /* Vertical Sync Pulse Width is 6 lines */ + + /* Displayed Image Aspect Ratio is 4:3 */ + [92] = 4u, [93] = 3u, [94] = 0u, + + /* Horizontal and Vertical Border Size is 0 px */ + [95] = 0u, [96] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [97] = 0x98, + + [99 ... 126] = 0 + }; + + ext[127] = get_raw_edid_checksum(ext); + + memcpy(raw_data + sizeof(raw), ext, sizeof(ext)); + + /* Only checking if frame is present. Don't care if is conformant. + * In real-life situations frames often are not 100% conformant, + * but are at least correct when it comes to key data fields. */ + assert_int_not_equal(EDID_ABSENT, decode_edid(raw_data, sizeof(raw_data), &out)); + + assert_int_equal(32, out.framebuffer_bits_per_pixel); + assert_int_equal(8, out.panel_bits_per_color); + assert_int_equal(24, out.panel_bits_per_pixel); + assert_int_equal(0, out.link_clock); + assert_int_equal(1920, out.x_resolution); + assert_int_equal(1080, out.y_resolution); + assert_int_equal(7680, out.bytes_per_line); + assert_int_equal(1, out.hdmi_monitor_detected); + assert_int_equal(0, strnlen(out.ascii_string, ARRAY_SIZE(out.ascii_string))); + assert_string_equal(out.manufacturer_name, EDID_MANUFACTURER_NAME); + + /* Mode */ + assert_null(out.mode.name); + assert_int_equal(148500, out.mode.pixel_clock); + assert_int_equal(1, out.mode.lvds_dual_channel); + assert_int_equal(0, out.mode.refresh); + assert_int_equal(1920, out.mode.ha); + assert_int_equal(280, out.mode.hbl); + assert_int_equal(88, out.mode.hso); + assert_int_equal(44, out.mode.hspw); + assert_int_equal(0, out.mode.hborder); + assert_int_equal(1080, out.mode.va); + assert_int_equal(45, out.mode.vbl); + assert_int_equal(16, out.mode.vso); + assert_int_equal(0, out.mode.vborder); + assert_int_equal(43, out.mode.phsync); + assert_int_equal(43, out.mode.pvsync); + assert_int_equal(0, out.mode.x_mm); + assert_int_equal(0, out.mode.y_mm); + + assert_int_equal(1, out.mode_is_supported[EDID_MODE_640x480_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_720x480_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_1280x720_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_1920x1080_60Hz]); +} + +static void test_decode_edid_frame_3(void **state) +{ + struct edid out; + unsigned char raw_data[128 * 2]; /* Frame with one extension */ + struct edid_raw raw = { + EDID_RAW_DEFAULT_PARAMS, + .video_input_type = EDID_DIGITAL_VSI + | EDID_INTERFACE_HDMI_A + | EDID_COLOR_BIT_DEPTH_8B, + .horizontal_size = 121, /* Aspect ratio 16:9 in landscape */ + .vertical_size = 68, /* Landscape flag */ + .display_gamma = 120, /* 220% */ + .supported_features = EDID_STANDBY_MODE(0) + | EDID_SUSPEND_MODE(0) + | EDID_ACTIVE_OFF(0) + | EDID_COLOR_FORMAT_RGB444_YCRCB422_YCRCB422 + | EDID_SRGB_SUPPORTED(1) + | EDID_PREFERRED_TIMING_EXTENDED_INFO + | EDID_DISPLAY_FREQUENCY_NON_CONTINUOUS, + .established_supported_timings = { + [0] = EDID_ESTABLISHED_TIMINGS_1_800x600_60Hz + | EDID_ESTABLISHED_TIMINGS_1_800x600_56Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_75Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_72Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_67Hz + | EDID_ESTABLISHED_TIMINGS_1_640x480_60Hz + | EDID_ESTABLISHED_TIMINGS_1_720x400_88Hz + | EDID_ESTABLISHED_TIMINGS_1_720x400_70Hz, + [1] = EDID_ESTABLISHED_TIMINGS_2_1280x1024_75Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_75Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_70Hz + | EDID_ESTABLISHED_TIMINGS_2_1024x768_60Hz + | EDID_ESTABLISHED_TIMINGS_2_832x624_75Hz + | EDID_ESTABLISHED_TIMINGS_2_800x600_75Hz + | EDID_ESTABLISHED_TIMINGS_2_800x600_72Hz, + }, + .manufacturers_reserved_timing = EDID_MANUFACTURERS_TIMINGS_1152x870_75Hz, + .standard_timings_supported = { + [0] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280), + [1] = EDID_ASPECT_RATIO_5_4 | EDID_FIELD_REFRESH_RATE(85), + + [2] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280), + [3] = EDID_ASPECT_RATIO_5_4 | EDID_FIELD_REFRESH_RATE(60), + + [4] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280), + [5] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85), + + [6] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1280), + [7] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(60), + + [8] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(1024), + [9] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(85), + + [10] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(848), + [11] = EDID_ASPECT_RATIO_16_9 | EDID_FIELD_REFRESH_RATE(60), + + [12] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(800), + [13] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(60), + + [14] = EDID_HORIZONTAL_ACCESSIBLE_PIXELS(640), + [15] = EDID_ASPECT_RATIO_4_3 | EDID_FIELD_REFRESH_RATE(60), + }, + .descriptor_block_1 = { + [0] = EDID_PIXEL_CLOCK(85500000u) & 0xFF, + [1] = (EDID_PIXEL_CLOCK(85500000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1360px + * Horizontal Blanking is 432px + */ + [2] = 0x50, [3] = 0xB0, [4] = 0x51, + + /* Vertical Addressable Video is 768 lines + * Vertical Blanking is 27 lines + */ + [5] = 0x00, [6] = 0x1B, [7] = 0x30, + + [8] = 64u, /* Horizontal Front Porch in pixels */ + [9] = 112u, /* Horizontal Pulse Sync Width in pixels */ + [10] = 0x36, /* Vertical Front Porch is 3 lines */ + [11] = 0u, /* Vertical Sync Pulse Width is 6 lines */ + + /* Horizontal Addressable Image Size is 1214mm + * Vertical Addressable Image Size is 683mm + */ + [12] = 0xBE, [13] = 0xAB, [14] = 0x42, + + [15] = 0x00, /* Horizontal border size is 0px*/ + [16] = 0x00, /* Vertical Border Size is 0px */ + + /* Timing is Non-Interlaced Video, + * Stereo Video is not supported, + * Digital separate and syncs are requires. + */ + [17] = 0x1E, + }, + .descriptor_block_2 = { + [0] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, + [1] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1280px + * Horizontal Blanking is 370px + */ + [2] = 0x00, [3] = 0x72, [4] = 0x51, + + /* Vertical Addressable Video is 720 lines + * Vertical Blanking is 30 lines + */ + [5] = 0xD0, [6] = 0x1E, [7] = 0x20, + + [8] = 110u, /* Horizontal Front Porch in pixels */ + [9] = 40u, /* Horizontal Pulse Sync Width in pixels */ + [10] = 0x55, /* Vertical Front Porch is 5 lines */ + [11] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + + /* Horizontal Addressable Image Size is 1214mm + * Vertical Addressable Image Size is 683mm + */ + [12] = 0xBE, [13] = 0xAB, [14] = 0x42, + + [15] = 0x00, /* Horizontal border size is 0px*/ + [16] = 0x00, /* Vertical Border Size is 0px */ + + /* Timing is Non-Interlaced Video, + * Stereo Video is not supported, + * Digital separate and syncs are requires. + */ + [17] = 0x1E, + }, + .descriptor_block_3 = { + /* Established timings III Block Tag */ + [0 ... 2] = 0u, [3] = 0xF7, [4] = 0u, + + /* + * VESA DMT Standard Version #10 + */ + [5] = 10u, + + /* 640x350@85Hz, + * 640x400@85Hz, + * 720x400@85Hz, + * 640x480@85Hz, + * 800x600@85Hz, + * 1024x768@85Hz, + * 1152x864@75Hz are supported. + */ + [6] = 0x7F, + + /* 1280x960@60Hz, + * 1280x960@85Hz, + * 1280x1024@60Hz, + * 1280x1024@85Hz + */ + [7] = 0x0F, + + /* 1400x1050@60Hz (Normal Blanking), + * 1400x1050@75Hz are supported. + */ + [8] = 0x03, + + /* 1400x1050@85Hz, + * 1600x1200@60Hz, + * 1600x1200@65Hz, + * 1600x1200@70Hz are supported. + */ + [9] = 0x87, + + /* 1600x1200@75Hz, + * 1600x1200@85Hz are supported. + */ + [10] = 0xC0, + + /* 1920 PC Timings are not supported. */ + [11] = 0u, + + /* Reserved */ + [12 ... 17] = 0, + }, + .descriptor_block_4 = { + /* Display Product Name Block Tag */ + [0] = 0, [1] = 0, [2] = 0, [3] = 0xFC, [4] = 0, + + /* Product name */ + [5] = 'A', + [6] = 'B', + [7] = 'C', + [8] = ' ', + [9] = 'P', + [10] = 'L', + [11] = 'A', + [12] = '5', + [13] = '5', + [14] = '\n', + [15] = ' ', + [16] = ' ', + [17] = ' ', + }, + .extension_flag = 0x0, /* No extensions */ + }; + + edid_raw_calc_checksum(&raw); + + memcpy(raw_data, &raw, sizeof(raw)); + + unsigned char ext[128] = { + [0] = 0x02, /* CEA 861 Extension Block Tag Code */ + [1] = 0x03, /* CEA 861 Block Version */ + [2] = 0x17, /* Detail Timing Descriptors start 0x17 bytesfrom here */ + + /* Underscan is supported + * Basic Audio is supported + * YCbCr 4:4:4 & YCbCr 4:2:2 are supported + * Number of native formats: 0 + */ + [3] = 0xF0, + + /* Video Data Block Tag Code is 2 + * Number of Short Video Descriptor Bytes i 6 + */ + [4] = 0x46, + + /* 1920x1080i 59.94/60 Hz 16 : 9 AR (CEA Format #5) is a supported format. */ + [5] = 0x05, + + /* 1280x720p 59.94/60 Hz 16 : 9 AR (CEA Format #4) is a supported format. */ + [6] = 0x04, + + /* 720x480p 59.94/60 Hz 16 : 9 AR (CEA Format #3) is a supported format. */ + [7] = 0x03, + + /* 720x480p 59.94/60 Hz 4 : 3 AR (CEA Format #2) is a supported format. */ + [8] = 0x02, + + /* 720x480i 59.94/60 Hz 16 : 9 AR (CEA Format #7) is a supported format. */ + [9] = 0x07, + + /* 720x480i 59.94/60 Hz 4 : 3 AR (CEA Format #6) is a supported format. */ + [10] = 0x06, + + /* Audio Data Block Tag Code is 1. + * Number of Short Audio Descriptor Bytes is 3. + */ + [11] = 0x23, + + /* Audio Format Tag Code is 1 --- LPCM is supported. + * Maximum number of audio channels is 2 + */ + [12] = 0x09, + + /* Supported Sampling Frequencies include: 48kHz; 44.1kHz & 32kHz. */ + [13] = 0x07, + + /* Supported Sampling Bit Rates include: 24 bit; 20 bit & 16 bit. */ + [14] = 0x07, + + /* Speaker Allocation Block Tag Code is 4. + * Number of Speaker Allocation + * Descriptor Bytes is 3. + */ + [15] = 0x83, + + /* Speaker Allocation is Front-Left & Front-Right */ + [16] = 0x01, + + /* Reserved */ + [17 ... 18] = 0, + + /* Vendor Specific Data Block Tag Code is 3. + * Number of Vendor Specific Data Bytes is 5. + */ + [19] = 0x65, + + /* 24bit IEEE registration Identifier is 0x000C03 */ + [20] = 0x03, [21] = 0x0C, [22] = 0x00, + + /* Vendor Specific Data is 0x10000 */ + [23] = 0x01, [24] = 0x00, + + /* Descriptor Block 5 [18 Bytes] */ + + [25] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, + [26] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1920px. + * Horizontal Blanking is 280px. + */ + [27] = 0x80, [28] = 0x18, [29] = 0x71, + + /* Vertical Addressable Video is 540 lines. + * Vertical Blanking is 22 lines. + */ + [30] = 0x1C, [31] = 0x16, [32] = 0x20, + + [33] = 88u, /* Horizontal Front Porch in pixels */ + [34] = 44u, /* Horizontal Sync Pulse Width in pixels */ + [35] = 0x25, /* Vertical Front Porch is 2 lines */ + [36] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + + /* Image size: 1039mm x 584mm */ + [37] = 0x0F, [38] = 0x48, [39] = 0x42, + + /* Horizontal and Vertical Border Size is 0 px */ + [40] = 0u, [41] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [42] = 0x9E, + + /* Descriptor Block 6 [18 Bytes] */ + + [43] = EDID_PIXEL_CLOCK(74250000u) & 0xFF, + [44] = (EDID_PIXEL_CLOCK(74250000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1280px. + * Horizontal Blanking is 370 px. + */ + [45] = 0x00, [46] = 0x72, [47] = 0x51, + + /* Vertical Addressable Video is 720 lines. + * Vertical Blanking is 30 lines. + */ + [48] = 0xD0, [49] = 0x1E, [50] = 0x20, + + [51] = 110u, /* Horizontal Front Porch in pixels */ + [52] = 40u, /* Horizontal Sync Pulse Width in pixels */ + [53] = 0x55, /* Vertical Front Porch is 5 lines */ + [54] = 0x00, /* Vertical Sync Pulse Width is 5 lines */ + + /* Image size: 1039mm x 584mm */ + [55] = 0x0F, [56] = 0x48, [57] = 0x42, + + /* Horizontal and Vertical Border Size is 0 px */ + [58] = 0u, [59] = 0u, + + /* Timing is Non-Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [60] = 0x1E, + + /* Descriptor Block 7 [18 Bytes] */ + + [61] = EDID_PIXEL_CLOCK(27000000u) & 0xFF, + [62] = (EDID_PIXEL_CLOCK(27000000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1440px. + * Horizontal Blanking is 276 px. + */ + [63] = 0xA0, [64] = 0x14, [65] = 0x51, + + /* Vertical Addressable Video is 240 lines. + * Vertical Blanking is 23 lines. + */ + [66] = 0xF0, [67] = 0x16, [68] = 0x00, + + [69] = 38u, /* Horizontal Front Porch in pixels */ + [70] = 124u, /* Horizontal Sync Pulse Width in pixels */ + [71] = 0x43, /* Vertical Front Porch is 4 lines */ + [72] = 0x00, /* Vertical Sync Pulse Width is 3 lines */ + + /* Image size: 1039mm x 584mm */ + [73] = 0x0F, [74] = 0x48, [75] = 0x42, + + /* Horizontal and Vertical Border Size is 0 px */ + [76] = 0u, [77] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [78] = 0x18, + + /* Descriptor Block 8 [18 Bytes] */ + + [79] = EDID_PIXEL_CLOCK(27027000u) & 0xFF, + [80] = (EDID_PIXEL_CLOCK(27027000u) >> 8) & 0xFF, + + /* Horizontal Addressable Video is 1440px. + * Horizontal Blanking is 276 px. + */ + [81] = 0xA0, [82] = 0x14, [83] = 0x51, + + /* Vertical Addressable Video is 240 lines. + * Vertical Blanking is 23 lines. + */ + [84] = 0xF0, [85] = 0x16, [86] = 0x00, + + [87] = 38u, /* Horizontal Front Porch in pixels */ + [88] = 124u, /* Horizontal Sync Pulse Width in pixels */ + [89] = 0x43, /* Vertical Front Porch is 4 lines */ + [90] = 0x00, /* Vertical Sync Pulse Width is 3 lines */ + + /* Image size: 1039mm x 584mm */ + [91] = 0x0F, [92] = 0x48, [93] = 0x42, + + /* Horizontal and Vertical Border Size is 0 px */ + [94] = 0u, [95] = 0u, + + /* Timing is Interlaced Video + * Stereo Video is not supported + * Digital Separate Syncs are required + */ + [96] = 0x98, + + [97 ... 126] = 0, + }; + + ext[127] = get_raw_edid_checksum(ext); + + memcpy(raw_data + sizeof(raw), ext, sizeof(ext)); + + /* Only checking if frame is present. Don't care if is conformant. + * In real-life situations frames often are not 100% conformant, + * but are at least correct when it comes to key data fields. */ + assert_int_not_equal(EDID_ABSENT, decode_edid(raw_data, sizeof(raw_data), &out)); + + assert_int_equal(32, out.framebuffer_bits_per_pixel); + assert_int_equal(8, out.panel_bits_per_color); + assert_int_equal(24, out.panel_bits_per_pixel); + assert_int_equal(0, out.link_clock); + assert_int_equal(1360, out.x_resolution); + assert_int_equal(768, out.y_resolution); + assert_int_equal(5440, out.bytes_per_line); + assert_int_equal(1, out.hdmi_monitor_detected); + assert_int_equal(0, strnlen(out.ascii_string, ARRAY_SIZE(out.ascii_string))); + assert_string_equal(out.manufacturer_name, EDID_MANUFACTURER_NAME); + + /* Mode */ + assert_null(out.mode.name); + assert_int_equal(85500, out.mode.pixel_clock); + assert_int_equal(0, out.mode.lvds_dual_channel); + assert_int_equal(0, out.mode.refresh); + assert_int_equal(1360, out.mode.ha); + assert_int_equal(432, out.mode.hbl); + assert_int_equal(64, out.mode.hso); + assert_int_equal(112, out.mode.hspw); + assert_int_equal(0, out.mode.hborder); + assert_int_equal(768, out.mode.va); + assert_int_equal(27, out.mode.vbl); + assert_int_equal(3, out.mode.vso); + assert_int_equal(0, out.mode.vborder); + assert_int_equal(43, out.mode.phsync); + assert_int_equal(43, out.mode.pvsync); + assert_int_equal(0, out.mode.x_mm); + assert_int_equal(0, out.mode.y_mm); + + assert_int_equal(1, out.mode_is_supported[EDID_MODE_640x480_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_720x480_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_1280x720_60Hz]); + assert_int_equal(0, out.mode_is_supported[EDID_MODE_1920x1080_60Hz]); +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_decode_edid_no_edid), + cmocka_unit_test(test_decode_edid_invalid_header), + cmocka_unit_test(test_decode_edid_frame_1), + cmocka_unit_test(test_decode_edid_frame_2), + cmocka_unit_test(test_decode_edid_frame_3), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} + diff --git a/tests/stubs/console.c b/tests/stubs/console.c index b6a7583..1baed18 100644 --- a/tests/stubs/console.c +++ b/tests/stubs/console.c @@ -1,13 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <stdarg.h> +#include <stdio.h> int do_printk(int msg_level, const char *fmt, ...) { - return 0; + int res = 0; + va_list v; + va_start(v, fmt); + res = do_vprintk(msg_level, fmt, v); + va_end(v); + return res; } +extern int vprintf(const char *fmt, va_list ap); + int do_vprintk(int msg_level, const char *fmt, va_list args) { + return vprintf(fmt, args); + //return 0; +} + +int console_log_level(int msg_level) +{ return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/46817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I796e660eebc4d2c3c32207bd3a6ee44aaffeb325 Gerrit-Change-Number: 46817 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003143 Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/mtrr.h: Rename CORE2 alternative SMRR registers
by Arthur Heymans (Code Review) 10 Nov '20

10 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46896 ) Change subject: cpu/x86/mtrr.h: Rename CORE2 alternative SMRR registers ...................................................................... cpu/x86/mtrr.h: Rename CORE2 alternative SMRR registers It is too easy to confuse those with IA32_SMRR_PHYS_x registers. Change-Id: Ice02ab6c0315a2be14ef110ede506262e3c0a4d5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/smm/gen1/smmrelocate.c M src/include/cpu/x86/mtrr.h 2 files changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/46896/1 diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index ae2440d..36884a1 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -59,8 +59,8 @@ printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n", relo_params->smrr_base.lo, relo_params->smrr_mask.lo); - wrmsr(MSR_SMRR_PHYS_BASE, relo_params->smrr_base); - wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask); + wrmsr(CORE2_SMRR_PHYS_BASE, relo_params->smrr_base); + wrmsr(CORE2_SMRR_PHYS_MASK, relo_params->smrr_mask); } static void fill_in_relocation_params(struct smm_relocation_params *params) diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 3bf8301c..a96f17f 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -31,9 +31,10 @@ #define IA32_SMRR_PHYS_MASK 0x1f3 #define SMRR_PHYS_MASK_LOCK (1 << 10) -/* Specific to model_6fx and model_1067x */ -#define MSR_SMRR_PHYS_BASE 0xa0 -#define MSR_SMRR_PHYS_MASK 0xa1 +/* Specific to model_6fx and model_1067x. + Those are named MSR_SMRR_PHYSBASE in the SDM. */ +#define CORE2_SMRR_PHYS_BASE 0xa0 +#define CORE2_SMRR_PHYS_MASK 0xa1 #define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg)) #define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/46896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice02ab6c0315a2be14ef110ede506262e3c0a4d5 Gerrit-Change-Number: 46896 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020