coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/cbnt: Stitch in ACMs in the coreboot image
by Arthur Heymans (Code Review) 10 Nov '20

10 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46456 ) Change subject: soc/intel/cbnt: Stitch in ACMs in the coreboot image ...................................................................... soc/intel/cbnt: Stitch in ACMs in the coreboot image Actual support CbNT will be added later on. Change-Id: Icc35c5e6c74d002efee43cc05ecc8023e00631e0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M src/cpu/intel/fit/Kconfig M src/security/intel/Kconfig M src/security/intel/Makefile.inc A src/security/intel/cbnt/Kconfig A src/security/intel/cbnt/Makefile.inc M src/security/intel/txt/Kconfig M src/security/intel/txt/Makefile.inc 8 files changed, 72 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/46456/1 diff --git a/Makefile.inc b/Makefile.inc index b5b81f0..29721b4 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -726,6 +726,16 @@ endif +ifeq ($(CONFIG_INTEL_CBNT_SUPPORT),y) + +CBNTIBB := --cbnt + +else + +CBNTIBB := + +endif # CONFIG_INTEL_CBNT_SUPPORT + ifeq ($(CONFIG_COMPRESS_BOOTBLOCK),y) $(objcbfs)/bootblock.lz4: $(objcbfs)/bootblock.elf $(objutil)/cbfstool/cbfs-compression-tool @@ -1057,6 +1067,7 @@ ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y) TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE) endif + ifneq ($(CONFIG_UPDATE_IMAGE),y) $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(IFITTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap $(obj)/fmap.desc $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc) @@ -1066,6 +1077,7 @@ -n bootblock \ -t bootblock \ $(TXTIBB) \ + $(CBNTIBB) \ -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) \ $(TS_OPTIONS) else # ifeq ($(CONFIG_ARCH_X86),y) diff --git a/src/cpu/intel/fit/Kconfig b/src/cpu/intel/fit/Kconfig index fa10802..9ea867e 100644 --- a/src/cpu/intel/fit/Kconfig +++ b/src/cpu/intel/fit/Kconfig @@ -5,7 +5,7 @@ config CPU_INTEL_NUM_FIT_ENTRIES int - default 16 if INTEL_TXT + default 16 if INTEL_TXT || INTEL_CBNT_SUPPORT default 4 depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE help diff --git a/src/security/intel/Kconfig b/src/security/intel/Kconfig index 9cdd8a6..0609a45 100644 --- a/src/security/intel/Kconfig +++ b/src/security/intel/Kconfig @@ -2,3 +2,4 @@ source "src/security/intel/txt/Kconfig" source "src/security/intel/stm/Kconfig" +source "src/security/intel/cbnt/Kconfig" diff --git a/src/security/intel/Makefile.inc b/src/security/intel/Makefile.inc index e00802a..20aea27 100644 --- a/src/security/intel/Makefile.inc +++ b/src/security/intel/Makefile.inc @@ -1,2 +1,3 @@ subdirs-y += txt subdirs-y += stm +subdirs-y += cbnt diff --git a/src/security/intel/cbnt/Kconfig b/src/security/intel/cbnt/Kconfig new file mode 100644 index 0000000..568b7e5 --- /dev/null +++ b/src/security/intel/cbnt/Kconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config INTEL_CBNT_SUPPORT + bool "Intel CBnT support" + default n + depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE + #depends on PLATFORM_HAS_DRAM_CLEAR + select INTEL_TXT_SUPPORT + help + Enables Intel Converged Bootguard and Trusted Execution Technology + Support. This will enable one to add a Key Manifest (KM) and a Boot + Policy Manifest (BPM) to the filesystem. It will also wrap a FIT around + the firmware and update appropriate entries. + +if INTEL_CBNT_SUPPORT + +config INTEL_CBNT_KEY_MANIFEST_BINARY + string "KM (Key Manifest) binary location" + help + Location of the Key Manifest (KM) + +config INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY + string "BPM (Boot Policy Manifest) binary location" + help + Location of the Boot Policy Manifest (BPM) + +endif # INTEL_CBNT_SUPPORT diff --git a/src/security/intel/cbnt/Makefile.inc b/src/security/intel/cbnt/Makefile.inc new file mode 100644 index 0000000..70c2353 --- /dev/null +++ b/src/security/intel/cbnt/Makefile.inc @@ -0,0 +1,25 @@ +ifeq ($(CONFIG_INTEL_CBNT_SUPPORT),y) + +ifneq ($(CONFIG_INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY),"") +cbfs-files-y += boot_policy_manifest.bin +boot_policy_manifest.bin-file := $(CONFIG_INTEL_CBNT_BOOT_POLICY_MANIFEST_BINARY) +boot_policy_manifest.bin-type := raw +boot_policy_manifest.bin-alignment := 0x10 + +INTERMEDIATE+=add_bpm_fit +add_bpm_fit: $(obj)/coreboot.pre $(IFITTOOL) + $(IFITTOOL) -r COREBOOT -a -n boot_policy_manifest.bin -t 12 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< +endif + +ifneq ($(CONFIG_INTEL_CBNT_KEY_MANIFEST_BINARY),"") +cbfs-files-y += key_manifest.bin +key_manifest.bin-file := $(CONFIG_INTEL_CBNT_KEY_MANIFEST_BINARY) +key_manifest.bin-type := raw +key_manifest.bin-alignment := 0x10 + +INTERMEDIATE+=add_km_fit +add_km_fit: $(obj)/coreboot.pre $(IFITTOOL) + $(IFITTOOL) -r COREBOOT -a -n key_manifest.bin -t 11 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< +endif + +endif # CONFIG_INTEL_CBNT_SUPPORT \ No newline at end of file diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index 70aa695..6ee8960 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -37,6 +37,7 @@ config INTEL_TXT_BIOSACM_ALIGNMENT hex + default 0x40000 if INTEL_CBNT_SUPPORT default 0x20000 # 128 KiB help Exceptions are Ivy and Sandy Bridge with 64 KiB and Purley with 256 KiB diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc index 712ab58..ff0dcdf 100644 --- a/src/security/intel/txt/Makefile.inc +++ b/src/security/intel/txt/Makefile.inc @@ -29,6 +29,8 @@ $(IFITTOOL) -r COREBOOT -a -n $(CONFIG_INTEL_TXT_CBFS_BIOS_ACM) -t 2 \ -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< +# CbNT does not use FIT for IBB +ifneq ($(CONFIG_INTEL_CBNT_SUPPORT),y) # Initial BootBlock files ibb-files := $(foreach file,$(cbfs-files), \ $(if $(shell echo '$(call extract_nth,7,$(file))'|grep -- --ibb), \ @@ -41,6 +43,8 @@ $(foreach file, $(ibb-files), $(shell $(IFITTOOL) -f $< -a -n $(file) -t 7 \ -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT)) true +endif # INTEL_CBNT_SUPPORT + endif # CPU_INTEL_FIRMWARE_INTERFACE_TABLE endif # INTEL_TXT -- To view, visit https://review.coreboot.org/c/coreboot/+/46456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc35c5e6c74d002efee43cc05ecc8023e00631e0 Gerrit-Change-Number: 46456 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/hp: Add HP EliteBook Folio 9480m
by Iru Cai (vimacs) (Code Review) 10 Nov '20

10 Nov '20

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45578 to review the following change. Change subject: mb/hp: Add HP EliteBook Folio 9480m ...................................................................... mb/hp: Add HP EliteBook Folio 9480m The code is based on autoport, with necessary modifications. This laptop uses SMSC MEC1322 embedded controller, but the EC interface is the same as the EliteBook laptops of previous generations that use KBC1126 EC. So it still uses ec/hp/kbc1126, but does not need EC firmware inserted into CBFS. Thanks to persmule for providing the laptop and pointing out how to program the system flash chip of it. Change-Id: I2328c43cbb1f488aa1d0ddd9116814d971e5d8ae Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A Documentation/mainboard/hp/9480m.md A Documentation/mainboard/hp/9480m_flash.webp M Documentation/mainboard/index.md A src/mainboard/hp/folio_9480m/Kconfig A src/mainboard/hp/folio_9480m/Kconfig.name A src/mainboard/hp/folio_9480m/Makefile.inc A src/mainboard/hp/folio_9480m/acpi/ec.asl A src/mainboard/hp/folio_9480m/acpi/platform.asl A src/mainboard/hp/folio_9480m/acpi/superio.asl A src/mainboard/hp/folio_9480m/acpi_tables.c A src/mainboard/hp/folio_9480m/board_info.txt A src/mainboard/hp/folio_9480m/bootblock.c A src/mainboard/hp/folio_9480m/devicetree.cb A src/mainboard/hp/folio_9480m/dsdt.asl A src/mainboard/hp/folio_9480m/gma-mainboard.ads A src/mainboard/hp/folio_9480m/gpio.c A src/mainboard/hp/folio_9480m/hda_verb.c A src/mainboard/hp/folio_9480m/mainboard.c A src/mainboard/hp/folio_9480m/romstage.c 19 files changed, 575 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/45578/1 diff --git a/Documentation/mainboard/hp/9480m.md b/Documentation/mainboard/hp/9480m.md new file mode 100644 index 0000000..015d7b9 --- /dev/null +++ b/Documentation/mainboard/hp/9480m.md @@ -0,0 +1,140 @@ +# HP EliteBook Folio 9480m + +This page is about the notebook [HP EliteBook Folio 9480m]. + +## Release status + +HP EliteBook Folio 9480m was released in 2014 and is now end of life. +It can be bought from a secondhand market like Taobao or eBay. + +## Required proprietary blobs + +The following blobs are required to operate the hardware: + +1. EC firmware +2. Intel ME firmware +3. mrc.bin + +HP EliteBook Folio 9480m uses SMSC MEC1322 as its embedded controller. +The EC firmware is stored in the flash chip, but we don't need to touch it +or use it in the coreboot build process. + +Intel ME firmware is in the flash chip. It is not needed when building coreboot. + +The Haswell memory reference code binary is needed when building coreboot. +Please see [mrc.bin](../../northbridge/intel/haswell/mrc.bin). + +## Programming + +Before flashing, remove the battery and the hard drive cover according to the +[Maintenance and Service Guide] of this laptop. + +![Two flash chips of HP EliteBook Folio 9480m](9480m_flash.webp) + +HP EliteBook Folio 9480m has two flash chips, a 16MB system flash, and a 2MB +private flash. To install coreboot, we need to program both flash chips. +Read [HP Sure Start] for detailed information. + +To access the system flash. We need to connect the AC adapter to the machine, +then clip on the flash chip with an SOIC-8 clip. An [STM32-based flash programmer] +made with an STM32 develop board is tested to work. + +To access the private flash chip. You can use a ch341a based flash programmer and +flash the chip with the AC adapter disconnected. + +Before flashing coreboot, we need to do the following: + +1. Erase the private flash to disable the IFD protection +2. Modify the IFD to shrink the BIOS region, so that we'll not use or override + the protected bootblock and PEI region, as well as the EC firmware + +To erase the private flash chip, attach it with the flash programmer via the SOIC-8 clip, +then run: + + flashrom -p <programmer> --erase + +To modify the IFD, we need a new flash layout. The default coreboot configuration +sets the flash chip size to 12MB. We use the following flash layout in the modified IFD: + + 00000000:00000fff fd + 00600000:00bfffff bios + 00003000:005fffff me + 00001000:00002fff gbe + +Write the above layout in a file, and use ifdtool to modify the IFD of a flash image. +Suppose the above layout file is ``layout.txt`` and the origin content of the system flash +is in ``factory-sys.rom``, run: + + ifdtool -n layout.txt factory-sys.rom + +Then a flash image with a new IFD will be in ``factory-sys.rom.new``. + +Flash the IFD of the system flash: + + flashrom -p <programmer> --ifd -i fd -w factory-sys.rom.new + +Then flash the coreboot image: + + # first extend the 12M coreboot.rom to 16M + fallocate -l 16M build/coreboot.rom + flashrom -p <programmer> --ifd -i bios -w build/coreboot.rom + +## Debugging + +The board can be debugged with EHCI debug. The EHCI debug port is the USB port on the left. + +## Test status + +### Known issues + +- No audio output from speaker +- GRUB payload freezes just like previous EliteBook laptops + +### Untested + +- Ethernet +- Dock +- VGA +- TPM +- SD card reader +- Fingerprint reader +- Smart Card reader + +### Working + +- i5-4310U CPU with 4G+4G memory +- SATA and M.2 SATA disk +- WLAN +- WWAN +- USB +- Keyboard and touchpad +- DisplayPort +- Audio output from haedphone jack +- Webcam +- Arch Linux with Linux 5.8.9 +- Memory initialization with mrc.bin version 1.6.1 Build 2 +- Graphics initialization with libgfxinit +- Payload: SeaBIOS, Tianocore +- EC firmware + - KBC Revision 92.15 from OEM firmware version 01.33 + - KBC Revision 92.17 from OEM firmware version 01.50 +- Internal flashing under coreboot + +## Technology + +```eval_rst ++------------------+-----------------------------+ +| CPU | Intel Haswell-ULT | ++------------------+-----------------------------+ +| PCH | Intel Lynx Point Low Power | ++------------------+-----------------------------+ +| EC | SMSC MEC1322 | ++------------------+-----------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+-----------------------------+ +``` + +[HP EliteBook Folio 9480m]: https://support.hp.com/us-en/product/hp-elitebook-folio-9480m-notebook-pc/7… +[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c05228980 +[STM32-based flash programmer]: https://github.com/dword1511/stm32-vserprog +[HP Sure Start]: hp_sure_start.md diff --git a/Documentation/mainboard/hp/9480m_flash.webp b/Documentation/mainboard/hp/9480m_flash.webp new file mode 100644 index 0000000..1abc306 --- /dev/null +++ b/Documentation/mainboard/hp/9480m_flash.webp Binary files differ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 335eae2..bc3f0c6 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -64,6 +64,7 @@ - [HP Sure Start](hp/hp_sure_start.md) - [EliteBook 2560p](hp/2560p.md) - [EliteBook 8760w](hp/8760w.md) +- [EliteBook Folio 9480m](hp/9480m.md) ## Intel diff --git a/src/mainboard/hp/folio_9480m/Kconfig b/src/mainboard/hp/folio_9480m/Kconfig new file mode 100644 index 0000000..9200b82 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/Kconfig @@ -0,0 +1,49 @@ +if BOARD_HP_FOLIO_9480M + +config BOARD_SPECIFIC_OPTIONS + def_bool y + # The board has a 16MB flash, but the end of the flash need + # to be reserved, so we use 12MB as default + select BOARD_ROMSIZE_KB_12288 + select EC_HP_KBC1126 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select INTEL_LYNXPOINT_LP + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SYSTEM_TYPE_LAPTOP + +config MAINBOARD_DIR + string + default "hp/folio_9480m" + +config MAINBOARD_PART_NUMBER + string + default "HP EliteBook Folio 9480m" + +config VGA_BIOS_FILE + string + default "pci8086,0a16.rom" + +config VGA_BIOS_ID + string + default "8086,0a16" + +config USBDEBUG_HCD_INDEX + int + default 1 + +config EC_HP_KBC1126_ECFW_IN_CBFS + bool + default n + +config EC_HP_KBC1126_GPE + hex + default 0x6 + +endif diff --git a/src/mainboard/hp/folio_9480m/Kconfig.name b/src/mainboard/hp/folio_9480m/Kconfig.name new file mode 100644 index 0000000..67c671d --- /dev/null +++ b/src/mainboard/hp/folio_9480m/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_FOLIO_9480M + bool "EliteBook Folio 9480m" diff --git a/src/mainboard/hp/folio_9480m/Makefile.inc b/src/mainboard/hp/folio_9480m/Makefile.inc new file mode 100644 index 0000000..fa23791 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += bootblock.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/folio_9480m/acpi/ec.asl b/src/mainboard/hp/folio_9480m/acpi/ec.asl new file mode 100644 index 0000000..baa17a4 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/hp/kbc1126/acpi/ec.asl> diff --git a/src/mainboard/hp/folio_9480m/acpi/platform.asl b/src/mainboard/hp/folio_9480m/acpi/platform.asl new file mode 100644 index 0000000..8023ae8 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/acpi/platform.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK,1) +{ + \_SB.PCI0.LPCB.EC0.ACPI = 1 + \_SB.PCI0.LPCB.EC0.SLPT = 0 + + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC0.SLPT = Arg0 +} diff --git a/src/mainboard/hp/folio_9480m/acpi/superio.asl b/src/mainboard/hp/folio_9480m/acpi/superio.asl new file mode 100644 index 0000000..55b1db5 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/hp/folio_9480m/acpi_tables.c b/src/mainboard/hp/folio_9480m/acpi_tables.c new file mode 100644 index 0000000..00963e1 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/acpi_tables.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <southbridge/intel/lynxpoint/nvs.h> + +void acpi_create_gnvs(struct global_nvs *gnvs) +{ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/folio_9480m/board_info.txt b/src/mainboard/hp/folio_9480m/board_info.txt new file mode 100644 index 0000000..fdd0d60 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/board_info.txt @@ -0,0 +1,7 @@ +Category: laptop +Board URL: https://support.hp.com/us-en/product/hp-elitebook-folio-9480m-notebook-pc/7… +ROM protocol: SPI +ROM package: SOIC-8 +ROM socketed: n +Flashrom support: y +Release year: 2014 diff --git a/src/mainboard/hp/folio_9480m/bootblock.c b/src/mainboard/hp/folio_9480m/bootblock.c new file mode 100644 index 0000000..ebc00fe --- /dev/null +++ b/src/mainboard/hp/folio_9480m/bootblock.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/hp/kbc1126/ec.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_superio(void) +{ + kbc1126_enter_conf(); + kbc1126_mailbox_init(); + kbc1126_kbc_init(); + kbc1126_ec_init(); + kbc1126_pm1_init(); + kbc1126_exit_conf(); +} diff --git a/src/mainboard/hp/folio_9480m/devicetree.cb b/src/mainboard/hp/folio_9480m/devicetree.cb new file mode 100644 index 0000000..6653cf9 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/devicetree.cb @@ -0,0 +1,86 @@ +chip northbridge/intel/haswell + register "dq_pins_interleaved" = "true" + register "ec_present" = "true" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight_pwm_hz" = "200" + register "usb_xhci_on_resume" = "true" + device cpu_cluster 0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x103c 0x22da inherit + device pci 00.0 on end # Host bridge + device pci 02.0 on end # Internal graphics VGA controller + device pci 03.0 on end # Mini-HD audio + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x007c0201" + register "gen2_dec" = "0x000c0101" + register "gen4_dec" = "0x000402e9" + register "sata_ahci" = "1" + register "sata_port0_gen3_dtle" = "0x6" + register "sata_port1_gen3_dtle" = "0x6" + # SATA(1), M.2(3) + register "sata_port_map" = "0xa" + device pci 13.0 off end # Intel Smart Sound DSP + device pci 14.0 on end # xHCI Controller + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2, Realtek Card Reader + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on # PCIe Port #4, WLAN + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + "M.2 2230" "SlotDataBusWidth1X" + end + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + # This laptop uses MEC1322, but it has the same interface + # as the KBC1126 laptops + chip ec/hp/kbc1126 + register "ec_data_port" = "0x62" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" + register "ec_fan_ctrl_value" = "0x6b" + device pnp ff.1 off end + end + end + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/hp/folio_9480m/dsdt.asl b/src/mainboard/hp/folio_9480m/dsdt.asl new file mode 100644 index 0000000..eef373a --- /dev/null +++ b/src/mainboard/hp/folio_9480m/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/hp/folio_9480m/gma-mainboard.ads b/src/mainboard/hp/folio_9480m/gma-mainboard.ads new file mode 100644 index 0000000..8eea59a --- /dev/null +++ b/src/mainboard/hp/folio_9480m/gma-mainboard.ads @@ -0,0 +1,20 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + HDMI1, + HDMI2, + eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/folio_9480m/gpio.c b/src/mainboard/hp/folio_9480m/gpio.c new file mode 100644 index 0000000..3ad465a --- /dev/null +++ b/src/mainboard/hp/folio_9480m/gpio.c @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/lp_gpio.h> + +const struct pch_lp_gpio_map mainboard_gpio_map[] = { + [0] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [2] = LP_GPIO_OUT_LOW, + [3] = LP_GPIO_OUT_HIGH, + [4] = LP_GPIO_OUT_HIGH, + [5] = LP_GPIO_OUT_HIGH, + [6] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [7] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [8] = LP_GPIO_OUT_HIGH, + [9] = LP_GPIO_OUT_HIGH, + [10] = LP_GPIO_OUT_HIGH, + [11] = LP_GPIO_OUT_HIGH, + [12] = LP_GPIO_NATIVE, + [13] = LP_GPIO_OUT_HIGH, + [14] = LP_GPIO_OUT_HIGH, + [15] = LP_GPIO_OUT_HIGH, + [16] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .route = GPIO_ROUTE_SMI }, + [17] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [18] = LP_GPIO_OUT_HIGH, + [19] = LP_GPIO_NATIVE, + [20] = LP_GPIO_NATIVE, + [21] = LP_GPIO_NATIVE, + [22] = LP_GPIO_OUT_HIGH, + [23] = LP_GPIO_OUT_HIGH, + [24] = LP_GPIO_OUT_HIGH, + [25] = LP_GPIO_OUT_HIGH, + [26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [28] = LP_GPIO_OUT_HIGH, + [29] = LP_GPIO_OUT_HIGH, + [30] = LP_GPIO_NATIVE, + [31] = LP_GPIO_NATIVE, + [32] = LP_GPIO_NATIVE, + [33] = LP_GPIO_NATIVE, + [34] = LP_GPIO_OUT_HIGH, + [35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [36] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .route = GPIO_ROUTE_SMI }, + [37] = LP_GPIO_NATIVE, + [38] = LP_GPIO_NATIVE, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [40] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL, + .route = GPIO_ROUTE_SMI }, + [41] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [42] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [43] = LP_GPIO_OUT_HIGH, + [44] = LP_GPIO_OUT_LOW, + [45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL }, + [46] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [47] = LP_GPIO_OUT_HIGH, + [48] = LP_GPIO_OUT_LOW, + [49] = LP_GPIO_OUT_HIGH, + [50] = LP_GPIO_OUT_HIGH, + [51] = LP_GPIO_OUT_HIGH, + [52] = LP_GPIO_OUT_HIGH, + [53] = LP_GPIO_OUT_HIGH, + [54] = LP_GPIO_OUT_LOW, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, + .pirq = GPIO_PIRQ_APIC_ROUTE }, + [56] = LP_GPIO_OUT_HIGH, + [57] = LP_GPIO_OUT_LOW, + [58] = LP_GPIO_OUT_HIGH, + [59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [60] = LP_GPIO_OUT_HIGH, + [61] = LP_GPIO_OUT_LOW, + [62] = LP_GPIO_NATIVE, + [63] = LP_GPIO_NATIVE, + [64] = LP_GPIO_OUT_HIGH, + [65] = LP_GPIO_OUT_LOW, + [66] = LP_GPIO_OUT_HIGH, + [67] = LP_GPIO_OUT_HIGH, + [68] = LP_GPIO_OUT_HIGH, + [69] = LP_GPIO_OUT_HIGH, + [70] = LP_GPIO_OUT_LOW, + [71] = LP_GPIO_NATIVE, + [72] = LP_GPIO_NATIVE, + [73] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [74] = LP_GPIO_NATIVE, + [75] = LP_GPIO_NATIVE, + [76] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL, .route = GPIO_ROUTE_SMI }, + [79] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [80] = LP_GPIO_OUT_LOW, + [81] = LP_GPIO_NATIVE, + [82] = LP_GPIO_OUT_HIGH, + [83] = LP_GPIO_OUT_HIGH, + [84] = LP_GPIO_OUT_HIGH, + [85] = LP_GPIO_OUT_HIGH, + [86] = LP_GPIO_OUT_HIGH, + [87] = LP_GPIO_OUT_HIGH, + [88] = LP_GPIO_OUT_HIGH, + [89] = LP_GPIO_OUT_HIGH, + [90] = LP_GPIO_OUT_HIGH, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [93] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL }, + [94] = LP_GPIO_OUT_HIGH, + LP_GPIO_END +}; diff --git a/src/mainboard/hp/folio_9480m/hda_verb.c b/src/mainboard/hp/folio_9480m/hda_verb.c new file mode 100644 index 0000000..fee9c3e --- /dev/null +++ b/src/mainboard/hp/folio_9480m/hda_verb.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0280, /* Codec Vendor / Device ID: Realtek */ + 0x103c22db, /* Subsystem ID */ + 13, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c22db), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x0321101f), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x03a11020), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40738105), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/folio_9480m/mainboard.c b/src/mainboard/hp/folio_9480m/mainboard.c new file mode 100644 index 0000000..98cc811 --- /dev/null +++ b/src/mainboard/hp/folio_9480m/mainboard.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/folio_9480m/romstage.c b/src/mainboard/hp/folio_9480m/romstage.c new file mode 100644 index 0000000..ca4046a --- /dev/null +++ b/src/mainboard/hp/folio_9480m/romstage.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQF, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQB, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQB, PIRQC, PIRQD); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} + +void mb_get_spd_map(uint8_t spd_map[4]) +{ + spd_map[0] = 0xa0; + spd_map[2] = 0xa4; +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* left, EHCI debug */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* right */ + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WLAN */ + { 0x0110, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* SmartCard */ + { 0x0080, 1, USB_OC_PIN_SKIP, USB_PORT_MINI_PCIE }, /* WWAN */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, /* Webcam */ + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + }; + struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = { + { 1, USB_OC_PIN_SKIP }, + { 1, USB_OC_PIN_SKIP }, /* left */ + { 1, USB_OC_PIN_SKIP }, /* right */ + { 0, USB_OC_PIN_SKIP }, + }; + memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); + memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2328c43cbb1f488aa1d0ddd9116814d971e5d8ae Gerrit-Change-Number: 45578 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 30

Change in coreboot[master]: vc/intel/FSP2_0/CPX-SP: add FSPM DIMM watermark option
by Jonathan Zhang (Code Review) 09 Nov '20

09 Nov '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46480 ) Change subject: vc/intel/FSP2_0/CPX-SP: add FSPM DIMM watermark option ...................................................................... vc/intel/FSP2_0/CPX-SP: add FSPM DIMM watermark option FSPM MemRefreshWatermark option support is present in FB's CPX-SP FSP binary, but not in Intel's CPX-SP FSP binary. Add a Kconfig HAVE_FSPM_DIMM_WATERMARK_OPTION to indicate whether the FSP binary supports such option. When such option is set, if corresponding VPD variable is set, use it to control the behavior. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I7592dfc8836f457d64f1976cba3b59f8251c7abe --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/romstage.c M src/mainboard/ocp/deltalake/vpd.h M src/soc/intel/xeon_sp/cpx/Kconfig M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h 5 files changed, 88 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/46480/1 diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index ff5599c..0777ad3 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -4,6 +4,7 @@ def_bool y select BOARD_ROMSIZE_KB_65536 select HAVE_ACPI_TABLES + select HAVE_FSPM_DIMM_WATERMARK_OPTION select MAINBOARD_USES_FSP2_0 select SOC_INTEL_COOPERLAKE_SP select SUPERIO_ASPEED_AST2400 diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 71a26c8..3cb514b 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -59,6 +59,25 @@ "DciEn to %d\n", FSP_DCI, FSP_DCI_DEFAULT); mupd->FspmConfig.PchDciEn = FSP_DCI_DEFAULT; } + + /* Set MemRefreshWaterMark */ + if (CONFIG(HAVE_FSPM_DIMM_WATERMARK_OPTION)) { + if (vpd_gets(FSPM_MEMREFRESHWATERMARK, val_str, VPD_LEN, VPD_RW_THEN_RO)) { + val = (uint8_t)atol(val_str); + if (val > 2) { + printk(BIOS_DEBUG, "Invalid MemRefreshWatermark value from VPD: " + "%d\n", val); + val = FSPM_MEMREFRESHWATERMARK_DEFAULT; + } + printk(BIOS_DEBUG, "Setting MemRefershWatermark %d from VPD\n", val); + mupd->FspmConfig.MemRefreshWaterMark = val; + } else { + printk(BIOS_INFO, "Not able to get VPD %s, default set " + "MemRefreshWatermark to %d\n", FSPM_MEMREFRESHWATERMARK, + FSPM_MEMREFRESHWATERMARK_DEFAULT); + mupd->FspmConfig.MemRefreshWaterMark = FSPM_MEMREFRESHWATERMARK_DEFAULT; + } + } } /* Update bifurcation settings according to different Configs */ diff --git a/src/mainboard/ocp/deltalake/vpd.h b/src/mainboard/ocp/deltalake/vpd.h index ae2099d..2db9851 100644 --- a/src/mainboard/ocp/deltalake/vpd.h +++ b/src/mainboard/ocp/deltalake/vpd.h @@ -32,4 +32,8 @@ #define FSP_DCI "fsp_dci_enable" /* 1 or 0: enable or disable DCI */ #define FSP_DCI_DEFAULT 0 /* Default value when the VPD variable is not found */ +/* FSPM MemRefreshWatermark: 0:Auto (default), 1: high, 2: low */ +#define FSPM_MEMREFRESHWATERMARK "fspm_mem_refresh_watermark" +#define FSPM_MEMREFRESHWATERMARK_DEFAULT 1 /* Default value when the VPD variable is not found */ + #endif diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 975afc9..1d69889 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -91,4 +91,7 @@ int default 512 +config HAVE_FSPM_DIMM_WATERMARK_OPTION + def_bool n + endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 37ff1bd..89922ef 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -495,237 +495,248 @@ **/ UINT8 serialDebugMsgLvl; -/** Offset 0x00C4 - IIO ConfigIOU0 +#if CONFIG_HAVE_FSPM_DIMM_WATERMARK_OPTION +/** Offset 0x00C4 - Usage type for Memory Refresh Watermark + Select Memory Refresh Watermark, 0: Auto (default), 1: High, 2: Low +**/ + UINT8 MemRefreshWaterMark; +#endif + +/** Offset 0x00C5 - IIO ConfigIOU0 ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU0[8]; -/** Offset 0x00CC - IIO ConfigIOU1 +/** Offset 0x00CD - IIO ConfigIOU1 ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU1[8]; -/** Offset 0x00D4 - IIO ConfigIOU2 +/** Offset 0x00D5 - IIO ConfigIOU2 ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU2[8]; -/** Offset 0x00DC - IIO ConfigIOU3 +/** Offset 0x00DD - IIO ConfigIOU3 ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU3[8]; -/** Offset 0x00E4 - IIO ConfigIOU4 +/** Offset 0x00E5 - IIO ConfigIOU4 ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO **/ UINT8 IioConfigIOU4[8]; -/** Offset 0x00EC - Usage type for IIO PCIE Config Table Ptr +/** Offset 0x00ED +**/ + UINT8 UnusedUpdSpace2[3]; + +/** Offset 0x00F0 - Usage type for IIO PCIE Config Table Ptr IIO PCIE Config Table Ptr **/ UINT32 IioPcieConfigTablePtr; -/** Offset 0x00F0 - Usage type for IIO PCIE Config Table Number +/** Offset 0x00F4 - Usage type for IIO PCIE Config Table Number IIO PCIE Config Table Number **/ UINT32 IioPcieConfigTableNumber; -/** Offset 0x00F4 - Usage type for IIO PCIE Root Port Enable or Disable +/** Offset 0x00F8 - Usage type for IIO PCIE Root Port Enable or Disable IIO PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, the value is 0x00 **/ UINT8 IIOPcieRootPortEnable; -/** Offset 0x00F5 - Usage type for IIO DeEmphasis +/** Offset 0x00F9 - Usage type for IIO DeEmphasis IIO DeEmphasis **/ UINT8 DeEmphasis; -/** Offset 0x00F6 - Usage type for IIO PCIE Root Port link speed +/** Offset 0x00FA - Usage type for IIO PCIE Root Port link speed IIO root port link speed **/ UINT8 IIOPciePortLinkSpeed; -/** Offset 0x00F7 - Usage type for IIO PCIE Root Port Max Payload +/** Offset 0x00FB - Usage type for IIO PCIE Root Port Max Payload IIO Root Port Max Payload **/ UINT8 IIOPcieMaxPayload; -/** Offset 0x00F8 - Usage type for IIO DfxDnTxPreset +/** Offset 0x00FC - Usage type for IIO DfxDnTxPreset IIO DfxDnTxPreset **/ UINT8 DfxDnTxPreset; -/** Offset 0x00F9 - Usage type for IIO DfxRxPreset +/** Offset 0x00FD - Usage type for IIO DfxRxPreset IIO DfxRxPreset **/ UINT8 DfxRxPreset; -/** Offset 0x00FA - Usage type for IIO DfxUpTxPreset +/** Offset 0x00FE - Usage type for IIO DfxUpTxPreset IIO DfxUpTxPreset **/ UINT8 DfxUpTxPreset; -/** Offset 0x00FB - Usage type for IIO PcieCommonClock +/** Offset 0x00FF - Usage type for IIO PcieCommonClock IIO PcieCommonClock **/ UINT8 PcieCommonClock; -/** Offset 0x00FC - Usage type for IIO NtbPpd +/** Offset 0x0100 - Usage type for IIO NtbPpd IIO NtbPpd **/ UINT8 NtbPpd; -/** Offset 0x00FD - Usage type for IIO NtbBarSizeOverride +/** Offset 0x0101 - Usage type for IIO NtbBarSizeOverride IIO NtbBarSizeOverride **/ UINT8 NtbBarSizeOverride; -/** Offset 0x00FE - Usage type for IIO NtbSplitBar +/** Offset 0x0102 - Usage type for IIO NtbSplitBar IIO NtbSplitBar **/ UINT8 NtbSplitBar; -/** Offset 0x00FF - Usage type for IIO NtbBarSizeImBar1 +/** Offset 0x0103 - Usage type for IIO NtbBarSizeImBar1 IIO NtbBarSizeImBar1 **/ UINT8 NtbBarSizeImBar1; -/** Offset 0x0100 - Usage type for IIO NtbBarSizeImBar2 +/** Offset 0x0104 - Usage type for IIO NtbBarSizeImBar2 IIO PNtbBarSizeImBar2 **/ UINT8 NtbBarSizeImBar2; -/** Offset 0x0101 - Usage type for IIO NtbBarSizeImBar2_0 +/** Offset 0x0105 - Usage type for IIO NtbBarSizeImBar2_0 IIO PNtbBarSizeImBar2_0 **/ UINT8 NtbBarSizeImBar2_0; -/** Offset 0x0102 - Usage type for IIO NtbBarSizeImBar2_1 +/** Offset 0x0106 - Usage type for IIO NtbBarSizeImBar2_1 IIO NtbBarSizeImBar2_1 **/ UINT8 NtbBarSizeImBar2_1; -/** Offset 0x0103 - Usage type for IIO NtbBarSizeEmBarSZ1 +/** Offset 0x0107 - Usage type for IIO NtbBarSizeEmBarSZ1 IIO NtbBarSizeEmBarSZ1 **/ UINT8 NtbBarSizeEmBarSZ1; -/** Offset 0x0104 - Usage type for IIO NtbBarSizeEmBarSZ2 +/** Offset 0x0108 - Usage type for IIO NtbBarSizeEmBarSZ2 IIO NtbBarSizeEmBarSZ2 **/ UINT8 NtbBarSizeEmBarSZ2; -/** Offset 0x0105 - Usage type for IIO NtbBarSizeEmBarSZ2_0 +/** Offset 0x0109 - Usage type for IIO NtbBarSizeEmBarSZ2_0 IIO NtbBarSizeEmBarSZ2_0 **/ UINT8 NtbBarSizeEmBarSZ2_0; -/** Offset 0x0106 - Usage type for IIO NtbBarSizeEmBarSZ2_1 +/** Offset 0x010A - Usage type for IIO NtbBarSizeEmBarSZ2_1 IIO NtbBarSizeEmBarSZ2_1 **/ UINT8 NtbBarSizeEmBarSZ2_1; -/** Offset 0x0107 - Usage type for IIO NtbXlinkCtlOverride +/** Offset 0x010B - Usage type for IIO NtbXlinkCtlOverride IIO NtbXlinkCtlOverride **/ UINT8 NtbXlinkCtlOverride; -/** Offset 0x0108 - Usage type for IIO VT-D Function +/** Offset 0x010C - Usage type for IIO VT-D Function IIO VT-D Function, if supported, the value is 0x01, if not supported, the value is 0x00 **/ UINT8 VtdSupport; -/** Offset 0x0109 - Usage type for IIO Pcie Port Hide +/** Offset 0x010D - Usage type for IIO Pcie Port Hide Hide or visible for IIO Pcie Port, 1 : Hide, 0 : Visible **/ UINT8 PEXPHIDE; -/** Offset 0x010A - Usage type for IIO Pcie Port Menu Hide +/** Offset 0x010E - Usage type for IIO Pcie Port Menu Hide Hide or visible for IIO Pcie Port Menu, 1 : Hide, 0 : Visible **/ UINT8 HidePEXPMenu; -/** Offset 0x010B - PchSirqMode +/** Offset 0x010F - PchSirqMode Enable or Disable PchSirqMode **/ UINT8 PchSirqMode; -/** Offset 0x010C - PchAdrEn +/** Offset 0x0110 - PchAdrEn Enable or Disable PchAdr **/ UINT8 PchAdrEn; -/** Offset 0x010D - ThermalDeviceEnable +/** Offset 0x0111 - ThermalDeviceEnable Enable or Disable ThermalDeviceEnable with PCI or ACPI mode **/ UINT8 ThermalDeviceEnable; -/** Offset 0x010E - } TYPE:{Combo +/** Offset 0x0112 - } TYPE:{Combo Root port swapping based on device connection status : TRUE or FALSE TRUE : 0x01, FALSE : 0x00 **/ UINT8 PchPcieRootPortFunctionSwap; -/** Offset 0x010F - PCH PCIE PLL Ssc +/** Offset 0x0113 - PCH PCIE PLL Ssc Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF **/ UINT8 PchPciePllSsc; -/** Offset 0x0110 - Usage type for PCH PCIE Root Port Index +/** Offset 0x0114 - Usage type for PCH PCIE Root Port Index Index assigned to every PCH PCIE Root Port **/ UINT8 PchPciePortIndex[20]; -/** Offset 0x0124 - Usage type for PCH PCIE Root Port Enable or Disable +/** Offset 0x0128 - Usage type for PCH PCIE Root Port Enable or Disable 0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, the value is 0x00 **/ UINT8 PchPcieForceEnable[20]; -/** Offset 0x0138 - Usage type for PCH PCIE Root Port Link Speed +/** Offset 0x013C - Usage type for PCH PCIE Root Port Link Speed 0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie Gen2 Speed, 0x03 : Pcie Gen3 Speed **/ UINT8 PchPciePortLinkSpeed[20]; -/** Offset 0x014C - PchDciEn +/** Offset 0x0150 - PchDciEn Enable or Disable Pch DciEn **/ UINT8 PchDciEn; -/** Offset 0x014D - MeUmaEnable +/** Offset 0x0151 - MeUmaEnable Enable or disable ME UMA feature **/ UINT8 MeUmaEnable; -/** Offset 0x014E - SerialIoUartDebugEnable +/** Offset 0x0152 - SerialIoUartDebugEnable Enable SerialIo Uart debug library in FSP. 0:Disable, 1:Enable **/ UINT8 SerialIoUartDebugEnable; -/** Offset 0x014F +/** Offset 0x0153 **/ - UINT8 UnusedUpdSpace2; + UINT8 UnusedUpdSpace3; -/** Offset 0x0150 - ISA Serial Base selection +/** Offset 0x0154 - ISA Serial Base selection Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8 0x3F8, 0x2F8 **/ UINT16 SerialIoUartDebugIoBase; -/** Offset 0x0152 +/** Offset 0x0156 **/ - UINT8 UnusedUpdSpace3[2]; + UINT8 UnusedUpdSpace4[2]; -/** Offset 0x0154 +/** Offset 0x0158 **/ UINT8 ReservedMemoryInitUpd[16]; } FSPM_CONFIG; @@ -746,11 +757,11 @@ **/ FSPM_CONFIG FspmConfig; -/** Offset 0x0164 +/** Offset 0x0168 **/ - UINT8 UnusedUpdSpace4[2]; + UINT8 UnusedUpdSpace5[6]; -/** Offset 0x0166 +/** Offset 0x016E **/ UINT16 UpdTerminator; } FSPM_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/46480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7592dfc8836f457d64f1976cba3b59f8251c7abe Gerrit-Change-Number: 46480 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: vc/intel/FSP2_0/CPX-SP: update FSP to ww43 release
by Jonathan Zhang (Code Review) 09 Nov '20

09 Nov '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46609 ) Change subject: vc/intel/FSP2_0/CPX-SP: update FSP to ww43 release ...................................................................... vc/intel/FSP2_0/CPX-SP: update FSP to ww43 release Intel CPX-SP FSP ww43 release added default values explanation to FSP-M header file. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Icc75f39f8f7a6d47690464dd4e5194f6e2ba12a8 --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h 1 file changed, 165 insertions(+), 159 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/46609/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 34aa6c1..2a169af 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -151,223 +151,231 @@ UINT8 CustomerRevision[32]; /** Offset 0x0060 - Bus Ratio - Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO + Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO. + Default 0x1 **/ UINT8 BusRatio[8]; /** Offset 0x0068 - D2K Credit Config - Set the D2K Credit Config + Set the D2K Credit Config. 1: Min,2: Med (Default), 3: Max. 1:Min, 2:Med, 3:Max **/ UINT8 D2KCreditConfig; /** Offset 0x0069 - Snoop Throttle Config - Set the Snoop Throttle Config - 0:DIS, 1:Min, 2:Med, 3:Max + Set the Snoop Throttle Config. 0: Disable(Default), 1: Min, 2: Med, 3: Max + 0:Disable, 1:Min, 2:Med, 3:Max **/ UINT8 SnoopThrottleConfig; /** Offset 0x006A - Snoop Throttle Config - Set the Snoop All Core Config - 0:DIS, 1:EN, 2:Auto + Set the Snoop All Core Config. 0: Disable(Default), 1: Enable, 2: Auto + 0:Disable, 1:Enable, 2:Auto **/ UINT8 SnoopAllCores; -/** Offset 0x006B - Legacy VGA Soc - Socket that claims the legacy VGA range +/** Offset 0x006B - Legacy VGA Socket + Socket that claims the legacy VGA range. Default: Socket 0 **/ UINT8 LegacyVgaSoc; /** Offset 0x006C - Legacy VGA Stack - Stack that claims the legacy VGA range + Stack that claims the legacy VGA range. Default: Stack 0 **/ UINT8 LegacyVgaStack; /** Offset 0x006D - Pcie P2P Performance Mode - Determine if to enable PCIe P2P Performance Mode + Enable: Enable PCIe P2P Performance Mode, Disable(Default): Disable PCIe + P2P Performance Mode $EN_DIS **/ UINT8 P2pRelaxedOrdering; /** Offset 0x006E - Debug Print Level - Set Debug Print Level + Debug Print Level Bitmask. 0: Disable, 1: Fatal, 2: Warning, 4: Summary, 8: Detail, + 0xF: All(Default) 1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All **/ UINT8 DebugPrintLevel; /** Offset 0x006F - SNC - Enable or Disable SNC + Enable(Default) or Disable SNC $EN_DIS **/ UINT8 SncEn; /** Offset 0x0070 - UMA Clustering - Set UMA Clusters + Set number of enabled UMA Clusters. 0: Disable(Default), 2: Two Clusters, + 4: Four Clusters 0:Disable, 2:Two Clusters, 4:Four Clusters **/ UINT8 UmaClustering; /** Offset 0x0071 - IODC Mode - IODC Setup Option + IODC Mode. 0: Disable, 1: Auto(Default), 2: Push, 3: AllocFlow 4: NonAlloc, 5: WCILF 0:Disable, 1:Auto, 2:Push, 3:AllocFlow 4:NonAlloc, 5:WCILF **/ UINT8 IoDcMode; /** Offset 0x0072 - Degrade Precedence - Setup Degrade Precedence + Degrade Precedence. 0: Topology(Default), 1: Feature 0:Topology, 1:Feature **/ UINT8 DegradePrecedence; /** Offset 0x0073 - Degrade 4 Socket Preference - Setup Degrade 4 Socket Preference + Degrade 4 Socket Preference. 0: Fully Connect(Default), 1: Dual Link Ring 0:Fully Connect, 1:Dual Link Ring **/ UINT8 Degrade4SPreference; /** Offset 0x0074 - Directory Mode - Enable or Disable Directory Mode + Enable(Default) or Disable Directory Mode $EN_DIS **/ UINT8 DirectoryModeEn; /** Offset 0x0075 - XPT Prefetch Enable - Enable or Disable XPT Prefetch + XPT Prefetch. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 XptPrefetchEn; /** Offset 0x0076 - KTI Prefetch Enable - Enable or Disable KTI Prefetch + Enable(Default) or Disable KTI Prefetch $EN_DIS **/ UINT8 KtiPrefetchEn; /** Offset 0x0077 - XPT Remote Prefetch Enable - Enable or Disable XPT Remote Prefetch Enable + Enable or Disable(Default) XPT Remote Prefetch $EN_DIS **/ UINT8 XptRemotePrefetchEn; /** Offset 0x0078 - KTI FPGA - Enable or Disable KTI FPGA - $EN_DIS + Enable or Disable KTI FPGA, Default: 0x1 (Enable) **/ UINT8 KtiFpgaEnable[8]; /** Offset 0x0080 - DDRT QoS Mode - Setup DDRT QoS + DDRT QoS. 0: Mode 0(Default), 1: Mode 1, 2: Mode 2 **/ UINT8 DdrtQosMode; /** Offset 0x0081 - KTI Link Speed Mode - Choose KTI Link Speed Mode + KTI Link Speed Mode. 0: Slow, 1: Full(Default) **/ UINT8 KtiLinkSpeedMode; /** Offset 0x0082 - KTI Link Speed - Setup KTI Link Speed + KTI Link Speed. 0: 128GT, 1: 144GT, 2: 160GT, 3: Max KTI Link Speed(Default), + 4: Frequency Per Link **/ UINT8 KtiLinkSpeed; /** Offset 0x0083 - KTI Link L0p - Enable or Disable KTI Link L0p + KTI Link L0p. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 KtiLinkL0pEn; /** Offset 0x0084 - KTI Link L1 - Enable or Disable KTI Link L1 + KTI Link L1. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 KtiLinkL1En; /** Offset 0x0085 - KTI Failover - Enable or Disable KTI Failover + KTI Failover. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 KtiFailoverEn; /** Offset 0x0086 - KTI LB Enable - Enable or Disable KTI LB + Enable or Disable(Default) KTI LB $EN_DIS **/ UINT8 KtiLbEn; /** Offset 0x0087 - KTI CRC Mode - Select KTI CRC Mode + KTI CRC Mode. 0: 16bit, 1: 32bit, 2: Auto(Default) 0:16bit, 1:32bit, 2:Auto **/ UINT8 KtiCrcMode; /** Offset 0x0088 - KTI CPU Socket Hotplug - Enable or Disable KTI CPU Socket Hotplug + Enable or Disable(Default) KTI CPU Socket Hotplug $EN_DIS **/ UINT8 KtiCpuSktHotPlugEn; /** Offset 0x0089 - KTI CPU Socket HotPlug Topology - Select KTI CPU Socket HotPlug Topology + KTI CPU Socket HotPlug Topology. 0: 4 Socket(Default), 1: 8 Socket 0:4Socket, 1:8Socket **/ UINT8 KtiCpuSktHotPlugTopology; /** Offset 0x008A - KTI SKU Mismatch Check - Enable or Disable KTI SKU Mismatch Check + Enable(Default) or Disable KTI SKU Mismatch Check $EN_DIS **/ UINT8 KtiSkuMismatchCheck; /** Offset 0x008B - IRQ Threshold - Select IRQ Threshold + IRQ Threshold. 0: Disable, 1: Auto(Default), 2: Low, 3: Medium, 4: High 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High **/ UINT8 IrqThreshold; -/** Offset 0x008C - IRQ Threshold - Enable or Disable +/** Offset 0x008C - TOR threshold - Loctorem threshold normal + TOR threshold - Loctorem threshold normal. 0: Disable, 1: Auto(Default), + 2: Low, 3: Medium, 4: High 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High **/ UINT8 TorThresLoctoremNorm; /** Offset 0x008D - TOR threshold - Loctorem threshold empty - Select TOR threshold - Loctorem threshold empty + TOR threshold - Loctorem threshold empty. 0: Disable, 1: Auto(Default), + 2: Low, 3: Medium, 4: High 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High **/ UINT8 TorThresLoctoremEmpty; /** Offset 0x008E - MBA BW Calibration - MBA BW Calibration setting + MBA BW Calibration setting. 0: Linear, 1: Biased, 2: Legacy, 3: Auto(Default) 0:Linear, 1:Biased, 2:Legacy, 3:Auto **/ UINT8 MbeBwCal; /** Offset 0x008F - TSC Sync in Sockets - Enable or Disable TSC Sync in Sockets + TSC Sync in Sockets. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 TscSyncEn; /** Offset 0x0090 - HA A to S directory optimization - Enable or Disable HA A to S directory optimization + HA A to S directory optimization. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 StaleAtoSOptEn; /** Offset 0x0091 - LLC Deadline Allocation - Enable or Disable LLC Deadline Allocation + Enable(Default) or Disable LLC Deadline Allocation $EN_DIS **/ UINT8 LLCDeadLineAlloc; /** Offset 0x0092 - Split Lock - Enable or Disable Split Lock + Split Lock. 0: Disable(Default), 1: Enable, 2: Auto **/ UINT8 SplitLock; /** Offset 0x0093 - MMCFG Base Address - Setup MMCFG Base Address - 0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6:Auto + MMCFG Base Address. 0: 1GB, 1: 1.5GB, 2: 1.75GB, 3: 2GB, 4: 2.25GB, 5: 3GB, 6: + Auto(Default) + 0:1GB, 1:1.5GB, 2:1.75GB, 3:2GB, 4:2.25GB, 5:3GB, 6:Auto **/ UINT8 mmCfgBase; /** Offset 0x0094 - MMCFG Size - Select MMCFG Size - 0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6: Auto + Select MMCFG Size. 0: 64MB, 1: 128MB, 2: 256MB, 3: 512MB, 4: 1GB, 5: 2GB, 6: + Auto(Default) + 0:64MB, 1:128MB, 2:256MB, 3:512MB, 4:1GB, 5:2GB, 6: Auto **/ UINT8 mmCfgSize; @@ -376,36 +384,36 @@ UINT8 UnusedUpdSpace0[3]; /** Offset 0x0098 - MMIO High Base Address - MMIO High Base Address, a hex number for Bit[51:32] + MMIO High Base Address, a hex number for Bit[51:32]. Default: 0x6 (Gives 0x200) **/ UINT32 mmiohBase; /** Offset 0x009C - CPU Physical Address Limit - CPU Physical Address Limit + Enable(Default) or Disable CPU Physical Address Limit 0:Disable, 1:Enable **/ UINT8 CpuPaLimit; /** Offset 0x009D - High Gap - Enable or Disable High Gap + Enable or Disable(Default) High Gap $EN_DIS **/ UINT8 highGap; /** Offset 0x009E - MMIO High Size MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space - per CPU. Range 1-1024 + per CPU. Range 1-1024, Default: 3 **/ UINT16 mmiohSize; -/** Offset 0x00A0 - } TYPE:{Combo - Enable or Disable +/** Offset 0x00A0 - ISOC + Enable(Default) or Disable ISOC $EN_DIS **/ UINT8 isocEn; /** Offset 0x00A1 - DCA - Enable or Disable DCA + Enable or Disable(Default) DCA $EN_DIS **/ UINT8 dcaEn; @@ -414,121 +422,115 @@ **/ UINT8 UnusedUpdSpace1[2]; -/** Offset 0x00A4 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00A4 - BoardTypeBitmask + Board Type Bitmask. Default: 0x1 **/ UINT32 BoardTypeBitmask; -/** Offset 0x00A8 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00A8 - AllLanesPtr + Pointer to array of ALL_LANES_EPARAM_LINK_INFO **/ UINT32 AllLanesPtr; -/** Offset 0x00AC - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00AC - PerLanePtr + Pointer to array of PER_LANE_EPARAM_LINK_INFO **/ UINT32 PerLanePtr; -/** Offset 0x00B0 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00B0 - AllLanesSizeOfTable + Number of elements in AllLanesPtr array. **/ UINT32 AllLanesSizeOfTable; -/** Offset 0x00B4 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00B4 - PerLaneSizeOfTable + Number of elements in PerLanePtr array. **/ UINT32 PerLaneSizeOfTable; -/** Offset 0x00B8 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00B8 - WaitTimeForPSBP + Number of milliseconds to wait for remote CPUs to initialize. Default: 30 sec **/ UINT32 WaitTimeForPSBP; -/** Offset 0x00BC - } TYPE:{Combo - Enable or Disable +/** Offset 0x00BC - IsKtiNvramDataReady + IsKtiNvramDataReady. Default: Disable $EN_DIS **/ UINT8 IsKtiNvramDataReady; -/** Offset 0x00BD - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00BD - BoardId + Board ID **/ UINT8 BoardId; -/** Offset 0x00BE - } TYPE:{Combo - Enable or Disable +/** Offset 0x00BE - WaSerializationEn + Enable(Default) or Disable BIOS serialization WA $EN_DIS **/ UINT8 WaSerializationEn; -/** Offset 0x00BF - } TYPE:{Combo - Enable or Disable +/** Offset 0x00BF - KtiInEnableMktme + Enable(Default) or Disable MkTme status decides D2Kti feature state $EN_DIS **/ UINT8 KtiInEnableMktme; -/** Offset 0x00C0 - Usage type for Processor VmxEnable Function - Processor VmxEnable Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +/** Offset 0x00C0 - Processor VmxEnable Function + Enable(Default) or Disable Processor VmxEnable Function $EN_DIS **/ UINT8 VmxEnable; -/** Offset 0x00C1 - Usage type for Processor X2apic Function - Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +/** Offset 0x00C1 - Processor X2apic Function + Enable(Default) or Disable Processor X2apic Function + $EN_DIS **/ UINT8 X2apic; -/** Offset 0x00C2 - Usage type for DDR frequency limit - Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +/** Offset 0x00C2 - DDR frequency limit + Enable(Default) or Disable Processor X2apic Function **/ UINT8 DdrFreqLimit; -/** Offset 0x00C3 - Usage type for Memory Serial Debug Message Level - Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +/** Offset 0x00C3 - Memory Serial Debug Message Level + Enable(Default) or Disable Processor X2apic Function **/ UINT8 serialDebugMsgLvl; #if CONFIG(HAVE_FSPM_DIMM_WATERMARK_OPTION) /** Offset 0x00C4 - Usage type for Memory Refresh Watermark - Select Memory Refresh Watermark, 0: Auto (default), 1: High, 2: Low + Select Memory Refresh Watermark, 0: Auto, 1: High(Default), 2: Low **/ UINT8 MemRefreshWaterMark; #endif /** Offset 0x00C5 - IIO ConfigIOU0 ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU0[8]; /** Offset 0x00CD - IIO ConfigIOU1 ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU1[8]; /** Offset 0x00D5 - IIO ConfigIOU2 ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU2[8]; /** Offset 0x00DD - IIO ConfigIOU3 ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU3[8]; /** Offset 0x00E5 - IIO ConfigIOU4 ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU4[8]; @@ -536,178 +538,182 @@ **/ UINT8 UnusedUpdSpace2[3]; -/** Offset 0x00F0 - Usage type for IIO PCIE Config Table Ptr - IIO PCIE Config Table Ptr +/** Offset 0x00F0 - IIO PCIE Config Table Ptr + Pointer to array of UPD_IIO_PCIE_PORT_CONFIG **/ UINT32 IioPcieConfigTablePtr; -/** Offset 0x00F4 - Usage type for IIO PCIE Config Table Number - IIO PCIE Config Table Number +/** Offset 0x00F4 - IIO PCIE Config Table Number + Number of elements in IioPcieConfigTablePtr array. **/ UINT32 IioPcieConfigTableNumber; -/** Offset 0x00F8 - Usage type for IIO PCIE Root Port Enable or Disable - IIO PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, - the value is 0x00 +/** Offset 0x00F8 - IIO PCIE Root Port Enable + Enable(Default) or Disable IIO PCH rootport **/ UINT8 IIOPcieRootPortEnable; -/** Offset 0x00F9 - Usage type for IIO DeEmphasis - IIO DeEmphasis +/** Offset 0x00F9 - IIO DeEmphasis + IIO DeEmphasis. Default: 0x1 **/ UINT8 DeEmphasis; -/** Offset 0x00FA - Usage type for IIO PCIE Root Port link speed - IIO root port link speed +/** Offset 0x00FA - IIO PCIe Root Port Link Speed + IIO PCIe Root Port Link Speed. 0: Auto(Default), 1: Gen1, 2: Gen2, 3: Gen3, 4: Gen4 + 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3, 4:Gen4 **/ UINT8 IIOPciePortLinkSpeed; -/** Offset 0x00FB - Usage type for IIO PCIE Root Port Max Payload - IIO Root Port Max Payload +/** Offset 0x00FB - IIO PCIe Root Port Max Payload + IIO PCIe Root Port Max Payload. 0: 128B, 1: 256B, 2: 512B, 7: Auto(Default) + 0:128B, 1: 256B, 2:512B, 7:Auto **/ UINT8 IIOPcieMaxPayload; -/** Offset 0x00FC - Usage type for IIO DfxDnTxPreset - IIO DfxDnTxPreset +/** Offset 0x00FC - IIO DfxDnTxPreset + IIO Downstream Transmitter Preset. Default: Auto(0xFF), otherwise preset 0-10 **/ UINT8 DfxDnTxPreset; -/** Offset 0x00FD - Usage type for IIO DfxRxPreset - IIO DfxRxPreset +/** Offset 0x00FD - IIO DfxRxPreset + IIO Downstream Reciever Preset. Default: Auto(0xFF), otherwise preset 0-10 **/ UINT8 DfxRxPreset; -/** Offset 0x00FE - Usage type for IIO DfxUpTxPreset - IIO DfxUpTxPreset +/** Offset 0x00FE - IIO DfxUpTxPreset + IIO Upstream Transmitter Preset. Default: Auto(0xFF), otherwise preset 0-10 **/ UINT8 DfxUpTxPreset; -/** Offset 0x00FF - Usage type for IIO PcieCommonClock - IIO PcieCommonClock +/** Offset 0x00FF - IIO PCIe Common Clock + IIO PCIe Common Clock. 0: Disable, 1: Enable(Default), 2: Auto **/ UINT8 PcieCommonClock; -/** Offset 0x0100 - Usage type for IIO NtbPpd - IIO NtbPpd +/** Offset 0x0100 - IIO Non-Transparent Port Definition + IIO Non-Transparent Port Definition. 0: Transparent(Default), 1: Non-Transparent + Bridge, 2: Non-Transparent Root Port **/ UINT8 NtbPpd; -/** Offset 0x0101 - Usage type for IIO NtbBarSizeOverride - IIO NtbBarSizeOverride +/** Offset 0x0101 - IIO Non-Transparent Bridge BAR Size Override + Enable or Disable(Default) IIO Non-Transparent Bridge BAR Size Override. **/ UINT8 NtbBarSizeOverride; -/** Offset 0x0102 - Usage type for IIO NtbSplitBar - IIO NtbSplitBar +/** Offset 0x0102 - IIO Non-Transparent Bridge Split BAR Mode + Enable or Disable(Default) IIO Non-Transparent Bridge Split BAR Mode **/ UINT8 NtbSplitBar; -/** Offset 0x0103 - Usage type for IIO NtbBarSizeImBar1 - IIO NtbBarSizeImBar1 +/** Offset 0x0103 - IIO NtbBarSizeImBar1 + IIO NtbBarSizeImBar1. Default: 0x16 **/ UINT8 NtbBarSizeImBar1; -/** Offset 0x0104 - Usage type for IIO NtbBarSizeImBar2 - IIO PNtbBarSizeImBar2 +/** Offset 0x0104 - IIO NtbBarSizeImBar2 + IIO PNtbBarSizeImBar2. Default: 0x16 **/ UINT8 NtbBarSizeImBar2; -/** Offset 0x0105 - Usage type for IIO NtbBarSizeImBar2_0 - IIO PNtbBarSizeImBar2_0 +/** Offset 0x0105 - IIO NtbBarSizeImBar2_0 + IIO PNtbBarSizeImBar2_0. Default: 0x0C **/ UINT8 NtbBarSizeImBar2_0; -/** Offset 0x0106 - Usage type for IIO NtbBarSizeImBar2_1 - IIO NtbBarSizeImBar2_1 +/** Offset 0x0106 - IIO NtbBarSizeImBar2_1 + IIO NtbBarSizeImBar2_1. Default: 0x0C **/ UINT8 NtbBarSizeImBar2_1; -/** Offset 0x0107 - Usage type for IIO NtbBarSizeEmBarSZ1 - IIO NtbBarSizeEmBarSZ1 +/** Offset 0x0107 - IIO NtbBarSizeEmBarSZ1 + IIO NtbBarSizeEmBarSZ1. . Default: 0x16 **/ UINT8 NtbBarSizeEmBarSZ1; -/** Offset 0x0108 - Usage type for IIO NtbBarSizeEmBarSZ2 - IIO NtbBarSizeEmBarSZ2 +/** Offset 0x0108 - IIO NtbBarSizeEmBarSZ2 + IIO NtbBarSizeEmBarSZ2. . Default: 0x16 **/ UINT8 NtbBarSizeEmBarSZ2; -/** Offset 0x0109 - Usage type for IIO NtbBarSizeEmBarSZ2_0 - IIO NtbBarSizeEmBarSZ2_0 +/** Offset 0x0109 - IIO NtbBarSizeEmBarSZ2_0 + IIO NtbBarSizeEmBarSZ2_0. . Default: 0x0C **/ UINT8 NtbBarSizeEmBarSZ2_0; -/** Offset 0x010A - Usage type for IIO NtbBarSizeEmBarSZ2_1 - IIO NtbBarSizeEmBarSZ2_1 +/** Offset 0x010A - IIO NtbBarSizeEmBarSZ2_1 + IIO NtbBarSizeEmBarSZ2_1. . Default: 0x0C **/ UINT8 NtbBarSizeEmBarSZ2_1; -/** Offset 0x010B - Usage type for IIO NtbXlinkCtlOverride - IIO NtbXlinkCtlOverride +/** Offset 0x010B - IIO Non-Transparent Cross Link Override + IIO Non-Transparent Cross Link Override. 1:Operate as RP, 2:Operate as NTB-NTB (NT + Port), 3:Operate as NTB-> DSP (NTB EP)(Default) **/ UINT8 NtbXlinkCtlOverride; -/** Offset 0x010C - Usage type for IIO VT-D Function - IIO VT-D Function, if supported, the value is 0x01, if not supported, the value is 0x00 +/** Offset 0x010C - VT-d Support + Enable or Disable(Default) VT-d Support **/ UINT8 VtdSupport; -/** Offset 0x010D - Usage type for IIO Pcie Port Hide +/** Offset 0x010D - IIO PCIe Port Hide Hide or visible for IIO Pcie Port, 1 : Hide, 0 : Visible **/ UINT8 PEXPHIDE; -/** Offset 0x010E - Usage type for IIO Pcie Port Menu Hide - Hide or visible for IIO Pcie Port Menu, 1 : Hide, 0 : Visible +/** Offset 0x010E - IIO Pcie Port Menu Hide + Hide or visible for IIO PCIe Port Menu, 1 : Hide, 0 : Visible **/ UINT8 HidePEXPMenu; /** Offset 0x010F - PchSirqMode - Enable or Disable PchSirqMode + PchSirqMode. 0: Quiet Mode(Default) 1: Continuous Mode **/ UINT8 PchSirqMode; /** Offset 0x0110 - PchAdrEn - Enable or Disable PchAdr + PchAdr 0:PLATFORM POR, 1:FORCE ENABLE(Default), 2:FORCE DISABLE **/ UINT8 PchAdrEn; /** Offset 0x0111 - ThermalDeviceEnable - Enable or Disable ThermalDeviceEnable with PCI or ACPI mode + Thermal Device Mode. 0: Disable, 1: Enabled in PCI mode, 2: Enabled in ACPI + mode(Default) **/ UINT8 ThermalDeviceEnable; -/** Offset 0x0112 - } TYPE:{Combo - Root port swapping based on device connection status : TRUE or FALSE +/** Offset 0x0112 - PchPcieRootPortFunctionSwap + Root port swapping based on device connection status : TRUE(Default) or FALSE TRUE : 0x01, FALSE : 0x00 **/ UINT8 PchPcieRootPortFunctionSwap; /** Offset 0x0113 - PCH PCIE PLL Ssc Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC - of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF + of 2.0%), Auto : 0xFE(Set to hardware default), Disable(Default) : 0xFF **/ UINT8 PchPciePllSsc; -/** Offset 0x0114 - Usage type for PCH PCIE Root Port Index +/** Offset 0x0114 - PCH PCIE Root Port Index Index assigned to every PCH PCIE Root Port **/ UINT8 PchPciePortIndex[20]; -/** Offset 0x0128 - Usage type for PCH PCIE Root Port Enable or Disable - 0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, - the value is 0x00 +/** Offset 0x0128 - PCH PCIE Root Port Enable or Disable + 0-19: PCH rootport, if port is enabled(Default), the value is 0x01, if the port + is disabled, the value is 0x00 **/ UINT8 PchPcieForceEnable[20]; -/** Offset 0x013C - Usage type for PCH PCIE Root Port Link Speed - 0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie - Gen2 Speed, 0x03 : Pcie Gen3 Speed +/** Offset 0x013C - PCH PCIE Root Port Link Speed + 0-19: PCH rootport, 0x00 : Pcie Auto Speed(Default), 0x01 : Pcie Gen1 Speed, 0x02 + : Pcie Gen2 Speed, 0x03 : Pcie Gen3 Speed **/ UINT8 PchPciePortLinkSpeed[20]; /** Offset 0x0150 - PchDciEn - Enable or Disable Pch DciEn + Enable or Disable(Default) PCH DCI **/ UINT8 PchDciEn; @@ -717,7 +723,7 @@ UINT8 MeUmaEnable; /** Offset 0x0152 - SerialIoUartDebugEnable - Enable SerialIo Uart debug library in FSP. + Enable(Default) or Disable SerialIo Uart debug library in FSP. 0:Disable, 1:Enable **/ UINT8 SerialIoUartDebugEnable; -- To view, visit https://review.coreboot.org/c/coreboot/+/46609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc75f39f8f7a6d47690464dd4e5194f6e2ba12a8 Gerrit-Change-Number: 46609 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/intel/{cnl,icl}: Enable support to configure interrupt overrides
by Aamir Bohra (Code Review) 09 Nov '20

09 Nov '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34517 ) Change subject: soc/intel/{cnl,icl}: Enable support to configure interrupt overrides ...................................................................... soc/intel/{cnl,icl}: Enable support to configure interrupt overrides This implementation selects SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE config. It would enable support from SOC to dynamically populate the PCI IRQ routing table based on the devices enabled from the mainboard. And pass the same to FSP to configure the IRQ entries in ITSS PIRx register. The same table can be used to generate the ACPI PIRQ mapping table. Change-Id: I8464d5797cb4ff85406c06e1ecb92c7207380acd Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/icelake/Kconfig 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/34517/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f859cd5..0283f2c 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -97,6 +97,7 @@ select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 5dca44b..79a19ee 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -51,6 +51,7 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SSE2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8464d5797cb4ff85406c06e1ecb92c7207380acd Gerrit-Change-Number: 34517 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: src/soc/intel/{cnl,icl}: Add support to configure interrupt overrides
by Aamir Bohra (Code Review) 09 Nov '20

09 Nov '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34349 ) Change subject: src/soc/intel/{cnl,icl}: Add support to configure interrupt overrides ...................................................................... src/soc/intel/{cnl,icl}: Add support to configure interrupt overrides Change-Id: If55701b7ad292e3357d0b419bb6168bd2c3e4030 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/fsp_params.c 4 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/34349/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 4235b7a..c8dfc13 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -97,6 +97,7 @@ select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index fe5b3dd..4eef58e 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -18,6 +18,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> #include <soc/intel/common/vbt.h> @@ -408,6 +409,11 @@ configure_gspi_cs(i, config, &params->SerialIoSpiCsPolarity[0], NULL, NULL); #endif + + /* Fill interrupt config override */ +#if CONFIG(SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) + get_irq_table((void *)params->DevIntConfigPtr, &params->NumOfDevIntConfig); +#endif } /* Mainboard GPIO Configuration */ diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index a2261a0..d31c8eb 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -51,6 +51,7 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET select SSE2 diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index ed86c27..ee45024 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -18,6 +18,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/xdci.h> #include <soc/intel/common/vbt.h> @@ -241,6 +242,12 @@ params->Heci3Enabled = config->Heci3Enabled; params->Device4Enable = config->Device4Enable; + + /* Fill interrupt config override */ +#if CONFIG(SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) + get_irq_table((void *)params->DevIntConfigPtr, &params->NumOfDevIntConfig); +#endif + } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If55701b7ad292e3357d0b419bb6168bd2c3e4030 Gerrit-Change-Number: 34349 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 16

Change in coreboot[master]: src/soc/intel/*/include: Get list of devices that needs IRQ programming
by Aamir Bohra (Code Review) 09 Nov '20

09 Nov '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34348 ) Change subject: src/soc/intel/*/include: Get list of devices that needs IRQ programming ...................................................................... src/soc/intel/*/include: Get list of devices that needs IRQ programming This implementation adds SOC function that returns list of PCI devices that needs IRQ programming. This list can be further used to program IRQ for these devices. Change-Id: I3482172f6cb549dece23e2b8b09b8b79578b83b7 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/irq.c M src/soc/intel/icelake/Makefile.inc A src/soc/intel/icelake/irq.c 4 files changed, 150 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34348/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 8a4a8b7..ed0d09c 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += graphics.c ramstage-y += gspi.c ramstage-y += i2c.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) += irq.c ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += me.c diff --git a/src/soc/intel/cannonlake/irq.c b/src/soc/intel/cannonlake/irq.c new file mode 100644 index 0000000..ce0e539 --- /dev/null +++ b/src/soc/intel/cannonlake/irq.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/irq.h> +#include <soc/pci_devs.h> +#include <stdint.h> + +static const int irq_devices[] = { + PCH_DEVFN_HDA, + PCH_DEVFN_SMBUS, + PCH_DEVFN_GBE, + PCH_DEVFN_TRACEHUB, + PCH_DEVFN_PCIE9, + PCH_DEVFN_PCIE10, + PCH_DEVFN_PCIE11, + PCH_DEVFN_PCIE12, + PCH_DEVFN_PCIE13, + PCH_DEVFN_PCIE14, + PCH_DEVFN_PCIE15, + PCH_DEVFN_PCIE16, + PCH_DEVFN_PCIE1, + PCH_DEVFN_PCIE2, + PCH_DEVFN_PCIE3, + PCH_DEVFN_PCIE4, + PCH_DEVFN_PCIE5, + PCH_DEVFN_PCIE6, + PCH_DEVFN_PCIE7, + PCH_DEVFN_PCIE8, + PCH_DEVFN_EMMC, + PCH_DEVFN_SATA, + PCH_DEVFN_CSE, + PCH_DEVFN_CSE_2, + PCH_DEVFN_CSE_IDER, + PCH_DEVFN_CSE_KT, + PCH_DEVFN_CSE_3, + PCH_DEVFN_CSE_4, + PCH_DEVFN_XHCI, + PCH_DEVFN_USBOTG, + PCH_DEVFN_CNViWIFI, + PCH_DEVFN_SDCARD, + PCH_DEVFN_ISH, + PCH_DEVFN_THERMAL, + PCH_DEVFN_UFS, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_UART2, + PCH_DEVFN_I2C5, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_GSPI2, +}; + +const int *get_soc_irq_devices(size_t *size) +{ + *size = ARRAY_SIZE(irq_devices); + return irq_devices; +} diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index cd02934..2973e15 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -43,6 +43,7 @@ ramstage-y += graphics.c ramstage-y += gspi.c ramstage-y += i2c.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) += irq.c ramstage-y += lockdown.c ramstage-y += memmap.c ramstage-y += p2sb.c diff --git a/src/soc/intel/icelake/irq.c b/src/soc/intel/icelake/irq.c new file mode 100644 index 0000000..ce0e539 --- /dev/null +++ b/src/soc/intel/icelake/irq.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/irq.h> +#include <soc/pci_devs.h> +#include <stdint.h> + +static const int irq_devices[] = { + PCH_DEVFN_HDA, + PCH_DEVFN_SMBUS, + PCH_DEVFN_GBE, + PCH_DEVFN_TRACEHUB, + PCH_DEVFN_PCIE9, + PCH_DEVFN_PCIE10, + PCH_DEVFN_PCIE11, + PCH_DEVFN_PCIE12, + PCH_DEVFN_PCIE13, + PCH_DEVFN_PCIE14, + PCH_DEVFN_PCIE15, + PCH_DEVFN_PCIE16, + PCH_DEVFN_PCIE1, + PCH_DEVFN_PCIE2, + PCH_DEVFN_PCIE3, + PCH_DEVFN_PCIE4, + PCH_DEVFN_PCIE5, + PCH_DEVFN_PCIE6, + PCH_DEVFN_PCIE7, + PCH_DEVFN_PCIE8, + PCH_DEVFN_EMMC, + PCH_DEVFN_SATA, + PCH_DEVFN_CSE, + PCH_DEVFN_CSE_2, + PCH_DEVFN_CSE_IDER, + PCH_DEVFN_CSE_KT, + PCH_DEVFN_CSE_3, + PCH_DEVFN_CSE_4, + PCH_DEVFN_XHCI, + PCH_DEVFN_USBOTG, + PCH_DEVFN_CNViWIFI, + PCH_DEVFN_SDCARD, + PCH_DEVFN_ISH, + PCH_DEVFN_THERMAL, + PCH_DEVFN_UFS, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_UART2, + PCH_DEVFN_I2C5, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_GSPI2, +}; + +const int *get_soc_irq_devices(size_t *size) +{ + *size = ARRAY_SIZE(irq_devices); + return irq_devices; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3482172f6cb549dece23e2b8b09b8b79578b83b7 Gerrit-Change-Number: 34348 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/intel/xeon_sp: Add common chip.h
by Marc Jones (Code Review) 09 Nov '20

09 Nov '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45969 ) Change subject: soc/intel/xeon_sp: Add common chip.h ...................................................................... soc/intel/xeon_sp: Add common chip.h Add a common chip.h which includes the configured Xeon specific header file. Rename the Xeon specific header files. Common files should call chip.h while Xeon silicon specific files call their named header file. This should allow addition of new Xeon silicon. This change prepares for additional common code changes. Change-Id: I1c5e3dec3ee24328b1e987fdae856e9e77fe5499 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/mainboard/ocp/deltalake/romstage.c A src/soc/intel/xeon_sp/chip.h M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/cpx/soc_acpi.c M src/soc/intel/xeon_sp/lpc.c M src/soc/intel/xeon_sp/skx/acpi.c M src/soc/intel/xeon_sp/skx/cpu.c M src/soc/intel/xeon_sp/skx/romstage.c M src/soc/intel/xeon_sp/skx/soc_acpi.c 11 files changed, 29 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/45969/1 diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 71a26c8..a711601 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -8,7 +8,7 @@ #include <soc/romstage.h> #include <string.h> -#include "chip.h" +#include <soc/intel/xeon_sp/chip.h> #include "ipmi.h" #include "vpd.h" diff --git a/src/soc/intel/xeon_sp/chip.h b/src/soc/intel/xeon_sp/chip.h new file mode 100644 index 0000000..77d15643 --- /dev/null +++ b/src/soc/intel/xeon_sp/chip.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_COMMON_CHIP_H_ +#define _SOC_COMMON_CHIP_H_ + +/* Common chip.h includes the approprate soc chip.h. */ + +#if (CONFIG(SOC_INTEL_SKYLAKE_SP)) + #include "skx/skx.h" +#endif + +#if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) + #include "cpx/cpx.h" +#endif + +#endif diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 93cd8ed..ea61c58 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -23,7 +23,7 @@ #include <soc/pm.h> #include <soc/soc_util.h> -#include "chip.h" +#include "cpx.h" static int acpi_sci_irq(void) { diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index eb8c0eb..25ad74b 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -15,7 +15,8 @@ #include <soc/cpu.h> #include <soc/msr.h> #include <soc/soc_util.h> -#include "chip.h" + +#include "cpx.h" static const void *microcode_patch; diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index a198c99..ee58313 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -4,7 +4,8 @@ #include <fsp/api.h> #include <soc/romstage.h> #include <soc/pci_devs.h> -#include "chip.h" + +#include "cpx.h" void __weak mainboard_memory_init_params(FSPM_UPD *mupd) { diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 4850855..038d7ae 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -17,7 +17,7 @@ #include <soc/pm.h> #include <soc/soc_util.h> -#include "chip.h" +#include "cpx.h" /* Check if the common/acpi weak function can be used */ unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index 3169545..5edfa4b 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -7,7 +7,7 @@ #include <soc/iomap.h> #include <soc/pcr_ids.h> -#include <chip.h> +#include "chip.h" static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = { { 0, 0 } diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index cbafbdb..8b2f9a1 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -15,7 +15,7 @@ #include <soc/pm.h> #include <string.h> -#include "chip.h" +#include "skx.h" acpi_cstate_t *soc_get_cstate_map(size_t *entries) { diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c index ea9f531..3e7aeb3 100644 --- a/src/soc/intel/xeon_sp/skx/cpu.c +++ b/src/soc/intel/xeon_sp/skx/cpu.c @@ -10,7 +10,8 @@ #include <soc/cpu.h> #include <soc/soc_util.h> #include <assert.h> -#include "chip.h" + +#include "skx.h" static const config_t *chip_config = NULL; diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c index a1c370d..93a6cd0 100644 --- a/src/soc/intel/xeon_sp/skx/romstage.c +++ b/src/soc/intel/xeon_sp/skx/romstage.c @@ -6,7 +6,7 @@ #include <soc/romstage.h> #include <soc/soc_util.h> -#include "chip.h" +#include "skx.h" void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index c116506..fedb83c 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -18,7 +18,7 @@ #include <soc/pm.h> #include <soc/soc_util.h> -#include "chip.h" +#include "skx.h" /* Check if the common/acpi weak function can be used */ unsigned long acpi_fill_mcfg(unsigned long current) -- To view, visit https://review.coreboot.org/c/coreboot/+/45969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c5e3dec3ee24328b1e987fdae856e9e77fe5499 Gerrit-Change-Number: 45969 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: soc/intel/xeon_sp/skx: Make devicetree config and ops generic
by Marc Jones (Code Review) 09 Nov '20

09 Nov '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45848 ) Change subject: soc/intel/xeon_sp/skx: Make devicetree config and ops generic ...................................................................... soc/intel/xeon_sp/skx: Make devicetree config and ops generic Prepare for common ACPI and de-duplication. Change the mainboard devicetree so that: soc_intel_xeon_sp_skx_ops -> soc_intel_xeon_sp_ops soc_intel_xeon_sp_skx_config -> soc_intel_xeon_sp_config This allows for common code between skx and cpx in future changes. Change-Id: Ib4509d54371aca02cc96f7a18821fac8ce5404aa Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/mainboard/ocp/tiogapass/devicetree.cb M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/skx/chip.h M src/soc/intel/xeon_sp/skx/soc_acpi.c 4 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/45848/1 diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 33f4090..01a6467 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -chip soc/intel/xeon_sp/skx +chip soc/intel/xeon_sp register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 845d7cb..589ca03 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -575,7 +575,7 @@ mainboard_silicon_init_params(silupd); } -struct chip_operations soc_intel_xeon_sp_skx_ops = { +struct chip_operations soc_intel_xeon_sp_ops = { CHIP_NAME("Intel Skylake-SP") .enable_dev = soc_enable_dev, .init = soc_init, diff --git a/src/soc/intel/xeon_sp/skx/chip.h b/src/soc/intel/xeon_sp/skx/chip.h index adb70e5..c3966e5 100644 --- a/src/soc/intel/xeon_sp/skx/chip.h +++ b/src/soc/intel/xeon_sp/skx/chip.h @@ -7,7 +7,7 @@ #include <intelblocks/cfg.h> #include <soc/irq.h> -struct soc_intel_xeon_sp_skx_config { +struct soc_intel_xeon_sp_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; @@ -74,7 +74,7 @@ uint32_t tcc_offset; }; -typedef struct soc_intel_xeon_sp_skx_config config_t; +typedef struct soc_intel_xeon_sp_config config_t; /* soc acpi function prototypes. To be removed when acpi.c is replaced by common/acpi.c */ void uncore_inject_dsdt(void); diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index c116506..8139dc4 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -586,7 +586,7 @@ acpi_slit_t *slit; acpi_dmar_t *dmar; - const struct soc_intel_xeon_sp_skx_config *const config = config_of(device); + const struct soc_intel_xeon_sp_config *const config = config_of(device); /* SRAT */ current = ALIGN(current, 8); -- To view, visit https://review.coreboot.org/c/coreboot/+/45848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4509d54371aca02cc96f7a18821fac8ce5404aa Gerrit-Change-Number: 45848 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: soc/intel/xeon_sp/cpx: Make devicetree config and ops generic
by Marc Jones (Code Review) 09 Nov '20

09 Nov '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45849 ) Change subject: soc/intel/xeon_sp/cpx: Make devicetree config and ops generic ...................................................................... soc/intel/xeon_sp/cpx: Make devicetree config and ops generic Prepare for common ACPI and de-duplication. Change the mainboard devicetree so that: soc_intel_xeon_sp_cpx_ops -> soc_intel_xeon_sp_ops soc_intel_xeon_sp_cpx_config -> soc_intel_xeon_sp_config This allows for common code between cpx and skx in future changes. Change-Id: Iecbe94a0dd395688d0c15e3f67f703e5ac4caa23 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/mainboard/intel/cedarisland_crb/devicetree.cb M src/mainboard/ocp/deltalake/devicetree.cb M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/chip.h M src/soc/intel/xeon_sp/cpx/soc_acpi.c 5 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/45849/1 diff --git a/src/mainboard/intel/cedarisland_crb/devicetree.cb b/src/mainboard/intel/cedarisland_crb/devicetree.cb index a82f022..9bca7b4 100644 --- a/src/mainboard/intel/cedarisland_crb/devicetree.cb +++ b/src/mainboard/intel/cedarisland_crb/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/intel/xeon_sp/cpx +chip soc/intel/xeon_sp device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index d51391d..0883244 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later -chip soc/intel/xeon_sp/cpx +chip soc/intel/xeon_sp register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 5ee7f6c..41bed62 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -609,7 +609,7 @@ p2sb_unhide(); } -struct chip_operations soc_intel_xeon_sp_cpx_ops = { +struct chip_operations soc_intel_xeon_sp_ops = { CHIP_NAME("Intel Cooperlake-SP") .enable_dev = chip_enable_dev, .init = chip_init, diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/chip.h index e7c146c..3dcc406 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.h +++ b/src/soc/intel/xeon_sp/cpx/chip.h @@ -29,7 +29,7 @@ PcieGen3 } pcie_link_speed; -struct soc_intel_xeon_sp_cpx_config { +struct soc_intel_xeon_sp_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; @@ -97,7 +97,7 @@ uint32_t tcc_offset; }; -typedef struct soc_intel_xeon_sp_cpx_config config_t; +typedef struct soc_intel_xeon_sp_config config_t; /* soc acpi function prototypes. To be removed when acpi.c is replaced by common/acpi.c */ void cpx_generate_p_state_entries(int core, int cores_per_package); diff --git a/src/soc/intel/xeon_sp/cpx/soc_acpi.c b/src/soc/intel/xeon_sp/cpx/soc_acpi.c index 1aa1192..63f82ae 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/cpx/soc_acpi.c @@ -690,7 +690,7 @@ acpi_slit_t *slit; acpi_dmar_t *dmar; - const struct soc_intel_xeon_sp_cpx_config *const config = config_of(device); + const struct soc_intel_xeon_sp_config *const config = config_of(device); /* SRAT */ current = ALIGN(current, 8); -- To view, visit https://review.coreboot.org/c/coreboot/+/45849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iecbe94a0dd395688d0c15e3f67f703e5ac4caa23 Gerrit-Change-Number: 45849 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 10

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