coreboot-gerrit October 2020

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Change in coreboot[master]: sb/intel/lynxpoint/acpi: Statically define _PRW values
by Angel Pons (Code Review) 13 Nov '20

13 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46780 ) Change subject: sb/intel/lynxpoint/acpi: Statically define _PRW values ...................................................................... sb/intel/lynxpoint/acpi: Statically define _PRW values In order for ACPI deduplication to be reproducible, the `ISLP` method needs to disappear. Replace the _PRW methods with a name and a macro. Change-Id: Id0a46965b66f1a70e8f8868af01a535207c9f5c7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/audio.asl M src/southbridge/intel/lynxpoint/acpi/pch.asl M src/southbridge/intel/lynxpoint/acpi/usb.asl 3 files changed, 9 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/46780/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/audio.asl b/src/southbridge/intel/lynxpoint/acpi/audio.asl index 98cdac9..43f2150 100644 --- a/src/southbridge/intel/lynxpoint/acpi/audio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/audio.asl @@ -7,15 +7,5 @@ Device (HDEF) { Name (_ADR, 0x001b0000) - - Name (PRWH, Package (){ 0x0d, 3 }) // LPT-H - Name (PRWL, Package (){ 0x6d, 3 }) // LPT-LP - - Method (_PRW, 0) { // Power Resources for Wake - If (\ISLP ()) { - Return (PRWL) - } Else { - Return (PRWH) - } - } + Name (_PRW, Package () { DEFAULT_PRW_VALUE, 3 }) } diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index cb5b823..e683c75 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -2,6 +2,12 @@ /* Intel Lynx Point PCH support */ +#if CONFIG(INTEL_LYNXPOINT_LP) +#define DEFAULT_PRW_VALUE 0x6d +#else +#define DEFAULT_PRW_VALUE 0x0d +#endif + Scope (\) { // Return TRUE if chipset is LynxPoint-LP diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index e807398..fbb7090 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -6,16 +6,7 @@ { Name (_ADR, 0x001d0000) - Name (PRWH, Package (){ 0x0d, 3 }) // LPT-H - Name (PRWL, Package (){ 0x6d, 3 }) // LPT-LP - - Method (_PRW, 0) { // Power Resources for Wake - If (\ISLP ()) { - Return (PRWL) - } Else { - Return (PRWH) - } - } + Name (_PRW, Package () { DEFAULT_PRW_VALUE, 3 }) // Leave USB ports on for to allow Wake from USB @@ -337,16 +328,7 @@ Return () } - Name (PRWH, Package (){ 0x0d, 3 }) // LPT-H - Name (PRWL, Package (){ 0x6d, 3 }) // LPT-LP - - Method (_PRW, 0) { // Power Resources for Wake - If (\ISLP ()) { - Return (PRWL) - } Else { - Return (PRWH) - } - } + Name (_PRW, Package () { DEFAULT_PRW_VALUE, 3 }) // Leave USB ports on for to allow Wake from USB -- To view, visit https://review.coreboot.org/c/coreboot/+/46780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0a46965b66f1a70e8f8868af01a535207c9f5c7 Gerrit-Change-Number: 46780 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/pch/acpi/hda.asl: Rename to `audio.asl`
by Angel Pons (Code Review) 13 Nov '20

13 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46779 ) Change subject: soc/intel/broadwell/pch/acpi/hda.asl: Rename to `audio.asl` ...................................................................... soc/intel/broadwell/pch/acpi/hda.asl: Rename to `audio.asl` This is merely to ease diffing Lynx Point and Broadwell ASL code. Tested with BUILD_TIMELESS=1, Google Buddy does not change. Change-Id: I9f6ab98388d2a2915a48377ebe9e724cfee4b95f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- R src/soc/intel/broadwell/pch/acpi/audio.asl M src/soc/intel/broadwell/pch/acpi/pch.asl 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/46779/1 diff --git a/src/soc/intel/broadwell/pch/acpi/hda.asl b/src/soc/intel/broadwell/pch/acpi/audio.asl similarity index 100% rename from src/soc/intel/broadwell/pch/acpi/hda.asl rename to src/soc/intel/broadwell/pch/acpi/audio.asl diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl index d68fa60..b7d6838 100644 --- a/src/soc/intel/broadwell/pch/acpi/pch.asl +++ b/src/soc/intel/broadwell/pch/acpi/pch.asl @@ -39,7 +39,7 @@ } // High Definition Audio (Azalia) 0:1b.0 -#include "hda.asl" +#include "audio.asl" // ADSP/SST 0:13.0 #include "adsp.asl" -- To view, visit https://review.coreboot.org/c/coreboot/+/46779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f6ab98388d2a2915a48377ebe9e724cfee4b95f Gerrit-Change-Number: 46779 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/pch/acpi: Clean up cosmetics
by Angel Pons (Code Review) 13 Nov '20

13 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46778 ) Change subject: soc/intel/broadwell/pch/acpi: Clean up cosmetics ...................................................................... soc/intel/broadwell/pch/acpi: Clean up cosmetics Use ASL 2.0 syntax where possible and uniformize code style to match the IASL disassembly. Some `Store` in gpio.asl change the binary if touched. Tested with BUILD_TIMELESS=1, Google Buddy does not change. Change-Id: Ic13c081fd7ee2212d851cc14263c1e2fd8970072 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/acpi/adsp.asl M src/soc/intel/broadwell/pch/acpi/ehci.asl M src/soc/intel/broadwell/pch/acpi/globalnvs.asl M src/soc/intel/broadwell/pch/acpi/gpio.asl M src/soc/intel/broadwell/pch/acpi/lpc.asl M src/soc/intel/broadwell/pch/acpi/pch.asl M src/soc/intel/broadwell/pch/acpi/serialio.asl M src/soc/intel/broadwell/pch/acpi/xhci.asl 8 files changed, 217 insertions(+), 231 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/46778/1 diff --git a/src/soc/intel/broadwell/pch/acpi/adsp.asl b/src/soc/intel/broadwell/pch/acpi/adsp.asl index 435db4d..51dd38c 100644 --- a/src/soc/intel/broadwell/pch/acpi/adsp.asl +++ b/src/soc/intel/broadwell/pch/acpi/adsp.asl @@ -25,11 +25,11 @@ Method (_CRS, 0, NotSerialized) { // Update BAR address and length if set in NVS - If (LNotEqual (\S8B0, Zero)) { + If (\S8B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B8A0) CreateDwordField (^RBUF, ^BAR1._BAS, B8A1) - Store (\S8B0, B8A0) - Store (\S8B1, B8A1) + B8A0 = \S8B0 + B8A1 = \S8B1 } Return (RBUF) @@ -37,7 +37,7 @@ Method (_STA, 0, NotSerialized) { - If (LEqual (\S8EN, 0)) { + If (\S8EN == 0) { Return (0x0) } Else { Return (0xF) diff --git a/src/soc/intel/broadwell/pch/acpi/ehci.asl b/src/soc/intel/broadwell/pch/acpi/ehci.asl index c02bc1a..632b19f 100644 --- a/src/soc/intel/broadwell/pch/acpi/ehci.asl +++ b/src/soc/intel/broadwell/pch/acpi/ehci.asl @@ -4,26 +4,25 @@ Device (EHCI) { - Name(_ADR, 0x001d0000) + Name (_ADR, 0x001d0000) Name (_PRW, Package(){ 0x6d, 3 }) // Leave USB ports on for to allow Wake from USB - Method(_S3D,0) // Highest D State in S3 State + Method (_S3D, 0) // Highest D State in S3 State { Return (2) } - Method(_S4D,0) // Highest D State in S4 State + Method (_S4D, 0) // Highest D State in S4 State { Return (2) } Device (HUB7) { - Name (_ADR, 0x00000000) + Name (_ADR, 0) - // How many are there? Device (PRT1) { Name (_ADR, 1) } // USB Port 0 Device (PRT2) { Name (_ADR, 2) } // USB Port 1 Device (PRT3) { Name (_ADR, 3) } // USB Port 2 diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl index 15f69dd..06ca564 100644 --- a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl +++ b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl @@ -11,7 +11,7 @@ * we have to fix it up in coreboot's ACPI creation phase. */ -External(NVSA) +External (NVSA) OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { @@ -87,35 +87,35 @@ /* Set flag to enable USB charging in S3 */ Method (S3UE) { - Store (One, \S3U0) + \S3U0 = 1 } /* Set flag to disable USB charging in S3 */ Method (S3UD) { - Store (Zero, \S3U0) + \S3U0 = 0 } /* Set flag to enable USB charging in S5 */ Method (S5UE) { - Store (One, \S5U0) + \S5U0 = 1 } /* Set flag to disable USB charging in S5 */ Method (S5UD) { - Store (Zero, \S5U0) + \S5U0 = 0 } /* Set flag to enable 3G module in S3 */ Method (S3GE) { - Store (One, \S33G) + \S33G = 1 } /* Set flag to disable 3G module in S3 */ Method (S3GD) { - Store (Zero, \S33G) + \S33G = 0 } diff --git a/src/soc/intel/broadwell/pch/acpi/gpio.asl b/src/soc/intel/broadwell/pch/acpi/gpio.asl index cfe0aed..6b20f27 100644 --- a/src/soc/intel/broadwell/pch/acpi/gpio.asl +++ b/src/soc/intel/broadwell/pch/acpi/gpio.asl @@ -15,7 +15,7 @@ } Name (_UID, 1) - Name (RBUF, ResourceTemplate() + Name (RBUF, ResourceTemplate () { DWordIo (ResourceProducer, MinFixed, // IsMinFixed @@ -41,10 +41,9 @@ CreateDwordField (^RBUF, ^BAR0._MAX, BMAX) CreateDwordField (^RBUF, ^BAR0._LEN, BLEN) - Store (GPIO_BASE_SIZE, BLEN) - Store (GPIO_BASE_ADDRESS, BMIN) - Store (Subtract (Add (GPIO_BASE_ADDRESS, - GPIO_BASE_SIZE), 1), BMAX) + BLEN = GPIO_BASE_SIZE + BMIN = GPIO_BASE_ADDRESS + BMAX = GPIO_BASE_ADDRESS + GPIO_BASE_SIZE - 1 Return (RBUF) } @@ -59,7 +58,7 @@ Method (GWAK, 1, Serialized) { // Local0 = GPIO Base Address - Store (And (GPBS, Not(0x1)), Local0) + Store (GPBS & ~1, Local0) // Local1 = BANK, Local2 = OFFSET Divide (Arg0, 32, Local2, Local1) @@ -69,7 +68,7 @@ // // Local3 = GPIOBASE + GPIO_OWN(BANK) - Store (Add (Local0, Multiply (Local1, 0x4)), Local3) + Store (Local0 + Local1 * 4, Local3) // GPIO_OWN(BANK) OperationRegion (IOWN, SystemIO, Local3, 4) @@ -78,14 +77,14 @@ } // GPIO_OWN[GPIO] = 0 (ACPI) - Store (And (GOWN, Not (ShiftLeft (0x1, Local2))), GOWN) + Store (GOWN & ~(1 << Local2), GOWN) // // Set ROUTE to SCI // // Local3 = GPIOBASE + GPIO_ROUTE(BANK) - Store (Add (Add (Local0, 0x30), Multiply (Local1, 0x4)), Local3) + Store (Local0 + 0x30 + Local1 * 4, Local3) // GPIO_ROUTE(BANK) OperationRegion (IROU, SystemIO, Local3, 4) @@ -94,14 +93,14 @@ } // GPIO_ROUTE[GPIO] = 0 (SCI) - Store (And (GROU, Not (ShiftLeft (0x1, Local2))), GROU) + Store (GROU & ~(1 << Local2), GROU) // // Set GPnCONFIG to GPIO|INPUT|INVERT // // Local3 = GPIOBASE + GPnCONFIG0(GPIO) - Store (Add (Add (Local0, 0x100), Multiply (Arg0, 0x8)), Local3) + Store (Local0 + 0x100 + Arg0 * 8, Local3) // GPnCONFIG(GPIO) OperationRegion (GPNC, SystemIO, Local3, 8) @@ -118,8 +117,8 @@ ISEN, 1, // SENSE: 0=ENABLE 1=DISABLE } - Store (0x1, GMOD) // GPIO - Store (0x1, GIOS) // INPUT - Store (0x1, GINV) // INVERT + GMOD = 1 // GPIO + GIOS = 1 // INPUT + GINV = 1 // INVERT } } diff --git a/src/soc/intel/broadwell/pch/acpi/lpc.asl b/src/soc/intel/broadwell/pch/acpi/lpc.asl index 0af85e6..ae54ce3 100644 --- a/src/soc/intel/broadwell/pch/acpi/lpc.asl +++ b/src/soc/intel/broadwell/pch/acpi/lpc.asl @@ -6,7 +6,7 @@ { Name (_ADR, 0x001f0000) - OperationRegion(LPC0, PCI_Config, 0x00, 0x100) + OperationRegion (LPC0, PCI_Config, 0, 0x100) Field (LPC0, AnyAcc, NoLock, Preserve) { Offset (0x02), @@ -37,8 +37,8 @@ Device (DMAC) // DMA Controller { - Name (_HID, EISAID("PNP0200")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("PNP0200")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x00, 0x00, 0x01, 0x20) IO (Decode16, 0x81, 0x81, 0x01, 0x11) @@ -50,21 +50,21 @@ Device (FWH) // Firmware Hub { - Name (_HID, EISAID("INT0800")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("INT0800")) + Name (_CRS, ResourceTemplate () { - Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + Memory32Fixed (ReadOnly, 0xff000000, 0x01000000) }) } Device (HPET) { - Name (_HID, EISAID("PNP0103")) + Name (_HID, EISAID ("PNP0103")) Name (_CID, 0x010CD041) - Name (BUF0, ResourceTemplate() + Name (BUF0, ResourceTemplate () { - Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) + Memory32Fixed (ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -72,7 +72,7 @@ If (HPTE) { // Note: Ancient versions of Windows don't want // to see the HPET in order to work right - If (LGreaterEqual(OSYS, 2001)) { + If (OSYS >= 2001) { Return (0xf) // Enable and show device } Else { Return (0xb) // Enable and don't show device @@ -86,16 +86,16 @@ { If (HPTE) { CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - If (Lequal(HPAS, 1)) { - Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) + If (HPAS == 1) { + HPT0 = CONFIG_HPET_ADDRESS + 0x1000 } - If (Lequal(HPAS, 2)) { - Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) + If (HPAS == 2) { + HPT0 = CONFIG_HPET_ADDRESS + 0x2000 } - If (Lequal(HPAS, 3)) { - Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) + If (HPAS == 3) { + HPT0 = CONFIG_HPET_ADDRESS + 0x3000 } } @@ -103,10 +103,10 @@ } } - Device(PIC) // 8259 Interrupt Controller + Device (PIC) // 8259 Interrupt Controller { - Name (_HID,EISAID("PNP0000")) - Name (_CRS, ResourceTemplate() + Name (_HID,EISAID ("PNP0000")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x20, 0x20, 0x01, 0x02) IO (Decode16, 0x24, 0x24, 0x01, 0x02) @@ -129,22 +129,22 @@ }) } - Device(MATH) // FPU + Device (MATH) // FPU { - Name (_HID, EISAID("PNP0C04")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("PNP0C04")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) - IRQNoFlags() { 13 } + IRQNoFlags () { 13 } }) } - Device(LDRC) // LPC device: Resource consumption + Device (LDRC) // LPC device: Resource consumption { - Name (_HID, EISAID("PNP0C02")) + Name (_HID, EISAID ("PNP0C02")) Name (_UID, 2) - Name (RBUF, ResourceTemplate() + Name (RBUF, ResourceTemplate () { IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO @@ -166,8 +166,8 @@ Device (RTC) // Real Time Clock { - Name (_HID, EISAID("PNP0B00")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("PNP0B00")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x70, 0x70, 1, 8) }) @@ -175,11 +175,11 @@ Device (TIMR) // Intel 8254 timer { - Name (_HID, EISAID("PNP0100")) - Name (_CRS, ResourceTemplate() { + Name (_HID, EISAID ("PNP0100")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x40, 0x40, 0x01, 0x04) IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags() {0} + IRQNoFlags () {0} }) } diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl index 7b57859..d68fa60 100644 --- a/src/soc/intel/broadwell/pch/acpi/pch.asl +++ b/src/soc/intel/broadwell/pch/acpi/pch.asl @@ -29,8 +29,8 @@ */ Method (ISWP) { - And (\_SB.PCI0.LPCB.PDID, 0xfff0, Local0) - If (LEqual (Local0, 0x9cc0)) { + Local0 = \_SB.PCI0.LPCB.PDID & 0xfff0 + If (Local0 == 0x9cc0) { Return (1) } Else { Return (0) @@ -68,7 +68,7 @@ Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -77,7 +77,7 @@ { /* Unrecognized UUID */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1 |= 4 Return (Arg3) } } diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl index 218ddc3..91fa758 100644 --- a/src/soc/intel/broadwell/pch/acpi/serialio.asl +++ b/src/soc/intel/broadwell/pch/acpi/serialio.asl @@ -11,21 +11,21 @@ Method (LPD0, 2, Serialized) { // PCI mode devices will be handled by OS PCI bus driver - If (LEqual (Arg1, 0)) { + If (Arg1 == 0) { Return } - OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4) + OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) Field (SPRT, DWordAcc, NoLock, Preserve) { SPCS, 32 } - And (SPCS, 0xFFFFFFFC, SPCS) - Store (SPCS, Local0) // Read back after writing + SPCS &= 0xFFFFFFFC + Local0 = SPCS // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used - And(Local0, Ones, Local0) + Local0 &= Ones } // Put SerialIO device in D3 state @@ -34,30 +34,30 @@ Method (LPD3, 2, Serialized) { // PCI mode devices will be handled by OS PCI bus driver - If (LEqual (Arg1, 0)) { + If (Arg1 == 0) { Return } - OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4) + OperationRegion (SPRT, SystemMemory, Arg0 + 0x84, 4) Field (SPRT, DWordAcc, NoLock, Preserve) { SPCS, 32 } - Or (SPCS, 0x3, SPCS) - Store (SPCS, Local0) // Read back after writing + SPCS |= 0x3 + Local0 = SPCS // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used - And(Local0, Ones, Local0) + Local0 &= Ones } // Serial IO Resource Consumption for BAR1 Device (SIOR) { - Name (_HID, EISAID("PNP0C02")) + Name (_HID, EISAID ("PNP0C02")) Name (_UID, 4) - Name (RBUF, ResourceTemplate() + Name (RBUF, ResourceTemplate () { // Serial IO BAR1 (PCI config space) resources Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D0) // SDMA @@ -74,67 +74,67 @@ Method (_CRS, 0, NotSerialized) { // SDMA - If (LNotEqual (\S0B1, Zero)) { + If (\S0B1 != 0) { CreateDwordField (^RBUF, ^B1D0._BAS, B0AD) CreateDwordField (^RBUF, ^B1D0._LEN, B0LN) - Store (\S0B1, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S0B1 + B0LN = SIO_BAR_LEN } // I2C0 - If (LNotEqual (\S1B1, Zero)) { + If (\S1B1 != 0) { CreateDwordField (^RBUF, ^B1D1._BAS, B1AD) CreateDwordField (^RBUF, ^B1D1._LEN, B1LN) - Store (\S1B1, B1AD) - Store (SIO_BAR_LEN, B1LN) + B1AD = \S1B1 + B1LN = SIO_BAR_LEN } // I2C1 - If (LNotEqual (\S2B1, Zero)) { + If (\S2B1 != 0) { CreateDwordField (^RBUF, ^B1D2._BAS, B2AD) CreateDwordField (^RBUF, ^B1D2._LEN, B2LN) - Store (\S2B1, B2AD) - Store (SIO_BAR_LEN, B2LN) + B2AD = \S2B1 + B2LN = SIO_BAR_LEN } // SPI0 - If (LNotEqual (\S3B1, Zero)) { + If (\S3B1 != 0) { CreateDwordField (^RBUF, ^B1D3._BAS, B3AD) CreateDwordField (^RBUF, ^B1D3._LEN, B3LN) - Store (\S3B1, B3AD) - Store (SIO_BAR_LEN, B3LN) + B3AD = \S3B1 + B3LN = SIO_BAR_LEN } // SPI1 - If (LNotEqual (\S4B1, Zero)) { + If (\S4B1 != 0) { CreateDwordField (^RBUF, ^B1D4._BAS, B4AD) CreateDwordField (^RBUF, ^B1D4._LEN, B4LN) - Store (\S4B1, B4AD) - Store (SIO_BAR_LEN, B4LN) + B4AD = \S4B1 + B4LN = SIO_BAR_LEN } // UART0 - If (LNotEqual (\S5B1, Zero)) { + If (\S5B1 != 0) { CreateDwordField (^RBUF, ^B1D5._BAS, B5AD) CreateDwordField (^RBUF, ^B1D5._LEN, B5LN) - Store (\S5B1, B5AD) - Store (SIO_BAR_LEN, B5LN) + B5AD = \S5B1 + B5LN = SIO_BAR_LEN } // UART1 - If (LNotEqual (\S6B1, Zero)) { + If (\S6B1 != 0) { CreateDwordField (^RBUF, ^B1D6._BAS, B6AD) CreateDwordField (^RBUF, ^B1D6._LEN, B6LN) - Store (\S6B1, B6AD) - Store (SIO_BAR_LEN, B6LN) + B6AD = \S6B1 + B6LN = SIO_BAR_LEN } // SDIO - If (LNotEqual (\S7B1, Zero)) { + If (\S7B1 != 0) { CreateDwordField (^RBUF, ^B1D7._BAS, B7AD) CreateDwordField (^RBUF, ^B1D7._LEN, B7LN) - Store (\S7B1, B7AD) - Store (SIO_BAR_LEN, B7LN) + B7AD = \S7B1 + B7LN = SIO_BAR_LEN } Return (RBUF) @@ -158,11 +158,11 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S0B0, Zero)) { + If (\S0B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S0B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S0B0 + B0LN = SIO_BAR_LEN } Return (RBUF) @@ -170,7 +170,7 @@ Method (_STA, 0, NotSerialized) { - If (LEqual (\S0EN, 0)) { + If (\S0EN == 0) { Return (0x0) } Else { Return (0xF) @@ -214,15 +214,15 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S1B0, Zero)) { + If (\S1B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S1B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S1B0 + B0LN = SIO_BAR_LEN } // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + If (\_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -231,7 +231,7 @@ Method (_STA, 0, NotSerialized) { - If (LEqual (\S1EN, 0)) { + If (\S1EN == 0) { Return (0x0) } Else { Return (0xF) @@ -285,15 +285,15 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S2B0, Zero)) { + If (\S2B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S2B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S2B0 + B0LN = SIO_BAR_LEN } // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + If (\_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -302,7 +302,7 @@ Method (_STA, 0, NotSerialized) { - If (LEqual (\S2EN, 0)) { + If (\S2EN == 0) { Return (0x0) } Else { Return (0xF) @@ -346,11 +346,11 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S3B0, Zero)) { + If (\S3B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S3B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S3B0 + B0LN = SIO_BAR_LEN } Return (RBUF) @@ -358,7 +358,7 @@ Method (_STA, 0, NotSerialized) { - If (LEqual (\S3EN, 0)) { + If (\S3EN == 0) { Return (0x0) } Else { Return (0xF) @@ -409,15 +409,15 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S4B0, Zero)) { + If (\S4B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S4B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S4B0 + B0LN = SIO_BAR_LEN } // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + If (\_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -426,7 +426,7 @@ Method (_STA, 0, NotSerialized) { - If (LEqual (\S4EN, 0)) { + If (\S4EN == 0) { Return (0x0) } Else { Return (0xF) @@ -477,15 +477,15 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S5B0, Zero)) { + If (\S5B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S5B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S5B0 + B0LN = SIO_BAR_LEN } // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + If (\_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -494,7 +494,7 @@ Method (_STA, 0, NotSerialized) { - If (LEqual (\S5EN, 0)) { + If (\S5EN == 0) { Return (0x0) } Else { Return (0xF) @@ -538,11 +538,11 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S6B0, Zero)) { + If (\S6B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S6B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S6B0 + B0LN = SIO_BAR_LEN } Return (RBUF) @@ -550,7 +550,7 @@ Method (_STA, 0, NotSerialized) { - If (LEqual (\S6EN, 0)) { + If (\S6EN == 0) { Return (0x0) } Else { Return (0xF) @@ -595,11 +595,11 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S7B0, Zero)) { + If (\S7B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S7B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S7B0 + B0LN = SIO_BAR_LEN } Return (RBUF) @@ -607,7 +607,7 @@ Method (_STA, 0, NotSerialized) { - If (LEqual (\S7EN, 0)) { + If (\S7EN == 0) { Return (0x0) } Else { Return (0xF) diff --git a/src/soc/intel/broadwell/pch/acpi/xhci.asl b/src/soc/intel/broadwell/pch/acpi/xhci.asl index 22e3cbc..4bdd310 100644 --- a/src/soc/intel/broadwell/pch/acpi/xhci.asl +++ b/src/soc/intel/broadwell/pch/acpi/xhci.asl @@ -9,7 +9,7 @@ Name (PLSD, 5) // Port Link State - RxDetect Name (PLSP, 7) // Port Link State - Polling - OperationRegion (XPRT, PCI_Config, 0x00, 0x100) + OperationRegion (XPRT, PCI_Config, 0, 0x100) Field (XPRT, AnyAcc, NoLock, Preserve) { Offset (0x0), @@ -45,8 +45,7 @@ // Clear status bits Method (LPCL, 0, Serialized) { - OperationRegion (XREG, SystemMemory, - ShiftLeft (^XMEM, 16), 0x600) + OperationRegion (XREG, SystemMemory, ^XMEM << 16, 0x600) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x510), // PORTSCNUSB3[0] @@ -60,32 +59,31 @@ } // Port Enabled/Disabled (Bit 1) - Name (PEDB, ShiftLeft (1, 1)) + Name (PEDB, 1 << 1) // Change Status (Bits 23:17) - Name (CHST, ShiftLeft (0x7f, 17)) + Name (CHST, 0x7f << 17) // Port 0 - And (PSC0, Not (PEDB), Local0) - Or (Local0, CHST, PSC0) + Local0 = PSC0 & ~PEDB + PSC0 = Local0 | CHST // Port 1 - And (PSC1, Not (PEDB), Local0) - Or (Local0, CHST, PSC1) + Local0 = PSC1 & ~PEDB + PSC1 = Local0 | CHST // Port 2 - And (PSC2, Not (PEDB), Local0) - Or (Local0, CHST, PSC2) + Local0 = PSC2 & ~PEDB + PSC2 = Local0 | CHST // Port 3 - And (PSC3, Not (PEDB), Local0) - Or (Local0, CHST, PSC3) + Local0 = PSC3 & ~PEDB + PSC3 = Local0 | CHST } Method (LPS0, 0, Serialized) { - OperationRegion (XREG, SystemMemory, - ShiftLeft (^XMEM, 16), 0x600) + OperationRegion (XREG, SystemMemory, ^XMEM << 16, 0x600) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x510), // PORTSCNUSB3 @@ -131,16 +129,14 @@ } // Wait for all powered ports to finish polling - Store (10, Local0) - While (LOr (LOr (LAnd (LEqual (PPR1, 1), LEqual (PLS1, PLSP)), - LAnd (LEqual (PPR2, 1), LEqual (PLS2, PLSP))), - LOr (LAnd (LEqual (PPR3, 1), LEqual (PLS3, PLSP)), - LAnd (LEqual (PPR4, 1), LEqual (PLS4, PLSP))))) + Local0 = 10 + While ((PPR1 == 1 && PLS1 == PLSP || PPR2 == 1 && PLS2 == PLSP) || + (PPR3 == 1 && PLS3 == PLSP || PPR4 == 1 && PLS4 == PLSP)) { - If (LEqual (Local0, 0)) { + If (Local0 == 0) { Break } - Decrement (Local0) + Local0-- Stall (10) } @@ -151,43 +147,37 @@ // 3) Write 1 to port status to clear // Local# indicate if port is reset - Store (0, Local1) - Store (0, Local2) - Store (0, Local3) - Store (0, Local4) + Local1 = 0 + Local2 = 0 + Local3 = 0 + Local4 = 0 - If (LAnd (LEqual (PLS1, PLSD), - LAnd (LEqual (CSC1, 0), LEqual (PPR1, 1)))) { - Store (1, WPR1) // Issue warm reset - Store (1, Local1) + If (PLS1 == PLSD && (CSC1 == 0 && PPR1 == 1)) { + WPR1 = 1 // Issue warm reset + Local1 = 1 } - If (LAnd (LEqual (PLS2, PLSD), - LAnd (LEqual (CSC2, 0), LEqual (PPR2, 1)))) { - Store (1, WPR2) // Issue warm reset - Store (1, Local2) + If (PLS2 == PLSD && (CSC2 == 0 && PPR2 == 1)) { + WPR2 = 1 // Issue warm reset + Local2 = 1 } - If (LAnd (LEqual (PLS3, PLSD), - LAnd (LEqual (CSC3, 0), LEqual (PPR3, 1)))) { - Store (1, WPR3) // Issue warm reset - Store (1, Local3) + If (PLS3 == PLSD && (CSC3 == 0 && PPR3 == 1)) { + WPR3 = 1 // Issue warm reset + Local3 = 1 } - If (LAnd (LEqual (PLS4, PLSD), - LAnd (LEqual (CSC4, 0), LEqual (PPR4, 1)))) { - Store (1, WPR4) // Issue warm reset - Store (1, Local4) + If (PLS4 == PLSD && (CSC4 == 0 && PPR4 == 1)) { + WPR4 = 1 // Issue warm reset + Local4 = 1 } // Poll for warm reset complete on all ports that were reset - Store (10, Local0) - While (LOr (LOr (LAnd (LEqual (Local1, 1), LEqual (WRC1, 0)), - LAnd (LEqual (Local2, 1), LEqual (WRC2, 0))), - LOr (LAnd (LEqual (Local3, 1), LEqual (WRC3, 0)), - LAnd (LEqual (Local4, 1), LEqual (WRC4, 0))))) + Local0 = 10 + While ((Local1 == 1 && WRC1 == 0 || Local2 == 1 && WRC2 == 0) || + (Local3 == 1 && WRC3 == 0 || Local4 == 1 && WRC4 == 0)) { - If (LEqual (Local0, 0)) { + If (Local0 == 0) { Break } - Decrement (Local0) + Local0-- Stall (10) } @@ -202,15 +192,14 @@ Method (_PS0, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { + If (^DVID == 0xFFFF) { Return () } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { + If (^XMEM == 0xFFFF || ^XMEM == 0) { Return () } - OperationRegion (XREG, SystemMemory, - Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200) + OperationRegion (XREG, SystemMemory, (^XMEM << 16) + 0x8000, 0x200) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x0e0), // AUX Reset Control 1 @@ -227,34 +216,34 @@ } // If device is in D3, set back to D0 - Store (^D0D3, Local0) - if (LEqual (Local0, 3)) { - Store (0, ^D0D3) + Local0 = ^D0D3 + if (Local0 == 3) { + ^D0D3 = 0 } - if (LNot (\ISWP())) { + If (!\ISWP()) { // Clear PCI 0xB0[14:13] - Store (0, ^MB13) - Store (0, ^MB14) + ^MB13 = 0 + ^MB14 = 0 // Clear MMIO 0x816C[14,2] - Store (0, CLK0) - Store (0, CLK1) + CLK0 = 0 + CLK1 = 0 // Set MMIO 0x8154[31] - Store (1, CLK2) + CLK2 = 1 // Handle per-port reset if needed LPS0 () // Set MMIO 0x80e0[15] - Store (1, AX15) + AX15 = 1 // Clear PCI CFG offset 0x40[11] - Store (0, ^SWAI) + ^SWAI = 0 // Clear PCI CFG offset 0x44[13:12] - Store (0, ^SAIP) + ^SAIP = 0 } Return () @@ -262,15 +251,14 @@ Method (_PS3, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { + If (^DVID == 0xFFFF) { Return () } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { + If (^XMEM == 0xFFFF || ^XMEM == 0) { Return () } - OperationRegion (XREG, SystemMemory, - Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200) + OperationRegion (XREG, SystemMemory, (^XMEM << 16) + 0x8000, 0x200) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x0e0), // AUX Reset Control 1 @@ -286,74 +274,74 @@ CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable } - Store (1, ^PMES) // Clear PME Status - Store (1, ^PMEE) // Enable PME + ^PMES = 1 // Clear PME Status + ^PMEE = 1 // Enable PME // If device is in D3, set back to D0 - Store (^D0D3, Local0) - if (LEqual (Local0, 3)) { - Store (0, ^D0D3) + Local0 = ^D0D3 + if (Local0 == 3) { + ^D0D3 = 0 } - if (LNot (\ISWP())) { + If (!\ISWP()) { // Set PCI 0xB0[14:13] - Store (1, ^MB13) - Store (1, ^MB14) + ^MB13 = 1 + ^MB14 = 1 // Set MMIO 0x816C[14,2] - Store (1, CLK0) - Store (1, CLK1) + CLK0 = 1 + CLK1 = 1 // Clear MMIO 0x8154[31] - Store (0, CLK2) + CLK2 = 0 // Clear MMIO 0x80e0[15] - Store (0, AX15) + AX15 = 0 // Set PCI CFG offset 0x40[11] - Store (1, ^SWAI) + ^SWAI = 1 // Set PCI CFG offset 0x44[13:12] - Store (1, ^SAIP) + ^SAIP = 1 } // Put device in D3 - Store (3, ^D0D3) + ^D0D3 = 3 Return () } - Name (_PRW, Package(){ 0x6d, 3 }) + Name (_PRW, Package (){ 0x6d, 3 }) // Leave USB ports on for to allow Wake from USB - Method(_S3D,0) // Highest D State in S3 State + Method (_S3D, 0) // Highest D State in S3 State { Return (3) } - Method(_S4D,0) // Highest D State in S4 State + Method (_S4D, 0) // Highest D State in S4 State { Return (3) } Device (HUB7) { - Name (_ADR, 0x00000000) + Name (_ADR, 0) // GPLD: Generate Port Location Data (PLD) Method (GPLD, 1, Serialized) { - Name (PCKG, Package (0x01) { + Name (PCKG, Package () { Buffer (0x10) {} }) - // REV: Revision 0x02 for ACPI 5.0 - CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) - Store (0x02, REV) + // REV: Revision 2 for ACPI 5.0 + CreateField (DerefOf (PCKG [0]), 0, 7, REV) + REV = 2 // VISI: Port visibility to user per port - CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) - Store (Arg0, VISI) + CreateField (DerefOf (PCKG [0]), 0x40, 1, VISI) + VISI = Arg0 Return (PCKG) } -- To view, visit https://review.coreboot.org/c/coreboot/+/46778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic13c081fd7ee2212d851cc14263c1e2fd8970072 Gerrit-Change-Number: 46778 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: sb/intel/lynxpoint/acpi: Clean up cosmetics
by Angel Pons (Code Review) 13 Nov '20

13 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46777 ) Change subject: sb/intel/lynxpoint/acpi: Clean up cosmetics ...................................................................... sb/intel/lynxpoint/acpi: Clean up cosmetics Use ASL 2.0 syntax where possible and uniformize code style to match the IASL disassembly. Some `Store` in gpio.asl change the binary if touched. Also remove outdated comment and remove `LynxPoint` from `serialio.asl`. Tested with BUILD_TIMELESS=1, Google Panther does not change. Change-Id: Ie0994fa546ff54ebb533afcc6205efb36da99a67 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/audio.asl M src/southbridge/intel/lynxpoint/acpi/globalnvs.asl M src/southbridge/intel/lynxpoint/acpi/gpio.asl M src/southbridge/intel/lynxpoint/acpi/lpc.asl M src/southbridge/intel/lynxpoint/acpi/pch.asl M src/southbridge/intel/lynxpoint/acpi/serialio.asl M src/southbridge/intel/lynxpoint/acpi/usb.asl 7 files changed, 243 insertions(+), 258 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46777/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/audio.asl b/src/southbridge/intel/lynxpoint/acpi/audio.asl index 2bae304..98cdac9 100644 --- a/src/southbridge/intel/lynxpoint/acpi/audio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/audio.asl @@ -8,8 +8,8 @@ { Name (_ADR, 0x001b0000) - Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H - Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP + Name (PRWH, Package (){ 0x0d, 3 }) // LPT-H + Name (PRWL, Package (){ 0x6d, 3 }) // LPT-LP Method (_PRW, 0) { // Power Resources for Wake If (\ISLP ()) { diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl index ee2d800..ccf9b08 100644 --- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl +++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl @@ -11,7 +11,7 @@ * we have to fix it up in coreboot's ACPI creation phase. */ -External(NVSA) +External (NVSA) OperationRegion (GNVS, SystemMemory, NVSA, 0xf00) Field (GNVS, ByteAcc, NoLock, Preserve) { @@ -112,41 +112,41 @@ /* Set flag to enable USB charging in S3 */ Method (S3UE) { - Store (One, \S3U0) - Store (One, \S3U1) + \S3U0 = 1 + \S3U1 = 1 } /* Set flag to disable USB charging in S3 */ Method (S3UD) { - Store (Zero, \S3U0) - Store (Zero, \S3U1) + \S3U0 = 0 + \S3U1 = 0 } /* Set flag to enable USB charging in S5 */ Method (S5UE) { - Store (One, \S5U0) - Store (One, \S5U1) + \S5U0 = 1 + \S5U1 = 1 } /* Set flag to disable USB charging in S5 */ Method (S5UD) { - Store (Zero, \S5U0) - Store (Zero, \S5U1) + \S5U0 = 0 + \S5U1 = 0 } /* Set flag to enable 3G module in S3 */ Method (S3GE) { - Store (One, \S33G) + \S33G = 1 } /* Set flag to disable 3G module in S3 */ Method (S3GD) { - Store (Zero, \S33G) + \S33G = 0 } External (\_TZ.SKIN) @@ -169,46 +169,46 @@ /* Update Fan 0 thresholds */ Method (F0UT, 2) { - Store (Arg0, \F0OF) - Store (Arg1, \F0ON) + \F0OF = Arg0 + \F0ON = Arg1 TZUP () } /* Update Fan 1 thresholds */ Method (F1UT, 2) { - Store (Arg0, \F1OF) - Store (Arg1, \F1ON) + \F1OF = Arg0 + \F1ON = Arg1 TZUP () } /* Update Fan 2 thresholds */ Method (F2UT, 2) { - Store (Arg0, \F2OF) - Store (Arg1, \F2ON) + \F2OF = Arg0 + \F2ON = Arg1 TZUP () } /* Update Fan 3 thresholds */ Method (F3UT, 2) { - Store (Arg0, \F3OF) - Store (Arg1, \F3ON) + \F3OF = Arg0 + \F3ON = Arg1 TZUP () } /* Update Fan 4 thresholds */ Method (F4UT, 2) { - Store (Arg0, \F4OF) - Store (Arg1, \F4ON) + \F4OF = Arg0 + \F4ON = Arg1 TZUP () } /* Update Temperature Sensor ID */ Method (TMPU, 1) { - Store (Arg0, \TMPS) + \TMPS = Arg0 TZUP () } diff --git a/src/southbridge/intel/lynxpoint/acpi/gpio.asl b/src/southbridge/intel/lynxpoint/acpi/gpio.asl index 7f30307..1a50968 100644 --- a/src/southbridge/intel/lynxpoint/acpi/gpio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/gpio.asl @@ -7,7 +7,7 @@ Name (_CID, "INT33C7") Name (_UID, 1) - Name (RBUF, ResourceTemplate() + Name (RBUF, ResourceTemplate () { DWordIo (ResourceProducer, MinFixed, // IsMinFixed @@ -33,10 +33,9 @@ CreateDwordField (^RBUF, ^BAR0._MAX, BMAX) CreateDwordField (^RBUF, ^BAR0._LEN, BLEN) - Store (DEFAULT_GPIOSIZE, BLEN) - Store (DEFAULT_GPIOBASE, BMIN) - Store (Subtract (Add (DEFAULT_GPIOBASE, - DEFAULT_GPIOSIZE), 1), BMAX) + BLEN = DEFAULT_GPIOSIZE + BMIN = DEFAULT_GPIOBASE + BMAX = DEFAULT_GPIOBASE + DEFAULT_GPIOSIZE - 1 Return (RBUF) } @@ -51,7 +50,7 @@ Method (GWAK, 1, NotSerialized) { // Local0 = GPIO Base Address - Store (And (GPBS, Not(0x1)), Local0) + Store (GPBS & ~1, Local0) // Local1 = BANK, Local2 = OFFSET Divide (Arg0, 32, Local2, Local1) @@ -61,7 +60,7 @@ // // Local3 = GPIOBASE + GPIO_OWN(BANK) - Store (Add (Local0, Multiply (Local1, 0x4)), Local3) + Store (Local0 + Local1 * 4, Local3) // GPIO_OWN(BANK) OperationRegion (IOWN, SystemIO, Local3, 4) @@ -70,14 +69,14 @@ } // GPIO_OWN[GPIO] = 0 (ACPI) - Store (And (GOWN, Not (ShiftLeft (0x1, Local2))), GOWN) + Store (GOWN & ~(1 << Local2), GOWN) // // Set ROUTE to SCI // // Local3 = GPIOBASE + GPIO_ROUTE(BANK) - Store (Add (Add (Local0, 0x30), Multiply (Local1, 0x4)), Local3) + Store (Local0 + 0x30 + Local1 * 4, Local3) // GPIO_ROUTE(BANK) OperationRegion (IROU, SystemIO, Local3, 4) @@ -86,14 +85,14 @@ } // GPIO_ROUTE[GPIO] = 0 (SCI) - Store (And (GROU, Not (ShiftLeft (0x1, Local2))), GROU) + Store (GROU & ~(1 << Local2), GROU) // // Set GPnCONFIG to GPIO|INPUT|INVERT // // Local3 = GPIOBASE + GPnCONFIG0(GPIO) - Store (Add (Add (Local0, 0x100), Multiply (Arg0, 0x8)), Local3) + Store (Local0 + 0x100 + Arg0 * 8, Local3) // GPnCONFIG(GPIO) OperationRegion (GPNC, SystemIO, Local3, 8) @@ -110,8 +109,8 @@ ISEN, 1, // SENSE: 0=ENABLE 1=DISABLE } - Store (0x1, GMOD) // GPIO - Store (0x1, GIOS) // INPUT - Store (0x1, GINV) // INVERT + GMOD = 1 // GPIO + GIOS = 1 // INPUT + GINV = 1 // INVERT } } diff --git a/src/southbridge/intel/lynxpoint/acpi/lpc.asl b/src/southbridge/intel/lynxpoint/acpi/lpc.asl index 8410d7ab..8f41e67 100644 --- a/src/southbridge/intel/lynxpoint/acpi/lpc.asl +++ b/src/southbridge/intel/lynxpoint/acpi/lpc.asl @@ -6,7 +6,7 @@ { Name (_ADR, 0x001f0000) - OperationRegion(LPC0, PCI_Config, 0x00, 0x100) + OperationRegion (LPC0, PCI_Config, 0, 0x100) Field (LPC0, AnyAcc, NoLock, Preserve) { Offset (0x02), @@ -37,8 +37,8 @@ Device (DMAC) // DMA Controller { - Name (_HID, EISAID("PNP0200")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("PNP0200")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x00, 0x00, 0x01, 0x20) IO (Decode16, 0x81, 0x81, 0x01, 0x11) @@ -50,21 +50,21 @@ Device (FWH) // Firmware Hub { - Name (_HID, EISAID("INT0800")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("INT0800")) + Name (_CRS, ResourceTemplate () { - Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + Memory32Fixed (ReadOnly, 0xff000000, 0x01000000) }) } Device (HPET) { - Name (_HID, EISAID("PNP0103")) + Name (_HID, EISAID ("PNP0103")) Name (_CID, 0x010CD041) - Name (BUF0, ResourceTemplate() + Name (BUF0, ResourceTemplate () { - Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) + Memory32Fixed (ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0) }) Method (_STA, 0) // Device Status @@ -72,7 +72,7 @@ If (HPTE) { // Note: Ancient versions of Windows don't want // to see the HPET in order to work right - If (LGreaterEqual(OSYS, 2001)) { + If (OSYS >= 2001) { Return (0xf) // Enable and show device } Else { Return (0xb) // Enable and don't show device @@ -86,16 +86,16 @@ { If (HPTE) { CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - If (Lequal(HPAS, 1)) { - Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) + If (HPAS == 1) { + HPT0 = CONFIG_HPET_ADDRESS + 0x1000 } - If (Lequal(HPAS, 2)) { - Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) + If (HPAS == 2) { + HPT0 = CONFIG_HPET_ADDRESS + 0x2000 } - If (Lequal(HPAS, 3)) { - Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) + If (HPAS == 3) { + HPT0 = CONFIG_HPET_ADDRESS + 0x3000 } } @@ -103,10 +103,10 @@ } } - Device(PIC) // 8259 Interrupt Controller + Device (PIC) // 8259 Interrupt Controller { - Name (_HID,EISAID("PNP0000")) - Name (_CRS, ResourceTemplate() + Name (_HID,EISAID ("PNP0000")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x20, 0x20, 0x01, 0x02) IO (Decode16, 0x24, 0x24, 0x01, 0x02) @@ -129,22 +129,22 @@ }) } - Device(MATH) // FPU + Device (MATH) // FPU { - Name (_HID, EISAID("PNP0C04")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("PNP0C04")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) - IRQNoFlags() { 13 } + IRQNoFlags () { 13 } }) } - Device(LDRC) // LPC device: Resource consumption + Device (LDRC) // LPC device: Resource consumption { - Name (_HID, EISAID("PNP0C02")) + Name (_HID, EISAID ("PNP0C02")) Name (_UID, 2) - Name (RBUF, ResourceTemplate() + Name (RBUF, ResourceTemplate () { IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO @@ -166,15 +166,15 @@ // LynxPoint-LP GPIO resources are defined in the // SerialIO GPIO device and LynxPoint-H GPIO resources // are defined here. - If (LNot (\ISLP ())) { + If (!\ISLP ()) { CreateByteField (^RBUF, ^GPR1._LEN, R1LN) CreateWordField (^RBUF, ^GPR1._MIN, R1MN) CreateWordField (^RBUF, ^GPR1._MAX, R1MX) // Update GPIO region length - Store (DEFAULT_GPIOBASE, R1MN) - Store (DEFAULT_GPIOBASE, R1MX) - Store (DEFAULT_GPIOSIZE, R1LN) + R1MN = DEFAULT_GPIOBASE + R1MX = DEFAULT_GPIOBASE + R1LN = DEFAULT_GPIOSIZE } Return (RBUF) } @@ -182,8 +182,8 @@ Device (RTC) // Real Time Clock { - Name (_HID, EISAID("PNP0B00")) - Name (_CRS, ResourceTemplate() + Name (_HID, EISAID ("PNP0B00")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x70, 0x70, 1, 8) }) @@ -191,11 +191,11 @@ Device (TIMR) // Intel 8254 timer { - Name (_HID, EISAID("PNP0100")) - Name (_CRS, ResourceTemplate() { + Name (_HID, EISAID ("PNP0100")) + Name (_CRS, ResourceTemplate () { IO (Decode16, 0x40, 0x40, 0x01, 0x04) IO (Decode16, 0x50, 0x50, 0x10, 0x04) - IRQNoFlags() {0} + IRQNoFlags () {0} }) } diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index a3c8188..cb5b823 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -22,11 +22,11 @@ OperationRegion (RCRB, SystemMemory, DEFAULT_RCBA, 0x4000) Field (RCRB, DWordAcc, Lock, Preserve) { - Offset(0x3404), // High Performance Timer Configuration + Offset (0x3404), // High Performance Timer Configuration HPAS, 2, // Address Select , 5, HPTE, 1, // Address Enable - Offset(0x3418), // FD (Function Disable) + Offset (0x3418), // FD (Function Disable) , 1, // Reserved PCID, 1, // PCI bridge disable SA1D, 1, // SATA1 disable @@ -46,7 +46,7 @@ RP8D, 1, // Root Port 8 disable TTRD, 1, // Thermal sensor registers disable SA2D, 1, // SATA2 disable - Offset(0x3428), // FD2 (Function Disable 2) + Offset (0x3428), // FD2 (Function Disable 2) BDFD, 1, // Display BDF ME1D, 1, // ME Interface 1 disable ME2D, 1, // ME Interface 2 disable @@ -81,7 +81,7 @@ Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -90,7 +90,7 @@ { /* Unrecognized UUID */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1 |= 4 Return (Arg3) } } diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 164b623..845949c 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -1,28 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -// Intel LynxPoint Serial IO Devices in ACPI Mode +// Intel Serial IO Devices in ACPI Mode // Serial IO Device BAR0 and BAR1 is 4KB #define SIO_BAR_LEN 0x1000 // This is defined in SSDT2 which is generated at boot based // on whether or not the device is enabled in ACPI mode. -External(\S0EN) -External(\S1EN) -External(\S2EN) -External(\S3EN) -External(\S4EN) -External(\S5EN) -External(\S6EN) -External(\S7EN) +External (\S0EN) +External (\S1EN) +External (\S2EN) +External (\S3EN) +External (\S4EN) +External (\S5EN) +External (\S6EN) +External (\S7EN) // Serial IO Resource Consumption for BAR1 Device (SIOR) { - Name (_HID, EISAID("PNP0C02")) + Name (_HID, EISAID ("PNP0C02")) Name (_UID, 4) - Name (RBUF, ResourceTemplate() + Name (RBUF, ResourceTemplate () { // Serial IO BAR1 (PCI config space) resources Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, B1D0) // SDMA @@ -39,67 +39,67 @@ Method (_CRS, 0, NotSerialized) { // SDMA - If (LNotEqual (\S0B1, Zero)) { + If (\S0B1 != 0) { CreateDwordField (^RBUF, ^B1D0._BAS, B0AD) CreateDwordField (^RBUF, ^B1D0._LEN, B0LN) - Store (\S0B1, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S0B1 + B0LN = SIO_BAR_LEN } // I2C0 - If (LNotEqual (\S1B1, Zero)) { + If (\S1B1 != 0) { CreateDwordField (^RBUF, ^B1D1._BAS, B1AD) CreateDwordField (^RBUF, ^B1D1._LEN, B1LN) - Store (\S1B1, B1AD) - Store (SIO_BAR_LEN, B1LN) + B1AD = \S1B1 + B1LN = SIO_BAR_LEN } // I2C1 - If (LNotEqual (\S2B1, Zero)) { + If (\S2B1 != 0) { CreateDwordField (^RBUF, ^B1D2._BAS, B2AD) CreateDwordField (^RBUF, ^B1D2._LEN, B2LN) - Store (\S2B1, B2AD) - Store (SIO_BAR_LEN, B2LN) + B2AD = \S2B1 + B2LN = SIO_BAR_LEN } // SPI0 - If (LNotEqual (\S3B1, Zero)) { + If (\S3B1 != 0) { CreateDwordField (^RBUF, ^B1D3._BAS, B3AD) CreateDwordField (^RBUF, ^B1D3._LEN, B3LN) - Store (\S3B1, B3AD) - Store (SIO_BAR_LEN, B3LN) + B3AD = \S3B1 + B3LN = SIO_BAR_LEN } // SPI1 - If (LNotEqual (\S4B1, Zero)) { + If (\S4B1 != 0) { CreateDwordField (^RBUF, ^B1D4._BAS, B4AD) CreateDwordField (^RBUF, ^B1D4._LEN, B4LN) - Store (\S4B1, B4AD) - Store (SIO_BAR_LEN, B4LN) + B4AD = \S4B1 + B4LN = SIO_BAR_LEN } // UART0 - If (LNotEqual (\S5B1, Zero)) { + If (\S5B1 != 0) { CreateDwordField (^RBUF, ^B1D5._BAS, B5AD) CreateDwordField (^RBUF, ^B1D5._LEN, B5LN) - Store (\S5B1, B5AD) - Store (SIO_BAR_LEN, B5LN) + B5AD = \S5B1 + B5LN = SIO_BAR_LEN } // UART1 - If (LNotEqual (\S6B1, Zero)) { + If (\S6B1 != 0) { CreateDwordField (^RBUF, ^B1D6._BAS, B6AD) CreateDwordField (^RBUF, ^B1D6._LEN, B6LN) - Store (\S6B1, B6AD) - Store (SIO_BAR_LEN, B6LN) + B6AD = \S6B1 + B6LN = SIO_BAR_LEN } // SDIO - If (LNotEqual (\S7B1, Zero)) { + If (\S7B1 != 0) { CreateDwordField (^RBUF, ^B1D7._BAS, B7AD) CreateDwordField (^RBUF, ^B1D7._LEN, B7LN) - Store (\S7B1, B7AD) - Store (SIO_BAR_LEN, B7LN) + B7AD = \S7B1 + B7LN = SIO_BAR_LEN } Return (RBUF) @@ -122,11 +122,11 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S0B0, Zero)) { + If (\S0B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S0B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S0B0 + B0LN = SIO_BAR_LEN } Return (RBUF) @@ -134,7 +134,7 @@ Method (_STA, 0, NotSerialized) { - If (LEqual (\S0EN, 0)) { + If (\S0EN == 0) { Return (0x0) } Else { Return (0xF) @@ -169,15 +169,15 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S1B0, Zero)) { + If (\S1B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S1B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S1B0 + B0LN = SIO_BAR_LEN } // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + If (\_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -186,7 +186,7 @@ Method (_STA, 0, NotSerialized) { - If (LEqual (\S1EN, 0)) { + If (\S1EN == 0) { Return (0x0) } Else { Return (0xF) @@ -204,21 +204,21 @@ // Put controller in D0 state Method (_PS0, 0, Serialized) { - And (^PSAT, 0xfffffffc, ^PSAT) - Store (^PSAT, Local0) // Read back after writing + ^PSAT &= 0xfffffffc + Local0 = ^PSAT // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used - And(Local0, Ones, Local0) + Local0 &= Ones } // Put controller in D3Hot state Method (_PS3, 0, Serialized) { - Or (^PSAT, 0x00000003, ^PSAT) - Store (^PSAT, Local0) // Read back after writing + ^PSAT |= 0x00000003 + Local0 = ^PSAT // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used - And(Local0, Ones, Local0) + Local0 &= Ones } } @@ -249,15 +249,15 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S2B0, Zero)) { + If (\S2B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S2B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S2B0 + B0LN = SIO_BAR_LEN } // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + If (\_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -266,7 +266,7 @@ Method (_STA, 0, NotSerialized) { - If (LEqual (\S2EN, 0)) { + If (\S2EN == 0) { Return (0x0) } Else { Return (0xF) @@ -284,21 +284,21 @@ // Put controller in D0 state Method (_PS0, 0, Serialized) { - And (^PSAT, 0xfffffffc, ^PSAT) - Store (^PSAT, Local0) // Read back after writing + ^PSAT &= 0xfffffffc + Local0 = ^PSAT // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used - And(Local0, Ones, Local0) + Local0 &= Ones } // Put controller in D3Hot state Method (_PS3, 0, Serialized) { - Or (^PSAT, 0x00000003, ^PSAT) - Store (^PSAT, Local0) // Read back after writing + ^PSAT |= 0x00000003 + Local0 = ^PSAT // Read back after writing // Use Local0 to avoid iasl warning: Method Local is set but never used - And(Local0, Ones, Local0) + Local0 &= Ones } } @@ -319,11 +319,11 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S3B0, Zero)) { + If (\S3B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S3B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S3B0 + B0LN = SIO_BAR_LEN } Return (RBUF) @@ -331,7 +331,7 @@ Method (_STA, 0, NotSerialized) { - If (LEqual (\S3EN, 0)) { + If (\S3EN == 0) { Return (0x0) } Else { Return (0xF) @@ -363,15 +363,15 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S4B0, Zero)) { + If (\S4B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S4B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S4B0 + B0LN = SIO_BAR_LEN } // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + If (\_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -380,7 +380,7 @@ Method (_STA, 0, NotSerialized) { - If (LEqual (\S4EN, 0)) { + If (\S4EN == 0) { Return (0x0) } Else { Return (0xF) @@ -412,15 +412,15 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S5B0, Zero)) { + If (\S5B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S5B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S5B0 + B0LN = SIO_BAR_LEN } // Check if Serial IO DMA Controller is enabled - If (LNotEqual (\_SB.PCI0.SDMA._STA, Zero)) { + If (\_SB.PCI0.SDMA._STA != 0) { Return (ConcatenateResTemplate (RBUF, DBUF)) } Else { Return (RBUF) @@ -429,7 +429,7 @@ Method (_STA, 0, NotSerialized) { - If (LEqual (\S5EN, 0)) { + If (\S5EN == 0) { Return (0x0) } Else { Return (0xF) @@ -454,11 +454,11 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S6B0, Zero)) { + If (\S6B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S6B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S6B0 + B0LN = SIO_BAR_LEN } Return (RBUF) @@ -466,7 +466,7 @@ Method (_STA, 0, NotSerialized) { - If (LEqual (\S6EN, 0)) { + If (\S6EN == 0) { Return (0x0) } Else { Return (0xF) @@ -491,11 +491,11 @@ Method (_CRS, 0, NotSerialized) { // Update BAR0 address and length if set in NVS - If (LNotEqual (\S7B0, Zero)) { + If (\S7B0 != 0) { CreateDwordField (^RBUF, ^BAR0._BAS, B0AD) CreateDwordField (^RBUF, ^BAR0._LEN, B0LN) - Store (\S7B0, B0AD) - Store (SIO_BAR_LEN, B0LN) + B0AD = \S7B0 + B0LN = SIO_BAR_LEN } Return (RBUF) @@ -503,7 +503,7 @@ Method (_STA, 0, NotSerialized) { - If (LEqual (\S7EN, 0)) { + If (\S7EN == 0) { Return (0x0) } Else { Return (0xF) diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index 4fd4a8e..e807398 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -1,15 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Intel Cougar Point USB support */ - // EHCI Controller 0:1d.0 Device (EHCI) { - Name(_ADR, 0x001d0000) + Name (_ADR, 0x001d0000) - Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H - Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP + Name (PRWH, Package (){ 0x0d, 3 }) // LPT-H + Name (PRWL, Package (){ 0x6d, 3 }) // LPT-LP Method (_PRW, 0) { // Power Resources for Wake If (\ISLP ()) { @@ -21,19 +19,19 @@ // Leave USB ports on for to allow Wake from USB - Method(_S3D,0) // Highest D State in S3 State + Method (_S3D, 0) // Highest D State in S3 State { Return (2) } - Method(_S4D,0) // Highest D State in S4 State + Method (_S4D, 0) // Highest D State in S4 State { Return (2) } Device (HUB7) { - Name (_ADR, 0x00000000) + Name (_ADR, 0) Device (PRT1) { Name (_ADR, 1) } // USB Port 0 Device (PRT2) { Name (_ADR, 2) } // USB Port 1 @@ -53,7 +51,7 @@ Name (PLSD, 5) // Port Link State - RxDetect Name (PLSP, 7) // Port Link State - Polling - OperationRegion (XPRT, PCI_Config, 0x00, 0x100) + OperationRegion (XPRT, PCI_Config, 0, 0x100) Field (XPRT, AnyAcc, NoLock, Preserve) { Offset (0x0), @@ -81,8 +79,7 @@ // Clear status bits Method (LPCL, 0, Serialized) { - OperationRegion (XREG, SystemMemory, - ShiftLeft (^XMEM, 16), 0x600) + OperationRegion (XREG, SystemMemory, ^XMEM << 16, 0x600) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x510), // PORTSCNUSB3[0] @@ -96,32 +93,31 @@ } // Port Enabled/Disabled (Bit 1) - Name (PEDB, ShiftLeft (1, 1)) + Name (PEDB, 1 << 1) // Change Status (Bits 23:17) - Name (CHST, ShiftLeft (0x7f, 17)) + Name (CHST, 0x7f << 17) // Port 0 - And (PSC0, Not (PEDB), Local0) - Or (Local0, CHST, PSC0) + Local0 = PSC0 & ~PEDB + PSC0 = Local0 | CHST // Port 1 - And (PSC1, Not (PEDB), Local0) - Or (Local0, CHST, PSC1) + Local0 = PSC1 & ~PEDB + PSC1 = Local0 | CHST // Port 2 - And (PSC2, Not (PEDB), Local0) - Or (Local0, CHST, PSC2) + Local0 = PSC2 & ~PEDB + PSC2 = Local0 | CHST // Port 3 - And (PSC3, Not (PEDB), Local0) - Or (Local0, CHST, PSC3) + Local0 = PSC3 & ~PEDB + PSC3 = Local0 | CHST } Method (LPS0, 0, Serialized) { - OperationRegion (XREG, SystemMemory, - ShiftLeft (^XMEM, 16), 0x600) + OperationRegion (XREG, SystemMemory, ^XMEM << 16, 0x600) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x510), // PORTSCNUSB3 @@ -167,16 +163,14 @@ } // Wait for all powered ports to finish polling - Store (10, Local0) - While (LOr (LOr (LAnd (LEqual (PPR1, 1), LEqual (PLS1, PLSP)), - LAnd (LEqual (PPR2, 1), LEqual (PLS2, PLSP))), - LOr (LAnd (LEqual (PPR3, 1), LEqual (PLS3, PLSP)), - LAnd (LEqual (PPR4, 1), LEqual (PLS4, PLSP))))) + Local0 = 10 + While ((PPR1 == 1 && PLS1 == PLSP || PPR2 == 1 && PLS2 == PLSP) || + (PPR3 == 1 && PLS3 == PLSP || PPR4 == 1 && PLS4 == PLSP)) { - If (LEqual (Local0, 0)) { + If (Local0 == 0) { Break } - Decrement (Local0) + Local0-- Stall (10) } @@ -187,43 +181,37 @@ // 3) Write 1 to port status to clear // Local# indicate if port is reset - Store (0, Local1) - Store (0, Local2) - Store (0, Local3) - Store (0, Local4) + Local1 = 0 + Local2 = 0 + Local3 = 0 + Local4 = 0 - If (LAnd (LEqual (PLS1, PLSD), - LAnd (LEqual (CSC1, 0), LEqual (PPR1, 1)))) { - Store (1, WPR1) // Issue warm reset - Store (1, Local1) + If (PLS1 == PLSD && (CSC1 == 0 && PPR1 == 1)) { + WPR1 = 1 // Issue warm reset + Local1 = 1 } - If (LAnd (LEqual (PLS2, PLSD), - LAnd (LEqual (CSC2, 0), LEqual (PPR2, 1)))) { - Store (1, WPR2) // Issue warm reset - Store (1, Local2) + If (PLS2 == PLSD && (CSC2 == 0 && PPR2 == 1)) { + WPR2 = 1 // Issue warm reset + Local2 = 1 } - If (LAnd (LEqual (PLS3, PLSD), - LAnd (LEqual (CSC3, 0), LEqual (PPR3, 1)))) { - Store (1, WPR3) // Issue warm reset - Store (1, Local3) + If (PLS3 == PLSD && (CSC3 == 0 && PPR3 == 1)) { + WPR3 = 1 // Issue warm reset + Local3 = 1 } - If (LAnd (LEqual (PLS4, PLSD), - LAnd (LEqual (CSC4, 0), LEqual (PPR4, 1)))) { - Store (1, WPR4) // Issue warm reset - Store (1, Local4) + If (PLS4 == PLSD && (CSC4 == 0 && PPR4 == 1)) { + WPR4 = 1 // Issue warm reset + Local4 = 1 } // Poll for warm reset complete on all ports that were reset - Store (10, Local0) - While (LOr (LOr (LAnd (LEqual (Local1, 1), LEqual (WRC1, 0)), - LAnd (LEqual (Local2, 1), LEqual (WRC2, 0))), - LOr (LAnd (LEqual (Local3, 1), LEqual (WRC3, 0)), - LAnd (LEqual (Local4, 1), LEqual (WRC4, 0))))) + Local0 = 10 + While ((Local1 == 1 && WRC1 == 0 || Local2 == 1 && WRC2 == 0) || + (Local3 == 1 && WRC3 == 0 || Local4 == 1 && WRC4 == 0)) { - If (LEqual (Local0, 0)) { + If (Local0 == 0) { Break } - Decrement (Local0) + Local0-- Stall (10) } @@ -238,15 +226,14 @@ Method (_PS0, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { + If (^DVID == 0xFFFF) { Return () } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { + If (^XMEM == 0xFFFF || ^XMEM == 0) { Return () } - OperationRegion (XREG, SystemMemory, - Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200) + OperationRegion (XREG, SystemMemory, (^XMEM << 16) + 0x8000, 0x200) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x0e0), // AUX Reset Control 1 @@ -263,30 +250,30 @@ } // If device is in D3, set back to D0 - Store (^D0D3, Local0) - if (LEqual (Local0, 3)) { - Store (0, ^D0D3) + Local0 = ^D0D3 + if (Local0 == 3) { + ^D0D3 = 0 } If (\ISLP ()) { // Clear PCI 0xB0[14:13] - Store (0, ^MB13) - Store (0, ^MB14) + ^MB13 = 0 + ^MB14 = 0 // Clear MMIO 0x816C[14,2] - Store (0, CLK0) - Store (0, CLK1) + CLK0 = 0 + CLK1 = 0 } // Set MMIO 0x8154[31] - Store (1, CLK2) + CLK2 = 1 If (\ISLP ()) { // Handle per-port reset if needed LPS0 () // Set MMIO 0x80e0[15] - Store (1, AX15) + AX15 = 1 } Return () @@ -294,15 +281,14 @@ Method (_PS3, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { + If (^DVID == 0xFFFF) { Return () } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { + If (^XMEM == 0xFFFF || ^XMEM == 0) { Return () } - OperationRegion (XREG, SystemMemory, - Add (ShiftLeft (^XMEM, 16), 0x8000), 0x200) + OperationRegion (XREG, SystemMemory, (^XMEM << 16) + 0x8000, 0x200) Field (XREG, DWordAcc, Lock, Preserve) { Offset (0x0e0), // AUX Reset Control 1 @@ -318,41 +304,41 @@ CLK1, 1, // USB3 Port Aux/Core Clock Gating Enable } - Store (1, ^PMES) // Clear PME Status - Store (1, ^PMEE) // Enable PME + ^PMES = 1 // Clear PME Status + ^PMEE = 1 // Enable PME // If device is in D3, set back to D0 - Store (^D0D3, Local0) - if (LEqual (Local0, 3)) { - Store (0, ^D0D3) + Local0 = ^D0D3 + if (Local0 == 3) { + ^D0D3 = 0 } If (\ISLP ()) { // Set PCI 0xB0[14:13] - Store (1, ^MB13) - Store (1, ^MB14) + ^MB13 = 1 + ^MB14 = 1 // Set MMIO 0x816C[14,2] - Store (1, CLK0) - Store (1, CLK1) + CLK0 = 1 + CLK1 = 1 } // Clear MMIO 0x8154[31] - Store (0, CLK2) + CLK2 = 0 If (\ISLP ()) { // Clear MMIO 0x80e0[15] - Store (0, AX15) + AX15 = 0 } // Put device in D3 - Store (3, ^D0D3) + ^D0D3 = 3 Return () } - Name (PRWH, Package(){ 0x0d, 3 }) // LPT-H - Name (PRWL, Package(){ 0x6d, 3 }) // LPT-LP + Name (PRWH, Package (){ 0x0d, 3 }) // LPT-H + Name (PRWL, Package (){ 0x6d, 3 }) // LPT-LP Method (_PRW, 0) { // Power Resources for Wake If (\ISLP ()) { @@ -364,33 +350,33 @@ // Leave USB ports on for to allow Wake from USB - Method(_S3D,0) // Highest D State in S3 State + Method (_S3D, 0) // Highest D State in S3 State { Return (3) } - Method(_S4D,0) // Highest D State in S4 State + Method (_S4D, 0) // Highest D State in S4 State { Return (3) } Device (HUB7) { - Name (_ADR, 0x00000000) + Name (_ADR, 0) // GPLD: Generate Port Location Data (PLD) Method (GPLD, 1, Serialized) { - Name (PCKG, Package (0x01) { + Name (PCKG, Package () { Buffer (0x10) {} }) - // REV: Revision 0x02 for ACPI 5.0 - CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) - Store (0x02, REV) + // REV: Revision 2 for ACPI 5.0 + CreateField (DerefOf (PCKG [0]), 0, 7, REV) + REV = 2 // VISI: Port visibility to user per port - CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) - Store (Arg0, VISI) + CreateField (DerefOf (PCKG [0]), 0x40, 1, VISI) + VISI = Arg0 Return (PCKG) } -- To view, visit https://review.coreboot.org/c/coreboot/+/46777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0994fa546ff54ebb533afcc6205efb36da99a67 Gerrit-Change-Number: 46777 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: [RFC] Add new board configuration entry to coreboot tables
by Tim Wawrzynczak (Code Review) 11 Nov '20

11 Nov '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46605 ) Change subject: [RFC] Add new board configuration entry to coreboot tables ...................................................................... [RFC] Add new board configuration entry to coreboot tables The new entry is intended to be the configuration entry to rule them all, possibly deprecating the three separate "strapping ID" tables with which it is slightly redundant with. In one entry, it should provide enough information to give firmware the information it needs at runtime to make decisions based on what kind of board it is or what is attached to it, all in one place. The new entry contains: - Board ID - DRAM ID (RAM code) - SKU ID - FW Config Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: I1ecec847ee77b72233587c1ad7f124e2027470bf --- M payloads/libpayload/include/coreboot_tables.h M src/commonlib/include/commonlib/coreboot_tables.h M src/include/fw_config.h M src/lib/coreboot_table.c 4 files changed, 59 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/46605/1 diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index bf8c0d9..fc10031 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -79,6 +79,7 @@ CB_TAG_MMC_INFO = 0x0035, CB_TAG_TCPA_LOG = 0x0036, CB_TAG_FMAP = 0x0037, + CB_TAG_BOARD_CONFIG = 0x0039, CB_TAG_CMOS_OPTION_TABLE = 0x00c8, CB_TAG_OPTION = 0x00c9, CB_TAG_OPTION_ENUM = 0x00ca, @@ -316,6 +317,16 @@ int32_t early_cmd1_status; }; +struct cb_board_config { + uint32_t tag; + uint32_t size; + + struct cbuint64 fw_config; + uint32_t board_id; + uint32_t dram_id; + uint32_t sku_id; +}; + #define CB_MAX_SERIALNO_LENGTH 32 struct cb_cmos_option_table { diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 6393c01..4fb7318 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -80,6 +80,8 @@ LB_TAG_TCPA_LOG = 0x0036, LB_TAG_FMAP = 0x0037, LB_TAG_PLATFORM_BLOB_VERSION = 0x0038, + LB_TAG_BOARD_CONFIG = 0x0039, + /* The following options are CMOS-related */ LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, LB_TAG_OPTION_ENUM = 0x00ca, @@ -415,6 +417,16 @@ struct mac_address mac_addrs[0]; }; +struct lb_board_config { + uint32_t tag; + uint32_t size; + + struct lb_uint64 fw_config; + uint32_t board_id; + uint32_t dram_id; + uint32_t sku_id; +}; + #define MAX_SERIALNO_LENGTH 32 /* The following structures are for the CMOS definitions table */ diff --git a/src/include/fw_config.h b/src/include/fw_config.h index c9ef75f..7eaad7d 100644 --- a/src/include/fw_config.h +++ b/src/include/fw_config.h @@ -8,6 +8,8 @@ #include <stdbool.h> #include <stdint.h> +#define DEFAULT_FW_CONFIG (uint64_t)0 + /** * struct fw_config - Firmware configuration field and option. * @field_name: Name of the field that this option belongs to. diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 9148405..82b718a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -1,22 +1,23 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/cbconfig.h> -#include <console/console.h> -#include <console/uart.h> -#include <ip_checksum.h> +#include <boardid.h> #include <boot/coreboot_tables.h> #include <boot/tables.h> #include <boot_device.h> -#include <string.h> -#include <version.h> -#include <boardid.h> -#include <device/device.h> -#include <fmap.h> -#include <stdlib.h> -#include <cbfs.h> -#include <cbmem.h> #include <bootmem.h> #include <bootsplash.h> +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include <console/uart.h> +#include <device/device.h> +#include <fmap.h> +#include <fw_config.h> +#include <ip_checksum.h> +#include <stdlib.h> +#include <string.h> +#include <version.h> #include <spi_flash.h> #include <security/vboot/misc.h> #include <security/vboot/vbnv_layout.h> @@ -211,6 +212,7 @@ __weak uint32_t board_id(void) { return UNDEFINED_STRAPPING_ID; } __weak uint32_t ram_code(void) { return UNDEFINED_STRAPPING_ID; } __weak uint32_t sku_id(void) { return UNDEFINED_STRAPPING_ID; } +__weak uint64_t fw_config_get(void) { return DEFAULT_FW_CONFIG; } static void lb_board_id(struct lb_header *header) { @@ -368,6 +370,24 @@ return mainboard; } +static struct lb_board_config *lb_board_config(struct lb_header *header) +{ + struct lb_record *rec; + struct lb_board_config *config; + rec = lb_new_record(header); + config = (struct lb_board_config *)rec; + + config->tag = LB_TAG_BOARD_CONFIG; + config->size = sizeof(*config); + + config->board_id = board_id(); + config->dram_id = ram_code(); + config->sku_id = sku_id(); + config->fw_config = pack_lb64(fw_config_get()); + + return config; +} + #if CONFIG(USE_OPTION_TABLE) static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header) { @@ -557,6 +577,9 @@ lb_boot_media_params(head); + /* Board configuration information */ + lb_board_config(head); + /* Add architecture records. */ lb_arch_add_records(head); -- To view, visit https://review.coreboot.org/c/coreboot/+/46605 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ecec847ee77b72233587c1ad7f124e2027470bf Gerrit-Change-Number: 46605 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

7 38

Change in coreboot[master]: soc/intel/common: Add support for CSE Lite driver to handle CSE RW an...
by Sridhar Siricilla (Code Review) 11 Nov '20

11 Nov '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46552 ) Change subject: soc/intel/common: Add support for CSE Lite driver to handle CSE RW and metadata ...................................................................... soc/intel/common: Add support for CSE Lite driver to handle CSE RW and metadata The patch modifies CSE Lite driver to support to have separate CBFS file for metadata of RW blobs. So, the driver expects separate CBFS files for CSE RW and it's metadata. Also, the driver initiates CSE Firmware update path if it finds the metadata's CBFS file. The change gives flexibility to modify RW blob's FMAP locations while maintaining uniform or little modified CSE Lite driver. Currently, CSE RW blob and it's metadata were unified into one RW blob. TEST=Verified on hatch. BRANCH=Puff Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I316344d23987d9907b64efafbe61f36ae7ade337 --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse_lite.c 3 files changed, 128 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/46552/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 1cb7d35..6512e3d 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -37,3 +37,15 @@ default "" help Intel CSE CBFS RW blob path and file name + +config SOC_INTEL_CSE_RW_METADATA_CBFS_NAME + string "CBFS entry name for CSE RW blob" + default "me_rw.metadata" + help + CBFS entry name for Intel CSE CBFS RW blob + +config SOC_INTEL_CSE_RW_METADATA_FILE + string "Intel CSE CBFS RW path and filename" + default "" + help + Intel CSE CBFS RW blob path and file name diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 11cc3c2..59ba0cb 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -4,11 +4,20 @@ ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c +ifneq ($(CONFIG_SOC_INTEL_CSE_RW_METADATA_FILE),"") +CSE_LITE_RW_METADATA = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_METADATA_CBFS_NAME)) +regions-for-file-$(CSE_LITE_RW_METADATA) = FW_MAIN_A,FW_MAIN_B +cbfs-files-y += $(CSE_LITE_RW_METADATA) +$(CSE_LITE_RW_METADATA)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_METADATA_FILE)) +$(CSE_LITE_RW_METADATA)-name := $(CSE_LITE_RW_METADATA) +$(CSE_LITE_RW_METADATA)-type := raw +endif + ifneq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"") -CSE_LITE_ME_RW = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME)) -regions-for-file-$(CSE_LITE_ME_RW) = FW_MAIN_A,FW_MAIN_B -cbfs-files-y += $(CSE_LITE_ME_RW) -$(CSE_LITE_ME_RW)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) -$(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW) -$(CSE_LITE_ME_RW)-type := raw +CSE_LITE_RW = $(call strip_quotes, $(CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME)) +regions-for-file-$(CSE_LITE_RW) = FW_MAIN_A, FW_MAIN_B +cbfs-files-y += $(CSE_LITE_RW) +$(CSE_LITE_RW)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) +$(CSE_LITE_RW)-name := $(CSE_LITE_RW) +$(CSE_LITE_RW)-type := raw endif diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index c9e4e1f..7218a92 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -12,9 +12,6 @@ #include <vb2_api.h> #include <soc/intel/common/reset.h> -/* CSE RW version size reserved in the CSE CBFS RW binary */ -#define CSE_RW_VERSION_SZ 16 - /* Converts bp index to boot partition string */ #define GET_BP_STR(bp_index) (bp_index ? "RW" : "RO") @@ -45,6 +42,9 @@ /* CSE recovery sub-error codes */ enum csme_failure_reason { + + /* No error */ + CSE_LITE_SKU_NO_ERROR = 0, /* Unspecified error */ CSE_LITE_SKU_UNSPECIFIED = 1, @@ -64,7 +64,10 @@ CSE_LITE_SKU_COMMUNICATION_ERROR = 6, /* Fails to wipe CSE runtime data */ - CSE_LITE_SKU_DATA_WIPE_ERROR = 7 + CSE_LITE_SKU_DATA_WIPE_ERROR = 7, + + /* CSE RW is not found */ + CSE_LITE_SKU_RW_BLOB_NOT_FOUND = 8, }; /* @@ -157,6 +160,13 @@ struct cse_bp_info bp_info; } __packed; +/* CSE CBFS RW metadata */ +struct cse_cbfs_rw_info { + /* CSE CBFS RW version */ + struct fw_version fw_ver; + uint8_t reserved[8]; +}; + static void cse_log_status_registers(void) { printk(BIOS_DEBUG, "cse_lite: CSE status registers: HFSTS1: 0x%x, HFSTS2: 0x%x " @@ -423,7 +433,7 @@ { struct cbfsf file_desc; - if (cbfs_boot_locate(&file_desc, CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME, NULL) < 0) + if (cbfs_boot_locate(&file_desc, CONFIG_SOC_INTEL_CSE_RW_METADATA_CBFS_NAME, NULL) < 0) return false; cbfs_file_data(source_rdev, &file_desc); @@ -503,15 +513,33 @@ return true; } -static bool cse_get_cbfs_rw_version(const struct region_device *source_rdev, - void *cse_cbfs_rw_ver) +static bool cse_get_cbfs_rw(struct region_device *rdev) +{ + struct cbfsf file_desc; + + if (cbfs_boot_locate(&file_desc, CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME, NULL) < 0) + return false; + + cbfs_file_data(rdev, &file_desc); + + return true; +} + +static bool cse_get_cbfs_rw_metadata(const struct region_device *source_info_rdev, + struct cse_cbfs_rw_info *source_info) { - if (rdev_readat(source_rdev, (void *) cse_cbfs_rw_ver, 0, sizeof(struct fw_version)) - != sizeof(struct fw_version)) { - printk(BIOS_ERR, "cse_lite: Failed to read CSE CBFW RW version\n"); + if (rdev_readat(source_info_rdev, (void *) source_info, 0, + sizeof(struct cse_cbfs_rw_info)) != sizeof(struct cse_cbfs_rw_info)) { + printk(BIOS_ERR, "cse_lite: Failed to read CSE CBFS RW metadata\n"); return false; } + + printk(BIOS_SPEW, "cse_lite: CSE CBFS RW version : %d.%d.%d.%d\n", + source_info->fw_ver.major, + source_info->fw_ver.minor, + source_info->fw_ver.hotfix, + source_info->fw_ver.build); return true; } @@ -522,30 +550,26 @@ * If ver_cmp_status > 0, coreboot upgrades CSE RW region */ static int cse_check_version_mismatch(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_cbfs_rw_info *source_info) { - struct fw_version cse_cbfs_rw_ver; const struct fw_version *cse_rw_ver; - if (!cse_get_cbfs_rw_version(source_rdev, &cse_cbfs_rw_ver)) - return false; - printk(BIOS_DEBUG, "cse_lite: CSE CBFS RW version : %d.%d.%d.%d\n", - cse_cbfs_rw_ver.major, - cse_cbfs_rw_ver.minor, - cse_cbfs_rw_ver.hotfix, - cse_cbfs_rw_ver.build); + source_info->fw_ver.major, + source_info->fw_ver.minor, + source_info->fw_ver.hotfix, + source_info->fw_ver.build); cse_rw_ver = cse_get_rw_version(cse_bp_info); - if (cse_cbfs_rw_ver.major != cse_rw_ver->major) - return cse_cbfs_rw_ver.major - cse_rw_ver->major; - else if (cse_cbfs_rw_ver.minor != cse_rw_ver->minor) - return cse_cbfs_rw_ver.minor - cse_rw_ver->minor; - else if (cse_cbfs_rw_ver.hotfix != cse_rw_ver->hotfix) - return cse_cbfs_rw_ver.hotfix - cse_rw_ver->hotfix; + if (source_info->fw_ver.major != cse_rw_ver->major) + return source_info->fw_ver.major - cse_rw_ver->major; + else if (source_info->fw_ver.minor != cse_rw_ver->minor) + return source_info->fw_ver.minor - cse_rw_ver->minor; + else if (source_info->fw_ver.hotfix != cse_rw_ver->hotfix) + return source_info->fw_ver.hotfix - cse_rw_ver->hotfix; else - return cse_cbfs_rw_ver.build - cse_rw_ver->build; + return source_info->fw_ver.build - cse_rw_ver->build; } /* Check if CSE RW data partition is valid or not */ @@ -587,8 +611,8 @@ return true; } -static bool cse_copy_rw(const struct region_device *target_rdev, const void *buf, size_t offset, - size_t size) +static bool cse_copy_rw(const struct region_device *target_rdev, const void *buf, + size_t offset, size_t size) { if (rdev_writeat(target_rdev, buf, offset, size) < 0) { printk(BIOS_ERR, "cse_lite: Failed to update CSE firmware\n"); @@ -599,36 +623,35 @@ } static bool cse_is_rw_version_latest(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_cbfs_rw_info *source_info) { - return !cse_check_version_mismatch(cse_bp_info, source_rdev); + return !cse_check_version_mismatch(cse_bp_info, source_info); } static bool cse_is_downgrade_instance(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_cbfs_rw_info *source_info) { - return cse_check_version_mismatch(cse_bp_info, source_rdev) < 0; + return cse_check_version_mismatch(cse_bp_info, source_info) < 0; } static bool cse_is_update_required(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev, struct region_device *target_rdev) + const struct cse_cbfs_rw_info *source_info, struct region_device *target_rdev) { return (!cse_is_rw_bp_sign_valid(target_rdev) || - !cse_is_rw_version_latest(cse_bp_info, source_rdev)); + !cse_is_rw_version_latest(cse_bp_info, source_info)); } static bool cse_write_rw_region(const struct region_device *target_rdev, const struct region_device *source_rdev) { - void *cse_cbfs_rw = rdev_mmap(source_rdev, CSE_RW_VERSION_SZ, - region_device_sz(source_rdev) - CSE_RW_VERSION_SZ); + + void *cse_cbfs_rw = rdev_mmap(source_rdev, 0, region_device_sz(source_rdev)); /* Points to CSE CBFS RW image after boot partition signature */ uint8_t *cse_cbfs_rw_wo_sign = (uint8_t *)cse_cbfs_rw + CSE_RW_SIGN_SIZE; /* Size of CSE CBFS RW image without boot partition signature */ - uint32_t cse_cbfs_rw_wo_sign_sz = region_device_sz(source_rdev) - - (CSE_RW_VERSION_SZ + CSE_RW_SIGN_SIZE); + uint32_t cse_cbfs_rw_wo_sign_sz = region_device_sz(source_rdev) - CSE_RW_SIGN_SIZE; /* Update except CSE RW signature */ if (!cse_copy_rw(target_rdev, cse_cbfs_rw_wo_sign, CSE_RW_SIGN_SIZE, @@ -639,29 +662,32 @@ if (!cse_copy_rw(target_rdev, (void *)cse_cbfs_rw, 0, CSE_RW_SIGN_SIZE)) goto exit_rw_update; - rdev_munmap(source_rdev, cse_cbfs_rw_wo_sign); - return true; + printk(BIOS_INFO, "cse_lite: CSE RW Update Successful\n"); + rdev_munmap(source_rdev, cse_cbfs_rw); + return CSE_LITE_SKU_NO_ERROR; exit_rw_update: - rdev_munmap(source_rdev, cse_cbfs_rw_wo_sign); - return false; + rdev_munmap(source_rdev, cse_cbfs_rw); + return CSE_LITE_SKU_FW_UPDATE_ERROR; } static bool cse_update_rw(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev, struct region_device *target_rdev) + struct region_device *target_rdev) { + + struct region_device source_rdev; + + if (!cse_get_cbfs_rw(&source_rdev)) + return CSE_LITE_SKU_RW_BLOB_NOT_FOUND; + if (!cse_erase_rw_region(target_rdev)) - return false; + return CSE_LITE_SKU_FW_UPDATE_ERROR; - if (!cse_write_rw_region(target_rdev, source_rdev)) - return false; - - printk(BIOS_INFO, "cse_lite: CSE RW Update Successful\n"); - return true; + return cse_write_rw_region(target_rdev, &source_rdev); } static bool cse_prep_for_rw_update(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_cbfs_rw_info *source_info) { /* * To set CSE's operation mode to HMRFPO mode: @@ -671,7 +697,7 @@ if (!cse_boot_to_ro(cse_bp_info)) return false; - if (cse_is_downgrade_instance(cse_bp_info, source_rdev) && + if (cse_is_downgrade_instance(cse_bp_info, source_info) && !cse_data_clear_request(cse_bp_info)) { printk(BIOS_ERR, "cse_lite: CSE FW downgrade is aborted\n"); return false; @@ -680,20 +706,18 @@ return cse_hmrfpo_enable(); } -static uint8_t cse_trigger_fw_update(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev, struct region_device *target_rdev) +static enum csme_failure_reason cse_trigger_fw_update(const struct cse_bp_info *cse_bp_info, + const struct cse_cbfs_rw_info *source_info, struct region_device *target_rdev) { - if (!cse_prep_for_rw_update(cse_bp_info, source_rdev)) + + if (!cse_prep_for_rw_update(cse_bp_info, source_info)) return CSE_LITE_SKU_COMMUNICATION_ERROR; - if (!cse_update_rw(cse_bp_info, source_rdev, target_rdev)) - return CSE_LITE_SKU_FW_UPDATE_ERROR; - - return 0; + return cse_update_rw(cse_bp_info, target_rdev); } static uint8_t cse_fw_update(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct region_device *source_info_rdev) { struct region_device target_rdev; @@ -702,9 +726,17 @@ return CSE_LITE_SKU_RW_ACCESS_ERROR; } - if (cse_is_update_required(cse_bp_info, source_rdev, &target_rdev)) { + struct cse_cbfs_rw_info source_info; + + /* Read CSE CBFS RW metadata */ + if (!cse_get_cbfs_rw_metadata(source_info_rdev, &source_info)) { + printk(BIOS_ERR, "cse_lite: Failed to get CSE RW blob metadata\n"); + return CSE_LITE_SKU_UNSPECIFIED; + } + + if (cse_is_update_required(cse_bp_info, &source_info, &target_rdev)) { printk(BIOS_DEBUG, "cse_lite: CSE RW update is initiated\n"); - return cse_trigger_fw_update(cse_bp_info, source_rdev, &target_rdev); + return cse_trigger_fw_update(cse_bp_info, &source_info, &target_rdev); } if (!cse_is_rw_bp_status_valid(cse_bp_info)) @@ -736,11 +768,15 @@ if (!cse_fix_data_failure_err(&cse_bp_info.bp_info)) cse_trigger_recovery(CSE_LITE_SKU_DATA_WIPE_ERROR); - /* If RW blob is present in CBFS, then trigger CSE firmware update */ + /* + * If CSE CBFS RW blob metadata is present in CBFS, then trigger CSE firmware update. + * The driver triggers recovery if CSE CBFS RW metadata is present in the CBFS and CSE + * CBFS RW blob is not available. + */ uint8_t rv; - struct region_device source_rdev; - if (cse_get_cbfs_rdev(&source_rdev)) { - rv = cse_fw_update(&cse_bp_info.bp_info, &source_rdev); + struct region_device source_info_rdev; + if (cse_get_cbfs_rdev(&source_info_rdev)) { + rv = cse_fw_update(&cse_bp_info.bp_info, &source_info_rdev); if (rv) cse_trigger_recovery(rv); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I316344d23987d9907b64efafbe61f36ae7ade337 Gerrit-Change-Number: 46552 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 11

Change in coreboot[master]: sc7180: add qclib_post_fixup to allow SoC specific code
by mturney mturney (Code Review) 11 Nov '20

11 Nov '20

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37795 ) Change subject: sc7180: add qclib_post_fixup to allow SoC specific code ...................................................................... sc7180: add qclib_post_fixup to allow SoC specific code * Provide hook for SoC specific code to run after QCLib Change-Id: I5507187fddfd7d0af0ee0983b06d67077de0dbc8 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M src/soc/qualcomm/common/include/soc/qclib_common.h M src/soc/qualcomm/common/qclib.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37795/1 diff --git a/src/soc/qualcomm/common/include/soc/qclib_common.h b/src/soc/qualcomm/common/include/soc/qclib_common.h index 19ec083..5817c08 100644 --- a/src/soc/qualcomm/common/include/soc/qclib_common.h +++ b/src/soc/qualcomm/common/include/soc/qclib_common.h @@ -72,5 +72,6 @@ uint32_t size, uint32_t attrs); void qclib_load_and_run(void); int qclib_soc_blob_load(void); +int qclib_post_fixup(void); #endif // _SOC_QUALCOMM_QCLIB_COMMON_H_ diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index ac80a76..ce07078 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -119,6 +119,7 @@ } __weak int qclib_soc_blob_load(void) { return 0; } +__weak int qclib_post_fixup(void) { return 0; } void qclib_load_and_run(void) { @@ -209,6 +210,12 @@ mmu_restore_context(&pre_qclib_mmu_context); mmu_enable(); + /* hook for SoC specific fixup after QCLib runs */ + if (qclib_post_fixup()) { + printk(BIOS_ERR, "qclib_post_fixup failed\n"); + goto fail; + } + /* step through I/F table, handling return values */ for (i = 0; i < qclib_cb_if_table.num_entries; i++) if (qclib_cb_if_table.te[i].blob_attributes & -- To view, visit https://review.coreboot.org/c/coreboot/+/37795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5507187fddfd7d0af0ee0983b06d67077de0dbc8 Gerrit-Change-Number: 37795 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: soc/amd/picasso: Use common SMM save state ops
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37019 ) Change subject: soc/amd/picasso: Use common SMM save state ops ...................................................................... soc/amd/picasso: Use common SMM save state ops Change-Id: I9eb42b9f9b14925a682356e21bbb0d2ccaeaafec Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/picasso/smihandler.c 1 file changed, 24 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37019/1 diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 39c2dfd..b04eddb 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <cpu/x86/cache.h> -#include <cpu/amd/amd64_save_state.h> #include <arch/acpi.h> #include <arch/hlt.h> #include <device/pci_def.h> @@ -41,17 +40,18 @@ SMM_IO_TRAP_PORT_ADDRESS_MASK); } -static void *find_save_state(int cmd) +static int find_save_state_node(int cmd) { int core; - amd64_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); u32 smm_io_trap; u8 reg_al; + u64 rax; /* Check all nodes looking for the one that issued the IO */ for (core = 0; core < CONFIG_MAX_CPUS; core++) { - state = smm_get_save_state(core); - smm_io_trap = state->smm_io_trap_offset; + if (ops->get_io_trap(core, &smm_io_trap)) + continue; /* Check for Valid IO Trap Word (bit1==1) */ if (!(smm_io_trap & SMM_IO_TRAP_VALID)) continue; @@ -62,30 +62,39 @@ if (pm_acpi_smi_cmd_port() != get_io_address(smm_io_trap)) continue; /* Check AL against the requested command */ - reg_al = state->rax; + if (ops->get_reg(core, RAX, &rax)) + continue; + reg_al = rax; if (reg_al == cmd) - return state; + return core; } - return NULL; + return -1; } static void southbridge_smi_gsmi(void) { + u32 ret, param; u8 sub_command; - amd64_smm_state_save_area_t *io_smi; - u32 reg_ebx; + int node = find_save_state_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); - io_smi = find_save_state(APM_CNT_ELOG_GSMI); - if (!io_smi) + if (node < -1) return; + /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; + uint64_t reg; + if (ops->get_reg(node, RAX, &reg)) + return; + sub_command = (u8)(reg >> 8); /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; + if (ops->get_reg(node, RBX, &reg)) + return; + param = reg & UINT32_MAX; /* drivers/elog/gsmi.c */ - io_smi->rax = gsmi_exec(sub_command, &reg_ebx); + ret = gsmi_exec(sub_command, (u32 *)param); + ops->set_reg(node, RAX, reg); } static void sb_apmc_smi_handler(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/37019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9eb42b9f9b14925a682356e21bbb0d2ccaeaafec Gerrit-Change-Number: 37019 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/amd/stoneyridge: Use common SMM save state ops
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37018 ) Change subject: soc/amd/stoneyridge: Use common SMM save state ops ...................................................................... soc/amd/stoneyridge: Use common SMM save state ops Change-Id: I2f98062dd254528c0c72e8739035c9e620a8497f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/stoneyridge/smihandler.c 1 file changed, 24 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/37018/1 diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 2b88397..d2945c8 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <cpu/x86/smm.h> #include <cpu/x86/cache.h> -#include <cpu/amd/amd64_save_state.h> #include <arch/acpi.h> #include <arch/hlt.h> #include <device/pci_def.h> @@ -41,17 +40,18 @@ SMM_IO_TRAP_PORT_ADDRESS_MASK); } -static void *find_save_state(int cmd) +static int find_save_state_node(int cmd) { int core; - amd64_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); u32 smm_io_trap; u8 reg_al; + u64 rax; /* Check all nodes looking for the one that issued the IO */ for (core = 0; core < CONFIG_MAX_CPUS; core++) { - state = smm_get_save_state(core); - smm_io_trap = state->smm_io_trap_offset; + if (ops->get_io_trap(core, &smm_io_trap)) + continue; /* Check for Valid IO Trap Word (bit1==1) */ if (!(smm_io_trap & SMM_IO_TRAP_VALID)) continue; @@ -62,30 +62,39 @@ if (pm_acpi_smi_cmd_port() != get_io_address(smm_io_trap)) continue; /* Check AL against the requested command */ - reg_al = state->rax; + if (ops->get_reg(core, RAX, &rax)) + continue; + reg_al = rax; if (reg_al == cmd) - return state; + return core; } - return NULL; + return -1; } static void southbridge_smi_gsmi(void) { + u32 ret, param; u8 sub_command; - amd64_smm_state_save_area_t *io_smi; - u32 reg_ebx; + int node = find_save_state_node(APM_CNT_ELOG_GSMI); + const struct smm_save_state_ops *ops = get_save_state_ops(); - io_smi = find_save_state(APM_CNT_ELOG_GSMI); - if (!io_smi) + if (node < -1) return; + /* Command and return value in EAX */ - sub_command = (io_smi->rax >> 8) & 0xff; + uint64_t reg; + if (ops->get_reg(node, RAX, &reg)) + return; + sub_command = (u8)(reg >> 8); /* Parameter buffer in EBX */ - reg_ebx = io_smi->rbx; + if (ops->get_reg(node, RBX, &reg)) + return; + param = reg & UINT32_MAX; /* drivers/elog/gsmi.c */ - io_smi->rax = gsmi_exec(sub_command, &reg_ebx); + ret = gsmi_exec(sub_command, (u32 *)param); + ops->set_reg(node, RAX, reg); } static void sb_apmc_smi_handler(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/37018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f98062dd254528c0c72e8739035c9e620a8497f Gerrit-Change-Number: 37018 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/intel/denverton_ns: Use common SMM save state ops
by Arthur Heymans (Code Review) 11 Nov '20

11 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37017 ) Change subject: soc/intel/denverton_ns: Use common SMM save state ops ...................................................................... soc/intel/denverton_ns: Use common SMM save state ops Change-Id: Ieb5baaa4e36d97414d87addf5c8e318b881e8996 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/denverton_ns/smihandler.c 1 file changed, 36 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/37017/1 diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index c292e4d..ce0022f 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -23,7 +23,6 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> -#include <cpu/intel/em64t100_save_state.h> #include <device/pci_def.h> #include <intelblocks/fast_spi.h> #include <spi-generic.h> @@ -168,35 +167,39 @@ * core in case we are not running on the same core that * initiated the IO transaction. */ -static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) +static int smi_apmc_find_state_save_node(u8 cmd) { - em64t100_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); int node; /* Check all nodes looking for the one that issued the IO */ for (node = 0; node < CONFIG_MAX_CPUS; node++) { - state = smm_get_save_state(node); - - /* Check for Synchronous IO (bit0==1) */ - if (!(state->io_misc_info & (1 << 0))) - continue; - - /* Make sure it was a write (bit4==0) */ - if (state->io_misc_info & (1 << 4)) - continue; - - /* Check for APMC IO port */ - if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) - continue; - + uint32_t io_misc_info; + uint64_t rax; + if (ops->get_reg(node, RAX, &rax)) + continue; /* ??? */ /* Check AX against the requested command */ - if ((state->rax & 0xff) != cmd) + if ((rax & 0xff) != cmd) continue; + if (ops->get_io_misc_info(node, &io_misc_info)) { - return state; + /* Check for Synchronous IO (bit0 == 1) */ + if (!(io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4 == 0) */ + if (io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + } + + return node; } - return NULL; + return -1; } static void finalize(void) @@ -217,7 +220,7 @@ static void southbridge_smi_apmc(void) { uint8_t reg8; - em64t100_smm_state_save_area_t *state; + const struct smm_save_state_ops *ops = get_save_state_ops(); /* Emulate B2 register as the FADT / Linux expects it */ @@ -254,13 +257,18 @@ "SMI#: SMM structures already initialized!\n"); return; } - state = smi_apmc_find_state_save(reg8); - if (state) { - /* EBX in the state save contains the GNVS pointer */ - gnvs = (global_nvs_t *)((uint32_t)state->rbx); - smm_initialized = 1; - printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); - } + int node = smi_apmc_find_state_save_node(APM_CNT_GNVS_UPDATE); + if (node < -1) + return; + + uint64_t rbx; + if (ops->get_reg(node, RBX, &rbx)) + return; + + /* EBX in the state save contains the GNVS pointer */ + gnvs = (global_nvs_t *)(u32)rbx; + smm_initialized = 1; + printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/37017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb5baaa4e36d97414d87addf5c8e318b881e8996 Gerrit-Change-Number: 37017 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020