coreboot-gerrit October 2020

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Change in coreboot[master]: sb/intel/lynxpoint: Add WildcatPoint SerialIO HIDs
by Angel Pons (Code Review) 13 Nov '20

13 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46975 ) Change subject: sb/intel/lynxpoint: Add WildcatPoint SerialIO HIDs ...................................................................... sb/intel/lynxpoint: Add WildcatPoint SerialIO HIDs This is merely to allow reusing the same SerialIO code for both. Change-Id: I6ddb01a9fdadbffe48324ff60f3d70e27513d775 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/serialio.asl 1 file changed, 16 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/46975/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 0e246f7..dd364bc 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -16,6 +16,15 @@ External (\S6EN) External (\S7EN) +// Generate a method object that returns different values for LPT and WPT +#define DYNAMIC_NAME(obj_name, lpt_id, wpt_id) \ + Method (obj_name) { \ + If (\ISWP ()) { \ + Return (wpt_id) \ + } \ + Return (lpt_id) \ + } + // Put SerialIO device in D0 state // Arg0 - Ref to offset 0x84 of device's PCI config space Method (LPD0, 1, Serialized) @@ -167,7 +176,7 @@ Device (I2C0) { // Serial IO I2C0 Controller - Name (_HID, "INT33C2") + DYNAMIC_NAME (_HID, "INT33C2", "INT3432") Name (_CID, "INT33C2") Name (_UID, 1) @@ -235,7 +244,7 @@ Device (I2C1) { // Serial IO I2C1 Controller - Name (_HID, "INT33C3") + DYNAMIC_NAME (_HID, "INT33C3", "INT3433") Name (_CID, "INT33C3") Name (_UID, 1) @@ -303,7 +312,7 @@ Device (SPI0) { // Serial IO SPI0 Controller - Name (_HID, "INT33C0") + DYNAMIC_NAME (_HID, "INT33C0", "INT3430") Name (_CID, "INT33C0") Name (_UID, 1) @@ -356,7 +365,7 @@ Device (SPI1) { // Serial IO SPI1 Controller - Name (_HID, "INT33C1") + DYNAMIC_NAME (_HID, "INT33C1", "INT3431") Name (_CID, "INT33C1") Name (_UID, 1) @@ -421,7 +430,7 @@ Device (UAR0) { // Serial IO UART0 Controller - Name (_HID, "INT33C4") + DYNAMIC_NAME (_HID, "INT33C4", "INT3434") Name (_CID, "INT33C4") Name (_UID, 1) @@ -486,7 +495,7 @@ Device (UAR1) { // Serial IO UART1 Controller - Name (_HID, "INT33C5") + DYNAMIC_NAME (_HID, "INT33C5", "INT3435") Name (_CID, "INT33C5") Name (_UID, 1) @@ -539,7 +548,7 @@ Device (SDIO) { // Serial IO SDIO Controller - Name (_HID, "INT33C6") + DYNAMIC_NAME (_HID, "INT33C6", "INT3436") Name (_CID, "PNP0D40") Name (_UID, 1) -- To view, visit https://review.coreboot.org/c/coreboot/+/46975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ddb01a9fdadbffe48324ff60f3d70e27513d775 Gerrit-Change-Number: 46975 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/intel/broadwell/pch/sata.c: Use common ABAR helpers
by Angel Pons (Code Review) 13 Nov '20

13 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47027 ) Change subject: soc/intel/broadwell/pch/sata.c: Use common ABAR helpers ...................................................................... soc/intel/broadwell/pch/sata.c: Use common ABAR helpers Change-Id: I2316794628be1ebc524aaa6a460ba6770b700a56 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/sata.c 1 file changed, 41 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/47027/1 diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/soc/intel/broadwell/pch/sata.c index 8b2c513..e157252 100644 --- a/src/soc/intel/broadwell/pch/sata.c +++ b/src/soc/intel/broadwell/pch/sata.c @@ -7,6 +7,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <delay.h> +#include <southbridge/intel/common/abar.h> #include <soc/intel/broadwell/pch/chip.h> #include "iobp.h" @@ -39,14 +40,15 @@ { const struct soc_intel_broadwell_pch_config *config = config_of(dev); u32 reg32; - u8 *abar; - int port; printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n"); /* Enable memory space decoding for ABAR */ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + const uintptr_t abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "ABAR: %p\n", (void *)abar); + /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a); @@ -75,38 +77,50 @@ pci_write_config32(dev, 0x94, reg32); /* Initialize AHCI memory-mapped space */ - abar = (u8 *)(pci_read_config32(dev, PCI_BASE_ADDRESS_5)); - printk(BIOS_DEBUG, "ABAR: %p\n", abar); - /* CAP (HBA Capabilities) : enable power management */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */ - reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ - reg32 |= (1 << 18); /* SAM: SATA AHCI MODE ONLY */ - write32(abar + 0x00, reg32); + union abar_reg_cap abar_cap = { + .raw = abar_read32(abar, ABAR_REG_CAP), + }; - /* PI (Ports implemented) */ - write32(abar + 0x0c, config->sata_port_map); - (void) read32(abar + 0x0c); /* Read back 1 */ - (void) read32(abar + 0x0c); /* Read back 2 */ + abar_cap.external_sata = 0; /* Should be configurable */ + abar_cap.enclosure_management = 0; + abar_cap.port_multiplier = 0; - /* CAP2 (HBA Capabilities Extended)*/ + abar_cap.partial_state = 1; + abar_cap.slumber_state = 1; + abar_cap.aggressive_link_pm = 1; + abar_cap.staggered_spinup = 1; + abar_cap.ahci_mode_only = 1; + + abar_write32(abar, ABAR_REG_CAP, abar_cap.raw); + + abar_write_ports_implemented(abar, config->sata_port_map); + + union abar_reg_cap_2 abar_cap_2 = { + .raw = abar_read32(abar, ABAR_REG_CAP_2), + }; + if (config->sata_devslp_disable) { - reg32 = read32(abar + 0x24); - reg32 &= ~(1 << 3); - write32(abar + 0x24, reg32); - } else { - /* Enable DEVSLP */ - reg32 = read32(abar + 0x24); - reg32 |= (1 << 5) | (1 << 4)|(1 << 3)|(1 << 2); - write32(abar + 0x24, reg32); + abar_cap_2.supports_device_sleep = 0; - for (port = 0; port < 4; port++) { + abar_write32(abar, ABAR_REG_CAP_2, abar_cap_2.raw); + } else { + abar_cap_2.auto_partial_to_slumber = 1; + abar_cap_2.supports_device_sleep = 1; + abar_cap_2.aggressive_devslp_mgmt = 1; + abar_cap_2.devslp_entry_slumber_only = 1; + + abar_write32(abar, ABAR_REG_CAP_2, abar_cap_2.raw); + + for (int port = 0; port < 4; port++) { if (!(config->sata_port_map & (1 << port))) continue; - reg32 = read32(abar + 0x144 + (0x80 * port)); - reg32 |= (1 << 1); /* DEVSLP DSP */ - write32(abar + 0x144 + (0x80 * port), reg32); + + union abar_reg_px_devslp px_devslp = { + .raw = abar_read32(abar, ABAR_REG_PxDEVSLP(port)), + }; + px_devslp.device_sleep_present = 1; + abar_write32(abar, ABAR_REG_PxDEVSLP(port), px_devslp.raw); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/47027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2316794628be1ebc524aaa6a460ba6770b700a56 Gerrit-Change-Number: 47027 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell: Split up acpi.c
by Angel Pons (Code Review) 13 Nov '20

13 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46796 ) Change subject: soc/intel/broadwell: Split up acpi.c ...................................................................... soc/intel/broadwell: Split up acpi.c Change-Id: Ie9c57b6f5c226cee8797027941fa03e69de52923 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/cpu/Makefile.inc A src/soc/intel/broadwell/cpu/acpi.c M src/soc/intel/broadwell/pch/Makefile.inc A src/soc/intel/broadwell/pch/acpi.c 5 files changed, 452 insertions(+), 396 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/46796/1 diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 7366642..9b5ac9e 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -26,128 +26,6 @@ #include <soc/systemagent.h> #include <soc/intel/broadwell/chip.h> -/* - * List of supported C-states in this processor. Only the ULT parts support C8, - * C9, and C10. - */ -enum { - C_STATE_C0, /* 0 */ - C_STATE_C1, /* 1 */ - C_STATE_C1E, /* 2 */ - C_STATE_C3, /* 3 */ - C_STATE_C6_SHORT_LAT, /* 4 */ - C_STATE_C6_LONG_LAT, /* 5 */ - C_STATE_C7_SHORT_LAT, /* 6 */ - C_STATE_C7_LONG_LAT, /* 7 */ - C_STATE_C7S_SHORT_LAT, /* 8 */ - C_STATE_C7S_LONG_LAT, /* 9 */ - C_STATE_C8, /* 10 */ - C_STATE_C9, /* 11 */ - C_STATE_C10, /* 12 */ - NUM_C_STATES -}; - -#define MWAIT_RES(state, sub_state) \ - { \ - .addrl = (((state) << 4) | (sub_state)), \ - .space_id = ACPI_ADDRESS_SPACE_FIXED, \ - .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ - .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ - .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ - } - -static acpi_cstate_t cstate_map[NUM_C_STATES] = { - [C_STATE_C0] = { }, - [C_STATE_C1] = { - .latency = 0, - .power = 1000, - .resource = MWAIT_RES(0, 0), - }, - [C_STATE_C1E] = { - .latency = 0, - .power = 1000, - .resource = MWAIT_RES(0, 1), - }, - [C_STATE_C3] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), - .power = 900, - .resource = MWAIT_RES(1, 0), - }, - [C_STATE_C6_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 800, - .resource = MWAIT_RES(2, 0), - }, - [C_STATE_C6_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 800, - .resource = MWAIT_RES(2, 1), - }, - [C_STATE_C7_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 700, - .resource = MWAIT_RES(3, 0), - }, - [C_STATE_C7_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 700, - .resource = MWAIT_RES(3, 1), - }, - [C_STATE_C7S_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(1), - .power = 700, - .resource = MWAIT_RES(3, 2), - }, - [C_STATE_C7S_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(2), - .power = 700, - .resource = MWAIT_RES(3, 3), - }, - [C_STATE_C8] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(3), - .power = 600, - .resource = MWAIT_RES(4, 0), - }, - [C_STATE_C9] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(4), - .power = 500, - .resource = MWAIT_RES(5, 0), - }, - [C_STATE_C10] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(5), - .power = 400, - .resource = MWAIT_RES(6, 0), - }, -}; - -static int cstate_set_s0ix[3] = { - C_STATE_C1E, - C_STATE_C7S_LONG_LAT, - C_STATE_C10 -}; - -static int cstate_set_non_s0ix[3] = { - C_STATE_C1E, - C_STATE_C3, - C_STATE_C7S_LONG_LAT -}; - -static int get_cores_per_package(void) -{ - struct cpuinfo_x86 c; - struct cpuid_result result; - int cores = 1; - - get_fms(&c, cpuid_eax(1)); - if (c.x86 != 6) - return 1; - - result = cpuid_ext(0xb, 1); - cores = result.ebx & 0xff; - - return cores; -} - unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, @@ -155,252 +33,6 @@ return current; } -static acpi_tstate_t tss_table_fine[] = { - { 100, 1000, 0, 0x00, 0 }, - { 94, 940, 0, 0x1f, 0 }, - { 88, 880, 0, 0x1e, 0 }, - { 82, 820, 0, 0x1d, 0 }, - { 75, 760, 0, 0x1c, 0 }, - { 69, 700, 0, 0x1b, 0 }, - { 63, 640, 0, 0x1a, 0 }, - { 57, 580, 0, 0x19, 0 }, - { 50, 520, 0, 0x18, 0 }, - { 44, 460, 0, 0x17, 0 }, - { 38, 400, 0, 0x16, 0 }, - { 32, 340, 0, 0x15, 0 }, - { 25, 280, 0, 0x14, 0 }, - { 19, 220, 0, 0x13, 0 }, - { 13, 160, 0, 0x12, 0 }, -}; - -static acpi_tstate_t tss_table_coarse[] = { - { 100, 1000, 0, 0x00, 0 }, - { 88, 875, 0, 0x1f, 0 }, - { 75, 750, 0, 0x1e, 0 }, - { 63, 625, 0, 0x1d, 0 }, - { 50, 500, 0, 0x1c, 0 }, - { 38, 375, 0, 0x1b, 0 }, - { 25, 250, 0, 0x1a, 0 }, - { 13, 125, 0, 0x19, 0 }, -}; - -static void generate_T_state_entries(int core, int cores_per_package) -{ - /* Indicate SW_ALL coordination for T-states */ - acpigen_write_TSD_package(core, cores_per_package, SW_ALL); - - /* Indicate FFixedHW so OS will use MSR */ - acpigen_write_empty_PTC(); - - /* Set a T-state limit that can be modified in NVS */ - acpigen_write_TPC("\\TLVL"); - - /* - * CPUID.(EAX=6):EAX[5] indicates support - * for extended throttle levels. - */ - if (cpuid_eax(6) & (1 << 5)) - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_fine), tss_table_fine); - else - acpigen_write_TSS_package( - ARRAY_SIZE(tss_table_coarse), tss_table_coarse); -} - -static void generate_C_state_entries(void) -{ - acpi_cstate_t map[3]; - int *set; - int i; - - config_t *config = config_of_soc(); - - if (config->s0ix_enable) - set = cstate_set_s0ix; - else - set = cstate_set_non_s0ix; - - for (i = 0; i < 3; i++) { - memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); - map[i].ctype = i + 1; - } - - /* Generate C-state tables */ - acpigen_write_CST_package(map, ARRAY_SIZE(map)); -} - -static int calculate_power(int tdp, int p1_ratio, int ratio) -{ - u32 m; - u32 power; - - /* - * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 - * - * Power = (ratio / p1_ratio) * m * tdp - */ - - m = (110000 - ((p1_ratio - ratio) * 625)) / 11; - m = (m * m) / 1000; - - power = ((ratio * 100000 / p1_ratio) / 100); - power *= (m / 100) * (tdp / 1000); - power /= 1000; - - return (int)power; -} - -static void generate_P_state_entries(int core, int cores_per_package) -{ - int ratio_min, ratio_max, ratio_turbo, ratio_step; - int coord_type, power_max, power_unit, num_entries; - int ratio, power, clock, clock_max; - msr_t msr; - - /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ - msr = rdmsr(MSR_MISC_PWR_MGMT); - if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) - coord_type = SW_ANY; - else - coord_type = HW_ALL; - - /* Get bus ratio limits and calculate clock speeds */ - msr = rdmsr(MSR_PLATFORM_INFO); - ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ - - /* Determine if this CPU has configurable TDP */ - if (cpu_config_tdp_levels()) { - /* Set max ratio to nominal TDP ratio */ - msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); - ratio_max = msr.lo & 0xff; - } else { - /* Max Non-Turbo Ratio */ - ratio_max = (msr.lo >> 8) & 0xff; - } - clock_max = ratio_max * CPU_BCLK; - - /* Calculate CPU TDP in mW */ - msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); - power_unit = 2 << ((msr.lo & 0xf) - 1); - msr = rdmsr(MSR_PKG_POWER_SKU); - power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; - - /* Write _PCT indicating use of FFixedHW */ - acpigen_write_empty_PCT(); - - /* Write _PPC with no limit on supported P-state */ - acpigen_write_PPC_NVS(); - - /* Write PSD indicating configured coordination type */ - acpigen_write_PSD_package(core, 1, coord_type); - - /* Add P-state entries in _PSS table */ - acpigen_write_name("_PSS"); - - /* Determine ratio points */ - ratio_step = PSS_RATIO_STEP; - num_entries = (ratio_max - ratio_min) / ratio_step; - while (num_entries > PSS_MAX_ENTRIES-1) { - ratio_step <<= 1; - num_entries >>= 1; - } - - /* P[T] is Turbo state if enabled */ - if (get_turbo_state() == TURBO_ENABLED) { - /* _PSS package count including Turbo */ - acpigen_write_package(num_entries + 2); - - msr = rdmsr(MSR_TURBO_RATIO_LIMIT); - ratio_turbo = msr.lo & 0xff; - - /* Add entry for Turbo ratio */ - acpigen_write_PSS_package( - clock_max + 1, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_turbo << 8, /*control*/ - ratio_turbo << 8); /*status*/ - } else { - /* _PSS package count without Turbo */ - acpigen_write_package(num_entries + 1); - } - - /* First regular entry is max non-turbo ratio */ - acpigen_write_PSS_package( - clock_max, /*MHz*/ - power_max, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio_max << 8, /*control*/ - ratio_max << 8); /*status*/ - - /* Generate the remaining entries */ - for (ratio = ratio_min + ((num_entries - 1) * ratio_step); - ratio >= ratio_min; ratio -= ratio_step) { - - /* Calculate power at this ratio */ - power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * CPU_BCLK; - - acpigen_write_PSS_package( - clock, /*MHz*/ - power, /*mW*/ - PSS_LATENCY_TRANSITION, /*lat1*/ - PSS_LATENCY_BUSMASTER, /*lat2*/ - ratio << 8, /*control*/ - ratio << 8); /*status*/ - } - - /* Fix package length */ - acpigen_pop_len(); -} - -void generate_cpu_entries(const struct device *device) -{ - int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; - int totalcores = dev_count_cpu(); - int cores_per_package = get_cores_per_package(); - int numcpus = totalcores/cores_per_package; - - printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", - numcpus, cores_per_package); - - for (cpuID = 1; cpuID <= numcpus; cpuID++) { - for (coreID = 1; coreID <= cores_per_package; coreID++) { - if (coreID > 1) { - pcontrol_blk = 0; - plen = 0; - } - - /* Generate processor \_SB.CPUx */ - acpigen_write_processor( - (cpuID - 1) * cores_per_package+coreID - 1, - pcontrol_blk, plen); - - /* Generate P-state tables */ - generate_P_state_entries( - coreID - 1, cores_per_package); - - /* Generate C-state tables */ - generate_C_state_entries(); - - /* Generate T-state tables */ - generate_T_state_entries( - cpuID - 1, cores_per_package); - - acpigen_pop_len(); - } - } - - /* PPKG is usually used for thermal management - of the first and only package. */ - acpigen_write_processor_package("PPKG", 0, cores_per_package); - - /* Add a method to notify processor nodes */ - acpigen_write_processor_cnot(cores_per_package); -} - static unsigned long acpi_fill_dmar(unsigned long current) { struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); @@ -471,31 +103,3 @@ return current; } - -unsigned long acpi_fill_madt(unsigned long current) -{ - int sci = acpi_sci_irq(); - acpi_madt_irqoverride_t *irqovr; - uint16_t flags = MP_IRQ_TRIGGER_LEVEL; - - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); - - if (sci >= 20) - flags |= MP_IRQ_POLARITY_LOW; - else - flags |= MP_IRQ_POLARITY_HIGH; - - /* SCI */ - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, sci, sci, flags); - - return current; -} diff --git a/src/soc/intel/broadwell/cpu/Makefile.inc b/src/soc/intel/broadwell/cpu/Makefile.inc index e9f4637..803696a 100644 --- a/src/soc/intel/broadwell/cpu/Makefile.inc +++ b/src/soc/intel/broadwell/cpu/Makefile.inc @@ -16,6 +16,7 @@ postcar-y += ../../../../cpu/intel/car/non-evict/exit_car.S +ramstage-y += acpi.c ramstage-y += cpu.c ramstage-y += smmrelocate.c diff --git a/src/soc/intel/broadwell/cpu/acpi.c b/src/soc/intel/broadwell/cpu/acpi.c new file mode 100644 index 0000000..ec3d588 --- /dev/null +++ b/src/soc/intel/broadwell/cpu/acpi.c @@ -0,0 +1,395 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> +#include <acpi/acpigen.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> +#include <cbmem.h> +#include <device/pci_ops.h> +#include <cpu/x86/smm.h> +#include <console/console.h> +#include <types.h> +#include <string.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/intel/turbo.h> +#include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <soc/acpi.h> +#include <soc/cpu.h> +#include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/msr.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <soc/systemagent.h> +#include <soc/intel/broadwell/chip.h> + +/* + * List of supported C-states in this processor. Only the ULT parts support C8, + * C9, and C10. + */ +enum { + C_STATE_C0, /* 0 */ + C_STATE_C1, /* 1 */ + C_STATE_C1E, /* 2 */ + C_STATE_C3, /* 3 */ + C_STATE_C6_SHORT_LAT, /* 4 */ + C_STATE_C6_LONG_LAT, /* 5 */ + C_STATE_C7_SHORT_LAT, /* 6 */ + C_STATE_C7_LONG_LAT, /* 7 */ + C_STATE_C7S_SHORT_LAT, /* 8 */ + C_STATE_C7S_LONG_LAT, /* 9 */ + C_STATE_C8, /* 10 */ + C_STATE_C9, /* 11 */ + C_STATE_C10, /* 12 */ + NUM_C_STATES +}; + +#define MWAIT_RES(state, sub_state) \ + { \ + .addrl = (((state) << 4) | (sub_state)), \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ + } + +static acpi_cstate_t cstate_map[NUM_C_STATES] = { + [C_STATE_C0] = { }, + [C_STATE_C1] = { + .latency = 0, + .power = 1000, + .resource = MWAIT_RES(0, 0), + }, + [C_STATE_C1E] = { + .latency = 0, + .power = 1000, + .resource = MWAIT_RES(0, 1), + }, + [C_STATE_C3] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .power = 900, + .resource = MWAIT_RES(1, 0), + }, + [C_STATE_C6_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 800, + .resource = MWAIT_RES(2, 0), + }, + [C_STATE_C6_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 800, + .resource = MWAIT_RES(2, 1), + }, + [C_STATE_C7_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 700, + .resource = MWAIT_RES(3, 0), + }, + [C_STATE_C7_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 700, + .resource = MWAIT_RES(3, 1), + }, + [C_STATE_C7S_SHORT_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(1), + .power = 700, + .resource = MWAIT_RES(3, 2), + }, + [C_STATE_C7S_LONG_LAT] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(2), + .power = 700, + .resource = MWAIT_RES(3, 3), + }, + [C_STATE_C8] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(3), + .power = 600, + .resource = MWAIT_RES(4, 0), + }, + [C_STATE_C9] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(4), + .power = 500, + .resource = MWAIT_RES(5, 0), + }, + [C_STATE_C10] = { + .latency = C_STATE_LATENCY_FROM_LAT_REG(5), + .power = 400, + .resource = MWAIT_RES(6, 0), + }, +}; + +static int cstate_set_s0ix[3] = { + C_STATE_C1E, + C_STATE_C7S_LONG_LAT, + C_STATE_C10 +}; + +static int cstate_set_non_s0ix[3] = { + C_STATE_C1E, + C_STATE_C3, + C_STATE_C7S_LONG_LAT +}; + +static int get_cores_per_package(void) +{ + struct cpuinfo_x86 c; + struct cpuid_result result; + int cores = 1; + + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return 1; + + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; + + return cores; +} + +static acpi_tstate_t tss_table_fine[] = { + { 100, 1000, 0, 0x00, 0 }, + { 94, 940, 0, 0x1f, 0 }, + { 88, 880, 0, 0x1e, 0 }, + { 82, 820, 0, 0x1d, 0 }, + { 75, 760, 0, 0x1c, 0 }, + { 69, 700, 0, 0x1b, 0 }, + { 63, 640, 0, 0x1a, 0 }, + { 57, 580, 0, 0x19, 0 }, + { 50, 520, 0, 0x18, 0 }, + { 44, 460, 0, 0x17, 0 }, + { 38, 400, 0, 0x16, 0 }, + { 32, 340, 0, 0x15, 0 }, + { 25, 280, 0, 0x14, 0 }, + { 19, 220, 0, 0x13, 0 }, + { 13, 160, 0, 0x12, 0 }, +}; + +static acpi_tstate_t tss_table_coarse[] = { + { 100, 1000, 0, 0x00, 0 }, + { 88, 875, 0, 0x1f, 0 }, + { 75, 750, 0, 0x1e, 0 }, + { 63, 625, 0, 0x1d, 0 }, + { 50, 500, 0, 0x1c, 0 }, + { 38, 375, 0, 0x1b, 0 }, + { 25, 250, 0, 0x1a, 0 }, + { 13, 125, 0, 0x19, 0 }, +}; + +static void generate_T_state_entries(int core, int cores_per_package) +{ + /* Indicate SW_ALL coordination for T-states */ + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + + /* Indicate FFixedHW so OS will use MSR */ + acpigen_write_empty_PTC(); + + /* Set a T-state limit that can be modified in NVS */ + acpigen_write_TPC("\\TLVL"); + + /* + * CPUID.(EAX=6):EAX[5] indicates support + * for extended throttle levels. + */ + if (cpuid_eax(6) & (1 << 5)) + acpigen_write_TSS_package( + ARRAY_SIZE(tss_table_fine), tss_table_fine); + else + acpigen_write_TSS_package( + ARRAY_SIZE(tss_table_coarse), tss_table_coarse); +} + +static void generate_C_state_entries(void) +{ + acpi_cstate_t map[3]; + int *set; + int i; + + config_t *config = config_of_soc(); + + if (config->s0ix_enable) + set = cstate_set_s0ix; + else + set = cstate_set_non_s0ix; + + for (i = 0; i < 3; i++) { + memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); + map[i].ctype = i + 1; + } + + /* Generate C-state tables */ + acpigen_write_CST_package(map, ARRAY_SIZE(map)); +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + + return (int)power; +} + +static void generate_P_state_entries(int core, int cores_per_package) +{ + int ratio_min, ratio_max, ratio_turbo, ratio_step; + int coord_type, power_max, power_unit, num_entries; + int ratio, power, clock, clock_max; + msr_t msr; + + /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) + coord_type = SW_ANY; + else + coord_type = HW_ALL; + + /* Get bus ratio limits and calculate clock speeds */ + msr = rdmsr(MSR_PLATFORM_INFO); + ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ + + /* Determine if this CPU has configurable TDP */ + if (cpu_config_tdp_levels()) { + /* Set max ratio to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + ratio_max = msr.lo & 0xff; + } else { + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + } + clock_max = ratio_max * CPU_BCLK; + + /* Calculate CPU TDP in mW */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + msr = rdmsr(MSR_PKG_POWER_SKU); + power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; + + /* Write _PCT indicating use of FFixedHW */ + acpigen_write_empty_PCT(); + + /* Write _PPC with no limit on supported P-state */ + acpigen_write_PPC_NVS(); + + /* Write PSD indicating configured coordination type */ + acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = PSS_RATIO_STEP; + num_entries = (ratio_max - ratio_min) / ratio_step; + while (num_entries > PSS_MAX_ENTRIES-1) { + ratio_step <<= 1; + num_entries >>= 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + acpigen_write_package(num_entries + 2); + + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + ratio_turbo = msr.lo & 0xff; + + /* Add entry for Turbo ratio */ + acpigen_write_PSS_package( + clock_max + 1, /*MHz*/ + power_max, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio_turbo << 8, /*control*/ + ratio_turbo << 8); /*status*/ + } else { + /* _PSS package count without Turbo */ + acpigen_write_package(num_entries + 1); + } + + /* First regular entry is max non-turbo ratio */ + acpigen_write_PSS_package( + clock_max, /*MHz*/ + power_max, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio_max << 8, /*control*/ + ratio_max << 8); /*status*/ + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = ratio * CPU_BCLK; + + acpigen_write_PSS_package( + clock, /*MHz*/ + power, /*mW*/ + PSS_LATENCY_TRANSITION, /*lat1*/ + PSS_LATENCY_BUSMASTER, /*lat2*/ + ratio << 8, /*control*/ + ratio << 8); /*status*/ + } + + /* Fix package length */ + acpigen_pop_len(); +} + +void generate_cpu_entries(const struct device *device) +{ + int coreID, cpuID, pcontrol_blk = ACPI_BASE_ADDRESS, plen = 6; + int totalcores = dev_count_cpu(); + int cores_per_package = get_cores_per_package(); + int numcpus = totalcores/cores_per_package; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", + numcpus, cores_per_package); + + for (cpuID = 1; cpuID <= numcpus; cpuID++) { + for (coreID = 1; coreID <= cores_per_package; coreID++) { + if (coreID > 1) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_SB.CPUx */ + acpigen_write_processor( + (cpuID - 1) * cores_per_package+coreID - 1, + pcontrol_blk, plen); + + /* Generate P-state tables */ + generate_P_state_entries( + coreID - 1, cores_per_package); + + /* Generate C-state tables */ + generate_C_state_entries(); + + /* Generate T-state tables */ + generate_T_state_entries( + cpuID - 1, cores_per_package); + + acpigen_pop_len(); + } + } + + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, cores_per_package); + + /* Add a method to notify processor nodes */ + acpigen_write_processor_cnot(cores_per_package); +} diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/soc/intel/broadwell/pch/Makefile.inc index 1c19613..119534f 100644 --- a/src/soc/intel/broadwell/pch/Makefile.inc +++ b/src/soc/intel/broadwell/pch/Makefile.inc @@ -1,5 +1,6 @@ bootblock-y += bootblock.c +ramstage-y += acpi.c ramstage-y += adsp.c romstage-y += early_pch.c ramstage-$(CONFIG_ELOG) += elog.c diff --git a/src/soc/intel/broadwell/pch/acpi.c b/src/soc/intel/broadwell/pch/acpi.c new file mode 100644 index 0000000..712bb46 --- /dev/null +++ b/src/soc/intel/broadwell/pch/acpi.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> +#include <acpi/acpigen.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> +#include <cbmem.h> +#include <device/pci_ops.h> +#include <cpu/x86/smm.h> +#include <console/console.h> +#include <types.h> +#include <string.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/intel/turbo.h> +#include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <soc/acpi.h> +#include <soc/cpu.h> +#include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/msr.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <soc/systemagent.h> +#include <soc/intel/broadwell/chip.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + int sci = acpi_sci_irq(); + acpi_madt_irqoverride_t *irqovr; + uint16_t flags = MP_IRQ_TRIGGER_LEVEL; + + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); + + if (sci >= 20) + flags |= MP_IRQ_POLARITY_LOW; + else + flags |= MP_IRQ_POLARITY_HIGH; + + /* SCI */ + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, sci, sci, flags); + + return current; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9c57b6f5c226cee8797027941fa03e69de52923 Gerrit-Change-Number: 46796 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/broadwell: Flatten northbridge folder structure
by Angel Pons (Code Review) 13 Nov '20

13 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46795 ) Change subject: soc/intel/broadwell: Flatten northbridge folder structure ...................................................................... soc/intel/broadwell: Flatten northbridge folder structure Having folders for bootblock and romstage is no longer necessary. Change-Id: I7d1f4063de6a1a1ff9ee7478e94f889a50102054 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Makefile.inc R src/soc/intel/broadwell/bootblock.c R src/soc/intel/broadwell/early_init.c R src/soc/intel/broadwell/raminit.c R src/soc/intel/broadwell/report_platform.c R src/soc/intel/broadwell/romstage.c D src/soc/intel/broadwell/romstage/Makefile.inc 7 files changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/46795/1 diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index dc6bd93..7ee6990 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,11 +1,14 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) -subdirs-y += romstage - subdirs-y += cpu subdirs-y += pch -bootblock-y += bootblock/systemagent.c +bootblock-y += bootblock.c + +romstage-y += early_init.c +romstage-y += raminit.c +romstage-y += report_platform.c +romstage-y += romstage.c ramstage-y += acpi.c ramstage-y += finalize.c diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock.c similarity index 100% rename from src/soc/intel/broadwell/bootblock/systemagent.c rename to src/soc/intel/broadwell/bootblock.c diff --git a/src/soc/intel/broadwell/romstage/systemagent.c b/src/soc/intel/broadwell/early_init.c similarity index 100% rename from src/soc/intel/broadwell/romstage/systemagent.c rename to src/soc/intel/broadwell/early_init.c diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/raminit.c similarity index 100% rename from src/soc/intel/broadwell/romstage/raminit.c rename to src/soc/intel/broadwell/raminit.c diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/soc/intel/broadwell/report_platform.c similarity index 100% rename from src/soc/intel/broadwell/romstage/report_platform.c rename to src/soc/intel/broadwell/report_platform.c diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage.c similarity index 100% rename from src/soc/intel/broadwell/romstage/romstage.c rename to src/soc/intel/broadwell/romstage.c diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc deleted file mode 100644 index 65cb9ad..0000000 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -romstage-y += raminit.c -romstage-y += report_platform.c -romstage-y += romstage.c -romstage-y += systemagent.c -- To view, visit https://review.coreboot.org/c/coreboot/+/46795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d1f4063de6a1a1ff9ee7478e94f889a50102054 Gerrit-Change-Number: 46795 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/broadwell: Relocate CPU files
by Angel Pons (Code Review) 13 Nov '20

13 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46794 ) Change subject: soc/intel/broadwell: Relocate CPU files ...................................................................... soc/intel/broadwell: Relocate CPU files Change-Id: Ib2ddce78db21db9c8deac632a77ecd71eb9887c2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Makefile.inc A src/soc/intel/broadwell/cpu/Makefile.inc R src/soc/intel/broadwell/cpu/bootblock.c R src/soc/intel/broadwell/cpu/cpu.c R src/soc/intel/broadwell/cpu/romstage.c R src/soc/intel/broadwell/cpu/smmrelocate.c R src/soc/intel/broadwell/cpu/tsc_freq.c M src/soc/intel/broadwell/romstage/Makefile.inc 8 files changed, 30 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/46794/1 diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index ce1dd9c..dc6bd93 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,24 +1,13 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/lapic -subdirs-y += ../../../cpu/x86/mtrr -subdirs-y += ../../../cpu/x86/smm -subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../cpu/intel/microcode -subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/intel/common +subdirs-y += cpu subdirs-y += pch -bootblock-y += bootblock/cpu.c bootblock-y += bootblock/systemagent.c -bootblock-y += ../../../cpu/intel/car/bootblock.c -bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S -bootblock-y += ../../../cpu/x86/early_reset.S ramstage-y += acpi.c -ramstage-y += cpu.c ramstage-y += finalize.c ramstage-y += gma.c ramstage-y += memmap.c @@ -29,18 +18,7 @@ romstage-y += pei_data.c ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c -ramstage-y += smmrelocate.c ramstage-y += systemagent.c -bootblock-y += tsc_freq.c -ramstage-y += tsc_freq.c -romstage-y += tsc_freq.c -smm-y += tsc_freq.c -postcar-y += tsc_freq.c -verstage-y += tsc_freq.c - -postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S - -cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin CPPFLAGS_common += -Isrc/soc/intel/broadwell/include diff --git a/src/soc/intel/broadwell/cpu/Makefile.inc b/src/soc/intel/broadwell/cpu/Makefile.inc new file mode 100644 index 0000000..e9f4637 --- /dev/null +++ b/src/soc/intel/broadwell/cpu/Makefile.inc @@ -0,0 +1,29 @@ +subdirs-y += ../../../../cpu/x86/lapic +subdirs-y += ../../../../cpu/x86/mtrr +subdirs-y += ../../../../cpu/x86/smm +subdirs-y += ../../../../cpu/x86/tsc +subdirs-y += ../../../../cpu/intel/microcode +subdirs-y += ../../../../cpu/intel/turbo +subdirs-y += ../../../../cpu/intel/common + +bootblock-y += bootblock.c +bootblock-y += ../../../../cpu/intel/car/bootblock.c +bootblock-y += ../../../../cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../../../../cpu/x86/early_reset.S + +romstage-y += romstage.c +romstage-y += ../../../../cpu/intel/car/romstage.c + +postcar-y += ../../../../cpu/intel/car/non-evict/exit_car.S + +ramstage-y += cpu.c +ramstage-y += smmrelocate.c + +bootblock-y += tsc_freq.c +ramstage-y += tsc_freq.c +romstage-y += tsc_freq.c +smm-y += tsc_freq.c +postcar-y += tsc_freq.c +verstage-y += tsc_freq.c + +cpu_microcode_bins += 3rdparty/blobs/soc/intel/broadwell/microcode.bin diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/cpu/bootblock.c similarity index 100% rename from src/soc/intel/broadwell/bootblock/cpu.c rename to src/soc/intel/broadwell/cpu/bootblock.c diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu/cpu.c similarity index 100% rename from src/soc/intel/broadwell/cpu.c rename to src/soc/intel/broadwell/cpu/cpu.c diff --git a/src/soc/intel/broadwell/romstage/cpu.c b/src/soc/intel/broadwell/cpu/romstage.c similarity index 100% rename from src/soc/intel/broadwell/romstage/cpu.c rename to src/soc/intel/broadwell/cpu/romstage.c diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/cpu/smmrelocate.c similarity index 100% rename from src/soc/intel/broadwell/smmrelocate.c rename to src/soc/intel/broadwell/cpu/smmrelocate.c diff --git a/src/soc/intel/broadwell/tsc_freq.c b/src/soc/intel/broadwell/cpu/tsc_freq.c similarity index 100% rename from src/soc/intel/broadwell/tsc_freq.c rename to src/soc/intel/broadwell/cpu/tsc_freq.c diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index b77e7a5..65cb9ad 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -1,5 +1,3 @@ -romstage-y += ../../../../cpu/intel/car/romstage.c -romstage-y += cpu.c romstage-y += raminit.c romstage-y += report_platform.c romstage-y += romstage.c -- To view, visit https://review.coreboot.org/c/coreboot/+/46794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2ddce78db21db9c8deac632a77ecd71eb9887c2 Gerrit-Change-Number: 46794 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: broadwell: Flatten `acpi_init_gnvs` function
by Angel Pons (Code Review) 13 Nov '20

13 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46793 ) Change subject: broadwell: Flatten `acpi_init_gnvs` function ...................................................................... broadwell: Flatten `acpi_init_gnvs` function Instead of relying on mainboards to call it, do like Lynx Point. Change-Id: Idb7457e0734e19d0a26f0762079e273b6e740475 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/acpi_tables.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/purism/librem_bdw/acpi_tables.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/pch/lpc.c 6 files changed, 26 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/46793/1 diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c index 54c23c9..5284cef 100644 --- a/src/mainboard/google/auron/acpi_tables.c +++ b/src/mainboard/google/auron/acpi_tables.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <arch/ioapic.h> #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <soc/acpi.h> @@ -9,8 +8,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 4fe7815..1197c0c 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> -#include <arch/ioapic.h> #include <device/device.h> #include <soc/acpi.h> #include <soc/nvs.h> @@ -10,8 +9,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 8c894a8..21a94bc 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> -#include <arch/ioapic.h> #include <device/device.h> #include <soc/acpi.h> #include <soc/nvs.h> @@ -10,8 +9,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); - /* Enable USB ports in S3 */ gnvs->s3u0 = 1; diff --git a/src/mainboard/purism/librem_bdw/acpi_tables.c b/src/mainboard/purism/librem_bdw/acpi_tables.c index a44808f..e127a56 100644 --- a/src/mainboard/purism/librem_bdw/acpi_tables.c +++ b/src/mainboard/purism/librem_bdw/acpi_tables.c @@ -2,11 +2,9 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> -#include <arch/ioapic.h> #include <soc/acpi.h> #include <soc/nvs.h> void acpi_create_gnvs(struct global_nvs *gnvs) { - acpi_init_gnvs(gnvs); } diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 651c5a4..7366642 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> +#include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <cbmem.h> #include <device/pci_ops.h> @@ -147,31 +148,6 @@ return cores; } -void acpi_init_gnvs(struct global_nvs *gnvs) -{ - /* Set unknown wake source */ - gnvs->pm1i = -1; - - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); - -#if CONFIG(CONSOLE_CBMEM) - /* Update the mem console pointer. */ - gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); -#endif - - if (CONFIG(CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); - if (CONFIG(EC_GOOGLE_CHROMEEC)) { - gnvs->chromeos.vbt2 = google_ec_running_ro() ? - ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; - } else { - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } - } -} - unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index 13ffd43..3102a5e 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -14,6 +14,8 @@ #include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <cbmem.h> +#include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/gnvs.h> #include <string.h> #include <soc/gpio.h> #include <soc/iobp.h> @@ -622,6 +624,29 @@ if (gnvs) { acpi_create_gnvs(gnvs); + + /* Set unknown wake source */ + gnvs->pm1i = -1; + + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + +#if CONFIG(CONSOLE_CBMEM) + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); +#endif + + if (CONFIG(CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_chromeos_acpi(&(gnvs->chromeos)); + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; + } else { + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } + } + /* And tell SMI about it */ apm_control(APM_CNT_GNVS_UPDATE); -- To view, visit https://review.coreboot.org/c/coreboot/+/46793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb7457e0734e19d0a26f0762079e273b6e740475 Gerrit-Change-Number: 46793 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: broadwell: Factor out `acpi_fill_madt` function
by Angel Pons (Code Review) 13 Nov '20

13 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46792 ) Change subject: broadwell: Factor out `acpi_fill_madt` function ...................................................................... broadwell: Factor out `acpi_fill_madt` function It is identical for all Broadwell mainboards, thus deduplicate it. Change-Id: I74559fbe42e44aa4d15ced5d88f6c15a1bf5203b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/acpi_tables.c M src/mainboard/google/jecht/acpi_tables.c M src/mainboard/intel/wtm2/acpi_tables.c M src/mainboard/purism/librem_bdw/acpi_tables.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/include/soc/acpi.h 6 files changed, 7 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/46792/1 diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c index 10dc637..54c23c9 100644 --- a/src/mainboard/google/auron/acpi_tables.c +++ b/src/mainboard/google/auron/acpi_tables.c @@ -24,18 +24,6 @@ gnvs->flvl = 1; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - return acpi_madt_irq_overrides(current); -} - void mainboard_fill_fadt(acpi_fadt_t *fadt) { fadt->preferred_pm_profile = PM_MOBILE; diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index f824cd8..4fe7815 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -25,18 +25,6 @@ gnvs->flvl = 1; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - return acpi_madt_irq_overrides(current); -} - void mainboard_fill_fadt(acpi_fadt_t *fadt) { fadt->preferred_pm_profile = PM_MOBILE; diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 62eb09a..8c894a8 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -23,18 +23,6 @@ gnvs->tmax = MAX_TEMPERATURE; } -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - return acpi_madt_irq_overrides(current); -} - void mainboard_fill_fadt(acpi_fadt_t *fadt) { fadt->preferred_pm_profile = PM_MOBILE; diff --git a/src/mainboard/purism/librem_bdw/acpi_tables.c b/src/mainboard/purism/librem_bdw/acpi_tables.c index ca6f64b..a44808f 100644 --- a/src/mainboard/purism/librem_bdw/acpi_tables.c +++ b/src/mainboard/purism/librem_bdw/acpi_tables.c @@ -10,15 +10,3 @@ { acpi_init_gnvs(gnvs); } - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - return acpi_madt_irq_overrides(current); -} diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 1b4db1d..651c5a4 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -496,12 +496,18 @@ return current; } -unsigned long acpi_madt_irq_overrides(unsigned long current) +unsigned long acpi_fill_madt(unsigned long current) { int sci = acpi_sci_irq(); acpi_madt_irqoverride_t *irqovr; uint16_t flags = MP_IRQ_TRIGGER_LEVEL; + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 2, IO_APIC_ADDR, 0); + /* INT_SRC_OVR */ irqovr = (void *)current; current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h index 0bf63a4..39d6cb4 100644 --- a/src/soc/intel/broadwell/include/soc/acpi.h +++ b/src/soc/intel/broadwell/include/soc/acpi.h @@ -12,7 +12,6 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10 -unsigned long acpi_madt_irq_overrides(unsigned long current); unsigned long northbridge_write_acpi_tables(const struct device *dev, unsigned long current, struct acpi_rsdp *rsdp); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74559fbe42e44aa4d15ced5d88f6c15a1bf5203b Gerrit-Change-Number: 46792 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell/acpi: Do not add PEG devices for LP
by Angel Pons (Code Review) 13 Nov '20

13 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46791 ) Change subject: nb/intel/haswell/acpi: Do not add PEG devices for LP ...................................................................... nb/intel/haswell/acpi: Do not add PEG devices for LP Haswell Low Power variants do not have PEG at all. Change-Id: Ia5577104b00bfc8713b54c3c43f8dcdd3bc367df Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/acpi/hostbridge.asl 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46791/1 diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 35246b3..28a33d8 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -200,5 +200,7 @@ /* Configurable TDP */ #include "ctdp.asl" +#if !CONFIG(INTEL_LYNXPOINT_LP) /* PCI Express Graphics */ #include "peg.asl" +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5577104b00bfc8713b54c3c43f8dcdd3bc367df Gerrit-Change-Number: 46791 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: nb/intel/haswell/acpi: Move PEG and CTDP includes downwards
by Angel Pons (Code Review) 13 Nov '20

13 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46790 ) Change subject: nb/intel/haswell/acpi: Move PEG and CTDP includes downwards ...................................................................... nb/intel/haswell/acpi: Move PEG and CTDP includes downwards This change is just to align with Broadwell. Change-Id: I25a481503f5df79502f5ae60c87e7dacb781adad Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/acpi/hostbridge.asl 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/46790/1 diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 3e617ec..35246b3 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -168,12 +168,6 @@ Return (MCRS) } -/* Configurable TDP */ -#include "ctdp.asl" - -/* PCI Express Graphics */ -#include "peg.asl" - /* PCI Device Resource Consumption */ Device (PDRC) { @@ -202,3 +196,9 @@ Return (PDRS) } } + +/* Configurable TDP */ +#include "ctdp.asl" + +/* PCI Express Graphics */ +#include "peg.asl" -- To view, visit https://review.coreboot.org/c/coreboot/+/46790 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25a481503f5df79502f5ae60c87e7dacb781adad Gerrit-Change-Number: 46790 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell/acpi: Merge `haswell.asl` into `hostbridge.asl`
by Angel Pons (Code Review) 13 Nov '20

13 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46789 ) Change subject: nb/intel/haswell/acpi: Merge `haswell.asl` into `hostbridge.asl` ...................................................................... nb/intel/haswell/acpi: Merge `haswell.asl` into `hostbridge.asl` Tested with BUILD_TIMELESS=1, Google Wolf remains identical. Change-Id: I710581156937b042ba4cf5948c65d0795ad37bbf Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/dsdt.asl M src/mainboard/asrock/h81m-hds/dsdt.asl M src/mainboard/google/beltino/dsdt.asl M src/mainboard/google/slippy/dsdt.asl M src/mainboard/intel/baskingridge/dsdt.asl M src/mainboard/lenovo/t440p/dsdt.asl M src/mainboard/supermicro/x10slm-f/dsdt.asl D src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl 9 files changed, 42 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/46789/1 diff --git a/src/mainboard/asrock/b85m_pro4/dsdt.asl b/src/mainboard/asrock/b85m_pro4/dsdt.asl index ea6dde6..bba5c2e 100644 --- a/src/mainboard/asrock/b85m_pro4/dsdt.asl +++ b/src/mainboard/asrock/b85m_pro4/dsdt.asl @@ -20,7 +20,7 @@ Device (\_SB.PCI0) { - #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <northbridge/intel/haswell/acpi/hostbridge.asl> #include <southbridge/intel/lynxpoint/acpi/pch.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/asrock/h81m-hds/dsdt.asl b/src/mainboard/asrock/h81m-hds/dsdt.asl index dd55ba8..d3e7ba1 100644 --- a/src/mainboard/asrock/h81m-hds/dsdt.asl +++ b/src/mainboard/asrock/h81m-hds/dsdt.asl @@ -20,7 +20,7 @@ { Device (PCI0) { - #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <northbridge/intel/haswell/acpi/hostbridge.asl> #include <southbridge/intel/lynxpoint/acpi/pch.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/google/beltino/dsdt.asl b/src/mainboard/google/beltino/dsdt.asl index 07a1d03..45442db 100644 --- a/src/mainboard/google/beltino/dsdt.asl +++ b/src/mainboard/google/beltino/dsdt.asl @@ -24,7 +24,7 @@ Scope (\_SB) { Device (PCI0) { - #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <northbridge/intel/haswell/acpi/hostbridge.asl> #include <southbridge/intel/lynxpoint/acpi/pch.asl> } } diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl index 71b7863..8ca683d 100644 --- a/src/mainboard/google/slippy/dsdt.asl +++ b/src/mainboard/google/slippy/dsdt.asl @@ -24,7 +24,7 @@ Scope (\_SB) { Device (PCI0) { - #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <northbridge/intel/haswell/acpi/hostbridge.asl> #include <southbridge/intel/lynxpoint/acpi/pch.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl index 7fdd69b..5971917 100644 --- a/src/mainboard/intel/baskingridge/dsdt.asl +++ b/src/mainboard/intel/baskingridge/dsdt.asl @@ -24,7 +24,7 @@ Scope (\_SB) { Device (PCI0) { - #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <northbridge/intel/haswell/acpi/hostbridge.asl> #include <southbridge/intel/lynxpoint/acpi/pch.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> diff --git a/src/mainboard/lenovo/t440p/dsdt.asl b/src/mainboard/lenovo/t440p/dsdt.asl index 426d801..9a54673 100644 --- a/src/mainboard/lenovo/t440p/dsdt.asl +++ b/src/mainboard/lenovo/t440p/dsdt.asl @@ -24,7 +24,7 @@ Device (\_SB.PCI0) { - #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <northbridge/intel/haswell/acpi/hostbridge.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/lynxpoint/acpi/pch.asl> } diff --git a/src/mainboard/supermicro/x10slm-f/dsdt.asl b/src/mainboard/supermicro/x10slm-f/dsdt.asl index 08a26ab..f8e9884 100644 --- a/src/mainboard/supermicro/x10slm-f/dsdt.asl +++ b/src/mainboard/supermicro/x10slm-f/dsdt.asl @@ -19,7 +19,7 @@ Device (\_SB.PCI0) { - #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <northbridge/intel/haswell/acpi/hostbridge.asl> #include <southbridge/intel/lynxpoint/acpi/pch.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl deleted file mode 100644 index 57344ab..0000000 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "../haswell.h" -#include "hostbridge.asl" -#include "peg.asl" -#include <southbridge/intel/common/rcba.h> - -/* PCI Device Resource Consumption */ -Device (PDRC) -{ - Name (_HID, EISAID ("PNP0C02")) - Name (_UID, 1) - - Name (PDRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000) - Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000) - Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000) - Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) - Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH - Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH - Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH - -#if CONFIG(CHROMEOS_RAMOOPS) - Memory32Fixed (ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) -#endif - }) - - // Current Resource Settings - Method (_CRS, 0, Serialized) - { - Return (PDRS) - } -} diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 534ff7f..33047c2 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include "../haswell.h" +#include <southbridge/intel/common/rcba.h> + Name (_HID, EISAID ("PNP0A08")) // PCIe Name (_CID, EISAID ("PNP0A03")) // PCI @@ -167,3 +170,35 @@ /* Configurable TDP */ #include "ctdp.asl" + +/* PCI Express Graphics */ +#include "peg.asl" + +/* PCI Device Resource Consumption */ +Device (PDRC) +{ + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 1) + + Name (PDRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000) + Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000) + Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000) + Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) + Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH + Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH + Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH + +#if CONFIG(CHROMEOS_RAMOOPS) + Memory32Fixed (ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, + CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) +#endif + }) + + // Current Resource Settings + Method (_CRS, 0, Serialized) + { + Return (PDRS) + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I710581156937b042ba4cf5948c65d0795ad37bbf Gerrit-Change-Number: 46789 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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