coreboot-gerrit October 2020

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Change in coreboot[master]: HACK: First set pwren to 0
by yongqiang niu (Code Review) 17 Nov '20

17 Nov '20

Hello Nicolas Boichat, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46581 to review the following change. Change subject: HACK: First set pwren to 0 ...................................................................... HACK: First set pwren to 0 Maybe not 100% necessary, but should still be good practise. BUG=b:155713214 TEST=boot asurada Change-Id: Ib8b3366795ae876227546be393681d8ac404e51b --- M src/mainboard/google/asurada/panel_anx7625.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/46581/1 diff --git a/src/mainboard/google/asurada/panel_anx7625.c b/src/mainboard/google/asurada/panel_anx7625.c index 0145859..10aa305 100644 --- a/src/mainboard/google/asurada/panel_anx7625.c +++ b/src/mainboard/google/asurada/panel_anx7625.c @@ -18,6 +18,7 @@ gpio_output(GPIO_PP3300_PANEL, 1); /* Turn on bridge */ + gpio_output(GPIO_MIPIBRDG_PWREN, 0); gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 0); gpio_output(GPIO_MIPIBRDG_PP1000_EN, 1); gpio_output(GPIO_MIPIBRDG_PP1800_EN, 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/46581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8b3366795ae876227546be393681d8ac404e51b Gerrit-Change-Number: 46581 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/amd/picasso: Drop the inclusion of entry16.ld and reset16.ld
by Furquan Shaikh (Code Review) 17 Nov '20

17 Nov '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43281 ) Change subject: soc/amd/picasso: Drop the inclusion of entry16.ld and reset16.ld ...................................................................... soc/amd/picasso: Drop the inclusion of entry16.ld and reset16.ld This change drops the inclusion of entry16.ld and reset16.ld instead adds the content of those files directly in memlayout.ld in picasso. This is done to allow the work for top-aligning bootblock to happen independent of Picasso layout. Once that is complete, Picasso layout can be re-evaluated to see if it can make use of the common bootblock linker file includes. TEST=Verified that coreboot.rom generated using --timeless is the same with and without this change for trembyle. Change-Id: Ib1218b24a06d0f69b856fb21458a6183fd21fcbc Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/amd/picasso/memlayout.ld 1 file changed, 16 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/43281/1 diff --git a/src/soc/amd/picasso/memlayout.ld b/src/soc/amd/picasso/memlayout.ld index 6f43ba1..b7f9167 100644 --- a/src/soc/amd/picasso/memlayout.ld +++ b/src/soc/amd/picasso/memlayout.ld @@ -95,7 +95,20 @@ } #if ENV_BOOTBLOCK -/* Bootblock specific scripts which provide more SECTION directives. */ -#include <cpu/x86/16bit/entry16.ld> -#include <cpu/x86/16bit/reset16.ld> + +gdtptr16_offset = gdtptr16 & 0xffff; +nullidt_offset = nullidt & 0xffff; + +SECTIONS { + /* Trigger an error if I have an unuseable start address */ + _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0; + _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); + + . = CONFIG_X86_RESET_VECTOR; + .reset . : { + *(.reset); + . = 15; + BYTE(0x00); + } +} #endif /* ENV_BOOTBLOCK */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1218b24a06d0f69b856fb21458a6183fd21fcbc Gerrit-Change-Number: 43281 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Enable SOC_INTEL_CSE_LITE_SKU_2_0
by Jamie Ryu (Code Review) 17 Nov '20

17 Nov '20

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46846 ) Change subject: mb/google/volteer: Enable SOC_INTEL_CSE_LITE_SKU_2_0 ...................................................................... mb/google/volteer: Enable SOC_INTEL_CSE_LITE_SKU_2_0 This enables CONFIG_SOC_INTEL_CSE_LITE_SKU_2_0 to add CSE RW blob into FW_MAIN_A_EXTN and FW_MAIN_B_EXTN FMAP regions to optimize boot time. BUG=b:166982406 TEST=build and boot volteer2 to OS. Verify warm boot time is reduced. Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: Ida67bfd022f4ef1031adbbb8361c8b84d20b92c8 --- M src/mainboard/google/volteer/Kconfig.name 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/46846/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index f59d82b..e3da732 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -6,12 +6,14 @@ select SOC_INTEL_CSE_LITE_SKU select USE_CAR_NEM_ENHANCED_V2 select DRIVERS_GENESYSLOGIC_GL9755 + select SOC_INTEL_CSE_LITE_SKU_2_0 config BOARD_GOOGLE_ELDRID bool "-> Eldrid" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU select USE_CAR_NEM_ENHANCED_V2 + select SOC_INTEL_CSE_LITE_SKU_2_0 config BOARD_GOOGLE_HALVOR bool "-> Halvor" @@ -33,6 +35,7 @@ select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU select USE_CAR_NEM_ENHANCED_V2 + select SOC_INTEL_CSE_LITE_SKU_2_0 config BOARD_GOOGLE_TODOR bool "-> Todor" @@ -57,12 +60,14 @@ select SOC_INTEL_CSE_LITE_SKU select USE_CAR_NEM_ENHANCED_V2 select DRIVERS_GENESYSLOGIC_GL9755 + select SOC_INTEL_CSE_LITE_SKU_2_0 config BOARD_GOOGLE_VOXEL bool "-> Voxel" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU select USE_CAR_NEM_ENHANCED_V2 + select SOC_INTEL_CSE_LITE_SKU_2_0 config BOARD_GOOGLE_BOLDAR bool "-> Boldar" @@ -71,3 +76,5 @@ config BOARD_GOOGLE_ELEMI bool "-> Elemi" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_CSE_LITE_SKU + select SOC_INTEL_CSE_LITE_SKU_2_0 -- To view, visit https://review.coreboot.org/c/coreboot/+/46846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida67bfd022f4ef1031adbbb8361c8b84d20b92c8 Gerrit-Change-Number: 46846 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/octopus/variants/bobba: Add G2Touch touchscreen support
by Sheng-Liang Pan (Code Review) 17 Nov '20

17 Nov '20

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46808 ) Change subject: mb/google/octopus/variants/bobba: Add G2Touch touchscreen support ...................................................................... mb/google/octopus/variants/bobba: Add G2Touch touchscreen support Add G2Touch touchscreen support for bobba. BUG=b:171636614 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage, and check touchscreen work. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: Ia361a56c050d7cbd7325b3c09fc34d8707441cc4 --- M src/mainboard/google/octopus/variants/bobba/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46808/1 diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index 20c376a..c3a63c7 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -210,6 +210,20 @@ register "has_power_resource" = "1" device i2c 39 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7502"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPIO_212_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_105)" + register "generic.reset_delay_ms" = "70" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_146)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end end # - I2C 7 end -- To view, visit https://review.coreboot.org/c/coreboot/+/46808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia361a56c050d7cbd7325b3c09fc34d8707441cc4 Gerrit-Change-Number: 46808 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/tiogapass: use ACPI to control GPIO [WIP]
by Maxim Polyakov (Code Review) 16 Nov '20

16 Nov '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39987 ) Change subject: mb/ocp/tiogapass: use ACPI to control GPIO [WIP] ...................................................................... mb/ocp/tiogapass: use ACPI to control GPIO [WIP] Change-Id: I0d4526c423b2192f51e515d993a05c03a3eaf58b Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/ocp/tiogapass/dsdt.asl 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/39987/1 diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index 9d33865..59ee7f8 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -35,5 +35,7 @@ // Xeon-SP ACPI tables Scope (\_SB) { #include <soc/intel/xeon_sp/skx/acpi/uncore.asl> + #include <soc/intel/common/acpi/pcr.asl> + #include <soc/intel/xeon_sp/acpi/gpio.asl> } } -- To view, visit https://review.coreboot.org/c/coreboot/+/39987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d4526c423b2192f51e515d993a05c03a3eaf58b Gerrit-Change-Number: 39987 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] mb/ocp/deltalake: use ACPI to control GPIO
by Maxim Polyakov (Code Review) 16 Nov '20

16 Nov '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45768 ) Change subject: [WIP] mb/ocp/deltalake: use ACPI to control GPIO ...................................................................... [WIP] mb/ocp/deltalake: use ACPI to control GPIO Change-Id: Ie5ec6bbc01092b743dea62aaf9dfc6dc3b3c0059 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/ocp/deltalake/dsdt.asl 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/45768/1 diff --git a/src/mainboard/ocp/deltalake/dsdt.asl b/src/mainboard/ocp/deltalake/dsdt.asl index c74b5fe..dd1fed2 100644 --- a/src/mainboard/ocp/deltalake/dsdt.asl +++ b/src/mainboard/ocp/deltalake/dsdt.asl @@ -20,4 +20,12 @@ // CPX-SP ACPI tables #include <soc/intel/xeon_sp/cpx/acpi/uncore.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/common/acpi/pcr.asl> + #include <soc/intel/xeon_sp/acpi/gpio.asl> + } + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/45768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5ec6bbc01092b743dea62aaf9dfc6dc3b3c0059 Gerrit-Change-Number: 45768 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: [WIP] mb/intel/cedarisland: use ACPI to control GPIO
by Maxim Polyakov (Code Review) 16 Nov '20

16 Nov '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45897 ) Change subject: [WIP] mb/intel/cedarisland: use ACPI to control GPIO ...................................................................... [WIP] mb/intel/cedarisland: use ACPI to control GPIO Change-Id: Ic3d6c3d5e64a640875aaff6a3b58b778080167bf Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/intel/cedarisland_crb/dsdt.asl 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/45897/1 diff --git a/src/mainboard/intel/cedarisland_crb/dsdt.asl b/src/mainboard/intel/cedarisland_crb/dsdt.asl index 407ee37..61e40ab 100644 --- a/src/mainboard/intel/cedarisland_crb/dsdt.asl +++ b/src/mainboard/intel/cedarisland_crb/dsdt.asl @@ -23,7 +23,8 @@ { #include <soc/intel/xeon_sp/cpx/acpi/southcluster.asl> #include <soc/intel/common/block/acpi/acpi/lpc.asl> - + #include <soc/intel/common/acpi/pcr.asl> + #include <soc/intel/xeon_sp/acpi/gpio.asl> } Device (UNC0) -- To view, visit https://review.coreboot.org/c/coreboot/+/45897 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3d6c3d5e64a640875aaff6a3b58b778080167bf Gerrit-Change-Number: 45897 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: device/pci: Add NULL check for PCI driver's .ops
by Nico Huber (Code Review) 16 Nov '20

16 Nov '20

Hello Felix Singer, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46297 to review the following change. Change subject: device/pci: Add NULL check for PCI driver's .ops ...................................................................... device/pci: Add NULL check for PCI driver's .ops Add a NULL check and only skip setting the default operations if `.ops` was set by a driver. Change-Id: I5dcc05ebb092fb9c4be929c81ea2b05a10b1311b Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/device/pci_device.c 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/46297/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 80dad7e..62c4535 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -955,13 +955,16 @@ if ((driver->vendor == dev->vendor) && device_id_match(driver, dev->device)) { dev->ops = (struct device_operations *)driver->ops; - printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n", - dev_path(dev), driver->vendor, driver->device, - (driver->ops->scan_bus ? "bus " : "")); - return; + break; } } + if (dev->ops) { + printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n", dev_path(dev), + driver->vendor, driver->device, (driver->ops->scan_bus ? "bus " : "")); + return; + } + /* If I don't have a specific driver use the default operations. */ switch (dev->hdr_type & 0x7f) { /* Header type */ case PCI_HEADER_TYPE_NORMAL: -- To view, visit https://review.coreboot.org/c/coreboot/+/46297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5dcc05ebb092fb9c4be929c81ea2b05a10b1311b Gerrit-Change-Number: 46297 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: Makefile.inc: Move adding SeaBIOS cbfs config files
by Arthur Heymans (Code Review) 16 Nov '20

16 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46415 ) Change subject: Makefile.inc: Move adding SeaBIOS cbfs config files ...................................................................... Makefile.inc: Move adding SeaBIOS cbfs config files Using the INTERMEDIATE target this can be done in the proper dir. Change-Id: Ie105231655ef4b49234f0944f638545fe79f07cb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M payloads/external/Makefile.inc 2 files changed, 25 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/46415/1 diff --git a/Makefile.inc b/Makefile.inc index 882673b..21c77f5 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1116,22 +1116,6 @@ # file (filled with \377 = 0xff) and copy the CBFS image over it. dd if=/dev/zero bs=$(call _toint,$(CONFIG_ROM_SIZE)) count=1 2> /dev/null | tr '\000' '\377' > $@.tmp dd if=$(obj)/coreboot.pre of=$@.tmp bs=8192 conv=notrunc 2> /dev/null -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) -ifneq ($(CONFIG_UPDATE_IMAGE),y) - @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" - $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup -endif -endif -endif -ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) - @printf " SeaBIOS Add sercon-port file\n" - $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port -endif -ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) - @printf " SeaBIOS Thread optionroms\n" - $(CBFSTOOL) $@.tmp add-int -i 2 -n etc/threads -endif ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index da199e4..6208578 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -106,6 +106,31 @@ bootorder-type := raw endif +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) +ifneq ($(CONFIG_UPDATE_IMAGE),y) +INTERMEDIATE+=seabios_ps2_timeout +seabios_ps2_timeout: $(obj)/coreboot.pre $(CBFSTOOL) + @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" + $(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup +endif +endif +endif + +ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) +INTERMEDIATE+=seabios_sercon +seabios_sercon: $(obj)/coreboot.pre $(CBFSTOOL) + @printf " SeaBIOS Add sercon-port file\n" +# $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port +endif + +ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) +INTERMEDIATE+=seabios_thread_optionroms +seabios_thread_optionroms: $(obj)/coreboot.pre $(CBFSTOOL) + @printf " SeaBIOS Thread optionroms\n" + $(CBFSTOOL) $@.tmp add-int -i 2 -n etc/threads +endif + # Depthcharge payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) -- To view, visit https://review.coreboot.org/c/coreboot/+/46415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie105231655ef4b49234f0944f638545fe79f07cb Gerrit-Change-Number: 46415 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/systemagent.c: Rename to `hostbridge.c`
by Angel Pons (Code Review) 16 Nov '20

16 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46797 ) Change subject: soc/intel/broadwell/systemagent.c: Rename to `hostbridge.c` ...................................................................... soc/intel/broadwell/systemagent.c: Rename to `hostbridge.c` Change-Id: Id1a0e02174456bb25df0721cfd3865645641a01a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Makefile.inc R src/soc/intel/broadwell/northbridge.c 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/46797/1 diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 7ee6990..7d21665 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -17,11 +17,11 @@ romstage-y += memmap.c postcar-y += memmap.c ramstage-y += minihd.c +ramstage-y += northbridge.c ramstage-y += pei_data.c romstage-y += pei_data.c ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c -ramstage-y += systemagent.c CPPFLAGS_common += -Isrc/soc/intel/broadwell/include diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/northbridge.c similarity index 100% rename from src/soc/intel/broadwell/systemagent.c rename to src/soc/intel/broadwell/northbridge.c -- To view, visit https://review.coreboot.org/c/coreboot/+/46797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1a0e02174456bb25df0721cfd3865645641a01a Gerrit-Change-Number: 46797 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020