coreboot-gerrit October 2020

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Change in coreboot[master]: [WIP] mb/google/volteer: Update flashmap descriptor to add CSE RW binary
by Jamie Ryu (Code Review) 18 Nov '20

18 Nov '20

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46431 ) Change subject: [WIP] mb/google/volteer: Update flashmap descriptor to add CSE RW binary ...................................................................... [WIP] mb/google/volteer: Update flashmap descriptor to add CSE RW binary BUG=b:166982406 TEST=build with cse rw binary and verify volteer boot time is close to 1 sec. Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: I87da3824933ed2dd8e8ed0fed8686d2a3527faea --- M src/mainboard/google/volteer/chromeos.fmd 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46431/1 diff --git a/src/mainboard/google/volteer/chromeos.fmd b/src/mainboard/google/volteer/chromeos.fmd old mode 100644 new mode 100755 index 07a5464..246561d --- a/src/mainboard/google/volteer/chromeos.fmd +++ b/src/mainboard/google/volteer/chromeos.fmd @@ -10,13 +10,15 @@ RW_LEGACY(CBFS)@0x0 0xb00000 RW_SECTION_A@0xb00000 0x5e0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x5cffc0 - RW_FWID_A@0x5dffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x34ffc0 + RW_FWID_A@0x35ffc0 0x40 + FW_MAIN_A_EXTN(CBFS)@0x360000 0x280000 } RW_SECTION_B@0x10e0000 0x5e0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x5cffc0 - RW_FWID_B@0x5dffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x34ffc0 + RW_FWID_B@0x35ffc0 0x40 + FW_MAIN_B_EXTN(CBFS)@0x360000 0x280000 } RW_MISC@0x16c0000 0x40000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { -- To view, visit https://review.coreboot.org/c/coreboot/+/46431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87da3824933ed2dd8e8ed0fed8686d2a3527faea Gerrit-Change-Number: 46431 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: soc/intel/common: Boot time optimization
by Sridhar Siricilla (Code Review) 18 Nov '20

18 Nov '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46312 ) Change subject: soc/intel/common: Boot time optimization ...................................................................... soc/intel/common: Boot time optimization Th CSE RW blob which will be used by coreboot to update CSE RW partition, is packed part of FW_MAIN_A and FW_MAIN_B. This increase the size of FW_MAIN_A and FW_MAIN_B. So, accordingly loads and hash calculation of FW_MAIN_A (or FW_MAIN_B) increases during verstage. The boot time impact is around 300ms. The patch addresses boot time by pulling CSE RW blob outside of FW_MAIN_A/B. So, it creates new FMAP region within RW_SECTION_A and RW_SECTION_B and adds CSE RW blob in the new regions as a CBFS file. Changes: 1. Makefile changes to accommodate CSE RW blob part of FW_MAIN_A_EXTN/ FW_MAIN_B_EXTN and add RW blob metadata file part of FW_MAIN_A/B. 2. Kconfig change to define CBFS name and default file name for RW blob metadata. 3. CSE Lite driver BUG=b:169077783 TEST=verified on hatch. Yet to verify on JSL/TGL platforms. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: If043c9cb99fb822b62633591bf9c5bd75dfe8349 --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/cse_lite.c 3 files changed, 227 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/46312/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 1cb7d35..0172fc2 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -37,3 +37,15 @@ default "" help Intel CSE CBFS RW blob path and file name + +config SOC_INTEL_CSE_RW_METADATA_CBFS_NAME + string "CBFS entry name for CSE RW blob" + default "me_rw_metadata" + help + CBFS entry name for Intel CSE CBFS RW blob + +config SOC_INTEL_CSE_RW_METADATA_FILE + string "Intel CSE CBFS RW path and filename" + default "" + help + Intel CSE CBFS RW blob path and file name diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 11cc3c2..9543156 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -4,11 +4,21 @@ ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c + ifneq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"") -CSE_LITE_ME_RW = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME)) -regions-for-file-$(CSE_LITE_ME_RW) = FW_MAIN_A,FW_MAIN_B -cbfs-files-y += $(CSE_LITE_ME_RW) -$(CSE_LITE_ME_RW)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) -$(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW) -$(CSE_LITE_ME_RW)-type := raw +CSE_LITE_RW = $(call strip_quotes, $(CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME)) +regions-for-file-$(CSE_LITE_RW) = FW_MAIN_A_EXTN,FW_MAIN_B_EXTN +cbfs-files-y += $(CSE_LITE_RW) +$(CSE_LITE_RW)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) +$(CSE_LITE_RW)-name := $(CSE_LITE_RW) +$(CSE_LITE_RW)-type := raw +endif + +ifneq ($(CONFIG_SOC_INTEL_CSE_RW_METADATA_FILE),"") +CSE_LITE_RW_METADATA = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_METADATA_CBFS_NAME)) +regions-for-file-$(CSE_LITE_RW_METADATA) = FW_MAIN_A,FW_MAIN_B +cbfs-files-y += $(CSE_LITE_RW_METADATA) +$(CSE_LITE_RW_METADATA)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_METADATA_FILE)) +$(CSE_LITE_RW_METADATA)-name := $(CSE_LITE_RW_METADATA) +$(CSE_LITE_RW_METADATA)-type := raw endif diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index c9e4e1f..5b50828 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -12,6 +12,11 @@ #include <vb2_api.h> #include <soc/intel/common/reset.h> + +#define FMAP_FW_MAIN_A_EXTN_NAME "FW_MAIN_A_EXTN" + +#define FMAP_FW_MAIN_B_EXTN_NAME "FW_MAIN_B_EXTN" + /* CSE RW version size reserved in the CSE CBFS RW binary */ #define CSE_RW_VERSION_SZ 16 @@ -64,7 +69,13 @@ CSE_LITE_SKU_COMMUNICATION_ERROR = 6, /* Fails to wipe CSE runtime data */ - CSE_LITE_SKU_DATA_WIPE_ERROR = 7 + CSE_LITE_SKU_DATA_WIPE_ERROR = 7, + + /* CSE RW is not found */ + CSE_LITE_SKU_RW_BLOB_NOT_FOUND = 8, + + /* CSE CBFS RW SHA-256 mismatch with the provided SHA */ + CSE_LITE_SKU_RW_BLOB_SHA256_MISMATCH = 9 }; /* @@ -157,6 +168,43 @@ struct cse_bp_info bp_info; } __packed; +/* CSE CBFS RW metadata */ +struct cse_cbfs_rw_info { + + /* This struct version */ + uint8_t version; + + /* CSE CBFS RW version */ + struct fw_version fw_ver; + + /* Ifwi build version */ + uint8_t ifwi_build_version; + + /* Indicate CSE CBFS RW is compressed or not */ + uint8_t compressed; + + /* SHA-256 of CSE CBFS RW */ + uint8_t hash[VB2_SHA256_DIGEST_SIZE]; + + uint8_t reserved[5]; +}; + +/* CSE Boot Partition Descriptor Table Header */ +struct cse_bpdt { + + /* Signature:0x000055AA is expected for a valid BP */ + uint32_t signature; + + /* reserved field */ + uint8_t reserved[8]; + + /* ifwi build version */ + uint32_t ifwi_build_ver; + + /* FIT tool version */ + struct fw_version fit_tool_ver; +}; + static void cse_log_status_registers(void) { printk(BIOS_DEBUG, "cse_lite: CSE status registers: HFSTS1: 0x%x, HFSTS2: 0x%x " @@ -419,11 +467,38 @@ return true; } +static bool cse_get_cbfs_rw(struct region_device *rdev) +{ + const char *fmap_fw_main_extn; + uint32_t cbfs_type = CBFS_TYPE_RAW; + static struct cbfsf fh; + struct vb2_context *ctx = vboot_get_context(); + if (ctx == NULL) + return false; + + if (vboot_is_firmware_slot_a(ctx)) + fmap_fw_main_extn = FMAP_FW_MAIN_A_EXTN_NAME; + else + fmap_fw_main_extn = FMAP_FW_MAIN_B_EXTN_NAME; + + if (cbfs_locate_file_in_region(&fh, fmap_fw_main_extn, + CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME, &cbfs_type)) { + printk(BIOS_ERR, "cse_lite: Failed to locate %s in the %s", + CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME, fmap_fw_main_extn); + + return false; + } + + cbfs_file_data(rdev, &fh); + + return true; +} + static bool cse_get_cbfs_rdev(struct region_device *source_rdev) { struct cbfsf file_desc; - if (cbfs_boot_locate(&file_desc, CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME, NULL) < 0) + if (cbfs_boot_locate(&file_desc, CONFIG_SOC_INTEL_CSE_RW_METADATA_CBFS_NAME, NULL) < 0) return false; cbfs_file_data(source_rdev, &file_desc); @@ -503,15 +578,32 @@ return true; } -static bool cse_get_cbfs_rw_version(const struct region_device *source_rdev, - void *cse_cbfs_rw_ver) +static bool cse_get_cbfs_rw_metadata(const struct region_device *source_info_rdev, + struct cse_cbfs_rw_info *source_info) { - if (rdev_readat(source_rdev, (void *) cse_cbfs_rw_ver, 0, sizeof(struct fw_version)) - != sizeof(struct fw_version)) { - printk(BIOS_ERR, "cse_lite: Failed to read CSE CBFW RW version\n"); + if (rdev_readat(source_info_rdev, (void *) source_info, 0, + sizeof(struct cse_cbfs_rw_info)) != sizeof(struct cse_cbfs_rw_info)) { + printk(BIOS_ERR, "cse_lite: Failed to read CSE CBFW RW blob metadata\n"); return false; } + + printk(BIOS_SPEW, "cse_lite: version: %d\n", source_info->version); + printk(BIOS_SPEW, "cse_lite: CSE CBFS RW version : %d.%d.%d.%d\n", + source_info->fw_ver.major, + source_info->fw_ver.minor, + source_info->fw_ver.hotfix, + source_info->fw_ver.build); + printk(BIOS_SPEW, "cse_lite: IFWI build version: 0x%x\n", + source_info->ifwi_build_version); + printk(BIOS_SPEW, "cse_lite: compressed blob: 0x%x\n", + source_info->compressed); + printk(BIOS_SPEW, "cse_lite: RW blob hash: "); + + for (uint8_t i = 0; i < 32; i++) + printk(BIOS_SPEW, "%x", source_info->hash[i]); + + printk(BIOS_SPEW, "\n"); return true; } @@ -522,30 +614,27 @@ * If ver_cmp_status > 0, coreboot upgrades CSE RW region */ static int cse_check_version_mismatch(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_cbfs_rw_info *source_info) { - struct fw_version cse_cbfs_rw_ver; const struct fw_version *cse_rw_ver; - if (!cse_get_cbfs_rw_version(source_rdev, &cse_cbfs_rw_ver)) - return false; printk(BIOS_DEBUG, "cse_lite: CSE CBFS RW version : %d.%d.%d.%d\n", - cse_cbfs_rw_ver.major, - cse_cbfs_rw_ver.minor, - cse_cbfs_rw_ver.hotfix, - cse_cbfs_rw_ver.build); + source_info->fw_ver.major, + source_info->fw_ver.minor, + source_info->fw_ver.hotfix, + source_info->fw_ver.build); cse_rw_ver = cse_get_rw_version(cse_bp_info); - if (cse_cbfs_rw_ver.major != cse_rw_ver->major) - return cse_cbfs_rw_ver.major - cse_rw_ver->major; - else if (cse_cbfs_rw_ver.minor != cse_rw_ver->minor) - return cse_cbfs_rw_ver.minor - cse_rw_ver->minor; - else if (cse_cbfs_rw_ver.hotfix != cse_rw_ver->hotfix) - return cse_cbfs_rw_ver.hotfix - cse_rw_ver->hotfix; + if (source_info->fw_ver.major != cse_rw_ver->major) + return source_info->fw_ver.major - cse_rw_ver->major; + else if (source_info->fw_ver.minor != cse_rw_ver->minor) + return source_info->fw_ver.minor - cse_rw_ver->minor; + else if (source_info->fw_ver.hotfix != cse_rw_ver->hotfix) + return source_info->fw_ver.hotfix - cse_rw_ver->hotfix; else - return cse_cbfs_rw_ver.build - cse_rw_ver->build; + return source_info->fw_ver.build - cse_rw_ver->build; } /* Check if CSE RW data partition is valid or not */ @@ -557,6 +646,21 @@ return rw_bp->status != BP_STATUS_DATA_FAILURE; } +static int cse_is_ifwi_build_version_latest(const struct cse_cbfs_rw_info *source_info, + const struct region_device *target_dev) +{ + uint32_t ifwi_build_ver; + uint8_t ifwi_build_ver_offset = offsetof(struct cse_bpdt, ifwi_build_ver); + + if (rdev_readat(target_dev, &ifwi_build_ver, ifwi_build_ver_offset, + sizeof(ifwi_build_ver)) != sizeof(ifwi_build_ver)) { + printk(BIOS_ERR, "cse_lite: Failed to read OEM Version CSE RW partition\n"); + return false; + } + + return (ifwi_build_ver == source_info->ifwi_build_version); +} + /* * It returns true if RW partition doesn't indicate BP_STATUS_DATA_FAILURE * otherwise false if any operation fails. @@ -587,8 +691,8 @@ return true; } -static bool cse_copy_rw(const struct region_device *target_rdev, const void *buf, size_t offset, - size_t size) +static bool cse_copy_rw(const struct region_device *target_rdev, const void *buf, + size_t offset, size_t size) { if (rdev_writeat(target_rdev, buf, offset, size) < 0) { printk(BIOS_ERR, "cse_lite: Failed to update CSE firmware\n"); @@ -599,36 +703,33 @@ } static bool cse_is_rw_version_latest(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_cbfs_rw_info *source_info) { - return !cse_check_version_mismatch(cse_bp_info, source_rdev); + return !cse_check_version_mismatch(cse_bp_info, source_info); } static bool cse_is_downgrade_instance(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_cbfs_rw_info *source_info) { - return cse_check_version_mismatch(cse_bp_info, source_rdev) < 0; + return cse_check_version_mismatch(cse_bp_info, source_info) < 0; } static bool cse_is_update_required(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev, struct region_device *target_rdev) + const struct cse_cbfs_rw_info *source_info, struct region_device *target_rdev) { return (!cse_is_rw_bp_sign_valid(target_rdev) || - !cse_is_rw_version_latest(cse_bp_info, source_rdev)); + !cse_is_rw_version_latest(cse_bp_info, source_info) || + !cse_is_ifwi_build_version_latest(source_info, target_rdev)); } static bool cse_write_rw_region(const struct region_device *target_rdev, - const struct region_device *source_rdev) + const void *cse_cbfs_rw, const size_t cse_cbfs_rw_sz) { - void *cse_cbfs_rw = rdev_mmap(source_rdev, CSE_RW_VERSION_SZ, - region_device_sz(source_rdev) - CSE_RW_VERSION_SZ); - /* Points to CSE CBFS RW image after boot partition signature */ uint8_t *cse_cbfs_rw_wo_sign = (uint8_t *)cse_cbfs_rw + CSE_RW_SIGN_SIZE; /* Size of CSE CBFS RW image without boot partition signature */ - uint32_t cse_cbfs_rw_wo_sign_sz = region_device_sz(source_rdev) - - (CSE_RW_VERSION_SZ + CSE_RW_SIGN_SIZE); + uint32_t cse_cbfs_rw_wo_sign_sz = cse_cbfs_rw_sz - CSE_RW_SIGN_SIZE; /* Update except CSE RW signature */ if (!cse_copy_rw(target_rdev, cse_cbfs_rw_wo_sign, CSE_RW_SIGN_SIZE, @@ -639,21 +740,19 @@ if (!cse_copy_rw(target_rdev, (void *)cse_cbfs_rw, 0, CSE_RW_SIGN_SIZE)) goto exit_rw_update; - rdev_munmap(source_rdev, cse_cbfs_rw_wo_sign); return true; exit_rw_update: - rdev_munmap(source_rdev, cse_cbfs_rw_wo_sign); return false; } -static bool cse_update_rw(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev, struct region_device *target_rdev) +static bool cse_update_rw(const struct cse_bp_info *cse_bp_info, const void *cse_cbfs_rw, + const size_t cse_blob_sz, struct region_device *target_rdev) { if (!cse_erase_rw_region(target_rdev)) return false; - if (!cse_write_rw_region(target_rdev, source_rdev)) + if (!cse_write_rw_region(target_rdev, cse_cbfs_rw, cse_blob_sz)) return false; printk(BIOS_INFO, "cse_lite: CSE RW Update Successful\n"); @@ -661,7 +760,7 @@ } static bool cse_prep_for_rw_update(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct cse_cbfs_rw_info *source_info) { /* * To set CSE's operation mode to HMRFPO mode: @@ -671,7 +770,7 @@ if (!cse_boot_to_ro(cse_bp_info)) return false; - if (cse_is_downgrade_instance(cse_bp_info, source_rdev) && + if (cse_is_downgrade_instance(cse_bp_info, source_info) && !cse_data_clear_request(cse_bp_info)) { printk(BIOS_ERR, "cse_lite: CSE FW downgrade is aborted\n"); return false; @@ -680,20 +779,54 @@ return cse_hmrfpo_enable(); } -static uint8_t cse_trigger_fw_update(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev, struct region_device *target_rdev) +/* The function calculates SHA-256 of CSE RW blob and compares it with the provided SHA value */ +static uint8_t cse_verify_rw_blob_sha256(const uint8_t *expected_rw_blob_sha, + const void *rw_blob, const size_t rw_blob_sz) + { - if (!cse_prep_for_rw_update(cse_bp_info, source_rdev)) + uint8_t rw_comp_sha[VB2_SHA256_DIGEST_SIZE]; + + if (!vb2_digest_buffer(rw_blob, rw_blob_sz, VB2_HASH_SHA256, rw_comp_sha, + VB2_SHA256_DIGEST_SIZE)) { + printk(BIOS_ERR, "cse_lite: CSE RW blob SHA-256 calculation has failed\n"); + return false; + } + + if (!memcmp(expected_rw_blob_sha, rw_comp_sha, VB2_SHA256_DIGEST_SIZE)) { + printk(BIOS_ERR, "cse_lite: Computed SHA is not matching with the given SHA\n"); + return false; + } + + return true; +} + +static uint8_t cse_trigger_fw_update(const struct cse_bp_info *cse_bp_info, + const struct cse_cbfs_rw_info *source_info, struct region_device *target_rdev) +{ + + struct region_device source_rdev; + + if (!cse_get_cbfs_rw(&source_rdev)) + return CSE_LITE_SKU_RW_BLOB_NOT_FOUND; + + void *cse_cbfs_rw = rdev_mmap(&source_rdev, 0, region_device_sz(&source_rdev)); + + if (cse_verify_rw_blob_sha256(source_info->hash, cse_cbfs_rw, + region_device_sz(&source_rdev))) + return CSE_LITE_SKU_RW_BLOB_SHA256_MISMATCH; + + if (!cse_prep_for_rw_update(cse_bp_info, source_info)) return CSE_LITE_SKU_COMMUNICATION_ERROR; - if (!cse_update_rw(cse_bp_info, source_rdev, target_rdev)) + if (!cse_update_rw(cse_bp_info, cse_cbfs_rw, region_device_sz(&source_rdev), + target_rdev)) return CSE_LITE_SKU_FW_UPDATE_ERROR; return 0; } static uint8_t cse_fw_update(const struct cse_bp_info *cse_bp_info, - const struct region_device *source_rdev) + const struct region_device *source_info_rdev) { struct region_device target_rdev; @@ -702,9 +835,17 @@ return CSE_LITE_SKU_RW_ACCESS_ERROR; } - if (cse_is_update_required(cse_bp_info, source_rdev, &target_rdev)) { + struct cse_cbfs_rw_info source_info; + + /* Read CSE RW blob metadata */ + if (!cse_get_cbfs_rw_metadata(source_info_rdev, &source_info)) { + printk(BIOS_ERR, "cse_lite: Failed to get CSE RW blob metadata\n"); + return CSE_LITE_SKU_UNSPECIFIED; + } + + if (cse_is_update_required(cse_bp_info, &source_info, &target_rdev)) { printk(BIOS_DEBUG, "cse_lite: CSE RW update is initiated\n"); - return cse_trigger_fw_update(cse_bp_info, source_rdev, &target_rdev); + return cse_trigger_fw_update(cse_bp_info, &source_info, &target_rdev); } if (!cse_is_rw_bp_status_valid(cse_bp_info)) @@ -736,11 +877,15 @@ if (!cse_fix_data_failure_err(&cse_bp_info.bp_info)) cse_trigger_recovery(CSE_LITE_SKU_DATA_WIPE_ERROR); - /* If RW blob is present in CBFS, then trigger CSE firmware update */ + /* + * If RW blob metadata is present in CBFS, then trigger CSE firmware update. + * The driver triggers if RW blob metadata is present in the CBFS and RW blob is not + * available. + */ uint8_t rv; - struct region_device source_rdev; - if (cse_get_cbfs_rdev(&source_rdev)) { - rv = cse_fw_update(&cse_bp_info.bp_info, &source_rdev); + struct region_device source_info_rdev; + if (cse_get_cbfs_rdev(&source_info_rdev)) { + rv = cse_fw_update(&cse_bp_info.bp_info, &source_info_rdev); if (rv) cse_trigger_recovery(rv); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If043c9cb99fb822b62633591bf9c5bd75dfe8349 Gerrit-Change-Number: 46312 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

8 36

Change in coreboot[master]: mainboard/volteer: enable early tcss chrome ec related code in mainboard
by Brandon Breitenstein (Code Review) 17 Nov '20

17 Nov '20

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45742 ) Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ...................................................................... mainboard/volteer: enable early tcss chrome ec related code in mainboard Since mainboard is the determining factor if a board uses chrome ec or not moving the early tcss code that relies on chrome ec from soc code to mainboard. BUG=b:151731851 BRANCH=none TEST=Built and verified that external display is coming up during recovery Change-Id: I08c151caa84c1970c77386d9eca156fd3c7f2a12 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 2 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/45742/1 diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 23c3e92..80a04d0 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -5,9 +5,11 @@ #include <baseboard/variants.h> #include <device/device.h> #include <drivers/spi/tpm/tpm.h> +#include <ec/google/chromeec/ec.h> #include <ec/ec.h> #include <fw_config.h> #include <security/tpm/tss.h> +#include <soc/early_tcss.h> #include <soc/gpio.h> #include <soc/ramstage.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -65,6 +67,78 @@ } } +void mainboard_early_tcss_enable(void) +{ + uint8_t dp_mode; + unsigned int num_ports; + int ret, i; + bool ufp, acc; + + ret = google_chromeec_get_num_pd_ports(&num_ports); + if (ret < 0) { + printk(BIOS_ERR, "get_num_pd_ports failed unable to continue\n"); + return; + } + + for (i = 0; i < num_ports; i++) { + uint8_t port_map, mux_flags; + struct tcss_mux mux_data; + + ret = google_chromeec_usb_get_pd_mux_info(i, &mux_flags); + if (ret < 0) { + printk(BIOS_ERR, "port C%d: get_pd_mux_info failed\n", i); + continue; + } + + ret = google_chromeec_pd_get_port_info(i, &port_map); + if (ret < 0) { + printk(BIOS_ERR, "port C%d: get_port_info failed\n", i); + continue; + } + + mux_data.usb2_port = port_map & USB_2_PORT_MASK; + mux_data.usb3_port = (port_map & USB_3_PORT_MASK) >> 4; + + //Add check for connected maybe? + + ret = google_chromeec_usb_pd_control(i, &ufp, &acc, &dp_mode); + if (ret < 0) { + printk(BIOS_ERR, "port C%d: pd_control failed\n", i); + continue; + } + + mux_data.usb = !!(mux_flags & USB_PD_MUX_USB_ENABLED); + mux_data.dp = !!(mux_flags & USB_PD_MUX_DP_ENABLED); + mux_data.cable = !!(mux_flags & USB_PD_CTRL_ACTIVE_CABLE); + mux_data.polarity = !!(mux_flags & USB_PD_MUX_POLARITY_INVERTED); + mux_data.hpd_irq = !!(mux_flags & USB_PD_MUX_HPD_IRQ); + mux_data.hpd_lvl = !!(mux_flags & USB_PD_MUX_HPD_LVL); + mux_data.ufp = !!ufp; + mux_data.acc = !!acc; + mux_data.dp_mode = dp_mode; + + printk(BIOS_DEBUG, "Port %d mux=0x%x\n" + "USB2 port = %x\n" + "USB3 port = %x\n" + "DP Mode = %x\n" + "dp = %d\n" + "usb = %d\n" + "cable = %d\n" + "polarity = %d\n" + "hpd_lvl = %d\n" + "hpd_irq = %d\n" + "ufp = %d\n" + "dbg_acc = %d\n", + i, (unsigned int)mux_flags, mux_data.usb2_port, + mux_data.usb3_port, mux_data.dp_mode, mux_data.dp, + mux_data.usb, mux_data.cable, mux_data.polarity, + mux_data.hpd_lvl, mux_data.hpd_irq, mux_data.ufp, + mux_data.acc); + + update_tcss_mux(i, mux_data); + } +} + static void mainboard_chip_init(void *chip_info) { const struct pad_config *base_pads; diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 43ba255..179aeb0 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -59,6 +59,8 @@ register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "0" + register "RMT" = "1" + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN -- To view, visit https://review.coreboot.org/c/coreboot/+/45742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08c151caa84c1970c77386d9eca156fd3c7f2a12 Gerrit-Change-Number: 45742 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: newchange

4 28

Change in coreboot[master]: src: Add missing 'include <console/console.h>'
by HAOUAS Elyes (Code Review) 17 Nov '20

17 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45540 ) Change subject: src: Add missing 'include <console/console.h>' ...................................................................... src: Add missing 'include <console/console.h>' "Die()" needs <console/console.h>. Change-Id: I250988d77b0b0a093a1d116bea44a0cbb84189dd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/poppy/variants/nami/memory.c M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c M src/soc/qualcomm/sc7180/qupv3_config.c M src/soc/qualcomm/sc7180/qupv3_i2c.c 4 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/45540/1 diff --git a/src/mainboard/google/poppy/variants/nami/memory.c b/src/mainboard/google/poppy/variants/nami/memory.c index 3e482a9..6faca2b 100644 --- a/src/mainboard/google/poppy/variants/nami/memory.c +++ b/src/mainboard/google/poppy/variants/nami/memory.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <console/console.h> #include <gpio.h> #include <variant/gpio.h> #include <string.h> diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c index 46499f4..bea9cd8 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/memory.c @@ -2,6 +2,7 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> +#include <console/console.h> #include <gpio.h> #include <soc/meminit.h> #include <soc/romstage.h> diff --git a/src/soc/qualcomm/sc7180/qupv3_config.c b/src/soc/qualcomm/sc7180/qupv3_config.c index 3dbe3e6..9614b4e 100644 --- a/src/soc/qualcomm/sc7180/qupv3_config.c +++ b/src/soc/qualcomm/sc7180/qupv3_config.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cbfs.h> +#include <console/console.h> #include <string.h> #include <soc/qupv3_config.h> diff --git a/src/soc/qualcomm/sc7180/qupv3_i2c.c b/src/soc/qualcomm/sc7180/qupv3_i2c.c index b80c3df..c9adba4 100644 --- a/src/soc/qualcomm/sc7180/qupv3_i2c.c +++ b/src/soc/qualcomm/sc7180/qupv3_i2c.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> +#include <console/console.h> #include <device/i2c_simple.h> #include <gpio.h> #include <inttypes.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I250988d77b0b0a093a1d116bea44a0cbb84189dd Gerrit-Change-Number: 45540 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: src: Add missing 'include <console/console.h>'
by HAOUAS Elyes (Code Review) 17 Nov '20

17 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45539 ) Change subject: src: Add missing 'include <console/console.h>' ...................................................................... src: Add missing 'include <console/console.h>' "printk()" needs <console/console.h>. Change-Id: Iac6b7000bcd8b1335fa3a0ba462a63aed2dc85b8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/aspeed/common/ast_mode_corebootfb.c M src/drivers/aspeed/common/ast_post.c M src/lib/asan.c M src/mainboard/emulation/qemu-q35/chromeos.c M src/mainboard/google/hatch/romstage_spd_smbus.c M src/mainboard/google/hatch/variants/baseboard/mainboard.c M src/mainboard/google/hatch/variants/jinlon/mainboard.c M src/mainboard/google/trogdor/mainboard.c M src/mainboard/google/volteer/romstage.c M src/security/vboot/vboot_logic.c M src/soc/amd/picasso/reset.c M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/skx/acpi.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7180/qcom_qup_se.c M src/soc/qualcomm/sc7180/qupv3_spi.c M src/southbridge/intel/ibexpeak/early_pch.c 19 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/45539/1 diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index b5f794b..bf974ff 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -2,6 +2,8 @@ /* * Copied from Linux drivers/gpu/drm/ast/ast_mode.c */ + +#include <console/console.h> #include <edid.h> #include <device/pci_def.h> diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c index c909182..68ecca8 100644 --- a/src/drivers/aspeed/common/ast_post.c +++ b/src/drivers/aspeed/common/ast_post.c @@ -2,6 +2,7 @@ #define COREBOOT_AST_FAILOVER_TIMEOUT 10000000 +#include <console/console.h> #include <delay.h> #include "ast_drv.h" diff --git a/src/lib/asan.c b/src/lib/asan.c index 6de0de1..cf91111 100644 --- a/src/lib/asan.c +++ b/src/lib/asan.c @@ -8,6 +8,7 @@ * */ +#include <console/console.h> #include <symbols.h> #include <assert.h> #include <arch/symbols.h> diff --git a/src/mainboard/emulation/qemu-q35/chromeos.c b/src/mainboard/emulation/qemu-q35/chromeos.c index fcf50a9..1af2e02 100644 --- a/src/mainboard/emulation/qemu-q35/chromeos.c +++ b/src/mainboard/emulation/qemu-q35/chromeos.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <boot/coreboot_tables.h> +#include <console/console.h> #include <vendorcode/google/chromeos/chromeos.h> #include "../qemu-i440fx/fw_cfg.h" diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c index d21e867..e697379 100644 --- a/src/mainboard/google/hatch/romstage_spd_smbus.c +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> +#include <console/console.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> #include <spd_bin.h> diff --git a/src/mainboard/google/hatch/variants/baseboard/mainboard.c b/src/mainboard/google/hatch/variants/baseboard/mainboard.c index 3b247e9..d641405 100644 --- a/src/mainboard/google/hatch/variants/baseboard/mainboard.c +++ b/src/mainboard/google/hatch/variants/baseboard/mainboard.c @@ -2,6 +2,7 @@ #include <baseboard/variants.h> #include <chip.h> +#include <console/console.h> #include <delay.h> #include <device/device.h> #include <device/pci_ids.h> diff --git a/src/mainboard/google/hatch/variants/jinlon/mainboard.c b/src/mainboard/google/hatch/variants/jinlon/mainboard.c index 564c18c..cf9344e 100644 --- a/src/mainboard/google/hatch/variants/jinlon/mainboard.c +++ b/src/mainboard/google/hatch/variants/jinlon/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <console/console.h> #include <ec/google/chromeec/ec.h> #include <device/device.h> #include <drivers/gfx/generic/chip.h> diff --git a/src/mainboard/google/trogdor/mainboard.c b/src/mainboard/google/trogdor/mainboard.c index 57f3a3b..54d8b0d 100644 --- a/src/mainboard/google/trogdor/mainboard.c +++ b/src/mainboard/google/trogdor/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootmode.h> +#include <console/console.h> #include <delay.h> #include <device/device.h> #include <device/i2c_simple.h> diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 8893785..375bb0c 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <console/console.h> #include <ec/google/chromeec/ec.h> #include <fsp/soc_binding.h> #include <fw_config.h> diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index c4c3b4b..43405bc 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -2,6 +2,7 @@ #include <arch/exception.h> #include <assert.h> +#include <console/console.h> #include <bootmode.h> #include <fmap.h> #include <security/tpm/tspi/crtm.h> diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index 902538ff..7a0074c 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/io.h> +#include <console/console.h> #include <reset.h> #include <soc/pci_devs.h> #include <soc/reset.h> diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 15874c0..f3e47e5 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -2,6 +2,7 @@ #include <assert.h> #include <commonlib/sort.h> +#include <console/console.h> #include <delay.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c index d984d9f..16f7856 100644 --- a/src/soc/intel/xeon_sp/skx/acpi.c +++ b/src/soc/intel/xeon_sp/skx/acpi.c @@ -7,6 +7,7 @@ #include <intelblocks/acpi.h> #include <device/pci.h> #include <cbmem.h> +#include <console/console.h> #include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/cpu.h> diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 845d7cb..0316e1e 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -2,6 +2,7 @@ #include <cbfs.h> #include <assert.h> +#include <console/console.h> #include <post.h> #include <device/pci.h> #include <soc/acpi.h> diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 62aa4d1..e9665c3 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -3,6 +3,7 @@ #ifndef _SOC_PCI_DEVS_H_ #define _SOC_PCI_DEVS_H_ +#include <console/console.h> #include <device/pci_def.h> #include <hob_iiouds.h> diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index 919735d..8763a9d 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -2,6 +2,7 @@ #include <assert.h> #include <commonlib/helpers.h> +#include <console/console.h> #include <delay.h> #include <device/mmio.h> #include <soc/clock.h> diff --git a/src/soc/qualcomm/sc7180/qcom_qup_se.c b/src/soc/qualcomm/sc7180/qcom_qup_se.c index cac590c..6750c3e 100644 --- a/src/soc/qualcomm/sc7180/qcom_qup_se.c +++ b/src/soc/qualcomm/sc7180/qcom_qup_se.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <soc/qcom_qup_se.h> struct qup qup[12] = { diff --git a/src/soc/qualcomm/sc7180/qupv3_spi.c b/src/soc/qualcomm/sc7180/qupv3_spi.c index d086a27..23914bb 100644 --- a/src/soc/qualcomm/sc7180/qupv3_spi.c +++ b/src/soc/qualcomm/sc7180/qupv3_spi.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> +#include <console/console.h> #include <lib.h> #include <soc/clock.h> #include <soc/gpio.h> diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index d9ac009..122c8e4 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <device/pci_ops.h> #include <device/smbus_host.h> #include <northbridge/intel/ironlake/ironlake.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac6b7000bcd8b1335fa3a0ba462a63aed2dc85b8 Gerrit-Change-Number: 45539 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: HACK: skip reading EDID completely
by yongqiang niu (Code Review) 17 Nov '20

17 Nov '20

Hello Nicolas Boichat, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46580 to review the following change. Change subject: HACK: skip reading EDID completely ...................................................................... HACK: skip reading EDID completely Something goes terribly wrong when reading the EDID, and ANX7625 does not seem to be able to recover from it. BUG=b:155713214 TEST=boot asurada Change-Id: I2230af30b709667f9858f6144b14681686003f28 --- M src/drivers/analogix/anx7625/anx7625.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/46580/1 diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index eb7e661..e3f969c 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -854,7 +854,9 @@ int ret; u8 edid[FOUR_BLOCK_SIZE]; - block_num = sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); + /* Something goes terribly wrong here, and ANX7625 does not seem to be able to recover from it. */ + if (0) + block_num = sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); block_num=1; memcpy(edid, &edp_edid, sizeof(edp_edid)); -- To view, visit https://review.coreboot.org/c/coreboot/+/46580 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2230af30b709667f9858f6144b14681686003f28 Gerrit-Change-Number: 46580 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: WIP: coreboot: Add eDP edid to skip get edid fail
by yongqiang niu (Code Review) 17 Nov '20

17 Nov '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46579 ) Change subject: WIP: coreboot: Add eDP edid to skip get edid fail ...................................................................... WIP: coreboot: Add eDP edid to skip get edid fail Add eDP edid to skip get edid fail and start display development Signed-off-by: Huijuan Xie <huijuan.xie(a)mediatek.corp-partner.google.com> Change-Id: I58c7ea1fd45a2def87593f9436d2c513c5b502af --- M src/drivers/analogix/anx7625/anx7625.c M src/soc/mediatek/common/dsi.c M src/soc/mediatek/common/include/soc/dsi_common.h 3 files changed, 67 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/46579/1 diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index 9f0b2e1..eb7e661 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -828,6 +828,26 @@ return ret; } +/*Add eDP EDID to skip get edid fail*/ +static const u8 edp_edid[128] = { + 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, + 0x0d, 0xae, 0x47, 0x12, 0x00, 0x00, 0x00, 0x00, + 0x13, 0x1c, 0x01, 0x04, 0x95, 0x19, 0x11, 0x78, + 0x02, 0x67, 0x75, 0x98, 0x59, 0x53, 0x90, 0x27, + 0x1c, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x61, 0x1f, + 0x56, 0x56, 0x50, 0x90, 0x0a, 0x30, 0x30, 0x20, + 0x36, 0x00, 0xfd, 0xa9, 0x00, 0x00, 0x00, 0x18, + 0x00, 0x00, 0x00, 0xfe, 0x00, 0x4e, 0x31, 0x32, + 0x30, 0x41, 0x43, 0x41, 0x2d, 0x45, 0x41, 0x31, + 0x0a, 0x20, 0x00, 0x00, 0x00, 0xfe, 0x00, 0x43, + 0x4d, 0x4e, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfe, + 0x00, 0x4e, 0x31, 0x32, 0x30, 0x41, 0x43, 0x41, + 0x2d, 0x45, 0x41, 0x31, 0x0a, 0x20, 0x00, 0xea, +}; + int anx7625_dp_get_edid(uint8_t bus, struct edid *out) { int block_num; @@ -835,6 +855,9 @@ u8 edid[FOUR_BLOCK_SIZE]; block_num = sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); + block_num=1; + + memcpy(edid, &edp_edid, sizeof(edp_edid)); if (block_num < 0) { ANXERROR("Failed to get eDP EDID.\n"); return -1; diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 2505bbc..ac289c8 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -130,8 +130,11 @@ if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) tmp_reg1 = SYNC_PULSE_MODE; } - +#if 1 //DSI pattern write32(&dsi0->dsi_mode_ctrl, tmp_reg1); + write32(&dsi0->dsi_bist_pattern, 0xff00); + write32(&dsi0->dsi_bist_con, 0x40); +#endif } static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes) @@ -415,7 +418,7 @@ { u32 data_rate; u32 bits_per_pixel = mtk_dsi_get_bits_per_pixel(format); - + data_rate = mtk_dsi_get_data_rate(bits_per_pixel, lanes, edid); if (!data_rate) return -1; @@ -434,5 +437,38 @@ mtk_dsi_set_mode(mode_flags); mtk_dsi_start(); + printk(BIOS_ERR, "dsi_start = 0x%08x\n", read32(&dsi0->dsi_start)); + printk(BIOS_ERR, "dsi_inten = 0x%08x\n", read32(&dsi0->dsi_inten)); + printk(BIOS_ERR, "dsi_intsta = 0x%08x\n", read32(&dsi0->dsi_intsta)); + printk(BIOS_ERR, "dsi_con_ctrl = 0x%08x\n", read32(&dsi0->dsi_con_ctrl)); + printk(BIOS_ERR, "dsi_mode_ctrl = 0x%08x\n", read32(&dsi0->dsi_mode_ctrl)); + printk(BIOS_ERR, "dsi_txrx_ctrl = 0x%08x\n", read32(&dsi0->dsi_txrx_ctrl)); + printk(BIOS_ERR, "dsi_psctrl = 0x%08x\n", read32(&dsi0->dsi_psctrl)); + printk(BIOS_ERR, "dsi_vsa_nl = 0x%08x\n", read32(&dsi0->dsi_vsa_nl)); + printk(BIOS_ERR, "dsi_vbp_nl = 0x%08x\n", read32(&dsi0->dsi_vbp_nl)); + printk(BIOS_ERR, "dsi_vfp_nl = 0x%08x\n", read32(&dsi0->dsi_vfp_nl)); + printk(BIOS_ERR, "dsi_vact_nl = 0x%08x\n", read32(&dsi0->dsi_vact_nl)); + printk(BIOS_ERR, "dsi_lfr_con = 0x%08x\n", read32(&dsi0->dsi_lfr_con)); + printk(BIOS_ERR, "dsi_lfr_sta = 0x%08x\n", read32(&dsi0->dsi_lfr_sta)); + printk(BIOS_ERR, "dsi_size_con = 0x%08x\n", read32(&dsi0->dsi_size_con)); + printk(BIOS_ERR, "dsi_vfp_early_stop = 0x%08x\n", read32(&dsi0->dsi_vfp_early_stop)); + printk(BIOS_ERR, "dsi_hsa_wc = 0x%08x\n", read32(&dsi0->dsi_hsa_wc)); + printk(BIOS_ERR, "dsi_hbp_wc = 0x%08x\n", read32(&dsi0->dsi_hbp_wc)); + printk(BIOS_ERR, "dsi_hfp_wc = 0x%08x\n", read32(&dsi0->dsi_hfp_wc)); + printk(BIOS_ERR, "dsi_bllp_wc = 0x%08x\n", read32(&dsi0->dsi_bllp_wc)); + printk(BIOS_ERR, "dsi_cmdq_size = 0x%08x\n", read32(&dsi0->dsi_cmdq_size)); + printk(BIOS_ERR, "dsi_hstx_cklp_wc = 0x%08x\n", read32(&dsi0->dsi_hstx_cklp_wc)); + printk(BIOS_ERR, "dsi_phy_lccon = 0x%08x\n", read32(&dsi0->dsi_phy_lccon)); + printk(BIOS_ERR, "dsi_phy_ld0con = 0x%08x\n", read32(&dsi0->dsi_phy_ld0con)); + printk(BIOS_ERR, "dsi_phy_timecon0 = 0x%08x\n", read32(&dsi0->dsi_phy_timecon0)); + printk(BIOS_ERR, "dsi_phy_timecon1 = 0x%08x\n", read32(&dsi0->dsi_phy_timecon1)); + printk(BIOS_ERR, "dsi_phy_timecon2 = 0x%08x\n", read32(&dsi0->dsi_phy_timecon2)); + printk(BIOS_ERR, "dsi_phy_timecon3 = 0x%08x\n", read32(&dsi0->dsi_phy_timecon3)); + printk(BIOS_ERR, "dsi_vm_cmd_con = 0x%08x\n", read32(&dsi0->dsi_vm_cmd_con)); + printk(BIOS_ERR, "dsi_bist_pattern = 0x%08x\n", read32(&dsi0->dsi_bist_pattern)); + printk(BIOS_ERR, "dsi_bist_con = 0x%08x\n", read32(&dsi0->dsi_bist_con)); + printk(BIOS_ERR, "dsi_force_commit = 0x%08x\n", read32(&dsi0->dsi_force_commit)); + return 0; } + diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h index 7bacec1..edb597a 100644 --- a/src/soc/mediatek/common/include/soc/dsi_common.h +++ b/src/soc/mediatek/common/include/soc/dsi_common.h @@ -75,10 +75,13 @@ u32 dsi_phy_timecon2; u32 dsi_phy_timecon3; u8 reserved4[16]; - u32 dsi_vm_cmd_con; - u8 reserved5[92]; + u32 dsi_vm_cmd_con;/*0x130*/ + u8 reserved5[68]; + u32 dsi_bist_pattern; /*0x178*/ + u32 dsi_bist_con;/* 0x17c */ + u8 reserved6[16]; u32 dsi_force_commit; /* Available since MT8183 */ - u8 reserved6[108]; + u8 reserved7[108]; u32 dsi_cmdq[128]; }; static struct dsi_regs *const dsi0 = (void *)DSI0_BASE; -- To view, visit https://review.coreboot.org/c/coreboot/+/46579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58c7ea1fd45a2def87593f9436d2c513c5b502af Gerrit-Change-Number: 46579 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: DEBUG: ANX read edid test
by yongqiang niu (Code Review) 17 Nov '20

17 Nov '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46837 ) Change subject: DEBUG: ANX read edid test ...................................................................... DEBUG: ANX read edid test Signed-off-by: Yongqiang Niu <yongqiang.niu(a)mediatek.com> Change-Id: Icaaf8d7a96d40839947beeb0b6d50521b314b91a --- M src/drivers/analogix/anx7625/anx7625.c 1 file changed, 28 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/46837/1 diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index 1f04346..121075a 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -848,24 +848,41 @@ 0x2d, 0x45, 0x41, 0x31, 0x0a, 0x20, 0x00, 0xea, }; +static void anx7625_read_ver(uint8_t bus) +{ + uint8_t version, revision; + + anx7625_reg_read(bus, RX_P0_ADDR, OCM_FW_VERSION, &version); + anx7625_reg_read(bus, RX_P0_ADDR, OCM_FW_REVERSION, &revision); + + ANXINFO("OCM : ver %#02x, rev %#02x.\n", version, revision); +} + int anx7625_dp_get_edid(uint8_t bus, struct edid *out) { int block_num; int ret; u8 edid[FOUR_BLOCK_SIZE]; - /* Something goes terribly wrong here, and ANX7625 does not seem to be able to recover from it. */ - block_num = sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); - if (block_num <= 0) { - block_num = 1; - memcpy(edid, &edp_edid, sizeof(edp_edid)); - ANXINFO("Failed to get eDP EDID, test with hard code edied.\n"); - } + anx7625_read_ver(bus); + ANXINFO("first time read edid\n"); + sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); + ANXERROR("get eDP EDID at 1st time done.\n"); - if (block_num < 0) { - ANXERROR("Failed to get eDP EDID.\n"); - return -1; - } + anx7625_read_ver(bus); + ANXINFO("2nd time read edid\n"); + sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); + ANXERROR("get eDP EDID at 2nd time done.\n"); + + anx7625_read_ver(bus); + ANXINFO("3rd time read edid\n"); + sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); + ANXERROR("get eDP EDID at 3rd time done.\n"); + anx7625_read_ver(bus); + + ANXINFO("use fixed edid\n"); + block_num = 0; + memcpy(edid, &edp_edid, sizeof(edp_edid)); ret = decode_edid(edid, (block_num + 1) * ONE_BLOCK_SIZE, out); if (ret != EDID_CONFORMANT) { -- To view, visit https://review.coreboot.org/c/coreboot/+/46837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icaaf8d7a96d40839947beeb0b6d50521b314b91a Gerrit-Change-Number: 46837 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: DEBUG: anx read edid test
by yongqiang niu (Code Review) 17 Nov '20

17 Nov '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46827 ) Change subject: DEBUG: anx read edid test ...................................................................... DEBUG: anx read edid test Signed-off-by: Yongqiang Niu <yongqiang.niu(a)mediatek.com> Change-Id: I3b880f69f3c0d987972bb6b337c636bfa130b9ce --- M src/drivers/analogix/anx7625/anx7625.c 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/46827/1 diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index e3f969c..1f04346 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -855,11 +855,13 @@ u8 edid[FOUR_BLOCK_SIZE]; /* Something goes terribly wrong here, and ANX7625 does not seem to be able to recover from it. */ - if (0) - block_num = sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); - block_num=1; + block_num = sp_tx_edid_read(bus, edid, FOUR_BLOCK_SIZE); + if (block_num <= 0) { + block_num = 1; + memcpy(edid, &edp_edid, sizeof(edp_edid)); + ANXINFO("Failed to get eDP EDID, test with hard code edied.\n"); + } - memcpy(edid, &edp_edid, sizeof(edp_edid)); if (block_num < 0) { ANXERROR("Failed to get eDP EDID.\n"); return -1; -- To view, visit https://review.coreboot.org/c/coreboot/+/46827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b880f69f3c0d987972bb6b337c636bfa130b9ce Gerrit-Change-Number: 46827 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: HACK: Enable display backlight
by yongqiang niu (Code Review) 17 Nov '20

17 Nov '20

Hello Nicolas Boichat, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46583 to review the following change. Change subject: HACK: Enable display backlight ...................................................................... HACK: Enable display backlight Change the polarity so that the backlight is at maximum. BUG=b:155713214 TEST=boot asurada Change-Id: I058af933e59be84cca77ea15b668be6efcc6539d --- M src/mainboard/google/asurada/mainboard.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/46583/1 diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index 30e98e8..56ecc9e 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -56,8 +56,8 @@ /* Set up backlight control pins as output pin and power-off by default */ static void configure_panel_backlight(void) { - gpio_output(GPIO(KPROW1), 0); - gpio_output(GPIO(DISP_PWM), 0); + gpio_output(GPIO(KPROW1), 1); + gpio_output(GPIO(DISP_PWM), 1); } static void power_on_panel(struct panel_description *panel) -- To view, visit https://review.coreboot.org/c/coreboot/+/46583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I058af933e59be84cca77ea15b668be6efcc6539d Gerrit-Change-Number: 46583 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-MessageType: newchange

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