coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3474 discussions

Change in coreboot[master]: mb/facebook/fbg1701/Kconfig: Add dependency
by Frans Hendriks (Code Review) 22 Nov '20

22 Nov '20

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46218 ) Change subject: mb/facebook/fbg1701/Kconfig: Add dependency ...................................................................... mb/facebook/fbg1701/Kconfig: Add dependency VENDORCODE_ELTAN items are only used when USE_VENDORCODE_ELTAN is enabled. Add dependency of USE_VENDORCODE_ELTAN. Change-Id: Ibcc40014930c90e29904661f5ffa41bc688d368b Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/facebook/fbg1701/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46218/1 diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index 0f23ed2..d86458f 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -49,6 +49,7 @@ default 0xfff9c000 config VENDORCODE_ELTAN_OEM_MANIFEST_LOC + depends on USE_VENDORCODE_ELTAN hex default 0xFFFE9000 @@ -69,14 +70,17 @@ default 0x4000 config VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST + depends on USE_VENDORCODE_ELTAN bool default y config VENDORCODE_ELTAN_VBOOT_MANIFEST + depends on USE_VENDORCODE_ELTAN string default "mainboard/facebook/fbg1701/manifest.h" config VENDORCODE_ELTAN_VBOOT_KEY_LOCATION + depends on USE_VENDORCODE_ELTAN hex default 0xFFFF9C00 -- To view, visit https://review.coreboot.org/c/coreboot/+/46218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcc40014930c90e29904661f5ffa41bc688d368b Gerrit-Change-Number: 46218 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: soc/intel/denverton_ns: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 22 Nov '20

22 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46240 ) Change subject: soc/intel/denverton_ns: Convert to ASL 2.0 syntax ...................................................................... soc/intel/denverton_ns: Convert to ASL 2.0 syntax Change-Id: I261add8142c3192ab944845e8e1a362a3aca00c8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/denverton_ns/acpi/globalnvs.asl M src/soc/intel/denverton_ns/acpi/irqlinks.asl M src/soc/intel/denverton_ns/acpi/northcluster.asl M src/soc/intel/denverton_ns/acpi/southcluster.asl 4 files changed, 66 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/46240/1 diff --git a/src/soc/intel/denverton_ns/acpi/globalnvs.asl b/src/soc/intel/denverton_ns/acpi/globalnvs.asl index f858cdf..7ce6c7a 100644 --- a/src/soc/intel/denverton_ns/acpi/globalnvs.asl +++ b/src/soc/intel/denverton_ns/acpi/globalnvs.asl @@ -62,27 +62,27 @@ /* Set flag to enable USB charging in S3 */ Method (S3UE) { - Store (One, \S3U0) - Store (One, \S3U1) + \S3U0 = 1 + \S3U1 = 1 } /* Set flag to disable USB charging in S3 */ Method (S3UD) { - Store (Zero, \S3U0) - Store (Zero, \S3U1) + \S3U0 = 0 + \S3U1 = 0 } /* Set flag to enable USB charging in S5 */ Method (S5UE) { - Store (One, \S5U0) - Store (One, \S5U1) + \S5U0 = 1 + \S5U1 = 1 } /* Set flag to disable USB charging in S5 */ Method (S5UD) { - Store (Zero, \S5U0) - Store (Zero, \S5U1) + \S5U0 = 0 + \S5U1 = 0 } diff --git a/src/soc/intel/denverton_ns/acpi/irqlinks.asl b/src/soc/intel/denverton_ns/acpi/irqlinks.asl index e62d84d..ef076bc 100644 --- a/src/soc/intel/denverton_ns/acpi/irqlinks.asl +++ b/src/soc/intel/denverton_ns/acpi/irqlinks.asl @@ -8,7 +8,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTA) + PRTA = 0x80 } // Possible Resource Settings for this Link @@ -28,10 +28,10 @@ CreateWordField(RTLA, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTA - ShiftLeft(1, And(PRTA, 0x0f), IRQ0) + IRQ0 = 1 << (PRTA & 0x0f) Return (RTLA) } @@ -44,14 +44,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTA) + Local0-- + PRTA = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTA, 0x80)) { + If (PRTA & 0x80) { Return (0x9) } Else { Return (0xb) @@ -67,7 +67,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTB) + PRTB = 0x80 } // Possible Resource Settings for this Link @@ -87,10 +87,10 @@ CreateWordField(RTLB, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTB - ShiftLeft(1, And(PRTB, 0x0f), IRQ0) + IRQ0 = 1 << (PRTB & 0x0f) Return (RTLB) } @@ -103,14 +103,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTB) + Local0-- + PRTB = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTB, 0x80)) { + If (PRTB & 0x80) { Return (0x9) } Else { Return (0xb) @@ -126,7 +126,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTC) + PRTC = 0x80 } // Possible Resource Settings for this Link @@ -146,10 +146,10 @@ CreateWordField(RTLC, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTC - ShiftLeft(1, And(PRTC, 0x0f), IRQ0) + IRQ0 = 1 << (PRTC & 0x0f) Return (RTLC) } @@ -162,14 +162,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTC) + Local0-- + PRTC = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTC, 0x80)) { + If (PRTC & 0x80) { Return (0x9) } Else { Return (0xb) @@ -185,7 +185,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTD) + PRTD = 0x80 } // Possible Resource Settings for this Link @@ -205,10 +205,10 @@ CreateWordField(RTLD, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTD - ShiftLeft(1, And(PRTD, 0x0f), IRQ0) + IRQ0 = 1 << (PRTD & 0x0f) Return (RTLD) } @@ -221,14 +221,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTD) + Local0-- + PRTD = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTD, 0x80)) { + If (PRTD & 0x80) { Return (0x9) } Else { Return (0xb) @@ -244,7 +244,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTE) + PRTE = 0x80 } // Possible Resource Settings for this Link @@ -264,10 +264,10 @@ CreateWordField(RTLE, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTE - ShiftLeft(1, And(PRTE, 0x0f), IRQ0) + IRQ0 = 1 << (PRTE & 0x0f) Return (RTLE) } @@ -280,14 +280,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTE) + Local0-- + PRTE = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTE, 0x80)) { + If (PRTE & 0x80) { Return (0x9) } Else { Return (0xb) @@ -303,7 +303,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTF) + PRTF = 0x80 } // Possible Resource Settings for this Link @@ -323,10 +323,10 @@ CreateWordField(RTLF, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTF - ShiftLeft(1, And(PRTF, 0x0f), IRQ0) + IRQ0 = 1 << (PRTF & 0x0f) Return (RTLF) } @@ -339,14 +339,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTF) + Local0-- + PRTF = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTF, 0x80)) { + If (PRTF & 0x80) { Return (0x9) } Else { Return (0xb) @@ -362,7 +362,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTG) + PRTG = 0x80 } // Possible Resource Settings for this Link @@ -382,10 +382,10 @@ CreateWordField(RTLG, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTG - ShiftLeft(1, And(PRTG, 0x0f), IRQ0) + IRQ0 = 1 << (PRTG & 0x0f) Return (RTLG) } @@ -398,14 +398,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTG) + Local0-- + PRTG = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTG, 0x80)) { + If (PRTG & 0x80) { Return (0x9) } Else { Return (0xb) @@ -421,7 +421,7 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTH) + PRTH = 0x80 } // Possible Resource Settings for this Link @@ -441,10 +441,10 @@ CreateWordField(RTLH, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTH - ShiftLeft(1, And(PRTH, 0x0f), IRQ0) + IRQ0 = 1 << (PRTH & 0x0f) Return (RTLH) } @@ -457,14 +457,14 @@ // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTH) + Local0-- + PRTH = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTH, 0x80)) { + If (PRTH & 0x80) { Return (0x9) } Else { Return (0xb) diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl index e1d1e40..40d745e 100644 --- a/src/soc/intel/denverton_ns/acpi/northcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl @@ -97,9 +97,9 @@ CreateDwordField(MCRS, ^PM01._LEN, PLEN) // MMIO Low is saved in NVS - Store (\MMOB, PMIN) - Store (\MMOL, PMAX) - Add (Subtract (PMAX, PMIN), 1, PLEN) + PMIN = \MMOB + PMAX = \MMOL + PLEN = PMAX - PMIN + 1 // Find PCI resource area in MCRS CreateQWordField(MCRS, ^PM02._MIN, P2MN) @@ -107,9 +107,9 @@ CreateQWordField(MCRS, ^PM02._LEN, P2LN) // MMIO High is saved in NVS - Store(\MMHB, P2MN) - Store(\MMHL, P2MX) - Add(Subtract(P2MX,P2MN),1,P2LN) + P2MN = \MMHB + P2MX = \MMHL + P2LN = P2MX - P2MN +1 Return (MCRS) } // End _CRS @@ -132,9 +132,9 @@ { // Fix up 32-bit TSEG CreateDWordField(PDRS, ^TSMB._BAS, TSMN) - Store(\TSGB, TSMN) + TSMN = \TSGB CreateDWordField(PDRS, ^TSMB._LEN, TSLN) - Store(\TSSZ, TSLN) + TSLN = \TSSZ Return(PDRS) } } diff --git a/src/soc/intel/denverton_ns/acpi/southcluster.asl b/src/soc/intel/denverton_ns/acpi/southcluster.asl index 68f55f2..72e12bd 100644 --- a/src/soc/intel/denverton_ns/acpi/southcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/southcluster.asl @@ -128,7 +128,7 @@ Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -137,7 +137,7 @@ { /* Unrecognized UUID */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1 |= 4 Return (Arg3) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I261add8142c3192ab944845e8e1a362a3aca00c8 Gerrit-Change-Number: 46240 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/facebook/fbg1701: Add VBOOT support
by Frans Hendriks (Code Review) 22 Nov '20

22 Nov '20

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46219 ) Change subject: mb/facebook/fbg1701: Add VBOOT support ...................................................................... mb/facebook/fbg1701: Add VBOOT support Add VBOOT support. Disabled USE_VENDOR_ELTAN when VBOOT is enabled. Add FMD file and split binary into RW and RO region settings. Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Tested on Facebook FBG1701 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Change-Id: I641bca58c0f7c81d5742235c8b2c184d13c00c55 --- M src/mainboard/facebook/fbg1701/Kconfig A src/mainboard/facebook/fbg1701/vboot-rw.fmd 2 files changed, 45 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/46219/1 diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index d86458f..d6d2a27 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -20,7 +20,18 @@ select DISABLE_HPET select INTEL_GMA_HAVE_VBT select HAVE_SPD_IN_CBFS - select USE_VENDORCODE_ELTAN + +config USE_VENDORCODE_ELTAN + depends on !VBOOT + default y + +config VBOOT_VBNV_CMOS + depends on VBOOT + default y + +config VBOOT_SLOTS_RW_AB + depends on VBOOT + default n config ONBOARD_SAMSUNG_MEM bool "Onboard memory manufacturer Samsung" @@ -88,4 +99,16 @@ bool default n +config FMDFILE + depends on VBOOT + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rw.fmd" + +config RW_REGION_ONLY + depends on VBOOT + default "%/payload logo.bmp %/ramstage vbt.bin %/dsdt.aml config %/postcar" + +config RO_REGION_ONLY + depends on VBOOT + default "spd.bin fsp.bin cpu_microcode_blob.bin" + endif # BOARD_FACEBOOK_FBG1701 diff --git a/src/mainboard/facebook/fbg1701/vboot-rw.fmd b/src/mainboard/facebook/fbg1701/vboot-rw.fmd new file mode 100644 index 0000000..51ee470 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/vboot-rw.fmd @@ -0,0 +1,21 @@ +FLASH 8M { + SI_BIOS@0x200000 0x600000 { + MISC_RW@0x0 0x08000 { + RW_MRC_CACHE@0 0x08000 + } + RW_SECTION_A@0x08000 0x578000 { + VBLOCK_A@0x0 0x10000 + RW_FWID_A@0x10000 0x40 + FW_MAIN_A(CBFS)@0x10040 0x567FC0 + } + WP_RO@0x580000 0x080000 { + RO_SECTION@0x0000 0x80000 { + FMAP@0x0 0x400 + RO_FRID@0xA00 0x40 + RO_FRID_PAD@0xA40 0x5c0 + GBB@0x1000 0x4000 + COREBOOT(CBFS)@0x5000 0x07B000 + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I641bca58c0f7c81d5742235c8b2c184d13c00c55 Gerrit-Change-Number: 46219 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

5 25

Change in coreboot[master]: lenovo/g505s: proper way of IRQ table programming
by Mike Banon (Code Review) 22 Nov '20

22 Nov '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46587 ) Change subject: lenovo/g505s: proper way of IRQ table programming ...................................................................... lenovo/g505s: proper way of IRQ table programming IRQ programming should be outside the obsolete MP table generation, just like the proper way done for asus/am1i-a AMD fam16h - closest example for Lenovo G505S: all the fam15h boards have these "bad IRQs". With this change applied, G505S boots fine to Linux, but a KolibriOS sees only 1 interrupt - which is still better than a previous 0. So an approach is correct, but the code should be improved. Any advice? Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I32341878e31047f888502291bbdaa76dad268223 --- M src/mainboard/lenovo/g505s/irq_tables.c M src/mainboard/lenovo/g505s/mainboard.c M src/mainboard/lenovo/g505s/mptable.c 3 files changed, 193 insertions(+), 120 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/46587/1 diff --git a/src/mainboard/lenovo/g505s/irq_tables.c b/src/mainboard/lenovo/g505s/irq_tables.c index 0baf079..8ae363e 100644 --- a/src/mainboard/lenovo/g505s/irq_tables.c +++ b/src/mainboard/lenovo/g505s/irq_tables.c @@ -1,88 +1,38 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/pirq_routing.h> -#include <console/console.h> -#include <device/pci_def.h> -#include <string.h> -#include <stdint.h> -static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, - u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, - u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, - u8 slot, u8 rfu) -{ - pirq_info->bus = bus; - pirq_info->devfn = devfn; - pirq_info->irq[0].link = link0; - pirq_info->irq[0].bitmap = bitmap0; - pirq_info->irq[1].link = link1; - pirq_info->irq[1].bitmap = bitmap1; - pirq_info->irq[2].link = link2; - pirq_info->irq[2].bitmap = bitmap2; - pirq_info->irq[3].link = link3; - pirq_info->irq[3].bitmap = bitmap3; - pirq_info->slot = slot; - pirq_info->rfu = rfu; -} +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x14 << 3) | 0x3, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1002, /* Vendor */ + 0x4384, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x3b, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x02 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, + {0x00, (0x10 << 3) | 0x0, {{0x03, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x11 << 3) | 0x0, {{0x04, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x12 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x13 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x14 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, + {0x00, (0x16 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x01, (0x00 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, + {0x02, (0x00 << 3) | 0x0, {{0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + } +}; unsigned long write_pirq_routing_table(unsigned long addr) { - struct irq_routing_table *pirq; - struct irq_info *pirq_info; - u32 slot_num; - u8 *v; - - u8 sum = 0; - int i; - - /* Align the table to be 16 byte aligned. */ - addr += 15; - addr &= ~15; - - /* This table must be between 0xf0000 & 0x100000 */ - printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); - - pirq = (void *)(addr); - v = (u8 *) (addr); - - pirq->signature = PIRQ_SIGNATURE; - pirq->version = PIRQ_VERSION; - - pirq->rtr_bus = 0; - pirq->rtr_devfn = PCI_DEVFN(0x14, 4); - - pirq->exclusive_irqs = 0; - - pirq->rtr_vendor = 0x1002; - pirq->rtr_device = 0x4384; - - pirq->miniport_data = 0; - - memset(pirq->rfu, 0, sizeof(pirq->rfu)); - - pirq_info = (void *)(&pirq->checksum + 1); - slot_num = 0; - - /* pci bridge */ - write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), - 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, - 0); - pirq_info++; - - slot_num++; - - pirq->size = 32 + 16 * slot_num; - - for (i = 0; i < pirq->size; i++) - sum += v[i]; - - sum = pirq->checksum - sum; - - if (sum != pirq->checksum) { - pirq->checksum = sum; - } - - printk(BIOS_INFO, "%s done.\n", __func__); - - return (unsigned long)pirq_info; + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/lenovo/g505s/mainboard.c b/src/mainboard/lenovo/g505s/mainboard.c index d900c94..3d666a8 100644 --- a/src/mainboard/lenovo/g505s/mainboard.c +++ b/src/mainboard/lenovo/g505s/mainboard.c @@ -7,8 +7,81 @@ #include <cpu/x86/smm.h> #include <device/device.h> +#include <southbridge/amd/agesa/hudson/pci_devs.h> +#include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h> +#include <southbridge/amd/common/amd_pci_util.h> +#include <northbridge/amd/agesa/family15tn/pci_devs.h> #include <southbridge/amd/agesa/hudson/smi.h> +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x5A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ + [0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/22 INTA-B */ + [0x30] = 0x05,0x04,0x05,0x04,0x05,0x04,0x1F,0x1F, + /* RSVD, SATA */ + [0x40] = 0x1F, 0x07 +}; + +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10,0x11,0x12,0x13,0x1F,0x1F,0x1F,0x1F, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/22 INTA-B */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x1F,0x1F, + /* RSVD, SATA */ + [0x40] = 0x1F, 0x13 +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ + {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ + {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */ + {NB_PCIE_PORT5_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* Edge: 02.5 */ + {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ +}; + +const u8 *picr_data = mainboard_picr_data; +const u8 *intr_data = mainboard_intr_data; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + static void pavilion_cold_boot_init(void) { /* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */ @@ -17,10 +90,16 @@ lenovo_g505s_ec_init(); } +/********************************************** + * enable the dedicated function in mainboard. + **********************************************/ static void mainboard_enable(struct device *dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); + hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH); global_smi_enable(); diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c index bc1759a..4f7272f 100644 --- a/src/mainboard/lenovo/g505s/mptable.c +++ b/src/mainboard/lenovo/g505s/mptable.c @@ -5,23 +5,48 @@ #include <arch/smp/mpspec.h> #include <stdint.h> #include <string.h> +#include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/agesa/hudson/hudson.h> +#include <drivers/generic/ioapic/chip.h> -u8 picr_data[0x54] = { - 0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ + [0x10] = 0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F, + [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, + [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* USB Devs 18/19/22 INTA-B */ + [0x30] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00, + [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* RSVD, SATA */ + [0x40] = 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00, + [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x50] = 0x1F,0x1F,0x1F,0x1F }; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 + +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10, + [0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* IMC INT0 - 5 */ + [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00, + [0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* USB Devs 18/19/22 INTA-B */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00, + [0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + /* RSVD, SATA */ + [0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00, + [0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + [0x50] = 0x10,0x11,0x12,0x13 }; static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) @@ -56,44 +81,60 @@ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + /* Initialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); + /* + * Type 1: Bus Entries: + * Bus ID, Bus Type + */ + // mptable_write_buses(mc, NULL, &bus_isa); my_smp_write_bus(mc, 0, "PCI "); my_smp_write_bus(mc, 1, "PCI "); bus_isa = 0x02; my_smp_write_bus(mc, bus_isa, "ISA "); - /* I/O APICs: APIC ID Version State Address */ + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + for (byte = 0x0; byte < sizeof(picr_data_ptr); byte ++) { outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); + outb(mainboard_picr_data[byte], 0xC01); } /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + for (byte = 0x0; byte < sizeof(intr_data_ptr); byte ++) { outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); + outb(mainboard_intr_data[byte], 0xC01); } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source Bus ID, + * Source Bus IRQ, Dest APIC ID, Dest PIN# + */ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) /* IOMMU */ PCI_INT(0x0, 0x00, 0x0, 0x10); @@ -102,27 +143,27 @@ PCI_INT(0x0, 0x00, 0x3, 0x13); /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); /* SMBUS */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); /* on board NIC & Slot PCIE. */ @@ -161,9 +202,12 @@ /* FCH PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13); - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32341878e31047f888502291bbdaa76dad268223 Gerrit-Change-Number: 46587 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

3 57

Change in coreboot[master]: mb/google/asurada: Get ram id from AUX_IN3
by Yidi Lin (Code Review) 21 Nov '20

21 Nov '20

Hello CK HU, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46391 to review the following change. Change subject: mb/google/asurada: Get ram id from AUX_IN3 ...................................................................... mb/google/asurada: Get ram id from AUX_IN3 Mapping the voltage of AUX_IN3 to ram id. Signed-off-by: CK Hu <ck.hu(a)mediatek.com> Change-Id: Iaadabea1b6aa91c48b137f7c6784ab7ee0adc473 --- M src/mainboard/google/asurada/boardid.c 1 file changed, 55 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/46391/1 diff --git a/src/mainboard/google/asurada/boardid.c b/src/mainboard/google/asurada/boardid.c index 2c8efcd..6dc1f7a 100644 --- a/src/mainboard/google/asurada/boardid.c +++ b/src/mainboard/google/asurada/boardid.c @@ -1,9 +1,58 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <boardid.h> +#include <console/console.h> +#include <soc/auxadc.h> /* board_id is provided by ec/google/chromeec/ec_boardid.c */ +#define ADC_LEVELS 15 + +enum { + RAM_ID_CHANNEL = 3, +}; + +static const int ram_voltages[ADC_LEVELS] = { + /* ID : Voltage (unit: uV) */ + /* 0 : */ 74300, + /* 1 : */ 211700, + /* 2 : */ 318800, + /* 3 : */ 428600, + /* 4 : */ 541700, + /* 5 : */ 665800, + /* 6 : */ 781400, + /* 7 : */ 900000, + /* 8 : */ 1023100, + /* 9 : */ 1137000, + /* 10 : */ 1240000, + /* 11 : */ 1342600, + /* 12 : */ 1457500, + /* 13 : */ 1575600, + /* 14 : */ 1683600, +}; + +static const int *adc_voltages[] = { + [RAM_ID_CHANNEL] = ram_voltages, +}; + +static uint32_t get_adc_index(unsigned int channel) +{ + int value = auxadc_get_voltage(channel); + + assert(channel < ARRAY_SIZE(adc_voltages)); + const int *voltages = adc_voltages[channel]; + assert(voltages); + + /* Find the closest voltage */ + uint32_t id; + for (id = 0; id < ADC_LEVELS - 1; id++) + if (value < (voltages[id] + voltages[id + 1]) / 2) + break; + printk(BIOS_DEBUG, "ADC[%d]: Raw value=%d ID=%d\n", channel, value, id); + return id; +} + uint32_t sku_id(void) { return 0; @@ -11,5 +60,10 @@ uint32_t ram_code(void) { - return 0; + static uint32_t cached_ram_code = BOARD_ID_INIT; + + if (cached_ram_code == BOARD_ID_INIT) + cached_ram_code = get_adc_index(RAM_ID_CHANNEL); + + return cached_ram_code; } -- To view, visit https://review.coreboot.org/c/coreboot/+/46391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaadabea1b6aa91c48b137f7c6784ab7ee0adc473 Gerrit-Change-Number: 46391 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: CK HU <ck.hu(a)mediatek.com> Gerrit-MessageType: newchange

6 24

Change in coreboot[master]: cbfs: Add metadata cache
by Julius Werner (Code Review) 21 Nov '20

21 Nov '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38423 to review the following change. Change subject: cbfs: Add metadata cache ...................................................................... cbfs: Add metadata cache This patch adds a new CBFS "mcache" (metadata cache) -- a memory buffer that stores the headers of all CBFS files. Similar to the existing FMAP cache, this cache should reduce the amount of SPI accesses we need to do every boot: rather than having to re-read all CBFS headers from SPI flash every time we're looking for a file, we can just walk the same list in this in-memory copy and finally use it to directly access the flash at the right position for the file data. This patch adds the code to support the cache but doesn't enable it on any platform. The next one will turn it on by default. Change-Id: I5b1084bfdad1c6ab0ee1b143ed8dd796827f4c65 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/Makefile.inc A src/commonlib/bsd/cbfs_mcache.c M src/commonlib/bsd/include/commonlib/bsd/cb_err.h M src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h M src/commonlib/include/commonlib/cbmem_id.h M src/include/cbfs.h M src/include/memlayout.h M src/include/symbols.h M src/lib/Kconfig M src/lib/cbfs.c M src/lib/coreboot_table.c M src/security/vboot/vboot_common.h M src/security/vboot/vboot_loader.c 13 files changed, 346 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/38423/1 diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index b2225cb..1a38e4a 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -37,6 +37,13 @@ ramstage-y += bsd/cbfs_private.c smm-y += bsd/cbfs_private.c +bootblock-y += bsd/cbfs_mcache.c +verstage-y += bsd/cbfs_mcache.c +romstage-y += bsd/cbfs_mcache.c +postcar-y += bsd/cbfs_mcache.c +ramstage-y += bsd/cbfs_mcache.c +smm-y += bsd/cbfs_mcache.c + decompressor-y += bsd/lz4_wrapper.c bootblock-y += bsd/lz4_wrapper.c verstage-y += bsd/lz4_wrapper.c diff --git a/src/commonlib/bsd/cbfs_mcache.c b/src/commonlib/bsd/cbfs_mcache.c new file mode 100644 index 0000000..d97dcce --- /dev/null +++ b/src/commonlib/bsd/cbfs_mcache.c @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */ + +#include <commonlib/bsd/cbfs_private.h> + +#define MCACHE_TOKEN_MAGIC 0xd +#define MCACHE_OFFSET_FULL 0 +#define MCACHE_OFFSET_END 1 + +struct mcache_token { + uint32_t offset : 28; + uint32_t magic : 4; +}; + +struct cbfs_mcache_build_args { + void *mcache; + void *end; + size_t offset; + int count; +}; + +static void make_token(struct cbfs_mcache_build_args *args, size_t new_offset) +{ + struct mcache_token *token = args->mcache; + + /* If there's no space for the token, lookup() will know the cache is full anyway. */ + if (args->end - args->mcache < sizeof(*token)) + return; + + token->magic = MCACHE_TOKEN_MAGIC; + token->offset = new_offset; + + args->mcache += sizeof(*token); +} + +static cb_err_t build_walker(cbfs_dev_t dev, size_t offset, union cbfs_mdata *mdata, + bool do_hash, void *arg) +{ + struct cbfs_mcache_build_args *args = arg; + const uint32_t data_offset = be32toh(mdata->h.offset); + const uint32_t data_length = be32toh(mdata->h.len); + + if (offset != args->offset) + make_token(args, offset); + + if (args->end - args->mcache < data_offset) { + make_token(args, MCACHE_OFFSET_FULL); + return CB_CBFS_CACHE_FULL; + } + + if (cbfs_copy_fill_metadata(args->mcache, mdata, dev, offset, do_hash) != CB_SUCCESS) + return CB_CBFS_IO; + + args->mcache += data_offset; + args->offset = ALIGN_UP(offset + data_offset + data_length, CBFS_ALIGNMENT); + args->count++; + + return CB_CBFS_NOT_FOUND; +} + +cb_err_t cbfs_mcache_build(cbfs_dev_t dev, void *mcache, size_t size, + struct vb2_hash *master_hash) +{ + struct cbfs_mcache_build_args args = { + .mcache = mcache, + .end = mcache + size, + .offset = 0, + .count = 0, + }; + + cb_err_t ret = cbfs_walk(dev, build_walker, &args, master_hash, 0); + if (ret == CB_CBFS_CACHE_FULL) + ERROR("mcache overflow, should increase CBFS_MCACHE size!\n"); + else if (ret != CB_CBFS_NOT_FOUND) + return ret; + + make_token(&args, MCACHE_OFFSET_END); + LOG("mcache @%p built for %d files, used %#zx bytes\n", + mcache, args.count, args.mcache - mcache); + return CB_SUCCESS; +} + +cb_err_t cbfs_mcache_lookup(cbfs_dev_t dev, void *mcache, size_t mcache_size, const char *name, + union cbfs_mdata *mdata_out, size_t *data_offset_out, + struct vb2_hash *master_hash) +{ + size_t namesize = strlen(name) + 1; /* Count trailing \0 so we can memcmp() it. */ + void *end = mcache + mcache_size; + void *current = mcache; + + size_t offset = 0; + while (end - current >= sizeof(struct mcache_token)) { + union cbfs_mdata *mdata = current; + + if (memcmp(mdata->h.magic, CBFS_FILE_MAGIC, sizeof(mdata->h.magic)) != 0) { + struct mcache_token *token = current; + if (token->magic != MCACHE_TOKEN_MAGIC) { + ERROR("CBFS mcache corrupted at %p\n", token); + return CB_ERR; + } + if (token->offset == MCACHE_OFFSET_END) + return CB_CBFS_NOT_FOUND; + if (token->offset == MCACHE_OFFSET_FULL) + break; + offset = token->offset; + current += sizeof(*token); + continue; + } + + const uint32_t data_offset = be32toh(mdata->h.offset); + const uint32_t data_length = be32toh(mdata->h.len); + if (namesize <= cbfs_filename_size(&mdata->h) && + memcmp(name, mdata->filename, namesize) == 0) { + LOG("Found '%s' @%#zx size %#x in mcache @%p\n", + name, offset, data_length, current); + *data_offset_out = offset + data_offset; + memcpy(mdata_out, mdata, data_offset); + return CB_SUCCESS; + } + + offset = ALIGN_UP(offset + data_offset + data_length, CBFS_ALIGNMENT); + current += data_offset; + } + + return cbfs_lookup(dev, name, mdata_out, data_offset_out, master_hash); +} + +size_t cbfs_mcache_real_size(void *mcache, size_t mcache_size) +{ + void *end = mcache + mcache_size; + void *current = mcache; + + while (end - current >= sizeof(struct mcache_token)) { + union cbfs_mdata *mdata = current; + + if (memcmp(mdata->h.magic, CBFS_FILE_MAGIC, sizeof(mdata->h.magic)) != 0) { + struct mcache_token *token = current; + current += sizeof(*token); + if (token->offset == MCACHE_OFFSET_END || + token->offset == MCACHE_OFFSET_FULL) + break; + } else { + current += be32toh(mdata->h.offset); + } + } + + return current - mcache; +} diff --git a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h index ab422e1..18aa4d7 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h @@ -39,6 +39,7 @@ CB_CBFS_IO = -400, /**< Underlying I/O error */ CB_CBFS_NOT_FOUND = -401, /**< File not found in directory */ CB_CBFS_HASH = -402, /**< Master hash validation failed */ + CB_CBFS_CACHE_FULL = -403, /**< Metadata cache overflowed */ }; /* Don't typedef the enum directly, so the size is unambiguous for serialization. */ diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h index b4fc1c7..374a460 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h @@ -92,4 +92,22 @@ cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out, size_t *data_offset_out, struct vb2_hash *master_hash); +/* Build an in-memory CBFS metadata cache out of the CBFS on |dev| into a |mcache_size| bytes + * memory area at |mcache|. Also verify |master_hash| unless it is NULL. */ +cb_err_t cbfs_mcache_build(cbfs_dev_t dev, void *mcache, size_t mcache_size, + struct vb2_hash *master_hash); + +/* + * Find a file named |name| in a CBFS metadata cache and copy its metadata into |mdata_out|. + * Pass out offset to the file data (on the storage backend). May fall back to cbfs_lookup() if + * metadata cache was too small for CBFS. |dev| and |master_hash| must have the same values as + * originally passed to cbfs_mcache_build(). + */ +cb_err_t cbfs_mcache_lookup(cbfs_dev_t dev, void *mcache, size_t mcache_size, const char *name, + union cbfs_mdata *mdata_out, size_t *data_offset_out, + struct vb2_hash *master_hash); + +/* Returns the amount of bytes actually used by the CBFS metadata cache in |mcache|. */ +size_t cbfs_mcache_real_size(void *mcache, size_t mcache_size); + #endif /* _COMMONLIB_BSD_CBFS_PRIVATE_H_ */ diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index b063cd1..8f4f7f3 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -79,6 +79,8 @@ #define CBMEM_ID_ROM2 0x524f4d32 #define CBMEM_ID_ROM3 0x524f4d33 #define CBMEM_ID_FMAP 0x464d4150 +#define CBMEM_ID_CBFS_RO_MCACHE 0x524d5346 +#define CBMEM_ID_CBFS_RW_MCACHE 0x574d5346 #define CBMEM_ID_FSP_LOGO 0x4c4f474f #define CBMEM_ID_TO_NAME_TABLE \ @@ -141,5 +143,7 @@ { CBMEM_ID_ROM1, "VGA ROM #1 "}, \ { CBMEM_ID_ROM2, "VGA ROM #2 "}, \ { CBMEM_ID_ROM3, "VGA ROM #3 "}, \ - { CBMEM_ID_FMAP, "FMAP "}, + { CBMEM_ID_FMAP, "FMAP "}, \ + { CBMEM_ID_CBFS_RO_MCACHE, "RO MCACHE "}, \ + { CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "} #endif /* _CBMEM_ID_H_ */ diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 2d16aa7..82c92d7 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -18,6 +18,7 @@ #include <commonlib/cbfs.h> #include <program_loading.h> +#include <types.h> /*********************************************** * Perform CBFS operations on the boot device. * @@ -59,8 +60,18 @@ /* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */ int cbfs_prog_stage_load(struct prog *prog); -/* Returns the region device of the currently active CBFS. - Return < 0 on error, 0 on success. */ -int cbfs_boot_region_device(struct region_device *rdev); +struct cbfs_boot_device { + struct region_device rdev; + void *mcache; + size_t mcache_size; +}; + +/* + * Retrieves the currently active CBFS boot device. If |force_ro| is set, will + * always return the read-only CBFS instead (this only makes a difference when + * CONFIG_VBOOT is enabled). May perform certain CBFS initialization tasks. + * Returns NULL on error (e.g. boot device IO error). + */ +const struct cbfs_boot_device *cbfs_get_boot_device(bool force_ro); #endif diff --git a/src/include/memlayout.h b/src/include/memlayout.h index e3aeec6..0d430dee 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -81,6 +81,9 @@ _ = ASSERT(sz >= FMAP_SIZE, \ STR(FMAP does not fit in FMAP_CACHE! (sz < FMAP_SIZE))); +#define CBFS_MCACHE(addr, sz) \ + REGION(cbfs_mcache, addr, sz, 8) + #if ENV_ROMSTAGE_OR_BEFORE #define PRERAM_CBFS_CACHE(addr, size) \ REGION(preram_cbfs_cache, addr, size, 4) \ diff --git a/src/include/symbols.h b/src/include/symbols.h index eec4701..a8e1a82 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -34,6 +34,7 @@ DECLARE_REGION(preram_cbfs_cache) DECLARE_REGION(postram_cbfs_cache) DECLARE_REGION(cbfs_cache) +DECLARE_REGION(cbfs_mcache) DECLARE_REGION(fmap_cache) DECLARE_REGION(payload) diff --git a/src/lib/Kconfig b/src/lib/Kconfig index dd9974a..26bf0be 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -75,3 +75,24 @@ If your platform really doesn't want to use an FMAP cache (e.g. due to space constraints), you can select this to disable warnings and save a bit more code. + +config NO_CBFS_MCACHE + bool + default y + help + Disables the CBFS metadata cache. This means that your platform does + not need to provide a CBFS_MCACHE section in memlayout and can save + the associated CAR/SRAM size. In that case every single CBFS file + lookup must re-read the same CBFS directory entries from flash to find + the respective file. + +config CBFS_MCACHE_RW_PERCENTAGE + int + depends on VBOOT + default 25 if CHROMEOS # Chrome OS stores many L10n files in RO only + default 50 + help + The amount of the CBFS_MCACHE area that's used for the RW CBFS, in + percent from 0 to 100. The remaining area will be used for the RO + CBFS. Default is an even 50/50 split. When VBOOT is disabled, this + will automatically be 0 (meaning the whole MCACHE is used for RO). diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index d6fb99c..40290fd 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -15,6 +15,7 @@ */ #include <assert.h> +#include <cbmem.h> #include <console/console.h> #include <string.h> #include <stdlib.h> @@ -30,30 +31,40 @@ #include <security/vboot/vboot_crtm.h> #include <security/vboot/vboot_common.h> +static cb_err_t cbfs_boot_lookup(const struct cbfs_boot_device *cbd, + const char *name, union cbfs_mdata *mdata, size_t *data_offset) +{ + if (CONFIG(NO_CBFS_MCACHE)) + return cbfs_lookup(&cbd->rdev, name, mdata, data_offset, NULL); + else + return cbfs_mcache_lookup(&cbd->rdev, + cbd->mcache, cbd->mcache_size, + name, mdata, data_offset, NULL); +} + int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) { - struct region_device rdev; - - if (cbfs_boot_region_device(&rdev)) + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + if (!cbd) return -1; union cbfs_mdata mdata; size_t data_offset; - cb_err_t err = cbfs_lookup(&rdev, name, &mdata, &data_offset, NULL); + cb_err_t err = cbfs_boot_lookup(cbd, name, &mdata, &data_offset); if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && err == CB_CBFS_NOT_FOUND) { printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n", name); - if (fmap_locate_area_as_rdev("COREBOOT", &rdev)) + if (!(cbd = cbfs_get_boot_device(true))) return -1; - err = cbfs_lookup(&rdev, name, &mdata, &data_offset, NULL); + err = cbfs_boot_lookup(cbd, name, &mdata, &data_offset); } if (err) return -1; size_t msize = be32toh(mdata.h.offset); - if (rdev_chain(&fh->metadata, &rdev, data_offset - msize, msize) || - rdev_chain(&fh->data, &rdev, data_offset, be32toh(mdata.h.len))) + if (rdev_chain(&fh->metadata, &cbd->rdev, data_offset - msize, msize) || + rdev_chain(&fh->data, &cbd->rdev, data_offset, be32toh(mdata.h.len))) return -1; if (type) { if (!*type) @@ -280,9 +291,66 @@ return 0; } -int cbfs_boot_region_device(struct region_device *rdev) +const struct cbfs_boot_device *cbfs_get_boot_device(bool force_ro) { + static struct cbfs_boot_device ro; + + if (!force_ro) { + const struct cbfs_boot_device *rw = vboot_get_cbfs_boot_device(); + if (rw) + return rw; + } + + if (region_device_sz(&ro.rdev)) + return &ro; + + if (!CONFIG(NO_CBFS_MCACHE)) { + const struct cbmem_entry *entry; + if (cbmem_possibly_online() && + (entry = cbmem_entry_find(CBMEM_ID_CBFS_RO_MCACHE))) { + ro.mcache = cbmem_entry_start(entry); + ro.mcache_size = cbmem_entry_size(entry); + } else if (ENV_ROMSTAGE_OR_BEFORE) { + ro.mcache = _cbfs_mcache; + ro.mcache_size = REGION_SIZE(cbfs_mcache) * + (100 - CONFIG_CBFS_MCACHE_RW_PERCENTAGE) / 100; + } + } + boot_device_init(); - return vboot_locate_cbfs(rdev) && - fmap_locate_area_as_rdev("COREBOOT", rdev); + if (fmap_locate_area_as_rdev("COREBOOT", &ro.rdev)) + return NULL; + + if (!CONFIG(NO_CBFS_MCACHE) && ENV_BOOTBLOCK) { + static bool mcache_done = false; + if (!mcache_done && ro.mcache_size > 0 && cbfs_mcache_build( + &ro.rdev, ro.mcache, ro.mcache_size, NULL)) + return NULL; + mcache_done = true; + } + return &ro; } + +#if !CONFIG(NO_CBFS_MCACHE) +static void mcache_to_cbmem(const struct cbfs_boot_device *cbd, u32 cbmem_id) +{ + if (!cbd) + return; + + size_t real_size = cbfs_mcache_real_size(cbd->mcache, cbd->mcache_size); + void *cbmem_mcache = cbmem_add(cbmem_id, real_size); + if (!cbmem_mcache) { + printk(BIOS_ERR, "ERROR: Cannot allocate CBMEM mcache %#x (%#zx bytes)!\n", + cbmem_id, real_size); + return; + } + memcpy(cbmem_mcache, cbd->mcache, real_size); +} + +static void cbfs_mcache_migrate(int unused) +{ + mcache_to_cbmem(vboot_get_cbfs_boot_device(), CBMEM_ID_CBFS_RW_MCACHE); + mcache_to_cbmem(cbfs_get_boot_device(true), CBMEM_ID_CBFS_RO_MCACHE); +} +ROMSTAGE_CBMEM_INIT_HOOK(cbfs_mcache_migrate) +#endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index e42cb3b..b46ca57 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -243,11 +243,8 @@ { struct lb_boot_media_params *bmp; const struct region_device *boot_dev; - struct region_device cbfs_dev; - - boot_device_init(); - - if (cbfs_boot_region_device(&cbfs_dev)) + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + if (!cbd) return; boot_dev = boot_device_ro(); @@ -258,8 +255,8 @@ bmp->tag = LB_TAG_BOOT_MEDIA_PARAMS; bmp->size = sizeof(*bmp); - bmp->cbfs_offset = region_device_offset(&cbfs_dev); - bmp->cbfs_size = region_device_sz(&cbfs_dev); + bmp->cbfs_offset = region_device_offset(&cbd->rdev); + bmp->cbfs_size = region_device_sz(&cbd->rdev); bmp->boot_media_size = region_device_sz(boot_dev); bmp->fmap_offset = get_fmap_flash_offset(); diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 976c26a..0ebefb6 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -16,6 +16,7 @@ #define __VBOOT_VBOOT_COMMON_H__ #include <commonlib/region.h> +#include <cbfs.h> #include <stdint.h> #include <vboot_api.h> #include <vboot_struct.h> @@ -71,7 +72,7 @@ int vboot_recovery_mode_memory_retrain(void); int vboot_can_enable_udc(void); void vboot_run_logic(void); -int vboot_locate_cbfs(struct region_device *rdev); +const struct cbfs_boot_device *vboot_get_cbfs_boot_device(void); #else /* !CONFIG_VBOOT */ static inline int vboot_developer_mode_enabled(void) { return 0; } static inline int vboot_recovery_mode_enabled(void) { return 0; } @@ -79,7 +80,7 @@ /* If VBOOT is not enabled, we are okay enabling USB device controller (UDC). */ static inline int vboot_can_enable_udc(void) { return 1; } static inline void vboot_run_logic(void) {} -static inline int vboot_locate_cbfs(struct region_device *rdev) { return -1; } +const struct cbfs_boot_device *vboot_get_cbfs_boot_device(void) { return NULL; } #endif void vboot_save_nvdata_only(struct vb2_context *ctx); diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 7e63775..a8db7a3 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -13,7 +13,10 @@ * GNU General Public License for more details. */ +#include <boot_device.h> #include <cbfs.h> +#include <cbmem.h> +#include <commonlib/bsd/cbfs_private.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> #include <rmodule.h> @@ -34,12 +37,26 @@ int vboot_executed; +static void build_rw_mcache(void) +{ + if (CONFIG(NO_CBFS_MCACHE)) + return; + + if (vboot_get_context()->flags & VB2_CONTEXT_RECOVERY_MODE) + return; /* No RW mcache if we're staying in RO. */ + + const struct cbfs_boot_device *cbd = vboot_get_cbfs_boot_device(); + if (cbfs_mcache_build(&cbd->rdev, cbd->mcache, cbd->mcache_size, NULL)) + die("Failed to build RW mcache."); /* TODO: -> recovery? */ +} + void vboot_run_logic(void) { if (verification_should_run()) { /* Note: this path is not used for VBOOT_RETURN_FROM_VERSTAGE */ verstage_main(); vboot_executed = 1; + build_rw_mcache(); } else if (verstage_should_load()) { struct cbfsf file; struct prog verstage = @@ -67,21 +84,40 @@ return; vboot_executed = 1; + build_rw_mcache(); } } -int vboot_locate_cbfs(struct region_device *rdev) +const struct cbfs_boot_device *vboot_get_cbfs_boot_device(void) { - struct vb2_context *ctx; - /* Don't honor vboot results until the vboot logic has run. */ if (!vboot_logic_executed()) - return -1; + return NULL; - ctx = vboot_get_context(); + static struct cbfs_boot_device cbd; + if (region_device_sz(&cbd.rdev)) + return &cbd; + struct vb2_context *ctx = vboot_get_context(); if (ctx->flags & VB2_CONTEXT_RECOVERY_MODE) - return -1; + return NULL; - return vboot_locate_firmware(ctx, rdev); + boot_device_init(); + if (vboot_locate_firmware(ctx, &cbd.rdev)) + return NULL; + + if (!CONFIG(NO_CBFS_MCACHE)) { + const struct cbmem_entry *entry; + if (cbmem_possibly_online() && + (entry = cbmem_entry_find(CBMEM_ID_CBFS_RW_MCACHE))) { + cbd.mcache = cbmem_entry_start(entry); + cbd.mcache_size = cbmem_entry_size(entry); + } else if (ENV_ROMSTAGE_OR_BEFORE) { + cbd.mcache_size = REGION_SIZE(cbfs_mcache) * + CONFIG_CBFS_MCACHE_RW_PERCENTAGE / 100; + cbd.mcache = _ecbfs_mcache - cbd.mcache_size; + } + } + + return &cbd; } -- To view, visit https://review.coreboot.org/c/coreboot/+/38423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b1084bfdad1c6ab0ee1b143ed8dd796827f4c65 Gerrit-Change-Number: 38423 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 60

Change in coreboot[master]: mb/google/volteer/var/elemi: enable Genesys Logic GL9763E
by Chen Wisley (Code Review) 20 Nov '20

20 Nov '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47040 ) Change subject: mb/google/volteer/var/elemi: enable Genesys Logic GL9763E ...................................................................... mb/google/volteer/var/elemi: enable Genesys Logic GL9763E Enable Genesys GL9763E as pci to emmc bridge. BUG=b:171467336 TEST=emerge-volteer coreboot Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> Change-Id: I858c12151df5b6fc19132869317edfa1b090335d --- M src/mainboard/google/volteer/Kconfig.name M src/mainboard/google/volteer/variants/elemi/overridetree.cb 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/47040/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 908c55b..851f563 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -73,3 +73,4 @@ select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU select USE_CAR_NEM_ENHANCED_V2 + select DRIVERS_GENESYSLOGIC_GL9763E diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 2139ad7..5f3bf86 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -6,6 +6,13 @@ register "IomTypeCPortPadCfg[0]" = "0x090E000A" register "IomTypeCPortPadCfg[1]" = "0x090E000D" + # Enable EMMC PCIE 5 using clk 5 + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpHotPlug[4]" = "1" + register "PcieClkSrcUsage[5]" = "4" + register "PcieClkSrcClkReq[5]" = "4" + #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ @@ -109,6 +116,7 @@ device generic 0 on end end end + device ref pcie_rp5 on end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. -- To view, visit https://review.coreboot.org/c/coreboot/+/47040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I858c12151df5b6fc19132869317edfa1b090335d Gerrit-Change-Number: 47040 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: mb/asus/f2a85-m_pro: Enable PCIe bridge 00:15.2 in AGESA
by Paul Menzel (Code Review) 20 Nov '20

20 Nov '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46527 ) Change subject: mb/asus/f2a85-m_pro: Enable PCIe bridge 00:15.2 in AGESA ...................................................................... mb/asus/f2a85-m_pro: Enable PCIe bridge 00:15.2 in AGESA Currently, the PCIe bridge 00:15.2 is not detected by coreboot, causing the connected network device also to be missing. With the vendor firmware 6601, `lspci -t` outputs: -[0000:00]-+-00.0 +-00.2 +-01.0 +-01.1 +-10.0 +-10.1 +-11.0 +-12.0 +-12.2 +-13.0 +-13.2 +-14.0 +-14.2 +-14.3 +-14.4-[01]-- +-15.0-[02]-- +-15.1-[03]----00.0 +-15.2-[04]----00.0 +-18.0 +-18.1 +-18.2 +-18.3 +-18.4 \-18.5 The AMD Fusion Controller Hub (FCH) has four PCIe General Purpose Ports (GPP), which can be exposed as one to four PCIe devices. Configure AGESA to expose the third, missing port, which exposes the PCIe bridge to coreboot. When coreboot tries to configure(?) the PCIe bridge it currently hangs the system. Sometimes it’s 00:15.1 and sometimes 00:15.2 – which might be dependent on the HUDSON_LEGACY_FREE setting. `CONFIG_HUDSON_LEGACY_FREE=y`: PCI: 00:14.4 bridge ctrl <- 0013 PCI: 00:14.4 cmd <- 00 PCI: 00:14.5 cmd <- 02 PCI: 00:15.0 bridge ctrl <- 0013 PCI: 00:15.0 cmd <- 00 PCI: 00:15.1 bridge ctrl <- 0013 PCI: 00:15.1 cmd <- 06 PCI: 00:15.2 bridge ctrl <- 0013 PCI: 00:15.2 cmd <- 07 Tagging the bridge as `hidden` in the devicetree, the hang does not occur, the payload is loaded, and Linux sets up the bridge and configures the network device. From coreboot log: PCI: 00:15.2 [0000/0000] hidden PCI: 00:15.0 scanning... do_pci_scan_bridge for PCI: 00:15.0 PCI: pci_scan_bus for bus 02 scan_bus: bus PCI: 00:15.0 finished in 2 msecs PCI: 00:15.1 scanning... do_pci_scan_bridge for PCI: 00:15.1 PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [1b21/1042] enabled scan_bus: bus PCI: 00:15.1 finished in 4 msecs PCI: 00:15.2 scanning... scan_static_bus for PCI: 00:15.2 scan_static_bus for PCI: 00:15.2 done scan_bus: bus PCI: 00:15.2 finished in 3 msecs scan_bus: bus DOMAIN: 0000 finished in 139 msecs scan_static_bus for Root Device done scan_bus: bus Root Device finished in 166 msecs done BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 293 ms found VGA at PCI: 00:01.0 Setting up VGA for PCI: 00:01.0 PCI: 00:14.4 PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:14.5 PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:15.0 PCI: 00:15.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:15.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:15.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:15.1 child on link 0 PCI: 03:00.0 PCI: 00:15.1 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:15.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:15.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10 PCI: 00:15.2 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:14.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:15.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:15.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:15.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:15.1 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:01.0 14 * [0x0 - 0xff] io PCI: 00:11.0 20 * [0x400 - 0x40f] io PCI: 00:11.0 10 * [0x410 - 0x417] io PCI: 00:11.0 18 * [0x418 - 0x41f] io PCI: 00:11.0 14 * [0x420 - 0x423] io PCI: 00:11.0 1c * [0x424 - 0x427] io PNP: 002e.b 62 * [0x428 - 0x429] io DOMAIN: 0000 io: base: 42a size: 42a align: 8 gran: 0 limit: fff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffffffff PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:14.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:15.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:15.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:15.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:15.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:15.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:15.1 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:15.1 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:00.0 10 * [0x0 - 0x7fff] mem PCI: 00:15.1 mem: base: 8000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 10 * [0x0 - 0xfffffff] prefmem PCI: 00:15.1 20 * [0x10000000 - 0x100fffff] mem PCI: 00:00.2 44 * [0x10100000 - 0x1017ffff] mem PCI: 00:01.0 18 * [0x10180000 - 0x101bffff] mem PCI: 00:01.1 10 * [0x101c0000 - 0x101c3fff] mem PCI: 00:14.2 10 * [0x101c4000 - 0x101c7fff] mem PCI: 00:10.0 10 * [0x101c8000 - 0x101c9fff] mem PCI: 00:10.1 10 * [0x101ca000 - 0x101cbfff] mem PCI: 00:12.0 10 * [0x101cc000 - 0x101ccfff] mem PCI: 00:13.0 10 * [0x101cd000 - 0x101cdfff] mem PCI: 00:14.5 10 * [0x101ce000 - 0x101cefff] mem PCI: 00:11.0 24 * [0x101cf000 - 0x101cf7ff] mem PCI: 00:12.2 10 * [0x101d0000 - 0x101d00ff] mem PCI: 00:13.2 10 * [0x101d1000 - 0x101d10ff] mem DOMAIN: 0000 mem: base: 101d1100 size: 101d1100 align: 28 gran: 0 limit: ffffffff done Linux (`CONFIG_PCI_DIRECT=y`): [ 3.644703] pci 0000:00:14.0: [1022:780b] type 00 class 0x0c0500 [ 3.650744] pci 0000:00:14.2: [1022:780d] type 00 class 0x040300 [ 3.656643] pci 0000:00:14.2: reg 0x10: [mem 0xf01c4000-0xf01c7fff 64bit] [ 3.663678] pci 0000:00:14.2: PME# supported from D0 D3hot D3cold [ 3.669627] pci 0000:00:14.2: pme_poll = true [ 3.674627] pci 0000:00:14.2: after device_set_wakeup_capable() [ 3.680630] pci 0000:00:14.2: after pci_pme_active() [ 3.685695] pci 0000:00:14.3: [1022:780e] type 00 class 0x060100 [ 3.691743] pci 0000:00:14.4: [1022:780f] type 01 class 0x060401 [ 3.697718] pci 0000:00:14.5: [1022:7809] type 00 class 0x0c0310 [ 3.703639] pci 0000:00:14.5: reg 0x10: [mem 0xf01ce000-0xf01cefff] [ 3.709746] pci 0000:00:15.0: [1022:43a0] type 01 class 0x060400 [ 3.715653] pci 0000:00:15.0: enabling Extended Tags [ 3.720663] pci 0000:00:15.0: supports D1 D2 [ 3.724715] pci 0000:00:15.1: [1022:43a1] type 01 class 0x060400 [ 3.731657] pci 0000:00:15.1: enabling Extended Tags [ 3.736664] pci 0000:00:15.1: supports D1 D2 [ 3.740718] pci 0000:00:15.2: [1022:43a2] type 01 class 0x060400 [ 3.746654] pci 0000:00:15.2: enabling Extended Tags [ 3.751663] pci 0000:00:15.2: supports D1 D2 [ 3.755694] pci 0000:00:18.0: calling quirk_mmio_always_on+0x0/0x10 @ 1 […] [ 3.872695] pci_bus 0000:01: extended config space not accessible [ 3.878676] pci 0000:00:14.4: PCI bridge to [bus 01] (subtractive decode) [ 3.885630] pci 0000:00:14.4: bridge window [io 0x0000-0xffff] [ 3.891632] pci 0000:00:14.4: bridge window [io 0x0000-0x0cf7 window] (subtractive decode) [ 3.900628] pci 0000:00:14.4: bridge window [io 0x0d00-0xffff window] (subtractive decode) [ 3.908628] pci 0000:00:14.4: bridge window [mem 0x000a0000-0x000bffff] (subtractive decode) [ 3.917628] pci 0000:00:14.4: bridge window [mem 0x000c0000-0x000dffff] (subtractive decode) [ 3.925628] pci 0000:00:14.4: bridge window [mem 0x80000000-0xffffffff] (subtractive decode) [ 3.934660] pci 0000:00:15.0: PCI bridge to [bus 02] [ 3.939631] pci 0000:00:15.0: bridge window [io 0x0000-0xffffffff] [ 3.945694] pci 0000:03:00.0: [1b21:1042] type 00 class 0x0c0330 [ 3.951664] pci 0000:03:00.0: reg 0x10: [mem 0xf0000000-0xf0007fff 64bit] [ 3.958796] pci 0000:03:00.0: PME# supported from D3hot D3cold [ 3.964628] pci 0000:03:00.0: pme_poll = true [ 3.969627] pci 0000:03:00.0: after device_set_wakeup_capable() [ 3.975631] pci 0000:03:00.0: after pci_pme_active() [ 3.980654] pci 0000:03:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s PCIe x1 link at 0000:00:15.1 (capable of 4.000 Gb/s with 5.0 GT/s PCIe x1 link) [ 3.997679] pci 0000:00:15.1: PCI bridge to [bus 03] [ 4.002634] pci 0000:00:15.1: bridge window [io 0x0000-0xffffffff] [ 4.008630] pci 0000:00:15.1: bridge window [mem 0xf0000000-0xf00fffff] [ 4.015635] pci 0000:00:15.2: bridge configuration invalid ([bus 00-00]), reconfiguring [ 4.023724] pci 0000:04:00.0: [10ec:8168] type 00 class 0x020000 [ 4.029644] pci 0000:04:00.0: reg 0x10: [io 0x0000-0x00ff] [ 4.034647] pci 0000:04:00.0: reg 0x18: [mem 0x00000000-0x00000fff 64bit pref] [ 4.042640] pci 0000:04:00.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref] [ 4.049725] pci 0000:04:00.0: supports D1 D2 [ 4.053628] pci 0000:04:00.0: PME# supported from D0 D1 D2 D3hot D3cold [ 4.060629] pci 0000:04:00.0: pme_poll = true [ 4.064628] pci 0000:04:00.0: after device_set_wakeup_capable() [ 4.070630] pci 0000:04:00.0: after pci_pme_active() [ 4.078681] pci 0000:00:15.2: PCI bridge to [bus 04-ff] [ 4.083634] pci 0000:00:15.2: bridge window [io 0x0000-0x0fff] [ 4.089630] pci 0000:00:15.2: bridge window [mem 0x00000000-0x000fffff] [ 4.096631] pci 0000:00:15.2: bridge window [mem 0x00000000-0x000fffff 64bit pref] [ 4.103629] pci_bus 0000:04: busn_res: [bus 04-ff] end is updated to 04 [ 4.110631] pci_bus 0000:00: on NUMA node 0 [ 4.114828] ACPI: PCI Interrupt Link [INTA] (IRQs 3 4 5 7 10 11 12 15) *0 [ 4.121659] ACPI: PCI Interrupt Link [INTB] (IRQs 3 4 5 7 10 11 12 15) *0 [ 4.128658] ACPI: PCI Interrupt Link [INTC] (IRQs 3 4 5 7 10 11 12 15) *0 [ 4.135657] ACPI: PCI Interrupt Link [INTD] (IRQs 3 4 5 7 10 11 12 15) *0 [ 4.142658] ACPI: PCI Interrupt Link [INTE] (IRQs 3 4 5 7 10 11 12 15) *0 [ 4.148656] ACPI: PCI Interrupt Link [INTF] (IRQs 9) *0 [ 4.154657] ACPI: PCI Interrupt Link [INTG] (IRQs 3 4 5 7 10 11 12 15) *0 [ 4.161657] ACPI: PCI Interrupt Link [INTH] (IRQs 3 4 5 7 10 11 12 15) *0 [ 4.167719] initcall acpi_init+0x0/0x2bd returned 0 after 969726 usecs […] [ 5.150814] calling pcibios_assign_resources+0x0/0x91 @ 1 [ 5.156316] pci 0000:00:15.2: BAR 9: assigned [mem 0x80000000-0x800fffff 64bit pref] [ 5.164060] pci 0000:00:15.2: BAR 7: assigned [io 0x1000-0x1fff] [ 5.170149] pci 0000:00:11.0: BAR 4: assigned [io 0x2000-0x200f] [ 5.176245] pci 0000:00:11.0: BAR 0: assigned [io 0x2010-0x2017] [ 5.182337] pci 0000:00:11.0: BAR 2: assigned [io 0x2018-0x201f] [ 5.188431] pci 0000:00:11.0: BAR 1: assigned [io 0x2020-0x2023] [ 5.194524] pci 0000:00:11.0: BAR 3: assigned [io 0x2024-0x2027] [ 5.200619] pci 0000:00:14.4: PCI bridge to [bus 01] [ 5.205590] pci 0000:00:15.0: PCI bridge to [bus 02] [ 5.210561] pci 0000:00:15.1: PCI bridge to [bus 03] [ 5.215525] pci 0000:00:15.1: bridge window [mem 0xf0000000-0xf00fffff] [ 5.222313] pci 0000:04:00.0: BAR 4: assigned [mem 0x80000000-0x80003fff 64bit pref] [ 5.230062] pci 0000:04:00.0: BAR 2: assigned [mem 0x80004000-0x80004fff 64bit pref] [ 5.237810] pci 0000:04:00.0: BAR 0: assigned [io 0x1000-0x10ff] [ 5.243903] pci 0000:00:15.2: PCI bridge to [bus 04] [ 5.248866] pci 0000:00:15.2: bridge window [io 0x1000-0x1fff] [ 5.254964] pci 0000:00:15.2: bridge window [mem 0x80000000-0x800fffff 64bit pref] […] [ 6.874003] calling pcie_portdrv_init+0x0/0x34 @ 1 [ 6.878886] tsc: Refined TSC clocksource calibration: 3900.222 MHz [ 6.885069] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x7070574e4ad, max_idle_ns: 881590678092 ns [ 6.895201] pcieport 0000:00:15.0: PME: Signaling with IRQ 24 [ 6.900958] clocksource: Switched to clocksource tsc [ 6.901197] pcieport 0000:00:15.1: PME: Signaling with IRQ 25 [ 6.911718] pcieport 0000:00:15.2: enabling device (0000 -> 0003) [ 6.917894] pcieport 0000:00:15.2: PME: Signaling with IRQ 26 [ 6.923697] initcall pcie_portdrv_init+0x0/0x34 returned 0 after 43763 usecs […] [ 7.713476] calling rtl8139_init_module+0x0/0x16 @ 1 [ 7.718532] initcall rtl8139_init_module+0x0/0x16 returned 0 after 9 usecs [ 7.725403] calling rtl8169_pci_driver_init+0x0/0x16 @ 1 [ 7.730818] r8169 0000:04:00.0: enabling device (0000 -> 0003) [ 7.737139] kworker/u4:3 (74) used greatest stack depth: 7064 bytes left [ 7.737417] libphy: r8169: probed [ 7.747418] r8169 0000:04:00.0 eth0: RTL8168f/8111f, 08:60:6e:74:7a:51, XID 480, IRQ 27 [ 7.755419] r8169 0000:04:00.0 eth0: jumbo features [frames: 9194 bytes, tx checksumming: ko] [ 7.763947] initcall rtl8169_pci_driver_init+0x0/0x16 returned 0 after 32368 usecs Change-Id: Ia1d60a212b0d249c7d8b3f8ec16baf5e93c985da Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/mainboard/asus/f2a85-m/buildOpts.c M src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/46527/1 diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 6b57711..b1d714d 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -51,6 +51,9 @@ #define BLDCFG_FCH_GPP_LINK_CONFIG PortA1B1C1D1 #define BLDCFG_FCH_GPP_PORT0_PRESENT TRUE #define BLDCFG_FCH_GPP_PORT1_PRESENT TRUE +#if CONFIG(BOARD_ASUS_F2A85_M_PRO) +#define BLDCFG_FCH_GPP_PORT2_PRESENT TRUE +#endif /* CONFIG_BOARD_ASUS_F2A85_M_PRO */ GPIO_CONTROL f2a85_m_gpio[] = { {-1} diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb index 4e124f2..3349f56 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb @@ -111,7 +111,7 @@ device pci 14.7 off end # Not present with BIOS ([AMD] FCH SD Flash Controller [1022:7806]) device pci 15.0 on end # PCI bridge device pci 15.1 on end # PCI bridge - device pci 15.2 on end # PCI bridge # Only present with the original boot firmware + device pci 15.2 hidden end # PCI bridge end #chip southbridge/amd/hudson device pci 18.0 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/46527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1d60a212b0d249c7d8b3f8ec16baf5e93c985da Gerrit-Change-Number: 46527 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

5 26

Change in coreboot[master]: Makefile.inc: Add CARRIER_DIR to component discovery
by Maxim Polyakov (Code Review) 20 Nov '20

20 Nov '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42609 ) Change subject: Makefile.inc: Add CARRIER_DIR to component discovery ...................................................................... Makefile.inc: Add CARRIER_DIR to component discovery The configuration of the COMe module contains an additional carriers directory, which contains the source codes for configuration for the different carrierboards into which this module is plugged. Let's take this into account in the build system to use CARRIER_DIR to select the type of board in the local Makefile.inc, as it has done for VARIANT_DIR. Used to build an image for the Kontron COMe-mAL10 module together with the Kontron Ref.Carrier-i T10 TNI. Change-Id: Ic6b2f8994b1293ae6f5bda8c9cc95128ba0abf7a Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/42609/1 diff --git a/Makefile.inc b/Makefile.inc index 86335d9..0f9d635 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -34,6 +34,7 @@ # Basic component discovery MAINBOARDDIR=$(call strip_quotes,$(CONFIG_MAINBOARD_DIR)) VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) +CARRIER_DIR:=$(call strip_quotes,$(CONFIG_CARRIER_DIR)) COREBOOT_EXPORTS += MAINBOARDDIR VARIANT_DIR ## Final build results, which CBFSTOOL uses to create the final -- To view, visit https://review.coreboot.org/c/coreboot/+/42609 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6b2f8994b1293ae6f5bda8c9cc95128ba0abf7a Gerrit-Change-Number: 42609 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 18

Change in coreboot[master]: soc/mediatek/mt8192: Add auxadc driver
by Yidi Lin (Code Review) 20 Nov '20

20 Nov '20

Hello Po Xu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46390 to review the following change. Change subject: soc/mediatek/mt8192: Add auxadc driver ...................................................................... soc/mediatek/mt8192: Add auxadc driver Add MT8192 auxadc driver. Signed-off-by: Po Xu <jg_poxu(a)mediatek.com> Change-Id: Id4553e99c3578fa40e28b19a6e010b52650ba41e --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/auxadc.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/auxadc.h A src/soc/mediatek/mt8192/include/soc/efuse.h 5 files changed, 116 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/46390/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index d417ae2..9bb9cfd 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8192),y) +bootblock-y += auxadc.c bootblock-y += bootblock.c bootblock-y += flash_controller.c bootblock-y += ../common/gpio.c gpio.c @@ -13,12 +14,14 @@ bootblock-y += mt6315.c bootblock-y += mt6359p.c +verstage-y += auxadc.c verstage-y += flash_controller.c verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c verstage-y += ../common/uart.c +romstage-y += auxadc.c romstage-y += ../common/cbmem.c romstage-y += emi.c romstage-y += flash_controller.c @@ -29,6 +32,7 @@ romstage-y += ../common/timer.c romstage-y += ../common/uart.c +ramstage-y += auxadc.c ramstage-y += flash_controller.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += emi.c diff --git a/src/soc/mediatek/mt8192/auxadc.c b/src/soc/mediatek/mt8192/auxadc.c new file mode 100755 index 0000000..3f9238b --- /dev/null +++ b/src/soc/mediatek/mt8192/auxadc.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <assert.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <soc/auxadc.h> +#include <soc/efuse.h> +#include <soc/infracfg.h> +#include <timer.h> + +static struct mtk_auxadc_regs *const mtk_auxadc = (void *)AUXADC_BASE; + +#define ADC_GE_A_SHIFT 10 +#define ADC_GE_A_MASK (0x3ff << ADC_GE_A_SHIFT) +#define ADC_OE_A_SHIFT 0 +#define ADC_OE_A_MASK (0x3ff << ADC_OE_A_SHIFT) +#define ADC_CALI_EN_A_SHIFT 20 +#define ADC_CALI_EN_A_MASK (0x1 << ADC_CALI_EN_A_SHIFT) + +static int cali_oe; +static int cali_ge; +static int calibrated = 0; +static void mt_auxadc_update_cali(void) +{ + uint32_t cali_reg; + int cali_ge_a; + int cali_oe_a; + + cali_reg = read32(&mtk_efuse->adc_cali_reg); + + if ((cali_reg & ADC_CALI_EN_A_MASK) != 0) { + cali_oe_a = (cali_reg & ADC_OE_A_MASK) >> ADC_OE_A_SHIFT; + cali_ge_a = (cali_reg & ADC_GE_A_MASK) >> ADC_GE_A_SHIFT; + cali_ge = cali_ge_a - 512; + cali_oe = cali_oe_a - 512; + } +} +static uint32_t auxadc_get_rawdata(int channel) +{ + setbits32(&mt8192_infracfg->module_sw_cg_1_clr, 1 << 10); + assert(wait_ms(300, !(read32(&mtk_auxadc->con2) & 0x1))); + + clrbits32(&mtk_auxadc->con1, 1 << channel); + assert(wait_ms(300, !(read32(&mtk_auxadc->data[channel]) & (1 << 12)))); + + setbits32(&mtk_auxadc->con1, 1 << channel); + udelay(25); + assert(wait_ms(300, read32(&mtk_auxadc->data[channel]) & (1 << 12))); + + uint32_t value = read32(&mtk_auxadc->data[channel]) & 0x0FFF; + + setbits32(&mt8192_infracfg->module_sw_cg_1_set, 1 << 10); + + return value; +} + +int auxadc_get_voltage(unsigned int channel) +{ + uint32_t raw_value; + assert(channel < 16); + + if (!calibrated) { + mt_auxadc_update_cali(); + calibrated = 1; + } + + /* 1.5V in 4096 steps */ + raw_value = auxadc_get_rawdata(channel); + raw_value = raw_value - cali_oe; + return (int)((int64_t)raw_value * 1500000 / (4096 + cali_ge)); +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h old mode 100644 new mode 100755 index e9cb788..9760c88 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -26,6 +26,7 @@ PMIF_SPMI_BASE = IO_PHYS + 0x00027000, PMICSPI_MST_BASE = IO_PHYS + 0x00028000, SPMI_MST_BASE = IO_PHYS + 0x00029000, + AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, SPI1_BASE = IO_PHYS + 0x01010000, @@ -37,6 +38,7 @@ SPI7_BASE = IO_PHYS + 0x0101E000, SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00, SFLASH_REG_BASE = IO_PHYS + 0x01234000, + EFUSEC_BASE = IO_PHYS + 0x01C10000, IOCFG_RM_BASE = IO_PHYS + 0x01C20000, IOCFG_BM_BASE = IO_PHYS + 0x01D10000, IOCFG_BL_BASE = IO_PHYS + 0x01D30000, diff --git a/src/soc/mediatek/mt8192/include/soc/auxadc.h b/src/soc/mediatek/mt8192/include/soc/auxadc.h new file mode 100755 index 0000000..18350d6 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/auxadc.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MTK_ADC_H +#define _MTK_ADC_H + +#include <stdint.h> + +typedef struct mtk_auxadc_regs { + uint32_t con0; + uint32_t con1; + uint32_t con1_set; + uint32_t con1_clr; + uint32_t con2; + uint32_t data[16]; + uint32_t reserved[16]; + uint32_t misc; +} mtk_auxadc_regs; + +/* Return voltage in uVolt */ +int auxadc_get_voltage(unsigned int channel); +#endif diff --git a/src/soc/mediatek/mt8192/include/soc/efuse.h b/src/soc/mediatek/mt8192/include/soc/efuse.h new file mode 100755 index 0000000..f0f3405 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/efuse.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MTK_EFUSE_H +#define _MTK_EFUSE_H + +#include <soc/addressmap.h> +#include <types.h> + +struct efuse_regs { + uint32_t rserved[109]; + uint32_t adc_cali_reg; +}; + +check_member(efuse_regs, adc_cali_reg, 0x1b4); +static struct efuse_regs *const mtk_efuse = (void *)EFUSEC_BASE; + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4553e99c3578fa40e28b19a6e010b52650ba41e Gerrit-Change-Number: 46390 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Po Xu <jg_poxu(a)mediatek.com> Gerrit-MessageType: newchange

7 40

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020