coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add txt_get_chipset_dpr callback
by Arthur Heymans (Code Review) 20 Nov '20

20 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46555 ) Change subject: soc/intel/xeon_sp/cpx: Add txt_get_chipset_dpr callback ...................................................................... soc/intel/xeon_sp/cpx: Add txt_get_chipset_dpr callback Change-Id: Id824324325d05b52fb2b9ced04fd3539cc37bd55 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h 2 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/46555/1 diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 11fe44b..c017d79 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -14,7 +14,9 @@ #include <soc/ramstage.h> #include <soc/pm.h> #include <soc/soc_util.h> +#include <soc/pci_devs.h> #include <stdlib.h> +#include <security/intel/txt/txt_platform.h> /* C620 IOAPIC has 120 redirection entries */ #define C620_IOAPIC_REDIR_ENTRIES 120 @@ -558,6 +560,38 @@ DEV_FUNC_EXIT(dev); } +union dpr_register txt_get_chipset_dpr(void) +{ + struct iiostack_resource info; + union dpr_register dpr; + const pci_devfn_t VTD = PCI_DEVFN(VTD_DEV, VTD_FUNC); + const struct device *dev = pcidev_path_on_root(VTD); + + if (dev == NULL) + die("Unable to find VTD PCI DEV"); + + dpr.raw = pci_read_config32(dev, VTD_LTDPR); + + get_iiostack_info(&info); + for (int s = 1; s < info.no_of_stacks; s++) { + uint8_t bus = info.res[s].BusBase; + dev = pcidev_path_on_bus(bus, VTD); + + if (dev == NULL) + die("Unable to find VTD PCI DEV"); + + union dpr_register test_dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; + if (memcmp(&dpr, &test_dpr, sizeof(dpr))) { + printk(BIOS_ERR, "LTDPR not the same on all IIO's"); + /* TODO: Have the caller check this */ + dpr.raw = 0; + return dpr; + } + } + + return dpr; +} + struct pci_operations soc_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 965bb66..4d04105 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -70,6 +70,7 @@ #define VTD_CAP_LOW 0x08 #define VTD_CAP_HIGH 0x0C #define VTD_EXT_CAP_HIGH 0x14 +#define VTD_LTDPR 0x290 /* CPU Devices */ #define CBDMA_DEV_NUM 0x04 -- To view, visit https://review.coreboot.org/c/coreboot/+/46555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id824324325d05b52fb2b9ced04fd3539cc37bd55 Gerrit-Change-Number: 46555 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 20

Change in coreboot[master]: soc/intel/tigerlake: Expose UPD to disable Precision Time Management
by Duncan Laurie (Code Review) 20 Nov '20

20 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46856 ) Change subject: soc/intel/tigerlake: Expose UPD to disable Precision Time Management ...................................................................... soc/intel/tigerlake: Expose UPD to disable Precision Time Management Expose a config option that allows disabling the FSP UPD which controls Precision Time Management for a particular PCIe root port. Since this is enabled by default the option is inverted to allow disabling for a particular port while not affecting others. BUG=b:160996445 TEST=boot on volteer with PTM disabled for the NVMe root port Change-Id: Icb51b256eb581d942b2d30fcabfae52fa90e48d4 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/46856/1 diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f752b5f..fcd6b0c 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -242,6 +242,9 @@ /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; + /* Disable PCIe Precision Time Measurement for Root Ports (enabled by default) */ + uint8_t PciePtmDisable[CONFIG_MAX_ROOT_PORTS]; + /* PCIe RP L1 substate */ enum L1_substates_control { L1_SS_FSP_DEFAULT, diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 887241b..1520cfe 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -186,6 +186,7 @@ params->PcieRpAdvancedErrorReporting[i] = config->PcieRpAdvancedErrorReporting[i]; params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; + params->PciePtm[i] = !config->PciePtmDisable[i]; } /* Enable ClkReqDetect for enabled port */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb51b256eb581d942b2d30fcabfae52fa90e48d4 Gerrit-Change-Number: 46856 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: mb/google/volteer/variants: Enable RTD3 for the NVMe device
by Duncan Laurie (Code Review) 20 Nov '20

20 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46262 ) Change subject: mb/google/volteer/variants: Enable RTD3 for the NVMe device ...................................................................... mb/google/volteer/variants: Enable RTD3 for the NVMe device Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9. BUG=b:160996445 TEST=TODO: only tested on volteer, needs test on real hardware Change-Id: I6ebf813c6c3364fec2e489a9742f04452be92c45 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/volteer/variants/delbin/gpio.c M src/mainboard/google/volteer/variants/delbin/overridetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/voxel/overridetree.cb 4 files changed, 26 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46262/1 diff --git a/src/mainboard/google/volteer/variants/delbin/gpio.c b/src/mainboard/google/volteer/variants/delbin/gpio.c index 5748bb3..bebf38f 100644 --- a/src/mainboard/google/volteer/variants/delbin/gpio.c +++ b/src/mainboard/google/volteer/variants/delbin/gpio.c @@ -27,8 +27,8 @@ /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), - /* B2 : VRALERT# ==> NC */ - PAD_NC(GPP_B2, NONE), + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index 21b1f07..ef52517 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -59,6 +59,14 @@ device i2c 15 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "clock_pin" = "0" + device pci 00.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 1ccdb87..7f806ea 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -126,6 +126,14 @@ device i2c 15 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "clock_pin" = "0" + device pci 00.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 8ce6875..7528a4f 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -182,6 +182,14 @@ device i2c 15 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "clock_pin" = "0" + device pci 00.0 on end + end + end device ref pmc hidden # The pmc_mux chip driver is a placeholder for the # PMC.MUX device in the ACPI hierarchy. -- To view, visit https://review.coreboot.org/c/coreboot/+/46262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ebf813c6c3364fec2e489a9742f04452be92c45 Gerrit-Change-Number: 46262 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox
by Duncan Laurie (Code Review) 20 Nov '20

20 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46261 ) Change subject: soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox ...................................................................... soc/intel/tigerlake: Enable RTD3 driver and IPC mailbox This SOC overrides the common PMC device and instantiates the PMC device in the SSDT. It needs to call the common PMC function to provide the IPC mailbox method. The common PCIe RTD3 driver can also be enabled which will allow mainboards to enable Runtime D3 power control for PCIe devices. BUG=b:160996445 TEST=boot on volteer with this driver enabled for the NVMe device in the devicetree and disassemble the SSDT to ensure that the RTD3 code is present. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: Ifa54ec3b8cebcc2752916cc4f8616fcb6fd2fecc --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/pmc.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46261/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 4df2e85..0be2225 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -45,6 +45,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index f2f8a06..a7705de 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -119,6 +119,9 @@ acpigen_write_mem32fixed(1, PCH_PWRM_BASE_ADDRESS, PCH_PWRM_BASE_SIZE); acpigen_write_resourcetemplate_footer(); + /* Define IPC Write Method */ + pmc_acpi_fill_ssdt_ipc_write_method(); + acpigen_pop_len(); /* PMC Device */ acpigen_pop_len(); /* Scope */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa54ec3b8cebcc2752916cc4f8616fcb6fd2fecc Gerrit-Change-Number: 46261 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: soc/intel/common: Add PCIe Runtime D3 driver for ACPI
by Duncan Laurie (Code Review) 20 Nov '20

20 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46260 ) Change subject: soc/intel/common: Add PCIe Runtime D3 driver for ACPI ...................................................................... soc/intel/common: Add PCIe Runtime D3 driver for ACPI This driver is for devices attached to a PCIe root port that support Runtime D3. It creates the necessary PowerResource in the root port to provide _ON/_OFF methods for which will turn off power and clocks to the device when it is in the D3cold state. The mainboard declares the driver in devicetree and provides the GPIOs that control power/reset for the device attached to the root port and the SRCCLK pin used for the PMC IPC mailbox to enable/disable the clock. An additional device property is created for storage devices if it matches the PCI storage class which is used to indicate that the storage device should use D3 for power savings. BUG=b:160996445 TEST=boot on volteer device with this driver enabled in the devicetree and disassemble the SSDT to ensure this code exists. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I13e59c996b4f5e4c2657694bda9fad869b64ffde --- M src/soc/intel/common/block/pcie/Kconfig M src/soc/intel/common/block/pcie/Makefile.inc A src/soc/intel/common/block/pcie/rtd3/Kconfig A src/soc/intel/common/block/pcie/rtd3/Makefile.inc A src/soc/intel/common/block/pcie/rtd3/chip.h A src/soc/intel/common/block/pcie/rtd3/rtd3.c 6 files changed, 306 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/46260/1 diff --git a/src/soc/intel/common/block/pcie/Kconfig b/src/soc/intel/common/block/pcie/Kconfig index 9c42af6..25cde37 100644 --- a/src/soc/intel/common/block/pcie/Kconfig +++ b/src/soc/intel/common/block/pcie/Kconfig @@ -7,6 +7,8 @@ if SOC_INTEL_COMMON_BLOCK_PCIE +source "src/soc/intel/common/block/pcie/*/Kconfig" + config PCIEXP_CLK_PM default y diff --git a/src/soc/intel/common/block/pcie/Makefile.inc b/src/soc/intel/common/block/pcie/Makefile.inc index 0cded9d..e2ad685 100644 --- a/src/soc/intel/common/block/pcie/Makefile.inc +++ b/src/soc/intel/common/block/pcie/Makefile.inc @@ -1,2 +1,4 @@ +subdirs-y += ./* + ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie_rp.c diff --git a/src/soc/intel/common/block/pcie/rtd3/Kconfig b/src/soc/intel/common/block/pcie/rtd3/Kconfig new file mode 100644 index 0000000..03e13da --- /dev/null +++ b/src/soc/intel/common/block/pcie/rtd3/Kconfig @@ -0,0 +1,9 @@ +config SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 + bool + default n + depends on HAVE_ACPI_TABLES + select PMC_IPC_MAILBOX_ACPI_INTERFACE + help + When enabled, this driver will add support for ACPI controlled + Runtime D3 using GPIOs for power/reset control of the device + attached to a PCIe root port. diff --git a/src/soc/intel/common/block/pcie/rtd3/Makefile.inc b/src/soc/intel/common/block/pcie/rtd3/Makefile.inc new file mode 100644 index 0000000..7edea97 --- /dev/null +++ b/src/soc/intel/common/block/pcie/rtd3/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE_RTD3) += rtd3.c diff --git a/src/soc/intel/common/block/pcie/rtd3/chip.h b/src/soc/intel/common/block/pcie/rtd3/chip.h new file mode 100644 index 0000000..062ce30 --- /dev/null +++ b/src/soc/intel/common/block/pcie/rtd3/chip.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_INTEL_COMMON_BLOCK_PCIE_RTD3_CHIP_H__ +#define __SOC_INTEL_COMMON_BLOCK_PCIE_RTD3_CHIP_H__ + +#include <acpi/acpi_device.h> + +struct soc_intel_common_block_pcie_rtd3_config { + struct acpi_gpio power_gpio; /* Power GPIO for this device */ + struct acpi_gpio reset_gpio; /* Reset GPIO for this device (optional) */ + unsigned int clock_pin; /* SRCCLK assigned to this root port */ +}; + +#endif /* __SOC_INTEL_COMMON_BLOCK_PCIE_RTD3_CHIP_H__ */ diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c new file mode 100644 index 0000000..0331e95 --- /dev/null +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -0,0 +1,278 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> +#include <acpi/acpi_device.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/pci.h> +#include <intelblocks/pmc.h> + +#include "chip.h" + +/* + * This UUID and the resulting ACPI Device Property is defined by the + * Power Management for Storage Hardware Devices: + * + * https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelin… + */ +#define PCIE_RTD3_STORAGE_UUID "5025030F-842F-4AB4-A561-99A5189762D0" + +/* Address for start of PCIe port control and status registers. */ +#define PCIE_PXCS_ADDRESS (CONFIG_MMCONF_BASE_ADDRESS + 0xe8000) + +#define PCH_PCIE_PXCS_CFG_LSTS 0x52 /* Link Status Register */ +#define PCH_PCIE_PXCS_CFG_SPR 0xe0 /* Scratchpad */ +#define PCH_PCIE_PXCS_CFG_RPPGEN 0xe2 /* Root Port Power Gating Enable */ +#define PCH_PCIE_CFG_LCAP_PN 0x4f /* Root Port Number */ + +/* + * Delay up to wait_ms until provided register matches expected value. + * + * Local7 = segments + * While (Local7 > 0) + * { + * If (name == val) { + * Break + * } + * Sleep (wait_ms_segment) + * Local7++ + * } + */ +static void pcie_rtd3_delay(uint32_t wait_ms, const char *name, uint64_t val) +{ + uint32_t wait_ms_segment = 1; + uint32_t segments = wait_ms; + + if (wait_ms > 32) { + wait_ms_segment = 16; + segments = wait_ms / 16; + } + + acpigen_write_store_int_to_op(segments, LOCAL7_OP); + acpigen_emit_byte(WHILE_OP); + acpigen_write_len_f(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LOCAL7_OP); + acpigen_emit_byte(ZERO_OP); + if (name) { + acpigen_write_if_lequal_namestr_int(name, val); + acpigen_emit_byte(BREAK_OP); + acpigen_pop_len(); /* If */ + } + acpigen_write_sleep(wait_ms_segment); + acpigen_emit_byte(DECREMENT_OP); + acpigen_emit_byte(LOCAL7_OP); + acpigen_pop_len(); /* While */ +} + +/* Called from _ON to get PCIe link back to active state. */ +static void pcie_rtd3_l23_exit(void) +{ + /* Skip if port is not in L2/L3. */ + acpigen_write_if_lequal_namestr_int("NCB7", 0); + acpigen_write_return_op(ZERO_OP); + acpigen_pop_len(); + + /* Initiate L2/L3 Ready To Detect transition. */ + acpigen_write_store_int_to_namestr(1, "L23R"); + + /* Wait for transition to detect. */ + pcie_rtd3_delay(320, "L23R", 0); + + /* Once in detect, wait for link active. */ + pcie_rtd3_delay(128, "LASX", 1); + + /* Track state of port if link is active. */ + acpigen_write_if_lequal_namestr_int("LASX", 1); + acpigen_write_store_int_to_namestr(0, "NCB7"); + acpigen_pop_len(); +} + +/* Called from _OFF to put PCIe link into L2/L3 state. */ +static void pcie_rtd3_l23_entry(void) +{ + /* Initiate L2/L3 Entry request. */ + acpigen_write_store_int_to_namestr(1, "L23E"); + + /* Wait for L2/L3 Entry request to clear. */ + pcie_rtd3_delay(128, "L23E", 0); + + /* Track state of port if L2/L3 entry request is clear. */ + acpigen_write_if_lequal_namestr_int("L23E", 0); + acpigen_write_store_int_to_namestr(1, "NCB7"); + acpigen_pop_len(); +} + +static void pcie_rtd3_method_on(unsigned int pcie_rp, unsigned int clock_pin, + const struct acpi_gpio *power_gpio, + const struct acpi_gpio *reset_gpio) +{ + acpigen_write_method_serialized("_ON", 0); + + /* Assert power gpio. */ + acpigen_enable_tx_gpio(power_gpio); + + /* Enable CLKSRC for root port. */ + pmc_acpi_set_pci_clock(pcie_rp, clock_pin, true); + + /* De-assert reset gpio. */ + if (reset_gpio->pin_count) + acpigen_disable_tx_gpio(reset_gpio); + + /* Trigger L3/S3 ready exit flow. */ + pcie_rtd3_l23_exit(); + + acpigen_pop_len(); +} + +static void pcie_rtd3_method_off(int pcie_rp, int clock_pin, + const struct acpi_gpio *power_gpio, + const struct acpi_gpio *reset_gpio) +{ + acpigen_write_method_serialized("_OFF", 0); + + /* Trigger L2/L3 ready entry flow. */ + pcie_rtd3_l23_entry(); + + /* Assert reset gpio. */ + if (reset_gpio->pin_count) + acpigen_enable_tx_gpio(reset_gpio); + + /* Disable CLKSRC for this root port. */ + pmc_acpi_set_pci_clock(pcie_rp, clock_pin, false); + + /* De-assert power gpio. */ + acpigen_disable_tx_gpio(power_gpio); + + acpigen_pop_len(); +} + +static void pcie_rtd3_method_status(const struct acpi_gpio *power_gpio) +{ + acpigen_write_method("_STA", 0); + + /* Read power gpio value into Local0. */ + acpigen_get_tx_gpio(power_gpio); + + acpigen_write_if_lequal_op_op(LOCAL0_OP, ZERO_OP); + acpigen_write_return_op(ZERO_OP); + acpigen_pop_len(); + acpigen_write_else(); + acpigen_write_return_op(ONE_OP); + acpigen_pop_len(); + + acpigen_pop_len(); +} + +static void pcie_rtd3_fill_ssdt(const struct device *dev) +{ + const struct soc_intel_common_block_pcie_rtd3_config *config = config_of(dev); + static const char * const power_res_states[] = { "_PR0", "_PR3" }; + const char *scope = acpi_device_scope(dev); + const struct opregion opregion = OPREGION("PXCS", SYSTEMMEMORY, PCIE_PXCS_ADDRESS, 0xff); + const struct fieldlist fieldlist[] = { + FIELDLIST_OFFSET(PCH_PCIE_PXCS_CFG_LSTS), + FIELDLIST_RESERVED(13), + FIELDLIST_NAMESTR("LASX", 1), /* Link Active Status */ + FIELDLIST_OFFSET(PCH_PCIE_PXCS_CFG_SPR), + FIELDLIST_RESERVED(7), + FIELDLIST_NAMESTR("NCB7", 1), + FIELDLIST_OFFSET(PCH_PCIE_PXCS_CFG_RPPGEN), + FIELDLIST_RESERVED(2), + FIELDLIST_NAMESTR("L23E", 1), /* L23_Rdy Entry Request */ + FIELDLIST_NAMESTR("L23R", 1), /* L23_Rdy Detect Transition */ + }; + uint8_t pcie_rp; + + if (!scope) { + printk(BIOS_ERR, "%s: scope not found: %s\n", __func__, dev_path(dev)); + return; + } + if (!config->power_gpio.pin_count) { + printk(BIOS_ERR, "%s: power gpio not provided for %s.\n", __func__, scope); + return; + } + if (config->clock_pin > CONFIG_MAX_PCIE_CLOCKS) { + printk(BIOS_ERR, "%s: Invalid clock pin %u for %s.\n", __func__, + config->clock_pin, scope); + return; + } + + /* Read port number of root port that this device is attached to. */ + pcie_rp = pci_read_config8(dev->bus->dev, PCH_PCIE_CFG_LCAP_PN); + if (pcie_rp == 0 || pcie_rp > CONFIG_MAX_ROOT_PORTS) { + printk(BIOS_ERR, "%s: Invalid root port number: %u\n", __func__, pcie_rp); + return; + } + /* Port number is 1-based, PMC IPC method expects 0-based. */ + pcie_rp--; + + printk(BIOS_INFO, "%s: Enable RTD3 for %s\n", scope, dev_path(dev->bus->dev)); + + /* The RTD3 power resource is added to the root port, not the device. */ + acpigen_write_scope(scope); + + acpigen_write_opregion(&opregion); + acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist), + FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); + + /* Power resources */ + acpigen_write_power_res("PRIC", 0, 0, power_res_states, ARRAY_SIZE(power_res_states)); + + pcie_rtd3_method_status(&config->power_gpio); + pcie_rtd3_method_on(pcie_rp, config->clock_pin, &config->power_gpio, + &config->reset_gpio); + pcie_rtd3_method_off(pcie_rp, config->clock_pin, &config->power_gpio, + &config->reset_gpio); + + acpigen_pop_len(); /* PowerResource */ + + /* Add property for OS to enable storage D3. */ + if ((dev->class >> 16) == PCI_BASE_CLASS_STORAGE) { + struct acpi_dp *dsd, *pkg; + + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_ADR(0); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + acpigen_write_name_integer("_S0W", 4); + + dsd = acpi_dp_new_table("_DSD"); + pkg = acpi_dp_new_table(PCIE_RTD3_STORAGE_UUID); + acpi_dp_add_integer(pkg, "StorageD3Enable", 1); + acpi_dp_add_package(dsd, pkg); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + + printk(BIOS_INFO, "%s: Added StorageD3Enable property\n", + acpi_device_path(dev)); + } + + acpigen_pop_len(); /* Scope */ +} + +static const char *pcie_rtd3_acpi_name(const struct device *dev) +{ + return "RTD3"; +} + +static struct device_operations pcie_rtd3_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt = pcie_rtd3_fill_ssdt, + .acpi_name = pcie_rtd3_acpi_name, + .ops_pci = &pci_dev_ops_pci, +}; + +static void pcie_rtd3_enable(struct device *dev) +{ + dev->ops = &pcie_rtd3_ops; +} + +struct chip_operations soc_intel_common_block_pcie_rtd3_ops = { + CHIP_NAME("Intel PCIe Runtime D3") + .enable_dev = pcie_rtd3_enable +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/46260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13e59c996b4f5e4c2657694bda9fad869b64ffde Gerrit-Change-Number: 46260 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 25

Change in coreboot[master]: ACPI: Define acpi_get_preferred_pm_profile()
by Kyösti Mälkki (Code Review) 19 Nov '20

19 Nov '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42140 ) Change subject: ACPI: Define acpi_get_preferred_pm_profile() ...................................................................... ACPI: Define acpi_get_preferred_pm_profile() Change-Id: I2e7f22ccccc6c0df8e7e9f354c50893a53a41714 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpi.c M src/arch/x86/Makefile.inc A src/arch/x86/acpi_pm.c M src/include/acpi/acpi.h 4 files changed, 27 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/42140/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 8bf4b49..24c6911 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1245,14 +1245,7 @@ fadt->x_dsdt_l = (unsigned long)dsdt; fadt->x_dsdt_h = 0; - if (CONFIG(SYSTEM_TYPE_CONVERTIBLE) || - CONFIG(SYSTEM_TYPE_LAPTOP)) - fadt->preferred_pm_profile = PM_MOBILE; - else if (CONFIG(SYSTEM_TYPE_DETACHABLE) || - CONFIG(SYSTEM_TYPE_TABLET)) - fadt->preferred_pm_profile = PM_TABLET; - else - fadt->preferred_pm_profile = PM_DESKTOP; + fadt->preferred_pm_profile = acpi_get_preferred_pm_profile(); acpi_fill_fadt(fadt); diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 0dd8d2b..d290c26 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -227,6 +227,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) +ramstage-y += acpi_pm.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c ramstage-y += c_start.S diff --git a/src/arch/x86/acpi_pm.c b/src/arch/x86/acpi_pm.c new file mode 100644 index 0000000..edc6706 --- /dev/null +++ b/src/arch/x86/acpi_pm.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <smbios.h> + +uint8_t acpi_get_preferred_pm_profile(void) +{ + int enclosure = smbios_mainboard_enclosure_type(); + + switch (enclosure) { + case SMBIOS_ENCLOSURE_LAPTOP: + case SMBIOS_ENCLOSURE_CONVERTIBLE: + return PM_MOBILE; + case SMBIOS_ENCLOSURE_DETACHABLE: + case SMBIOS_ENCLOSURE_TABLET: + return PM_TABLET; + case SMBIOS_ENCLOSURE_DESKTOP: + return PM_DESKTOP; + case SMBIOS_ENCLOSURE_UNKNOWN: + default: + return PM_UNSPECIFIED; + } +} diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index e6c18c2..b3f70d6 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1013,6 +1013,8 @@ } #endif +uint8_t acpi_get_preferred_pm_profile(void); + /* Returns ACPI_Sx values. */ int acpi_get_sleep_type(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/42140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e7f22ccccc6c0df8e7e9f354c50893a53a41714 Gerrit-Change-Number: 42140 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

7 21

Change in coreboot[master]: APCI S3: Split arch-agnostic parts
by Kyösti Mälkki (Code Review) 19 Nov '20

19 Nov '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42614 ) Change subject: APCI S3: Split arch-agnostic parts ...................................................................... APCI S3: Split arch-agnostic parts Change-Id: I9fc2d1cdbb280f781045882bc4ac98c67946953e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/Makefile.inc A src/acpi/acpi_pm.c M src/arch/x86/Makefile.inc M src/arch/x86/acpi_s3.c 4 files changed, 48 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/42614/1 diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc index 7e37e1a..108f427 100644 --- a/src/acpi/Makefile.inc +++ b/src/acpi/Makefile.inc @@ -3,6 +3,7 @@ ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) ramstage-y += acpi.c +ramstage-y += acpi_pm.c ramstage-y += acpigen.c ramstage-y += acpigen_dsm.c ramstage-y += acpigen_ps2_keybd.c @@ -12,6 +13,8 @@ ramstage-y += sata.c ramstage-y += soundwire.c +postcar-y += acpi_pm.c + ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/acpi_tables.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c endif diff --git a/src/acpi/acpi_pm.c b/src/acpi/acpi_pm.c new file mode 100644 index 0000000..b88b761 --- /dev/null +++ b/src/acpi/acpi_pm.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <console/console.h> +#include <romstage_handoff.h> + +/* This is filled with acpi_is_wakeup() call early in ramstage. */ +static int acpi_slp_type = -1; + +static void acpi_handoff_wakeup(void) +{ + if (acpi_slp_type < 0) { + if (romstage_handoff_is_resume()) { + printk(BIOS_DEBUG, "S3 Resume\n"); + acpi_slp_type = ACPI_S3; + } else { + printk(BIOS_DEBUG, "Normal boot\n"); + acpi_slp_type = ACPI_S0; + } + } +} + +int acpi_is_wakeup(void) +{ + acpi_handoff_wakeup(); + /* Both resume from S2 and resume from S3 restart at CPU reset */ + return (acpi_slp_type == ACPI_S3 || acpi_slp_type == ACPI_S2); +} + +int acpi_is_wakeup_s3(void) +{ + acpi_handoff_wakeup(); + return (acpi_slp_type == ACPI_S3); +} + +int acpi_is_wakeup_s4(void) +{ + acpi_handoff_wakeup(); + return (acpi_slp_type == ACPI_S4); +} + +void __weak mainboard_suspend_resume(void) +{ +} diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 6297384..6773b270 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -157,7 +157,6 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) -romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c romstage-y += boot.c romstage-y += post.c # gdt_init.S is included by entry32.inc when romstage is the first C @@ -198,7 +197,6 @@ $(eval $(call create_class_compiler,postcar,x86_32)) postcar-generic-ccopts += -D__POSTCAR__ -postcar-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c postcar-y += boot.c postcar-y += post.c postcar-y += gdt_init.S @@ -235,7 +233,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) -ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c +ramstage-y += acpi_s3.c ramstage-$(CONFIG_ACPI_BERT) += acpi_bert_storage.c ramstage-y += boot.c ramstage-y += post.c diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 814719a..8017dff 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -9,45 +9,6 @@ #include <cpu/x86/smm.h> #include <fallback.h> #include <timestamp.h> -#include <romstage_handoff.h> - -#if ENV_RAMSTAGE || ENV_POSTCAR - -/* This is filled with acpi_is_wakeup() call early in ramstage. */ -static int acpi_slp_type = -1; - -static void acpi_handoff_wakeup(void) -{ - if (acpi_slp_type < 0) { - if (romstage_handoff_is_resume()) { - printk(BIOS_DEBUG, "S3 Resume\n"); - acpi_slp_type = ACPI_S3; - } else { - printk(BIOS_DEBUG, "Normal boot\n"); - acpi_slp_type = ACPI_S0; - } - } -} - -int acpi_is_wakeup(void) -{ - acpi_handoff_wakeup(); - /* Both resume from S2 and resume from S3 restart at CPU reset */ - return (acpi_slp_type == ACPI_S3 || acpi_slp_type == ACPI_S2); -} - -int acpi_is_wakeup_s3(void) -{ - acpi_handoff_wakeup(); - return (acpi_slp_type == ACPI_S3); -} - -int acpi_is_wakeup_s4(void) -{ - acpi_handoff_wakeup(); - return (acpi_slp_type == ACPI_S4); -} -#endif /* ENV_RAMSTAGE */ #define WAKEUP_BASE 0x600 @@ -56,10 +17,6 @@ extern unsigned char __wakeup; extern unsigned int __wakeup_size; -void __weak mainboard_suspend_resume(void) -{ -} - void __noreturn acpi_resume(void *wake_vec) { if (CONFIG(HAVE_SMI_HANDLER)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/42614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9fc2d1cdbb280f781045882bc4ac98c67946953e Gerrit-Change-Number: 42614 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: soc/intel/fsp-car: Halt on improperly configured coreboot
by Arthur Heymans (Code Review) 19 Nov '20

19 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37280 ) Change subject: soc/intel/fsp-car: Halt on improperly configured coreboot ...................................................................... soc/intel/fsp-car: Halt on improperly configured coreboot Test if Kconfig symbols actually match what FSP does. If it is not the case it best to halt right away instead of continuing to boot with possibly hard to debug problems. Change-Id: I8520adc868f08938af27ee686a8777c281afd4f9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/37280/1 diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 4174f36..bde3849 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -86,6 +86,11 @@ cmp $0, %eax jnz .halt_forever + /* Check sanity of coreboot Kconfig symbols that need to match what FSP + does */ + cmpl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %edx + jne .halt_forever + /* Setup bootblock stack */ movl _ecar_stack, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/37280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8520adc868f08938af27ee686a8777c281afd4f9 Gerrit-Change-Number: 37280 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: drivers/intel/fsp1.1/car: Halt on improperly configured coreboot
by Arthur Heymans (Code Review) 19 Nov '20

19 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37281 ) Change subject: drivers/intel/fsp1.1/car: Halt on improperly configured coreboot ...................................................................... drivers/intel/fsp1.1/car: Halt on improperly configured coreboot Test if Kconfig symbols actually match what FSP does. If it is not the case it best to halt right away instead of continuing to boot with possibly hard to debug problems. Change-Id: Ieec8259149cc8fd71c40fd1511a6a2cfa67c5337 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/cache_as_ram.S 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/37281/1 diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index fb39884..748c267 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -143,6 +143,11 @@ cmp $0, %eax jne halt2 + /* Check sanity of coreboot Kconfig symbols that need to match what FSP + does */ + cmpl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %edx + jne .halt_forever + /* Setup BSP stack */ movl _ecar_stack, %esp -- To view, visit https://review.coreboot.org/c/coreboot/+/37281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieec8259149cc8fd71c40fd1511a6a2cfa67c5337 Gerrit-Change-Number: 37281 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: mb/google/volteer: Modify touchscreen IRQ to level trigger
by Casper Chang (Code Review) 19 Nov '20

19 Nov '20

Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46830 ) Change subject: mb/google/volteer: Modify touchscreen IRQ to level trigger ...................................................................... mb/google/volteer: Modify touchscreen IRQ to level trigger Modify IRQ to level trigger to meet touchscreen device requirement. BUG=b:170358155 TEST=Build Pass and test with vendor's latest touchscreen firmware Signed-off-by: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Change-Id: I30f6a43c2c783865e90264b6c7fcdc6002267a1d --- M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/46830/1 diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 2db1f08..ba3f985 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -98,7 +98,7 @@ chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" -- To view, visit https://review.coreboot.org/c/coreboot/+/46830 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30f6a43c2c783865e90264b6c7fcdc6002267a1d Gerrit-Change-Number: 46830 Gerrit-PatchSet: 1 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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