coreboot-gerrit October 2020

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Change in coreboot[master]: soc/amd/picasso: Update coreboot UPD variable names to include units
by Bao Zheng (Code Review) 06 Nov '20

06 Nov '20

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46840 to review the following change. Change subject: soc/amd/picasso: Update coreboot UPD variable names to include units ...................................................................... soc/amd/picasso: Update coreboot UPD variable names to include units Use command below to change the variable globally. sed -i "s/\<variable\>/variable_u/g" `grep variable -rl ./ --exclude-dir=build` BUG=b:171334623 TEST=Build Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/berknip/overridetree.cb M src/mainboard/google/zork/variants/dalboz/overridetree.cb M src/mainboard/google/zork/variants/dirinboz/overridetree.cb M src/mainboard/google/zork/variants/ezkinil/overridetree.cb M src/mainboard/google/zork/variants/morphius/overridetree.cb M src/mainboard/google/zork/variants/trembyle/overridetree.cb M src/mainboard/google/zork/variants/vilboz/overridetree.cb M src/mainboard/google/zork/variants/woomax/overridetree.cb M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/romstage.c M src/soc/amd/picasso/root_complex.c M src/vendorcode/amd/fsp/picasso/FspmUpd.h M util/mainboard/google/dalboz/template/overridetree.cb M util/mainboard/google/trembyle/template/overridetree.cb 16 files changed, 158 insertions(+), 158 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/46840/1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 58e25e6..00e77c0 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -15,22 +15,22 @@ # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time - register "prochot_l_deassertion_ramp_time" = "20" #mS + register "prochot_l_deassertion_ramp_time_mS" = "20" # Lower die temperature limit - register "thermctl_limit" = "100" #degrees C + register "thermctl_limit_degreeC" = "100" # FP5 Processor Voltage Supply PSI Currents - register "psi0_current_limit" = "18000" #mA - register "psi0_soc_current_limit" = "12000" #mA - register "vddcr_soc_voltage_margin" = "0" #mV - register "vddcr_vdd_voltage_margin" = "0" #mV + register "psi0_current_limit_mA" = "18000" + register "psi0_soc_current_limit_mA" = "12000" + register "vddcr_soc_voltage_margin" = "0" + register "vddcr_vdd_voltage_margin" = "0" # VRM Limits - register "vrm_maximum_current_limit" = "0" #mA - register "vrm_soc_maximum_current_limit" = "0" #mA - register "vrm_current_limit" = "0" #mA - register "vrm_soc_current_limit" = "0" #mA + register "vrm_maximum_current_limit_mA" = "0" + register "vrm_soc_maximum_current_limit_mA" = "0" + register "vrm_current_limit_mA" = "0" + register "vrm_soc_current_limit_mA" = "0" # Misc SMU settings register "sb_tsi_alert_comparator_mode_en" = "0" diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 3ab70a2..c1f82a7 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -15,22 +15,22 @@ # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time - register "prochot_l_deassertion_ramp_time" = "20" #mS + register "prochot_l_deassertion_ramp_time_mS" = "20" # Lower die temperature limit - register "thermctl_limit" = "100" #degrees C + register "thermctl_limit_degreeC" = "100" # FP5 Processor Voltage Supply PSI Currents - register "psi0_current_limit" = "18000" #mA - register "psi0_soc_current_limit" = "12000" #mA + register "psi0_current_limit_mA" = "18000" + register "psi0_soc_current_limit_mA" = "12000" register "vddcr_soc_voltage_margin" = "0" #mV register "vddcr_vdd_voltage_margin" = "0" #mV # VRM Limits - register "vrm_maximum_current_limit" = "0" #mA - register "vrm_soc_maximum_current_limit" = "0" #mA - register "vrm_current_limit" = "0" #mA - register "vrm_soc_current_limit" = "0" #mA + register "vrm_maximum_current_limit_mA" = "0" + register "vrm_soc_maximum_current_limit_mA" = "0" + register "vrm_current_limit_mA" = "0" + register "vrm_soc_current_limit_mA" = "0" # Misc SMU settings register "sb_tsi_alert_comparator_mode_en" = "0" diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index 674d557..e7f4d40 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -9,15 +9,15 @@ register "system_config" = "3" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "20000" #mw - register "fast_ppt_limit" = "24000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "12000" #mw + register "slow_ppt_limit_mW" = "20000" + register "fast_ppt_limit_mW" = "24000" + register "slow_ppt_time_constant_sec" = "5" + register "stapm_time_constant_sec" = "200" + register "sustained_power_limit_mW" = "12000" - register "telemetry_vddcr_vdd_slope" = "65599" #mA + register "telemetry_vddcr_vdd_slope_mA" = "65599" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "29788" #mA + register "telemetry_vddcr_soc_slope_mA" = "29788" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb index 1ddb17b..961fc12 100644 --- a/src/mainboard/google/zork/variants/dalboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb @@ -9,17 +9,17 @@ register "system_config" = "1" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "6000" #mw - register "fast_ppt_limit" = "9000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "2500" #second - register "sustained_power_limit" = "4800" #mw + register "slow_ppt_limit_mw" = "6000" + register "fast_ppt_limit_mw" = "9000" + register "slow_ppt_time_constant_sec" = "5" + register "stapm_time_constant_sec" = "2500" + register "sustained_power_limit_mW" = "4800" # End : OPN Performance Configuration - register "telemetry_vddcr_vdd_slope" = "30231" #mA + register "telemetry_vddcr_vdd_slope_mA" = "30231" register "telemetry_vddcr_vdd_offset" = "0-1" - register "telemetry_vddcr_soc_slope" = "22644" #mA + register "telemetry_vddcr_soc_slope_mA" = "22644" register "telemetry_vddcr_soc_offset" = "68" # I2C2 for touchscreen and trackpad diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index a11fa5e..5aed9d3 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -9,15 +9,15 @@ register "system_config" = "1" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "6000" #mw - register "fast_ppt_limit" = "9000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "2500" #second - register "sustained_power_limit" = "4800" #mw + register "slow_ppt_limit_mW" = "6000" + register "fast_ppt_limit_mW" = "9000" + register "slow_ppt_time_constant_sec" = "5" + register "stapm_time_constant_sec" = "2500" + register "sustained_power_limit_mW" = "4800" - register "telemetry_vddcr_vdd_slope" = "42465" #mA + register "telemetry_vddcr_vdd_slope_mA" = "42465" register "telemetry_vddcr_vdd_offset" = "69" - register "telemetry_vddcr_soc_slope" = "42667" #mA + register "telemetry_vddcr_soc_slope_mA" = "42667" register "telemetry_vddcr_soc_offset" = "167" # End : OPN Performance Configuration diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb index 5ef2f0a..1846f51 100644 --- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -9,15 +9,15 @@ register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "20000" #mw - register "fast_ppt_limit" = "24000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "12000" #mw + register "slow_ppt_limit_mW" = "20000" + register "fast_ppt_limit_mW" = "24000" + register "slow_ppt_time_constant_sec" = "5" + register "stapm_time_constant_sec" = "200" + register "sustained_power_limit_mW" = "12000" - register "telemetry_vddcr_vdd_slope" = "62413" #mA + register "telemetry_vddcr_vdd_slope_mA" = "62413" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "28977" #mA + register "telemetry_vddcr_soc_slope_mA" = "28977" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index 43a9439..78c516f 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -9,24 +9,24 @@ register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "20000" #mw - register "fast_ppt_limit" = "24000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "12000" #mw - register "thermctl_limit" = "100" #degrees C + register "slow_ppt_limit_mW" = "20000" + register "fast_ppt_limit_mW" = "24000" + register "slow_ppt_time_constant_sec" = "5" + register "stapm_time_constant_sec" = "200" + register "sustained_power_limit_mW" = "12000" + register "thermctl_limit_degreeC" = "100" - register "telemetry_vddcr_vdd_slope" = "78709" #mA + register "telemetry_vddcr_vdd_slope_mA" = "78709" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "29035" #mA + register "telemetry_vddcr_soc_slope_mA" = "29035" register "telemetry_vddcr_soc_offset" = "0" # Set STAPM confiuration for tablet mode register "dptc_enable" = "1" - register "slow_ppt_limit_tablet_mode" = "20000" #mw - register "fast_ppt_limit_tablet_mode" = "24000" #mw - register "sustained_power_limit_tablet_mode" = "12000" #mw - register "thermctl_limit_tablet_mode" = "70" #degrees C + register "slow_ppt_limit_tablet_mode_mW" = "20000" + register "fast_ppt_limit_tablet_mode_mW" = "24000" + register "sustained_power_limit_tablet_mode_mW" = "12000" + register "thermctl_limit_tablet_mode_degreeC" = "70" # End : OPN Performance Configuration diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb index f06f03d..d2385c6 100644 --- a/src/mainboard/google/zork/variants/trembyle/overridetree.cb +++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb @@ -9,15 +9,15 @@ register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "25000" #mw - register "fast_ppt_limit" = "30000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "15000" #mw + register "slow_ppt_limit_mW" = "25000" + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_time_constant_sec" = "5" + register "stapm_time_constant_sec" = "200" + register "sustained_power_limit_mW" = "15000" - register "telemetry_vddcr_vdd_slope" = "71222" #mA + register "telemetry_vddcr_vdd_slope_mA" = "71222" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "28977" #mA + register "telemetry_vddcr_soc_slope_mA" = "28977" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index a93beb5..fe11a88 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -10,17 +10,17 @@ register "system_config" = "1" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "6000" # mW - register "fast_ppt_limit" = "9000" # mW - register "slow_ppt_time_constant" = "5" # second - register "stapm_time_constant" = "1400" # second - register "sustained_power_limit" = "4800" # mW + register "slow_ppt_limit_mW" = "6000" # mW + register "fast_ppt_limit_mW" = "9000" # mW + register "slow_ppt_time_constant_sec" = "5" # second + register "stapm_time_constant_sec" = "1400" # second + register "sustained_power_limit_mW" = "4800" # mW # End : OPN Performance Configuration - register "telemetry_vddcr_vdd_slope" = "32643" #mA + register "telemetry_vddcr_vdd_slope_mA" = "32643" #mA register "telemetry_vddcr_vdd_offset" = "208" - register "telemetry_vddcr_soc_slope" = "22742" #mA + register "telemetry_vddcr_soc_slope_mA" = "22742" #mA register "telemetry_vddcr_soc_offset" = "-83" # USB OC pin mapping diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb index 19d66fc..fa8fefc 100644 --- a/src/mainboard/google/zork/variants/woomax/overridetree.cb +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -10,15 +10,15 @@ register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "25000" #mw - register "fast_ppt_limit" = "30000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "15000" #mw + register "slow_ppt_limit_mW" = "25000" + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_time_constant_sec" = "5" + register "stapm_time_constant_sec" = "200" + register "sustained_power_limit_mW" = "15000" - register "telemetry_vddcr_vdd_slope" = "102586" #mA + register "telemetry_vddcr_vdd_slope_mA" = "102586" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "26967" #mA + register "telemetry_vddcr_soc_slope_mA" = "26967" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 3098a81..1813289 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -102,22 +102,22 @@ uint8_t system_config; /* STAPM Configuration */ - uint32_t fast_ppt_limit; - uint32_t slow_ppt_limit; - uint32_t slow_ppt_time_constant; - uint32_t stapm_time_constant; - uint32_t sustained_power_limit; + uint32_t fast_ppt_limit_mW; + uint32_t slow_ppt_limit_mW; + uint32_t slow_ppt_time_constant_sec; + uint32_t stapm_time_constant_sec; + uint32_t sustained_power_limit_mW; /* Enable dptc for tablet mode (0 = disable, 1 = enable) */ uint8_t dptc_enable; /* STAPM Configuration for tablet mode (need enable dptc_enable first) */ - uint32_t fast_ppt_limit_tablet_mode; - uint32_t slow_ppt_limit_tablet_mode; - uint32_t sustained_power_limit_tablet_mode; + uint32_t fast_ppt_limit_tablet_mode_mW; + uint32_t slow_ppt_limit_tablet_mode_mW; + uint32_t sustained_power_limit_tablet_mode_mW; /* PROCHOT_L de-assertion Ramp Time */ - uint32_t prochot_l_deassertion_ramp_time; + uint32_t prochot_l_deassertion_ramp_time_mS; enum { DOWNCORE_AUTO = 0, @@ -128,29 +128,29 @@ uint8_t smt_disable; /* 1=disable SMT, 0=enable SMT */ /* Lower die temperature limit */ - uint32_t thermctl_limit; - uint32_t thermctl_limit_tablet_mode; + uint32_t thermctl_limit_degreeC; + uint32_t thermctl_limit_tablet_mode_degreeC; /* FP5 Processor Voltage Supply PSI Currents. 0 indicates use SOC default */ - uint32_t psi0_current_limit; - uint32_t psi0_soc_current_limit; + uint32_t psi0_current_limit_mA; + uint32_t psi0_soc_current_limit_mA; uint32_t vddcr_soc_voltage_margin; uint32_t vddcr_vdd_voltage_margin; /* VRM Limits. 0 indicates use SOC default */ - uint32_t vrm_maximum_current_limit; - uint32_t vrm_soc_maximum_current_limit; - uint32_t vrm_current_limit; - uint32_t vrm_soc_current_limit; + uint32_t vrm_maximum_current_limit_mA; + uint32_t vrm_soc_maximum_current_limit_mA; + uint32_t vrm_current_limit_mA; + uint32_t vrm_soc_current_limit_mA; /* Misc SMU settings */ uint8_t sb_tsi_alert_comparator_mode_en; uint8_t core_dldo_bypass; uint8_t min_soc_vid_offset; uint8_t aclk_dpm0_freq_400MHz; - uint32_t telemetry_vddcr_vdd_slope; + uint32_t telemetry_vddcr_vdd_slope_mA; uint32_t telemetry_vddcr_vdd_offset; - uint32_t telemetry_vddcr_soc_slope; + uint32_t telemetry_vddcr_soc_slope_mA; uint32_t telemetry_vddcr_soc_offset; struct { diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index b967431..6da5b0d 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -105,37 +105,37 @@ mcfg->system_config = config->system_config; - if ((config->slow_ppt_limit) && - (config->fast_ppt_limit) && - (config->slow_ppt_time_constant) && - (config->stapm_time_constant)) { - mcfg->slow_ppt_limit = config->slow_ppt_limit; - mcfg->fast_ppt_limit = config->fast_ppt_limit; - mcfg->slow_ppt_time_constant = config->slow_ppt_time_constant; - mcfg->stapm_time_constant = config->stapm_time_constant; + if ((config->slow_ppt_limit_mW) && + (config->fast_ppt_limit_mW) && + (config->slow_ppt_time_constant_sec) && + (config->stapm_time_constant_sec)) { + mcfg->slow_ppt_limit_mW = config->slow_ppt_limit_mW; + mcfg->fast_ppt_limit_mW = config->fast_ppt_limit_mW; + mcfg->slow_ppt_time_constant_sec = config->slow_ppt_time_constant_sec; + mcfg->stapm_time_constant_sec = config->stapm_time_constant_sec; } mcfg->ccx_down_core_mode = config->downcore_mode; mcfg->ccx_disable_smt = config->smt_disable; - mcfg->sustained_power_limit = config->sustained_power_limit; - mcfg->prochot_l_deassertion_ramp_time = config->prochot_l_deassertion_ramp_time; - mcfg->thermctl_limit = config->thermctl_limit; - mcfg->psi0_current_limit = config->psi0_current_limit; - mcfg->psi0_soc_current_limit = config->psi0_soc_current_limit; + mcfg->sustained_power_limit_mW = config->sustained_power_limit_mW; + mcfg->prochot_l_deassertion_ramp_time_mS = config->prochot_l_deassertion_ramp_time_mS; + mcfg->thermctl_limit_degreeC = config->thermctl_limit_degreeC; + mcfg->psi0_current_limit_mA = config->psi0_current_limit_mA; + mcfg->psi0_soc_current_limit_mA = config->psi0_soc_current_limit_mA; mcfg->vddcr_soc_voltage_margin = config->vddcr_soc_voltage_margin; mcfg->vddcr_vdd_voltage_margin = config->vddcr_vdd_voltage_margin; - mcfg->vrm_maximum_current_limit = config->vrm_maximum_current_limit; - mcfg->vrm_soc_maximum_current_limit = config->vrm_soc_maximum_current_limit; - mcfg->vrm_current_limit = config->vrm_current_limit; - mcfg->vrm_soc_current_limit = config->vrm_soc_current_limit; + mcfg->vrm_maximum_current_limit_mA = config->vrm_maximum_current_limit_mA; + mcfg->vrm_soc_maximum_current_limit_mA = config->vrm_soc_maximum_current_limit_mA; + mcfg->vrm_current_limit_mA = config->vrm_current_limit_mA; + mcfg->vrm_soc_current_limit_mA = config->vrm_soc_current_limit_mA; mcfg->sb_tsi_alert_comparator_mode_en = config->sb_tsi_alert_comparator_mode_en; mcfg->core_dldo_bypass = config->core_dldo_bypass; mcfg->min_soc_vid_offset = config->min_soc_vid_offset; mcfg->aclk_dpm0_freq_400MHz = config->aclk_dpm0_freq_400MHz; - mcfg->telemetry_vddcr_vdd_slope = config->telemetry_vddcr_vdd_slope; + mcfg->telemetry_vddcr_vdd_slope_mA = config->telemetry_vddcr_vdd_slope_mA; mcfg->telemetry_vddcr_vdd_offset = config->telemetry_vddcr_vdd_offset; - mcfg->telemetry_vddcr_soc_slope = config->telemetry_vddcr_soc_slope; + mcfg->telemetry_vddcr_soc_slope_mA = config->telemetry_vddcr_soc_slope_mA; mcfg->telemetry_vddcr_soc_offset = config->telemetry_vddcr_soc_offset; mcfg->hd_audio_enable = devtree_hda_dev_enabled(); mcfg->sata_enable = devtree_sata_dev_enabled(); diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 174cddc..72a0974 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -200,15 +200,15 @@ if (!config->dptc_enable) return; - struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit, - config->sustained_power_limit, - config->fast_ppt_limit, - config->slow_ppt_limit); + struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC, + config->sustained_power_limit_mW, + config->fast_ppt_limit_mW, + config->slow_ppt_limit_mW); struct dptc_input tablet_mode_input = DPTC_INPUTS( - config->thermctl_limit_tablet_mode, - config->sustained_power_limit_tablet_mode, - config->fast_ppt_limit_tablet_mode, - config->slow_ppt_limit_tablet_mode); + config->thermctl_limit_tablet_mode_degreeC, + config->sustained_power_limit_tablet_mode_mW, + config->fast_ppt_limit_tablet_mode_mW, + config->slow_ppt_limit_tablet_mode_mW); /* Scope (\_SB) */ acpigen_write_scope("\\_SB"); diff --git a/src/vendorcode/amd/fsp/picasso/FspmUpd.h b/src/vendorcode/amd/fsp/picasso/FspmUpd.h index 56e1a5e..57002f0 100644 --- a/src/vendorcode/amd/fsp/picasso/FspmUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspmUpd.h @@ -18,33 +18,33 @@ /** Offset 0x004C**/ uint32_t serial_port_stride; /** Offset 0x0050**/ uint32_t serial_port_baudrate; /** Offset 0x0054**/ uint32_t serial_port_refclk; - /** Offset 0x0058**/ uint32_t telemetry_vddcr_vdd_slope; - /** Offset 0x005C**/ uint32_t telemetry_vddcr_vdd_slope2; - /** Offset 0x0060**/ uint32_t telemetry_vddcr_vdd_slope3; - /** Offset 0x0064**/ uint32_t telemetry_vddcr_vdd_slope4; - /** Offset 0x0068**/ uint32_t telemetry_vddcr_vdd_slope5; + /** Offset 0x0058**/ uint32_t telemetry_vddcr_vdd_slope_mA; + /** Offset 0x005C**/ uint32_t telemetry_vddcr_vdd_slope2_mA; + /** Offset 0x0060**/ uint32_t telemetry_vddcr_vdd_slope3_mA; + /** Offset 0x0064**/ uint32_t telemetry_vddcr_vdd_slope4_mA; + /** Offset 0x0068**/ uint32_t telemetry_vddcr_vdd_slope5_mA; /** Offset 0x006C**/ uint32_t telemetry_vddcr_vdd_offset; - /** Offset 0x0070**/ uint32_t telemetry_vddcr_soc_slope; + /** Offset 0x0070**/ uint32_t telemetry_vddcr_soc_slope_mA; /** Offset 0x0074**/ uint32_t telemetry_vddcr_soc_offset; /** Offset 0x0078**/ uint8_t aa_mode_en; /** Offset 0x0079**/ uint8_t unused2; /** Offset 0x007A**/ uint8_t unused3; /** Offset 0x007B**/ uint8_t unused4; - /** Offset 0x007C**/ uint32_t fast_ppt_limit; - /** Offset 0x0080**/ uint32_t slow_ppt_limit; - /** Offset 0x0084**/ uint32_t slow_ppt_time_constant; - /** Offset 0x0088**/ uint32_t psi0_current_limit; - /** Offset 0x008C**/ uint32_t psi0_soc_current_limit; - /** Offset 0x0090**/ uint32_t thermctl_limit; - /** Offset 0x0094**/ uint32_t vrm_maximum_current_limit; - /** Offset 0x0098**/ uint32_t vrm_soc_maximum_current_limit; - /** Offset 0x009C**/ uint32_t sustained_power_limit; - /** Offset 0x00A0**/ uint32_t stapm_time_constant; - /** Offset 0x00A4**/ uint32_t prochot_l_deassertion_ramp_time; - /** Offset 0x00A8**/ uint32_t vrm_current_limit; - /** Offset 0x00AC**/ uint32_t vrm_soc_current_limit; - /** Offset 0x00B0**/ uint32_t vddcr_soc_voltage_margin; - /** Offset 0x00B4**/ uint32_t vddcr_vdd_voltage_margin; + /** Offset 0x007C**/ uint32_t fast_ppt_limit_mw; + /** Offset 0x0080**/ uint32_t slow_ppt_limit_mw; + /** Offset 0x0084**/ uint32_t slow_ppt_time_constant_sec; + /** Offset 0x0088**/ uint32_t psi0_current_limit_mA; + /** Offset 0x008C**/ uint32_t psi0_soc_current_limit_mA; + /** Offset 0x0090**/ uint32_t thermctl_limit_degreeC; + /** Offset 0x0094**/ uint32_t vrm_maximum_current_limit_mA; + /** Offset 0x0098**/ uint32_t vrm_soc_maximum_current_limit_mA; + /** Offset 0x009C**/ uint32_t sustained_power_limit_mW; + /** Offset 0x00A0**/ uint32_t stapm_time_constant_sec; + /** Offset 0x00A4**/ uint32_t prochot_l_deassertion_ramp_time_mS; + /** Offset 0x00A8**/ uint32_t vrm_current_limit_mA; + /** Offset 0x00AC**/ uint32_t vrm_soc_current_limit_mA; + /** Offset 0x00B0**/ uint32_t vddcr_soc_voltage_margin_mV; + /** Offset 0x00B4**/ uint32_t vddcr_vdd_voltage_margin_mV; /** Offset 0x00B8**/ uint32_t smu_feature_control_defines; /** Offset 0x00BC**/ uint32_t smu_feature_control_defines_ext; /** Offset 0x00C0**/ uint8_t sb_tsi_alert_comparator_mode_en; diff --git a/util/mainboard/google/dalboz/template/overridetree.cb b/util/mainboard/google/dalboz/template/overridetree.cb index 7645ba3..d870177 100644 --- a/util/mainboard/google/dalboz/template/overridetree.cb +++ b/util/mainboard/google/dalboz/template/overridetree.cb @@ -10,11 +10,11 @@ register "system_config" = "1" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "6000" #mw - register "fast_ppt_limit" = "9000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "2500" #second - register "sustained_power_limit" = "4800" #mw + register "slow_ppt_limit_mW" = "6000" + register "fast_ppt_limit_mW" = "9000" + register "slow_ppt_time_constant_sec" = "5" + register "stapm_time_constant_sec" = "2500" + register "sustained_power_limit_mW" = "4800" # End : OPN Performance Configuration diff --git a/util/mainboard/google/trembyle/template/overridetree.cb b/util/mainboard/google/trembyle/template/overridetree.cb index d332fce..9788025 100644 --- a/util/mainboard/google/trembyle/template/overridetree.cb +++ b/util/mainboard/google/trembyle/template/overridetree.cb @@ -10,15 +10,15 @@ register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "25000" #mw - register "fast_ppt_limit" = "30000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "15000" #mw + register "slow_ppt_limit_mW" = "25000" + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_time_constant_sec" = "5" + register "stapm_time_constant_sec" = "200" + register "sustained_power_limit_mW" = "15000" - register "telemetry_vddcr_vdd_slope" = "71222" #mA + register "telemetry_vddcr_vdd_slope_mA" = "71222" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "28977" #mA + register "telemetry_vddcr_soc_slope_mA" = "28977" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/46840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3 Gerrit-Change-Number: 46840 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: newchange

5 20

Change in coreboot[master]: mb/ocp/deltalake: Insert IO port in linux command line
by Bryant Ou (Code Review) 06 Nov '20

06 Nov '20

Bryant Ou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45410 ) Change subject: mb/ocp/deltalake: Insert IO port in linux command line ...................................................................... mb/ocp/deltalake: Insert IO port in linux command line Search "uart8250,io," string in CONFIG_LINUX_COMMAND_LINE, then insert uart base address which defined in VPD. Tested=On OCP Delta Lake, payload use correct uart base address to output messages via VPD variable. Signed-off-by: Bryant Ou <Bryant.Ou.Q(a)gmail.com> Change-Id: I8747a23c7246aabe8c01ad5be668e1672b586f2c --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/ramstage.c 2 files changed, 76 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45410/1 diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index 5671664..0ab8bbb 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -54,4 +54,10 @@ bool default y +config LINUX_COMMAND_LINE_OVERRIDE + bool + default y + help + Override linux command line by using VPD. + endif # BOARD_OCP_DELTALAKE diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index e00f1c3..115f7d3 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -10,6 +10,7 @@ #include <soc/ramstage.h> #include <soc/soc_util.h> #include <stdio.h> +#include <stdlib.h> #include <string.h> #include <smbios.h> #include <device/pci_def.h> @@ -18,10 +19,13 @@ #include <hob_iiouds.h> #include <hob_memmap.h> #include <cpxsp_dl_gpio.h> - +#include <program_loading.h> +#include <drivers/vpd/vpd.h> +#include "vpd.h" #include "ipmi.h" #define SLOT_ID_LEN 2 +#define COMMAND_LINE_LOC 0x91000 extern struct fru_info_str fru_strings; static char slot_id_str[SLOT_ID_LEN]; @@ -285,3 +289,68 @@ } BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL); + +#if (CONFIG(LINUX_COMMAND_LINE_OVERRIDE)) +void platform_segment_loaded(uintptr_t start, size_t size, int flags) +{ + char *port; + char *dupstr = strdup((char*)start); + const char s[] = {"uart8250,io,"}; + char *new = NULL; + char *p; + char *slice[10]; + char *found; + char *pre; + char *t1; + char *t2; + int count = 0; + int i; + int c; + int len; + int pos; + + /* Add IO port into linux command line */ + if (start == COMMAND_LINE_LOC) { + port = malloc(VPD_LEN); + if (vpd_gets(UART_IOPORT, port, VPD_LEN, VPD_RW_THEN_RO)) { + port = strconcat(port, ","); + } else { + printk(BIOS_ERR, "UART_IOPORT is not found in VPD\n"); + port = strconcat(UART_IOPORT_DEFAULT, ","); + } + strcpy(new, ""); + for (p = strtok(dupstr, " "); p; p = strtok(NULL, " ")) { + slice[count] = p; + count++; + } + for (i = 0; i < count; i++) { + len = strlen(slice[i]); + found = strstr(slice[i], s); + if (found != NULL) { + pos = found - slice[i] + strlen(s); + t1 = malloc(pos); + for (c = 0; c < pos; c++) { + *(t1 + c) = *(slice[i] + c); + } + *(t1 + c) = '\0'; + pre = strconcat(t1, port); + free(t1); + t2 = malloc(len - pos + 2); + for (c = 0; c < (len - pos + 1); c++) { + *(t2 + c) = *((slice[i] + pos) + c); + } + *(t2 + c) = '\0'; + pre = strconcat(pre, t2); + free(t2); + slice[i] = strdup(pre); + } + new = strconcat(new, slice[i]); + if (i < count - 1) + new = strconcat(new, " "); + } + free(port); + memset((uint8_t*)start, 0, size); + memcpy((uint8_t*)start, new, strlen(new)); + } +} +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8747a23c7246aabe8c01ad5be668e1672b586f2c Gerrit-Change-Number: 45410 Gerrit-PatchSet: 1 Gerrit-Owner: Bryant Ou <bryant.ou.q(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/google/octopus/variants/garg: update new LTE SKU
by Kevin Chiu (Code Review) 06 Nov '20

06 Nov '20

Hello Kevin Chiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47015 to review the following change. Change subject: mb/google/octopus/variants/garg: update new LTE SKU ...................................................................... mb/google/octopus/variants/garg: update new LTE SKU Add new SKU definition: Garg360 (LTE DB, touch, no stylus, rear camera) SKU ID - 39 BUG=b:170708728 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage Change-Id: Ifec4e1360bd1aff3825bc6413b0a2ccd8b822075 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/octopus/variants/garg/gpio.c M src/mainboard/google/octopus/variants/garg/include/variant/sku.h M src/mainboard/google/octopus/variants/garg/variant.c 3 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/47015/1 diff --git a/src/mainboard/google/octopus/variants/garg/gpio.c b/src/mainboard/google/octopus/variants/garg/gpio.c index 67e1056..7ae59f8 100644 --- a/src/mainboard/google/octopus/variants/garg/gpio.c +++ b/src/mainboard/google/octopus/variants/garg/gpio.c @@ -71,6 +71,7 @@ return hdmi_override_table; case SKU_17_LTE: case SKU_18_LTE_TS: + case SKU_39_2A2C_360_LTE_TS_STYLUES: *num = ARRAY_SIZE(lte_override_table); return lte_override_table; default: diff --git a/src/mainboard/google/octopus/variants/garg/include/variant/sku.h b/src/mainboard/google/octopus/variants/garg/include/variant/sku.h index 8fc63cc..b325801 100644 --- a/src/mainboard/google/octopus/variants/garg/include/variant/sku.h +++ b/src/mainboard/google/octopus/variants/garg/include/variant/sku.h @@ -12,6 +12,7 @@ SKU_20_2A2C_TS = 20, SKU_37_2A2C_360 = 37, SKU_38_2A2C_360_TS_NO_STYLUES = 38, + SKU_39_2A2C_360_LTE_TS_STYLUES = 39, SKU_49_2A2C_TS = 49, SKU_50_HDMI = 50, SKU_51_2A2C = 51, diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c index 0a6574d..a0ae71f 100644 --- a/src/mainboard/google/octopus/variants/garg/variant.c +++ b/src/mainboard/google/octopus/variants/garg/variant.c @@ -37,6 +37,7 @@ switch (google_chromeec_get_board_sku()) { case SKU_17_LTE: case SKU_18_LTE_TS: + case SKU_39_2A2C_360_LTE_TS_STYLUES: power_off_lte_module(); return; default: @@ -54,6 +55,7 @@ switch (google_chromeec_get_board_sku()) { case SKU_17_LTE: case SKU_18_LTE_TS: + case SKU_39_2A2C_360_LTE_TS_STYLUES: cfg->disable_xhci_lfps_pm = 1; return; default: -- To view, visit https://review.coreboot.org/c/coreboot/+/47015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifec4e1360bd1aff3825bc6413b0a2ccd8b822075 Gerrit-Change-Number: 47015 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: amdfwtool: Fix the gcc warning about sign comparison
by Bao Zheng (Code Review) 06 Nov '20

06 Nov '20

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45893 to review the following change. Change subject: amdfwtool: Fix the gcc warning about sign comparison ...................................................................... amdfwtool: Fix the gcc warning about sign comparison New (maybe) compile tool complains the warning below. warning: comparison between signed and unsigned integer expressions [-Wsign-compare] Fix all of them. Change-Id: I59624326233284e6c3595df49625563254949c45 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/45893/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index f385068..e6341a7 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -646,7 +646,7 @@ return -2; } - if (fd_stat.st_size > room) { + if ((size_t)fd_stat.st_size > room) { printf("Error: %s will not fit. Exiting.\n", src_file); close(fd); return -3; @@ -667,7 +667,7 @@ amd_fw_entry *fw_table) { ssize_t bytes; - int i; + uint32_t i; ctx->current += sizeof(embedded_firmware); ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT); @@ -841,7 +841,7 @@ static int locate_bdt2_bios(bios_directory_table *level2, uint64_t *source, uint32_t *size) { - int i; + uint32_t i; *source = 0; *size = 0; @@ -1154,7 +1154,7 @@ static void register_fw_fuse(char *str) { - int i; + uint32_t i; for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { if (amd_psp_fw_table[i].type != AMD_PSP_FUSE_CHAIN) @@ -1167,7 +1167,7 @@ static void register_fw_token_unlock(void) { - int i; + uint32_t i; for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { if (amd_psp_fw_table[i].type != AMD_TOKEN_UNLOCK) @@ -1202,7 +1202,7 @@ static void register_bdt_data(amd_bios_type type, int sub, int ins, char name[]) { - int i; + uint32_t i; for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) { if (amd_bios_table[i].type == type @@ -1217,7 +1217,7 @@ static void register_fw_addr(amd_bios_type type, char *src_str, char *dst_str, char *size_str) { - int i; + uint32_t i; for (i = 0; i < sizeof(amd_bios_table) / sizeof(amd_bios_entry); i++) { if (amd_bios_table[i].type != type) continue; -- To view, visit https://review.coreboot.org/c/coreboot/+/45893 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59624326233284e6c3595df49625563254949c45 Gerrit-Change-Number: 45893 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: soc/intel/tigerlake: Disable C1 Cstate Demotion
by Ravishankar Sarawadi (Code Review) 05 Nov '20

05 Nov '20

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46438 ) Change subject: soc/intel/tigerlake: Disable C1 Cstate Demotion ...................................................................... soc/intel/tigerlake: Disable C1 Cstate Demotion Disable C1 state auto demotion to improve SoC power. When set, processor will conditionally demote C3/C6/C7 requests to C1 based on uncore auto-demote information. BUG=b:161215906 TEST=Measure and confirm power usage reduction for key use cases eg 'Google Meets video call' Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Signed-off-by: Shweta Malik <shweta.malik(a)intel.com> Change-Id: I649cafbaf03917d76521aa5f76ec58d218e1a1b1 --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/46438/1 diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 38f444b..f9f17f8 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -357,6 +357,10 @@ /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ params->EnableMultiPhaseSiliconInit = 1; + + /* Disable C1 Cstate Demotion */ + params->C1StateAutoDemotion = 0; + mainboard_silicon_init_params(params); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I649cafbaf03917d76521aa5f76ec58d218e1a1b1 Gerrit-Change-Number: 46438 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-MessageType: newchange

3 19

Change in coreboot[master]: [RFC]mb/ocp/deltalake: append Linuxboot command line option
by Jonathan Zhang (Code Review) 05 Nov '20

05 Nov '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47055 ) Change subject: [RFC]mb/ocp/deltalake: append Linuxboot command line option ...................................................................... [RFC]mb/ocp/deltalake: append Linuxboot command line option If Linuxboot is used as payload, and if corresponding VPD variable is set, use the value to append Linuxboot command line option as defined at build time. With this, user can customize linuxboot boot behavior without needing a different image. For example, user can increase log level. Note that this code should not be in mainboard, I hope to get community feedback on where it should be. TESTED=tested on DeltaLake, with this VPD setting: vpd -f build/coreboot.rom -i RW_VPD -s linux_command_line="loglevel=7 cpuidle.off=1" Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Bryant Ou <Bryant.Ou.Q(a)gmail.com> Change-Id: I5f5cde3957c2716864f55d70f18f47b493164ed8 --- M src/mainboard/ocp/deltalake/ramstage.c M src/mainboard/ocp/deltalake/vpd.h 2 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/47055/1 diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 9d57090..800ad5a 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -5,11 +5,13 @@ #include <bootstate.h> #include <drivers/ipmi/ipmi_ops.h> #include <drivers/ocp/dmi/ocp_dmi.h> +#include <drivers/vpd/vpd.h> #include <gpio.h> #include <soc/lewisburg_pch_gpio_defs.h> #include <soc/ramstage.h> #include <soc/soc_util.h> #include <stdio.h> +#include <stdlib.h> #include <string.h> #include <smbios.h> #include <device/pci_def.h> @@ -18,10 +20,15 @@ #include <hob_iiouds.h> #include <hob_memmap.h> #include <cpxsp_dl_gpio.h> +#include <program_loading.h> #include "ipmi.h" +#include "vpd.h" #define SLOT_ID_LEN 2 +/* copied from util/cbfstool/linux_trampoline.h */ +#define COMMAND_LINE_LOC 0x91000 +#define LINUX_CMD_LEN 72 extern struct fru_info_str fru_strings; static char slot_id_str[SLOT_ID_LEN]; @@ -307,3 +314,42 @@ } BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL); + +#if CONFIG_PAYLOAD_LINUX +/* + * If Linuxboot is the payload, and if LINUX_COMMAND_LINE is defined as VPD + * variable, use the value to append original Linux command line option as + * defined at build time + */ +void platform_segment_loaded(uintptr_t start, size_t size, int flags) +{ + if (start != COMMAND_LINE_LOC) + return; + + char cmdline[LINUX_CMD_LEN] = ""; + if (!vpd_gets(LINUX_COMMAND_LINE, cmdline, LINUX_CMD_LEN, VPD_RW_THEN_RO)) + return; + + char *orig_cmdline = strdup((char *)start); + char *new_cmdline = NULL; + size_t new_cmdline_len; + printk(BIOS_INFO, "Build time defined Linux command line: %s\n", + orig_cmdline); + printk(BIOS_INFO, "VPD defined Linux command line: %s\n", cmdline); + + new_cmdline = strconcat(orig_cmdline, " "); + new_cmdline = strconcat(new_cmdline, cmdline); + new_cmdline_len = strlen(new_cmdline); + printk(BIOS_INFO, "Updated Linux command line: %s, len: %ld\n", new_cmdline, new_cmdline_len); + if (new_cmdline_len >= size) { + printk(BIOS_ERR, "Updated Linux command line has size %ld bigger than %ld.\n", + new_cmdline_len, size); + free(new_cmdline); + return; + } + + memset((uint8_t *)start, 0, size); + memcpy((uint8_t *)start, new_cmdline, strlen(new_cmdline)); + free(new_cmdline); +} +#endif diff --git a/src/mainboard/ocp/deltalake/vpd.h b/src/mainboard/ocp/deltalake/vpd.h index 43070c2..cb9588b 100644 --- a/src/mainboard/ocp/deltalake/vpd.h +++ b/src/mainboard/ocp/deltalake/vpd.h @@ -36,4 +36,7 @@ #define COREBOOT_LOG_LEVEL "coreboot_log_level" #define COREBOOT_LOG_LEVEL_DEFAULT 4 +/* Linuxboot kernel command line */ +#define LINUX_COMMAND_LINE "linux_command_line" + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f5cde3957c2716864f55d70f18f47b493164ed8 Gerrit-Change-Number: 47055 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/msi/ms7707/Kconfig: Drop invalid defaults
by Angel Pons (Code Review) 05 Nov '20

05 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45672 ) Change subject: mb/msi/ms7707/Kconfig: Drop invalid defaults ...................................................................... mb/msi/ms7707/Kconfig: Drop invalid defaults The PCI ID corresponds to the iGPU, which is disabled in the devicetree. Also, the VBIOS file does not exist at the specified location. Change-Id: I4f128d3057dc7218f32320c4e23466eb31af4e54 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/msi/ms7707/Kconfig 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/45672/1 diff --git a/src/mainboard/msi/ms7707/Kconfig b/src/mainboard/msi/ms7707/Kconfig index e6095ba..93a43f9 100644 --- a/src/mainboard/msi/ms7707/Kconfig +++ b/src/mainboard/msi/ms7707/Kconfig @@ -33,12 +33,4 @@ hex default 0x200000 -config VGA_BIOS_FILE - string - default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/vgabios.bin" - -config VGA_BIOS_ID - string - default "8086,0102" - endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f128d3057dc7218f32320c4e23466eb31af4e54 Gerrit-Change-Number: 45672 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in em100[master]: Add install and uninstall targets to Makefile
by Stefan Reinauer (Code Review) 05 Nov '20

05 Nov '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/46927 ) Change subject: Add install and uninstall targets to Makefile ...................................................................... Add install and uninstall targets to Makefile - Will install em100 to /usr/local/bin - Will install udev rule to /etc/udev/rules.d Assumes that there is a plugdev group (some systems may not have it) Signed-off-by: Alexander Amelkin <a.amelkin(a)yadro.com> Change-Id: Ibfcd6f9f2f577b1f7d8d2d4b0a89405d38264d3d --- M Makefile 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/27/46927/1 diff --git a/Makefile b/Makefile index a5b8c33..14c928e 100644 --- a/Makefile +++ b/Makefile @@ -71,6 +71,14 @@ distclean: clean rm -f em100pro_chips.h +install: em100 60-dediprog-em100pro.rules + install -m 644 60-dediprog-em100pro.rules /etc/udev/rules.d/ + install -s -m 750 -g plugdev em100 /usr/local/bin/ + +uninstall: /usr/local/bin/em100 + rm -f /etc/udev/rules.d/60-dediprog-em100pro.rules + rm -f /usr/local/bin/em100 + -include .dependencies .PHONY: clean distclean tarballs -- To view, visit https://review.coreboot.org/c/em100/+/46927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Ibfcd6f9f2f577b1f7d8d2d4b0a89405d38264d3d Gerrit-Change-Number: 46927 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: mb/google/volteer: Add boldar GPIO configuration
by Aamir Bohra (Code Review) 05 Nov '20

05 Nov '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46131 ) Change subject: mb/google/volteer: Add boldar GPIO configuration ...................................................................... mb/google/volteer: Add boldar GPIO configuration Change-Id: I214a615e8104c181c96c88dae6bd9278ed6250ab Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- A src/mainboard/google/volteer/variants/boldar/Makefile.inc A src/mainboard/google/volteer/variants/boldar/gpio.c 2 files changed, 301 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46131/1 diff --git a/src/mainboard/google/volteer/variants/boldar/Makefile.inc b/src/mainboard/google/volteer/variants/boldar/Makefile.inc new file mode 100644 index 0000000..13269db --- /dev/null +++ b/src/mainboard/google/volteer/variants/boldar/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/boldar/gpio.c b/src/mainboard/google/volteer/variants/boldar/gpio.c new file mode 100644 index 0000000..f429adf --- /dev/null +++ b/src/mainboard/google/volteer/variants/boldar/gpio.c @@ -0,0 +1,296 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + + /* A5 : USB_C0_AUXP_DC */ + PAD_CFG_GPO(GPP_A5, 1, DEEP), + /* A6 : USB_C0_AUXN_DC */ + PAD_CFG_GPO(GPP_A6, 1, DEEP), + /* A8 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_A8, NONE, DEEP), + /* A9 : ESPI_CLK */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* A10 : ESPI_RST_L */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* A13 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A21 : EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A23, 1, DEEP), + + /* B3 : PEN_DET_ODL */ + PAD_CFG_GPI(GPP_B3, NONE, DEEP), + /* B4 : WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* B5 : ISH_I2C0_CVF_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + /* B6 : ISH_I2C0_CVF_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* B7 : ISH_I2C0_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_I2C0_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* B9 : NC */ + PAD_NC(GPP_B9, UP_20K), + /* B10 : NC */ + PAD_NC(GPP_B10, UP_20K), + /* B15 : FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, LEVEL), + /* B16 : PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + /* B17 : PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + /* B18 : EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_B18, 1, DEEP), + /* B19 : NC */ + PAD_NC(GPP_B19, UP_20K), + /* B20 : NC */ + PAD_NC(GPP_B20, UP_20K), + /* B21 : NC */ + PAD_NC(GPP_B21, UP_20K), + /* B22 : NC */ + PAD_NC(GPP_B22, UP_20K), + + /* C0 : EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : USI_RST_L */ + PAD_CFG_GPO(GPP_C1, 0, DEEP), + /* C3 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C3, NONE, PLTRST, LEVEL, INVERT) + /* C4 : EN_PP5000_PEN */ + PAD_CFG_GPO(GPP_C4, 1, DEEP), + /* C7 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + + /* D0 : SSD_RTD3_EN */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), + /* D1 : ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, NONE, DEEP), + /* D2 : ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* D3 : ISH_ALS_RGB_INT_L */ + PAD_CFG_GPI(GPP_D3, NONE, DEEP), + /* D4 : FCAM_RST_L */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* D6 : WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D8 : SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D9 : SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_D9, NONE, DEEP), + /* D10 : EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_D10, 1, DEEP), + /* D11 : PEN_ALERT_ODL */ + PAD_CFG_GPI(GPP_D11, NONE, DEEP), + /* D12 : PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_D12, 0, DEEP) + /* D13 : UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : EN_PP3300_SD */ + PAD_NC(GPP_D16, UP_20K), + /* D17 : EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 0, DEEP), + /* D18 : FCAM_SNRPWR_EN */ + PAD_CFG_GPO(GPP_D18, 0, DEEP), + + /* E1 : PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E2 : WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 0, DEEP), + /* E7 : USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E8 : SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + + /* E10 : PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + /* E11 : PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + /* E12 : PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + /* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + /* E15 : TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E16 : WWAN_SIM1_DET_OD */ + PAD_CFG_GPI(GPP_E16, NONE, DEEP), + /* E17 : WWAN_PERST_L */ + PAD_CFG_GPO(GPP_E17, 1, DEEP), + + /* F6 : WWAN_CONFIG3 */ + PAD_CFG_GPI(GPP_F6, NONE, DEEP), + /* A7 : EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_F7, 1, DEEP), + /* F9 : HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, EDGE_BOTH), + /* F10 : EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), + /* F11 : PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), + /* F12 : PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), + /* F13 : PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), + /* F14 : WLAN_RST_ODL */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F15 : RCAM_RST_L */ + PAD_CFG_GPO(GPP_F15, 1, DEEP), + /* F16 : PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_F17, 1, DEEP), + /* F18 : WWAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), + /* F19 : WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + /* F20 : WWAN_RST_ODL */ + PAD_CFG_GPI(GPP_F20, NONE, DEEP), + /* F21 : WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), + + /* H3 : SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H4 : PCH_I2C0_MISC_SCL */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : PCH_I2C0_MISC_SDA */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : PCH_I2C1_CAM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : PCH_I2C1_CAM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : WWAN_WLAN_COEX1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* H9 : WWAN_WLAN_COEX2 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + /* H10 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + /* H11 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + /* H12 : WWAN_CONFIG0 */ + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + /* H14 : RCAM_SNRPWR_EN */ + PAD_CFG_GPO(GPP_H13, 0, DEEP), + /* H15 : DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : USB_C1_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_H19, 1, DEEP), + /* H20 : EN_MIPI_RCAM_PWR */ + PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* H21 : CAM_MCLK1 */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* H22 : CAM_MCLK0 */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + + /* R0 : I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R4 : DMIC_CLK0 */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), + /* R5 : DMIC_DATA0 */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), + /* R6 : WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1), + /* R7 : SAR0_INT_L */ + PAD_CFG_GPI_APIC(GPP_R7, NONE, PLTRST, LEVEL, NONE), + + /* S0 : I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), + /* S1 : I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF2), + /* S2 : I2S1_PCH_TX_SPKR_RX */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF3), + /* S3 : I2S1_PCH_TX_SPKR_RX */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF3), + /* S5 : SPKR_INT_L */ + PAD_CFG_GPI_APIC(GPP_S5, NONE, PLTRST, LEVEL, NONE), + /* S6 : DMIC_CLK1 */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), + /* S7 : DMIC_DATA1 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + + /* A7 : MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_A7, NONE, DEEP), + /* A12 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A17 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* A19 : MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_A19, NONE, DEEP), + /* A20 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_A20, NONE, DEEP), + + /* B11 : PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + + /* C0 : EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C1, NONE, PLTRST, LEVEL, INVERT), + + /* D10 : EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_D10, 1, DEEP), + /* D12 : PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_D12, 0, DEEP), + /* D15 : MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_D15, NONE, DEEP), + /* D16 : EN_PP3300_SD */ + PAD_NC(GPP_D16, UP_20K), + + /* E10 : PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + /* E11 : PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + /* E12 : PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + /* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + + /* F14 : WLAN_PERST_L */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F20 : WWAN_RST_ODL + To meet timing constrains - drive reset low. + Deasserted in ramstage. */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I214a615e8104c181c96c88dae6bd9278ed6250ab Gerrit-Change-Number: 46131 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

5 25

Change in coreboot[master]: haswell: Add Intel TXT support in romstage
by Angel Pons (Code Review) 05 Nov '20

05 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46608 ) Change subject: haswell: Add Intel TXT support in romstage ...................................................................... haswell: Add Intel TXT support in romstage Provide necessary romstage hooks to allow unblocking the memory with SCLEAN. Note that this is slow, and took four minutes with 4 GiB of RAM. Tested on Asrock B85M Pro4 with tboot. When Linux has tboot support compiled in, booting as well as S3 suspend and resume are functional. However, SINIT will TXT reset when the iGPU is enabled, and using a dGPU will result in DMAR-related problems as soon as the IOMMU is enabled. Change-Id: I60beb7d79a30f460bbd5d94e4cba0244318c124e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/romstage.c M src/security/intel/txt/Makefile.inc M src/security/intel/txt/common.c A src/security/intel/txt/romstage.c M src/security/intel/txt/txt.h M src/security/intel/txt/txt_register.h 6 files changed, 200 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46608/1 diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 5b025eb..3227c02 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -4,11 +4,14 @@ #include <console/console.h> #include <cf9_reset.h> #include <device/device.h> +#include <device/mmio.h> #include <timestamp.h> #include <cpu/x86/lapic.h> #include <cbmem.h> #include <commonlib/helpers.h> #include <romstage_handoff.h> +#include <security/intel/txt/txt.h> +#include <security/intel/txt/txt_register.h> #include <cpu/intel/haswell/haswell.h> #include <northbridge/intel/haswell/chip.h> #include <northbridge/intel/haswell/haswell.h> @@ -108,12 +111,27 @@ report_platform_info(); + if (CONFIG(INTEL_TXT)) + intel_txt_romstage_init(); + copy_spd(&pei_data); sdram_initialize(&pei_data); timestamp_add_now(TS_AFTER_INITRAM); + if (CONFIG(INTEL_TXT)) { + printk(BIOS_DEBUG, "Check TXT_ERROR register after MRC\n"); + + intel_txt_log_acm_error(read32((void *)TXT_ERROR)); + + intel_txt_log_spad(); + + intel_txt_memory_has_secrets(); + + txt_dump_regions(); + } + post_code(0x3b); intel_early_me_status(); diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc index 64726cd..f7d6f9c 100644 --- a/src/security/intel/txt/Makefile.inc +++ b/src/security/intel/txt/Makefile.inc @@ -1,6 +1,8 @@ ifeq ($(CONFIG_INTEL_TXT),y) +romstage-y += romstage.c romstage-y += getsec_sclean.S +romstage-y += getsec.c romstage-y += common.c romstage-$(CONFIG_INTEL_TXT_LOGGING) += logging.c diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index 88e2b5d..4dd4ad3 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -290,6 +290,48 @@ return acm_data; } +#define MCU_BASE_ADDR (TXT_BASE + 0x278) +#define BIOACM_ADDR (TXT_BASE + 0x27c) +#define APINIT_ADDR (TXT_BASE + 0x290) +#define SEMAPHORE (TXT_BASE + 0x294) + +/* Returns on failure, resets the computer on success */ +void intel_txt_run_sclean(void) +{ + struct region_device acm; + size_t acm_len; + + void *acm_data = intel_txt_prepare_bios_acm(&acm, &acm_len); + + if (!acm_data) + return; + + /* FIXME: Do we need to program these two? */ + //write32((void *)MCU_BASE_ADDR, 0xffe1a990); + //write32((void *)APINIT_ADDR, 0xfffffff0); + + write32((void *)BIOACM_ADDR, (uintptr_t)acm_data); + write32((void *)SEMAPHORE, 0); + + /* + * The time SCLEAN will take depends on the installed RAM size. + * On Haswell with 8 GiB of DDR3, it takes five or ten minutes. (rough estimate) + */ + printk(BIOS_ALERT, "TEE-TXT: Invoking SCLEAN. This can take several minutes.\n"); + + /* + * Invoke the BIOS ACM. If successful, the system will reset with memory unlocked. + */ + getsec_sclean((uintptr_t)acm_data, acm_len); + + /* + * However, if this function returns, the BIOS ACM could not be invoked. This is bad. + */ + printk(BIOS_CRIT, "TEE-TXT: getsec_sclean could not launch the BIOS ACM.\n"); + + rdev_munmap(&acm, acm_data); +} + /* * Test all bits for TXT execution. * diff --git a/src/security/intel/txt/romstage.c b/src/security/intel/txt/romstage.c new file mode 100644 index 0000000..7a12deb --- /dev/null +++ b/src/security/intel/txt/romstage.c @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/mmio.h> +#include <cf9_reset.h> +#include <console/console.h> +#include <cpu/intel/common/common.h> +#include <cpu/x86/msr.h> +#include <southbridge/intel/common/pmbase.h> +#include <timer.h> +#include <types.h> + +#include <security/tpm/tis.h> + +#include "txt.h" +#include "txt_register.h" +#include "txt_getsec.h" + +static bool is_establishment_bit_asserted(void) +{ + struct stopwatch timer; + uint8_t access; + + /* Spec says no less than 30 milliseconds */ + stopwatch_init_msecs_expire(&timer, 50); + + while (true) { + access = read8((void *)TPM_ACCESS_REG); + + /* Register returns all ones if TPM is missing */ + if (access == 0xff) + return false; + + if (access & TPM_ACCESS_VALID) + break; + + /* On timeout, assume that the TPM is not working */ + if (stopwatch_expired(&timer)) + return false; + } + + /* This bit uses inverted logic: if cleared, establishment is asserted */ + return !(access & TPM_ACCESS_ESTABLISHMENT); +} + +static bool is_txt_cpu(void) +{ + const uint32_t ecx = cpu_get_feature_flags_ecx(); + + return (ecx & (CPUID_SMX | CPUID_VMX)) == (CPUID_SMX | CPUID_VMX); +} + +static bool is_txt_chipset(void) +{ + uint32_t eax; + + const bool success = getsec_capabilities(&eax); + + return success && eax & 1; +} + +/* Print the bad news */ +static void print_memory_is_locked(void) +{ + if (!CONFIG(INTEL_TXT_LOGGING)) + return; + + printk(BIOS_EMERG, "FATAL: Cannot run SCLEAN. Memory will remain locked.\n"); + printk(BIOS_EMERG, "\n"); + printk(BIOS_EMERG, "If you still want to boot, your options are:\n"); + printk(BIOS_EMERG, "\n"); + printk(BIOS_EMERG, " 1. Flash a coreboot image with a valid BIOS ACM.\n"); + printk(BIOS_EMERG, " Then, try again and hope it works this time.\n"); + printk(BIOS_EMERG, "\n"); + printk(BIOS_EMERG, " 2. If possible, remove the TPM from the system.\n"); + printk(BIOS_EMERG, " Reinstalling the TPM might lock memory again.\n"); + printk(BIOS_EMERG, "\n"); + printk(BIOS_EMERG, " 3. Disconnect all power sources, and RTC battery.\n"); + printk(BIOS_EMERG, " This may not work on all TXT-enabled platforms.\n"); + printk(BIOS_EMERG, "\n"); +} + +void intel_txt_romstage_init(void) +{ + /* Bail early if the CPU doesn't support TXT */ + if (!is_txt_cpu()) + return; + + /* We need to use GETSEC here, so enable it */ + enable_getsec_or_reset(); + + if (!is_txt_chipset()) + return; + + const uint8_t txt_ests = read8((void *)TXT_ESTS); + + const bool establishment = is_establishment_bit_asserted(); + const bool is_wake_error = !!(txt_ests & TXT_ESTS_WAKE_ERROR_STS); + + if (CONFIG(INTEL_TXT_LOGGING)) { + + printk(BIOS_INFO, "TEE-TXT: TPM established: %s\n", + establishment ? "true" : "false"); + } + + if (establishment && is_wake_error) { + + printk(BIOS_ERR, "TEE-TXT: Secrets remain in memory. SCLEAN is required.\n"); + + if (txt_ests & TXT_ESTS_TXT_RESET_STS) { + printk(BIOS_ERR, "TEE-TXT: TXT_RESET bit set, doing full reset!\n"); + full_reset(); + } + + /* FIXME: Clear SLP_TYP# */ + write_pmbase32(4, read_pmbase32(4) & ~(0x7 << 10)); + + intel_txt_run_sclean(); + + /* If running the BIOS ACM is impossible, manual intervention is required */ + print_memory_is_locked(); + + /* FIXME: vboot A/B could be used to recover, but has not been tested */ + die("Could not execute BIOS ACM to unlock the memory.\n"); + } +} diff --git a/src/security/intel/txt/txt.h b/src/security/intel/txt/txt.h index fc5c49e..976cc74 100644 --- a/src/security/intel/txt/txt.h +++ b/src/security/intel/txt/txt.h @@ -17,10 +17,13 @@ #define ACM_E_UUID_NOT_MATCH 0x09 #define ACM_E_PLATFORM_IS_NOT_PROD 0x10 +void intel_txt_romstage_init(void); + void intel_txt_log_bios_acm_error(void); int intel_txt_log_acm_error(const uint32_t acm_error); void intel_txt_log_spad(void); bool intel_txt_memory_has_secrets(void); +void intel_txt_run_sclean(void); int intel_txt_run_bios_acm(const u8 input_params); bool intel_txt_prepare_txt_env(void); diff --git a/src/security/intel/txt/txt_register.h b/src/security/intel/txt/txt_register.h index c19ec13..bb735b6 100644 --- a/src/security/intel/txt/txt_register.h +++ b/src/security/intel/txt/txt_register.h @@ -99,6 +99,16 @@ #define TXT_E2STS_SECRET_STS (1ull << 1) /* + * TCG PC Client Platform TPM Profile (PTP) Specification + * + * Note: Only locality 0 registers are publicly accessible. + */ + +#define TPM_BASE 0xfed40000UL + +#define TPM_ACCESS_REG (TPM_BASE + 0x00) + +/* * TXT Memory regions * Chapter 5.3 * Intel Trusted Execution Technology Lab Handout -- To view, visit https://review.coreboot.org/c/coreboot/+/46608 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60beb7d79a30f460bbd5d94e4cba0244318c124e Gerrit-Change-Number: 46608 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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