coreboot-gerrit October 2020

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Change in coreboot[master]: soc/intel/broadwell: Drop unnecessary `sa_dev`
by Angel Pons (Code Review) 16 Dec '20

16 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46982 ) Change subject: soc/intel/broadwell: Drop unnecessary `sa_dev` ...................................................................... soc/intel/broadwell: Drop unnecessary `sa_dev` Change-Id: Icc70adb0c3527a082622fd0ab70888e6cdf6b0ed Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/northbridge.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/46982/1 diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index 5fec655..eb8b5f0 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -268,7 +268,6 @@ uint64_t mc_values[NUM_MAP_ENTRIES]; unsigned long dpr_size = 0; u32 dpr_reg; - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* Read in the MAP registers and report their values */ mc_read_map_entries(dev, &mc_values[0]); @@ -280,7 +279,7 @@ * the DPR register reports the TOP of the region, which is the same * as TSEG base. The region size is reported in MiB in bits 11:4. */ - dpr_reg = pci_read_config32(sa_dev, DPR); + dpr_reg = pci_read_config32(dev, DPR); if (dpr_reg & DPR_EPM) { dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16; printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size); -- To view, visit https://review.coreboot.org/c/coreboot/+/46982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc70adb0c3527a082622fd0ab70888e6cdf6b0ed Gerrit-Change-Number: 46982 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/mediatek/mt8192: Keep CONN MCU in reset state
by Yidi Lin (Code Review) 16 Dec '20

16 Dec '20

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46447 to review the following change. Change subject: soc/mediatek/mt8192: Keep CONN MCU in reset state ...................................................................... soc/mediatek/mt8192: Keep CONN MCU in reset state Keep the CONN MCU in reset state to prevent CONN from asserting the clk26m request to SPM. TEST=clk26m request from conn has been released. Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: Ia1b706da497ba2827341051459c3628e2ae9240f --- M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/46447/1 diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 35e8ff2..cafa1dd 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -306,6 +306,9 @@ DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) +DEFINE_BITFIELD(WDT_SWSYSRST_KEY, 31, 24) +DEFINE_BITFIELD(WDT_SWSYSRST_CONN_MCU, 12, 12) + enum { INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = ((0x1f << 12) | \ (0x1 << 17) | \ diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index 0366cd6..fdd0b1e 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -10,6 +10,7 @@ #include <soc/infracfg.h> #include <soc/mcucfg.h> #include <soc/pll.h> +#include <soc/wdt.h> enum mux_id { TOP_AXI_SEL, @@ -460,6 +461,11 @@ /* enable [14] dramc_pll104m_ck */ setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); + + /* reset CONNSYS MCU */ + SET32_BITFIELDS(&mtk_wdt->wdt_swsysrst, + WDT_SWSYSRST_KEY, 0x88, + WDT_SWSYSRST_CONN_MCU, 1); } void mt_pll_raise_little_cpu_freq(u32 freq) -- To view, visit https://review.coreboot.org/c/coreboot/+/46447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1b706da497ba2827341051459c3628e2ae9240f Gerrit-Change-Number: 46447 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: soc/mediatek/mt8192: Do dramc init settings
by CK HU (Code Review) 16 Dec '20

16 Dec '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44700 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc init settings ...................................................................... soc/mediatek/mt8192: Do dramc init settings Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: Ie4877b69de1bfa4ff981d8eb386efbddb9e0f5c2 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_basic_api.c A src/soc/mediatek/mt8192/dramc_pi_main.c A src/soc/mediatek/mt8192/dramc_utility.c M src/soc/mediatek/mt8192/emi.c 5 files changed, 242 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/44700/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index dd80beb..e82f182 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -16,6 +16,7 @@ verstage-y += ../common/uart.c romstage-y += ../common/cbmem.c +romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_utility.c romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c new file mode 100644 index 0000000..9b1216c --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> +#include <string.h> +#include <timer.h> + +void global_option_init(struct ddr_cali *cali) +{ +} + +void dfs_init_for_calibration(const struct ddr_cali *cali) +{ +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c new file mode 100644 index 0000000..e2c7500 --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> +#include <soc/mt6359p.h> + +static void set_vcore_voltage_for_each_freq(const struct ddr_cali *cali) +{ + u32 vcore = get_vcore_value(cali); + + dramc_info("Set DRAM vcore voltage to %u\n", vcore); + mt6359p_buck_set_voltage(MT6359P_GPU11, vcore); +} + +static void dramc_calibration_all_channels(struct ddr_cali *cali) +{ +} + +void init_dram(const struct dramc_data *dparam) +{ + u32 bc_bak; + u8 k_shuffle, k_shuffle_end; + u8 pll_mode = 0; + bool first_freq_k = true; + + struct ddr_cali cali = {0}; + struct mr_values mr_value; + const struct ddr_base_info *ddr_info = &dparam->ddr_info; + + cali.pll_mode = &pll_mode; + cali.mr_value = &mr_value; + cali.support_ranks = ddr_info->support_ranks; + cali.cbt_mode[RANK_0] = ddr_info->cbt_mode[RANK_0]; + cali.cbt_mode[RANK_1] = ddr_info->cbt_mode[RANK_1]; + cali.emi_config = &ddr_info->emi_config; + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + global_option_init(&cali); + bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + dramc_set_broadcast(bc_bak); + + if (ddr_info->config_dvfs == DRAMC_ENABLE_DVFS) + k_shuffle_end = CALI_SEQ_MAX; + else + k_shuffle_end = CALI_SEQ1; + + for (k_shuffle = CALI_SEQ0; k_shuffle < k_shuffle_end; k_shuffle++) { + set_cali_datas(&cali, dparam, k_shuffle); + set_vcore_voltage_for_each_freq(&cali); + dfs_init_for_calibration(&cali); + + dramc_calibration_all_channels(&cali); + + first_freq_k= false; + } +} diff --git a/src/soc/mediatek/mt8192/dramc_utility.c b/src/soc/mediatek/mt8192/dramc_utility.c new file mode 100644 index 0000000..526059a --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_utility.c @@ -0,0 +1,166 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> +#include <soc/infracfg.h> + +struct dfs_frequency_table { + u32 frequency; + dram_freq_grp freq_group; + dram_div_mode div_mode; + dram_dfs_shu shuffle_saved; + vref_cali_mode vref_cali; + u32 vcore; +}; + +static const struct dfs_frequency_table freq_shuffle_table[DRAM_DFS_SHU_MAX] = { + /* frequency freq_group div_mode shuffle_saved vref_cali vcore*/ + [CALI_SEQ0] = {800, DDRFREQ_800, DIV8_MODE, DRAM_DFS_SHU4, VREF_CALI_ON, 650000}, + [CALI_SEQ1] = {1200, DDRFREQ_1200, DIV8_MODE, DRAM_DFS_SHU2, VREF_CALI_ON, 662500}, + [CALI_SEQ2] = {600, DDRFREQ_600, DIV8_MODE, DRAM_DFS_SHU5, VREF_CALI_OFF, 650000}, + [CALI_SEQ3] = {933, DDRFREQ_933, DIV8_MODE, DRAM_DFS_SHU3, VREF_CALI_OFF, 662500}, + [CALI_SEQ4] = {400, DDRFREQ_400, DIV4_MODE, DRAM_DFS_SHU6, VREF_CALI_OFF, 650000}, + [CALI_SEQ5] = {2133, DDRFREQ_2133, DIV8_MODE, DRAM_DFS_SHU0, VREF_CALI_ON, 725000}, + [CALI_SEQ6] = {1600, DDRFREQ_1600, DIV8_MODE, DRAM_DFS_SHU1, VREF_CALI_OFF, 687500}, +}; + +void dramc_set_broadcast(u32 onoff) +{ + write32(&mt8192_infracfg->dramc_wbr, onoff); +} + +u32 dramc_get_broadcast(void) +{ + return read32(&mt8192_infracfg->dramc_wbr); +} + +u8 get_fsp(const struct ddr_cali *cali) +{ + return cali->fsp; +} + +dram_div_mode get_div_mode(const struct ddr_cali *cali) +{ + return cali->div_mode; +} + +dram_freq_grp get_freq_group(const struct ddr_cali *cali) +{ + return cali->freq_group; +} + +dbi_mode get_write_dbi(const struct ddr_cali *cali) +{ + return cali->w_dbi[get_fsp(cali)]; +} + +dram_odt_state get_odt_state(const struct ddr_cali *cali) +{ + return cali->odt_onoff; +} + +dram_dfs_shu get_shu(const struct ddr_cali *cali) +{ + return cali->shu; +} + +dram_cbt_mode get_cbt_mode(const struct ddr_cali *cali) +{ + return cali->cbt_mode[cali->rank]; +} + +u32 get_vcore_value(const struct ddr_cali *cali) +{ + return cali->vcore_voltage; +} + +u32 get_frequency(const struct ddr_cali *cali) +{ + return cali->frequency; +} + +vref_cali_mode get_vref_cali(const struct ddr_cali *cali) +{ + return cali->vref_cali; +} + +dram_pinmux_type get_pinmux_type(const struct ddr_cali *cali) +{ + return cali->pinmux_type; +} + +u8 get_mck2ui_div_shift(const struct ddr_cali *cali) +{ + if (get_div_mode(cali) == DIV4_MODE) + return 2; + else + return 3; +} + +dram_dfs_shu get_shu_save_by_k_shu(dram_cali_seq k_shu) +{ + return freq_shuffle_table[k_shu].shuffle_saved; +} + +dram_freq_grp get_freq_group_by_shu_save(dram_dfs_shu shu) +{ + for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++) + if (freq_shuffle_table[k_shu].shuffle_saved == shu) + return freq_shuffle_table[k_shu].freq_group; + + dramc_err("Invalid shuffle:%d\n", shu); + return DDRFREQ_800; +} + +u32 get_frequency_by_shu(dram_dfs_shu shu) +{ + for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++) + if (freq_shuffle_table[k_shu].shuffle_saved == shu) + return freq_shuffle_table[k_shu].frequency; + + dramc_err("Invalid shuffle:%d\n", shu); + return 800; +} + +dram_freq_grp get_highest_freq_group(void) +{ + dram_freq_grp highest_freq = DDRFREQ_800; + + for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++) + if (freq_shuffle_table[k_shu].freq_group > highest_freq) + highest_freq = freq_shuffle_table[k_shu].freq_group; + + dramc_dbg("Highest freq is :%d\n", highest_freq); + return highest_freq; +} + +void set_cali_datas(struct ddr_cali *cali, const struct dramc_data *dparam, dram_cali_seq k_shu) +{ + cali->chn = CHANNEL_A; + cali->rank = RANK_0; + cali->fsp = (freq_shuffle_table[k_shu].freq_group < DDRFREQ_1600) ? FSP_0 : FSP_1; + cali->w_dbi[FSP_0] = DBI_OFF; + cali->w_dbi[FSP_1] = DBI_ON; + cali->frequency = freq_shuffle_table[k_shu].frequency; + cali->freq_group = freq_shuffle_table[k_shu].freq_group; + cali->div_mode = freq_shuffle_table[k_shu].div_mode; + cali->shu = freq_shuffle_table[k_shu].shuffle_saved; + cali->vref_cali = freq_shuffle_table[k_shu].vref_cali; + cali->vcore_voltage = freq_shuffle_table[k_shu].vcore; + cali->odt_onoff = (cali->fsp == FSP_0) ? ODT_OFF : ODT_ON; + cali->params = &dparam->freq_params[cali->shu]; + + dramc_dbg("cali data(size:%ld) use fsp:%d, freq_group:%d, div_mode:%d, shu:%d, vref_cali:%d, odt_onoff:%d, vcore:%d\n", + sizeof(*cali), cali->fsp, cali->freq_group, cali->div_mode, cali->shu, + cali->vref_cali, cali->odt_onoff, cali->vcore_voltage); +} + +void dramc_auto_refresh_switch(u8 chn, bool enable) +{ + SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, enable ? 0 : 1); + + if (!enable) { + udelay(READ32_BITFIELD(&ch[chn].nao.misc_statusa, + MISC_STATUSA_REFRESH_QUEUE_CNT)); + } +} diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c index 9e48918..f83acd3 100644 --- a/src/soc/mediatek/mt8192/emi.c +++ b/src/soc/mediatek/mt8192/emi.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/emi.h> +#include <soc/dramc_pi_api.h> size_t sdram_size(void) { @@ -11,4 +11,5 @@ void mt_set_emi(const struct dramc_data *dparam) { + init_dram(dparam); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4877b69de1bfa4ff981d8eb386efbddb9e0f5c2 Gerrit-Change-Number: 44700 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common: Use only byte access for IOMUX
by Kyösti Mälkki (Code Review) 16 Dec '20

16 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42978 ) Change subject: soc/amd/common: Use only byte access for IOMUX ...................................................................... soc/amd/common: Use only byte access for IOMUX Change-Id: Ia3c4fb41b5851b1c0ffc6bbec7d1c051e232fc94 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h 1 file changed, 2 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/42978/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index e684e36..34300af 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -239,36 +239,18 @@ write8(acpimmio_smbus + reg, value); } +/* These iomux_read/write8 are to be deprecated to enforce proper + use of <gpio.h> API for pin configurations. */ static inline uint8_t iomux_read8(uint8_t reg) { return read8(acpimmio_iomux + reg); } -static inline uint16_t iomux_read16(uint8_t reg) -{ - return read16(acpimmio_iomux + reg); -} - -static inline uint32_t iomux_read32(uint8_t reg) -{ - return read32(acpimmio_iomux + reg); -} - static inline void iomux_write8(uint8_t reg, uint8_t value) { write8(acpimmio_iomux + reg, value); } -static inline void iomux_write16(uint8_t reg, uint16_t value) -{ - write16(acpimmio_iomux + reg, value); -} - -static inline void iomux_write32(uint8_t reg, uint32_t value) -{ - write32(acpimmio_iomux + reg, value); -} - static inline uint8_t misc_read8(uint8_t reg) { return read8(acpimmio_misc + reg); -- To view, visit https://review.coreboot.org/c/coreboot/+/42978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3c4fb41b5851b1c0ffc6bbec7d1c051e232fc94 Gerrit-Change-Number: 42978 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP: dcm: mt8192: Enable DCM
by Yidi Lin (Code Review) 16 Dec '20

16 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46407 ) Change subject: WIP: dcm: mt8192: Enable DCM ...................................................................... WIP: dcm: mt8192: Enable DCM Enable DCM settings. /* INFRACFG_AO */ dcm_infracfg_ao_aximem_bus_dcm(on); dcm_infracfg_ao_infra_bus_dcm(on); dcm_infracfg_ao_infra_conn_bus_dcm(on); dcm_infracfg_ao_infra_rx_p2p_dcm(on); dcm_infracfg_ao_peri_bus_dcm(on); dcm_infracfg_ao_peri_module_dcm(on); /* INFRA_AO_BCRM */ dcm_infra_ao_bcrm_infra_bus_dcm(on); dcm_infra_ao_bcrm_peri_bus_dcm(on); /* INFRACFG_AO_MEM */ /* move to preloader */ /* dcm_infracfg_ao_mem_dcm_emi_group(on); */ Change-Id: I5528d176b6bb1f9a5960de981766235510e6ebf1 --- M src/soc/mediatek/mt8192/include/soc/pll.h M src/soc/mediatek/mt8192/pll.c 2 files changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/46407/1 diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 09c4c471..35e8ff2 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -306,4 +306,59 @@ DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) +enum { + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = ((0x1f << 12) | \ + (0x1 << 17) | \ + (0x1 << 18)), + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON = ((0x10 << 12) | \ + (0x1 << 17) | \ + (0x0 << 18)), + INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK = ((0x1 << 0) | \ + (0x1 << 1) | \ + (0x1 << 3) | \ + (0x1 << 4) | \ + (0x1f << 5) | \ + (0x1f << 10) | \ + (0x1 << 20) | \ + (0x1 << 23) | \ + (0x1 << 30)), + INFRACFG_AO_INFRA_BUS_DCM_REG0_ON = ((0x1 << 0) | \ + (0x1 << 1) | \ + (0x0 << 3) | \ + (0x0 << 4) | \ + (0x10 << 5) | \ + (0x1 << 10) | \ + (0x1 << 20) | \ + (0x1 << 23) | \ + (0x1 << 30)), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK = ((0x1 << 8)), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON = ((0x1 << 8)), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK = ((0x1 << 8)), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON = ((0x0 << 8)), + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK = ((0xf << 0)), + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON = ((0x0 << 0)), + INFRACFG_AO_PERI_BUS_DCM_REG0_MASK = ((0x1 << 0) | \ + (0x1 << 1) | \ + (0x1 << 3) | \ + (0x1 << 4) | \ + (0x1f << 5) | \ + (0x1f << 10) | \ + (0x1f << 15) | \ + (0x1 << 20) | \ + (0x1 << 21)), + INFRACFG_AO_PERI_BUS_DCM_REG0_ON = ((0x1 << 0) | \ + (0x1 << 1) | \ + (0x0 << 3) | \ + (0x0 << 4) | \ + (0x1f << 5) | \ + (0x0 << 10) | \ + (0x1f << 15) | \ + (0x1 << 20) | \ + (0x1 << 21)), + INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK = ((0x1 << 29) | \ + (0x1 << 31)), + INFRACFG_AO_PERI_MODULE_DCM_REG0_ON = ((0x1 << 29) | \ + (0x1 << 31)), +}; + #endif /* SOC_MEDIATEK_MT8192_PLL_H */ diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index 24cfafd..0366cd6 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -427,6 +427,27 @@ /* enable infrasys DCM */ setbits32(&mt8192_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); + // dcm_infracfg_ao_aximem_bus_dcm + clrsetbits_le32(&mt8192_infracfg->infra_aximem_idle_bit_en_0, + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK, INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON); + // dcm_infracfg_ao_infra_bus_dcm + clrsetbits_le32(&mt8192_infracfg->infra_bus_dcm_ctrl, + INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK, INFRACFG_AO_INFRA_BUS_DCM_REG0_ON); + // dcm_infracfg_ao_infra_conn_bus_dcm + clrsetbits_le32(&mt8192_infracfg->module_sw_cg_2_set, + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON); + clrsetbits_le32(&mt8192_infracfg->module_sw_cg_2_clr, + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK, INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON); + // dcm_infracfg_ao_infra_rx_p2p_dcm + clrsetbits_le32(&mt8192_infracfg->p2p_rx_clk_on, + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK, INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON); + // dcm_infracfg_ao_peri_bus_dcm + clrsetbits_le32(&mt8192_infracfg->peri_bus_dcm_ctrl, + INFRACFG_AO_PERI_BUS_DCM_REG0_MASK, INFRACFG_AO_PERI_BUS_DCM_REG0_ON); + // dcm_infracfg_ao_peri_module_dcm + clrsetbits_le32(&mt8192_infracfg->peri_bus_dcm_ctrl, + INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK, INFRACFG_AO_PERI_MODULE_DCM_REG0_ON); + /* initialize SPM request */ setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x3ff); clrsetbits32(&mtk_topckgen->clk_scp_cfg_1, 0x100c, 0x3); -- To view, visit https://review.coreboot.org/c/coreboot/+/46407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5528d176b6bb1f9a5960de981766235510e6ebf1 Gerrit-Change-Number: 46407 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-MessageType: newchange

4 47

Change in coreboot[master]: soc/mediatek/mt8192: ufs: disable refer clk
by Yidi Lin (Code Review) 16 Dec '20

16 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46408 ) Change subject: soc/mediatek/mt8192: ufs: disable refer clk ...................................................................... soc/mediatek/mt8192: ufs: disable refer clk ufs refer clk is enabled by default, which will cause the UFSHCI hold the SPM signal and lead to suspend fail. Since ufs kernel driver is not built-in, so disable refer clk in coreboot stage. Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com> Signed-off-by: Chaotian Jing <chaotian.jing(a)mediatek.com> Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ufs.h M src/soc/mediatek/mt8192/soc.c A src/soc/mediatek/mt8192/ufs.c 5 files changed, 33 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46408/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 4ce5e6a..7b098e8 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -48,6 +48,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c ramstage-y += devapc.c +ramstage-y += ufs.c ramstage-y += mcupm.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 19728a3..85eac5b 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -47,6 +47,7 @@ SPI7_BASE = IO_PHYS + 0x0101E000, SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00, SFLASH_REG_BASE = IO_PHYS + 0x01234000, + UFSHCI_BASE = IO_PHYS + 0x01270000, EFUSEC_BASE = IO_PHYS + 0x01C10000, IOCFG_RM_BASE = IO_PHYS + 0x01C20000, IOCFG_BM_BASE = IO_PHYS + 0x01D10000, diff --git a/src/soc/mediatek/mt8192/include/soc/ufs.h b/src/soc/mediatek/mt8192/include/soc/ufs.h new file mode 100644 index 0000000..259aaf4 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/ufs.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_UFS_H +#define SOC_MEDIATEK_MT8192_UFS_H + +#include <device/mmio.h> +#include <soc/addressmap.h> + +void ufs_disable_refclk(void); + +enum ufshci_offset { + REG_UFS_REFCLK_CTRL = 0x144, +}; + +#define UFS_REFCLK_CTRL (ufshci_base + (unsigned long)REG_UFS_REFCLK_CTRL) + +#endif /* SOC_MEDIATEK_MT8192_UFS_H */ diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index ba153f2..c865e6f 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -6,6 +6,7 @@ #include <symbols.h> #include <soc/devapc.h> #include <soc/mcupm.h> +#include <soc/ufs.h> static void soc_read_resources(struct device *dev) { @@ -16,7 +17,8 @@ { mtk_mmu_disable_l2c_sram(); dapc_init(); - mcupm_init(); + mcupm_init(); + ufs_disable_refclk(); } static struct device_operations soc_ops = { diff --git a/src/soc/mediatek/mt8192/ufs.c b/src/soc/mediatek/mt8192/ufs.c new file mode 100644 index 0000000..854ef4c --- /dev/null +++ b/src/soc/mediatek/mt8192/ufs.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ufs.h> + +static unsigned long ufshci_base = (unsigned long)UFSHCI_BASE; + +void ufs_disable_refclk(void) +{ + /* disable ref clock to let UFSHCI release SPM signal */ + write32((void*)UFS_REFCLK_CTRL, 0); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0 Gerrit-Change-Number: 46408 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 31

Change in coreboot[master]: soc/mediatek/mt8192: Initialize audio pll tuner frequency
by Yidi Lin (Code Review) 16 Dec '20

16 Dec '20

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46400 to review the following change. Change subject: soc/mediatek/mt8192: Initialize audio pll tuner frequency ...................................................................... soc/mediatek/mt8192: Initialize audio pll tuner frequency Add AUDPLL TUNER init code. TEST=Boots correctly on MT8192EVB. Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> Change-Id: I1f1b5b55a0a16d42311b16b89b15b31e1aa04670 --- M src/soc/mediatek/mt8192/pll.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/46400/1 diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index 11750d2..24cfafd 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -392,6 +392,10 @@ for (i = 0; i < ARRAY_SIZE(rates); i++) pll_set_rate(&plls[rates[i].id], rates[i].rate); + /* AUDPLL Tuner Frequency Set */ + write32(&mtk_apmixed->apll1_tuner_con0, read32(&mtk_apmixed->apll1_con2) + 1); + write32(&mtk_apmixed->apll2_tuner_con0, read32(&mtk_apmixed->apll2_con2) + 1); + /* xPLL Frequency Enable */ for (i = 0; i < APMIXED_PLL_MAX; i++) { if (i == APMIXED_USBPLL) -- To view, visit https://review.coreboot.org/c/coreboot/+/46400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f1b5b55a0a16d42311b16b89b15b31e1aa04670 Gerrit-Change-Number: 46400 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: [WIP] soc/amd/common/block/acpimmio: Redo acpimmio for psp_verstage a...
by Kyösti Mälkki (Code Review) 15 Dec '20

15 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42523 ) Change subject: [WIP] soc/amd/common/block/acpimmio: Redo acpimmio for psp_verstage again ...................................................................... [WIP] soc/amd/common/block/acpimmio: Redo acpimmio for psp_verstage again Change-Id: I3cb1b5a90023ebc4359835be716c5e3f9451df60 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/Makefile.inc M src/soc/amd/common/block/acpimmio/mmio_util.c D src/soc/amd/common/block/acpimmio/mmio_util_psp.c A src/soc/amd/common/block/acpimmio/psp_verstage_stub.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h D src/soc/amd/common/block/include/amdblocks/acpimmio_psp.h 7 files changed, 67 insertions(+), 245 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/42523/1 diff --git a/src/soc/amd/common/block/acpimmio/Makefile.inc b/src/soc/amd/common/block/acpimmio/Makefile.inc index 13864e4..28d78d5 100644 --- a/src/soc/amd/common/block/acpimmio/Makefile.inc +++ b/src/soc/amd/common/block/acpimmio/Makefile.inc @@ -13,5 +13,5 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO),y) verstage-$(CONFIG_ARCH_VERSTAGE_X86_32) += biosram.c verstage-$(CONFIG_ARCH_VERSTAGE_X86_32) += mmio_util.c -verstage-$(CONFIG_ARCH_VERSTAGE_ARM) += mmio_util_psp.c +verstage-$(CONFIG_ARCH_VERSTAGE_ARM) += mmio_util.c endif diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index c5f82f9..2bfa878 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -2,9 +2,12 @@ #include <types.h> #include <arch/io.h> -#include <amdblocks/acpimmio_map.h> #include <amdblocks/acpimmio.h> +#if CONSTANT_ACPIMMIO_BASE_ADDRESS +#include <amdblocks/acpimmio_map.h> +#endif + DECLARE_ACPIMMIO(acpimmio_sm_pci, SM_PCI); DECLARE_ACPIMMIO(acpimmio_gpio_100, GPIO_100); DECLARE_ACPIMMIO(acpimmio_smi, SMI); diff --git a/src/soc/amd/common/block/acpimmio/mmio_util_psp.c b/src/soc/amd/common/block/acpimmio/mmio_util_psp.c deleted file mode 100644 index 75f71e4..0000000 --- a/src/soc/amd/common/block/acpimmio/mmio_util_psp.c +++ /dev/null @@ -1,163 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -#include <arch/io.h> -#include <device/mmio.h> -#include <amdblocks/acpimmio.h> - -static uintptr_t iomux_bar; - -void iomux_set_bar(void *bar) -{ - iomux_bar = (uintptr_t)bar; -} - -u8 iomux_read8(u8 reg) -{ - return read8((void *)(iomux_bar + reg)); -} - -u16 iomux_read16(u8 reg) -{ - return read16((void *)(iomux_bar + reg)); -} - -u32 iomux_read32(u8 reg) -{ - return read32((void *)(iomux_bar + reg)); -} - -void iomux_write8(u8 reg, u8 value) -{ - write8((void *)(iomux_bar + reg), value); -} - -void iomux_write16(u8 reg, u16 value) -{ - write16((void *)(iomux_bar + reg), value); -} - -void iomux_write32(u8 reg, u32 value) -{ - write32((void *)(iomux_bar + reg), value); -} - -static uintptr_t misc_bar; - -void misc_set_bar(void *bar) -{ - misc_bar = (uintptr_t)bar; -} - -u8 misc_read8(u8 reg) -{ - return read8((void *)(misc_bar + reg)); -} - -u16 misc_read16(u8 reg) -{ - return read16((void *)(misc_bar + reg)); -} - -u32 misc_read32(u8 reg) -{ - return read32((void *)(misc_bar + reg)); -} - -void misc_write8(u8 reg, u8 value) -{ - write8((void *)(misc_bar + reg), value); -} - -void misc_write16(u8 reg, u16 value) -{ - write16((void *)(misc_bar + reg), value); -} - -void misc_write32(u8 reg, u32 value) -{ - write32((void *)(misc_bar + reg), value); -} - -static uintptr_t gpio_bar; - -void gpio_set_bar(void *bar) -{ - gpio_bar = (uintptr_t)bar; -} - -void *gpio_get_bar(void) -{ - return (void *)gpio_bar; -} - -static uintptr_t aoac_bar; - -void aoac_set_bar(void *bar) -{ - aoac_bar = (uintptr_t)bar; -} - -u8 aoac_read8(u8 reg) -{ - return read8((void *)(aoac_bar + reg)); -} - -void aoac_write8(u8 reg, u8 value) -{ - write8((void *)(aoac_bar + reg), value); -} - -static uintptr_t io_bar; - -void io_set_bar(void *bar) -{ - io_bar = (uintptr_t)bar; -} - -u8 io_read8(u16 reg) -{ - return read8((void *)(io_bar + reg)); -} - -void io_write8(u16 reg, u8 value) -{ - write8((void *)(io_bar + reg), value); -} - -/* PM registers are accessed a byte at a time via CD6/CD7 */ -uint8_t pm_io_read8(uint8_t reg) -{ - outb(reg, PM_INDEX); - return inb(PM_DATA); -} - -uint16_t pm_io_read16(uint8_t reg) -{ - return (pm_io_read8(reg + sizeof(uint8_t)) << 8) | pm_io_read8(reg); -} - -uint32_t pm_io_read32(uint8_t reg) -{ - return (pm_io_read16(reg + sizeof(uint16_t)) << 16) | pm_io_read16(reg); -} - -void pm_io_write8(uint8_t reg, uint8_t value) -{ - outb(reg, PM_INDEX); - outb(value, PM_DATA); -} - -void pm_io_write16(uint8_t reg, uint16_t value) -{ - pm_io_write8(reg, value & 0xff); - value >>= 8; - pm_io_write8(reg + sizeof(uint8_t), value & 0xff); -} - -void pm_io_write32(uint8_t reg, uint32_t value) -{ - pm_io_write16(reg, value & 0xffff); - value >>= 16; - pm_io_write16(reg + sizeof(uint16_t), value & 0xffff); -} diff --git a/src/soc/amd/common/block/acpimmio/psp_verstage_stub.c b/src/soc/amd/common/block/acpimmio/psp_verstage_stub.c new file mode 100644 index 0000000..9c74f8f --- /dev/null +++ b/src/soc/amd/common/block/acpimmio/psp_verstage_stub.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpimmio.h> + +static void iomux_set_bar(void *bar) +{ + acpimmio_iomux_bar = bar; +} + +static void misc_set_bar(void *bar) +{ + acpimmio_misc_bar = bar; +} + +static void gpio_set_bar(void *bar) +{ + acpimmio_gpio0_bar = bar; +} + +static void aoac_set_bar(void *bar) +{ + acpimmio_aoac_bar = bar; +} + +static void io_set_bar(void *bar) +{ + acpimmio_io_bar = bar; +} diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 3caed11..3f00ae2 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -6,6 +6,40 @@ #include <device/mmio.h> #include <types.h> +/* For x86 base is constant, while PSP does mapping runtime. */ +#define CONSTANT_ACPIMMIO_BASE_ADDRESS ENV_X86 + +#if CONSTANT_ACPIMMIO_BASE_ADDRESS +#define MAYBE_CONST const +#define DECLARE_ACPIMMIO(ptr, bank) \ + uint8_t *const ptr = (void *)(AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## bank ## _BANK) +#else +#define MAYBE_CONST +#define DECLARE_ACPIMMIO(ptr, bank) uint8_t *ptr +#endif + +extern uint8_t *MAYBE_CONST acpimmio_gpio_100; +extern uint8_t *MAYBE_CONST acpimmio_sm_pci; +extern uint8_t *MAYBE_CONST acpimmio_smi; +extern uint8_t *MAYBE_CONST acpimmio_pmio; +extern uint8_t *MAYBE_CONST acpimmio_pmio2; +extern uint8_t *MAYBE_CONST acpimmio_biosram; +extern uint8_t *MAYBE_CONST acpimmio_cmosram; +extern uint8_t *MAYBE_CONST acpimmio_cmos; +extern uint8_t *MAYBE_CONST acpimmio_acpi; +extern uint8_t *MAYBE_CONST acpimmio_asf; +extern uint8_t *MAYBE_CONST acpimmio_smbus; +extern uint8_t *MAYBE_CONST acpimmio_wdt; +extern uint8_t *MAYBE_CONST acpimmio_hpet; +extern uint8_t *MAYBE_CONST acpimmio_iomux; +extern uint8_t *MAYBE_CONST acpimmio_misc; +extern uint8_t *MAYBE_CONST acpimmio_dpvga; +extern uint8_t *MAYBE_CONST acpimmio_gpio0; +extern uint8_t *MAYBE_CONST acpimmio_xhci_pm; +extern uint8_t *MAYBE_CONST acpimmio_acdc_tmr; +extern uint8_t *MAYBE_CONST acpimmio_aoac; + +#undef MAYBE_CONST /* Enable the AcpiMmio range at 0xfed80000 */ @@ -23,13 +57,6 @@ void pm_io_write16(uint8_t reg, uint16_t value); void pm_io_write32(uint8_t reg, uint32_t value); -#if !ENV_X86 - -#include <amdblocks/acpimmio_psp.h> - -#else - -#include <amdblocks/acpimmio_map.h> static inline uint8_t sm_pci_read8(uint8_t reg) { @@ -384,6 +411,4 @@ write8(acpimmio_aoac + reg, value); } -#endif /* ENV_X86 */ - #endif /* __AMDBLOCKS_ACPIMMIO_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 912e891..5d71287 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -112,20 +112,8 @@ * across family/model products. */ -/* For x86 base is constant, while PSP does mapping runtime. */ -#define CONSTANT_ACPIMMIO_BASE_ADDRESS ENV_X86 - #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 -#if CONSTANT_ACPIMMIO_BASE_ADDRESS -#define MAYBE_CONST const -#define DECLARE_ACPIMMIO(ptr, bank) \ - uint8_t *const ptr = (void *)(AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## bank ## _BANK) -#else -#define MAYBE_CONST -#define DECLARE_ACPIMMIO(ptr, bank) uint8_t *ptr -#endif - #ifdef __ACPI__ /* ASL fails on additions. */ @@ -161,29 +149,6 @@ #define ACPIMMIO_ASF_BASE (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ASF_BANK) #define ACPIMMIO_SMBUS_BASE (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_SMBUS_BANK) -extern uint8_t *MAYBE_CONST acpimmio_gpio_100; -extern uint8_t *MAYBE_CONST acpimmio_sm_pci; -extern uint8_t *MAYBE_CONST acpimmio_smi; -extern uint8_t *MAYBE_CONST acpimmio_pmio; -extern uint8_t *MAYBE_CONST acpimmio_pmio2; -extern uint8_t *MAYBE_CONST acpimmio_biosram; -extern uint8_t *MAYBE_CONST acpimmio_cmosram; -extern uint8_t *MAYBE_CONST acpimmio_cmos; -extern uint8_t *MAYBE_CONST acpimmio_acpi; -extern uint8_t *MAYBE_CONST acpimmio_asf; -extern uint8_t *MAYBE_CONST acpimmio_smbus; -extern uint8_t *MAYBE_CONST acpimmio_wdt; -extern uint8_t *MAYBE_CONST acpimmio_hpet; -extern uint8_t *MAYBE_CONST acpimmio_iomux; -extern uint8_t *MAYBE_CONST acpimmio_misc; -extern uint8_t *MAYBE_CONST acpimmio_dpvga; -extern uint8_t *MAYBE_CONST acpimmio_gpio0; -extern uint8_t *MAYBE_CONST acpimmio_xhci_pm; -extern uint8_t *MAYBE_CONST acpimmio_acdc_tmr; -extern uint8_t *MAYBE_CONST acpimmio_aoac; - -#undef MAYBE_CONST - #endif #endif /* __AMDBLOCKS_ACPIMMIO_MAP_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_psp.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_psp.h deleted file mode 100644 index b8ca7b5..0000000 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_psp.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#ifndef __AMDBLOCKS_ACPIMMIO_PSP_H__ -#define __AMDBLOCKS_ACPIMMIO_PSP_H__ - -#include <device/mmio.h> -#include <types.h> - -void iomux_set_bar(void *bar); -void *iomux_get_bar(void); -void misc_set_bar(void *bar); -void *misc_get_bar(void); -void gpio_set_bar(void *bar); -void *gpio_get_bar(void); -void aoac_set_bar(void *bar); -void *aoac_get_bar(void); -void io_set_bar(void *bar); -u8 io_read8(u16 reg); -void io_write8(u16 reg, u8 value); - -u8 iomux_read8(u8 reg); -u16 iomux_read16(u8 reg); -u32 iomux_read32(u8 reg); -void iomux_write8(u8 reg, u8 value); -void iomux_write16(u8 reg, u16 value); -void iomux_write32(u8 reg, u32 value); -u8 misc_read8(u8 reg); -u16 misc_read16(u8 reg); -u32 misc_read32(u8 reg); -void misc_write8(u8 reg, u8 value); -void misc_write16(u8 reg, u16 value); -void misc_write32(u8 reg, u32 value); -u8 aoac_read8(u8 reg); -void aoac_write8(u8 reg, u8 value); - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/42523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb1b5a90023ebc4359835be716c5e3f9451df60 Gerrit-Change-Number: 42523 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 27

Change in coreboot[master]: soc/amd/common: Move lpc_util to verstage_x86
by Kyösti Mälkki (Code Review) 15 Dec '20

15 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43328 ) Change subject: soc/amd/common: Move lpc_util to verstage_x86 ...................................................................... soc/amd/common: Move lpc_util to verstage_x86 The file seems to be all about PCI configuration access. Change-Id: I1e64d3d7df3caa33ee92961fe7246d03f2707ab4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/lpc/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/43328/1 diff --git a/src/soc/amd/common/block/lpc/Makefile.inc b/src/soc/amd/common/block/lpc/Makefile.inc index 7db176b..b55004c 100644 --- a/src/soc/amd/common/block/lpc/Makefile.inc +++ b/src/soc/amd/common/block/lpc/Makefile.inc @@ -1,7 +1,7 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc.c bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c -verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c +verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c -- To view, visit https://review.coreboot.org/c/coreboot/+/43328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e64d3d7df3caa33ee92961fe7246d03f2707ab4 Gerrit-Change-Number: 43328 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: soc/amd/common: Redo ACPIMMIO_BASE and _BANK
by Kyösti Mälkki (Code Review) 15 Dec '20

15 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42894 ) Change subject: soc/amd/common: Redo ACPIMMIO_BASE and _BANK ...................................................................... soc/amd/common: Redo ACPIMMIO_BASE and _BANK Change-Id: I31f2d04d9fc8bdd9e270fb3cb48d71f215999a50 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h M src/soc/amd/common/block/smbus/sm.c M src/soc/amd/common/block/smbus/smbus.c M src/soc/amd/picasso/acpi/aoac.asl M src/soc/amd/stoneyridge/smbus_spd.c 6 files changed, 16 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/42894/1 diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 5084672..8acd27f 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -5,12 +5,9 @@ #include <amdblocks/acpimmio_map.h> #include <amdblocks/acpimmio.h> -#define ACPI_BANK_PTR(bank) \ - (void *)(uintptr_t)(AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## bank ## _BANK) - #if CONSTANT_ACPIMMIO_BASE_ADDRESS #define DECLARE_ACPIMMIO(ptr, bank) \ - uint8_t *const ptr = ACPI_BANK_PTR(bank) + uint8_t *const ptr = (void *)(uintptr_t)ACPIMMIO_BASE(bank) #else #define DECLARE_ACPIMMIO(ptr, bank) uint8_t *ptr #endif diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 758a5562..e5caefc 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -95,13 +95,10 @@ #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 #ifdef __ACPI__ - -/* ASL fails on additions. */ +/* ASL MemoryFixed32() fails if these are additions. */ #define ACPIMMIO_MISC_BASE 0xfed80e00 #define ACPIMMIO_GPIO0_BASE 0xfed81500 -#define ACPIMMIO_AOAC_BASE 0xfed81e00 - -#else +#endif #define ACPIMMIO_SM_PCI_BANK 0x0000 #define ACPIMMIO_GPIO_100_BANK 0x0100 @@ -126,10 +123,6 @@ #define ACPIMMIO_ACDCTMR_BANK 0x1d00 #define ACPIMMIO_AOAC_BANK 0x1e00 -/* FIXME: Passing host base for SMBUS is not long-term solution. */ -#define ACPIMMIO_ASF_BASE (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ASF_BANK) -#define ACPIMMIO_SMBUS_BASE (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_SMBUS_BANK) - -#endif +#define ACPIMMIO_BASE(bank) (AMD_SB_ACPI_MMIO_ADDR + ACPIMMIO_ ## bank ## _BANK) #endif /* __AMDBLOCKS_ACPIMMIO_MAP_H__ */ diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c index c5c1ed8..f540e97 100644 --- a/src/soc/amd/common/block/smbus/sm.c +++ b/src/soc/amd/common/block/smbus/sm.c @@ -27,9 +27,9 @@ pbus = get_pbus_smbus(dev); res = find_resource(pbus->dev, 0x90); if (res->base == SMB_BASE_ADDR) - return ACPIMMIO_SMBUS_BASE; + return ACPIMMIO_BASE(SMBUS); - return ACPIMMIO_ASF_BASE; + return ACPIMMIO_BASE(ASF); } static int lsmbus_recv_byte(struct device *dev) diff --git a/src/soc/amd/common/block/smbus/smbus.c b/src/soc/amd/common/block/smbus/smbus.c index e304483..fe1862f 100644 --- a/src/soc/amd/common/block/smbus/smbus.c +++ b/src/soc/amd/common/block/smbus/smbus.c @@ -13,12 +13,15 @@ */ #define SMBUS_TIMEOUT (100 * 1000 * 10) +/* FIXME: Passing host base for SMBUS is not long-term solution. + It is possible to have multiple buses behind same host. */ + static u8 controller_read8(uintptr_t base, u8 reg) { switch (base) { - case ACPIMMIO_SMBUS_BASE: + case ACPIMMIO_BASE(SMBUS): return smbus_read8(reg); - case ACPIMMIO_ASF_BASE: + case ACPIMMIO_BASE(ASF): return asf_read8(reg); default: printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%lx\n", @@ -30,10 +33,10 @@ static void controller_write8(uintptr_t base, u8 reg, u8 val) { switch (base) { - case ACPIMMIO_SMBUS_BASE: + case ACPIMMIO_BASE(SMBUS): smbus_write8(reg, val); break; - case ACPIMMIO_ASF_BASE: + case ACPIMMIO_BASE(ASF): asf_write8(reg, val); break; default: diff --git a/src/soc/amd/picasso/acpi/aoac.asl b/src/soc/amd/picasso/acpi/aoac.asl index f26f85f..1b9e255 100644 --- a/src/soc/amd/picasso/acpi/aoac.asl +++ b/src/soc/amd/picasso/acpi/aoac.asl @@ -4,7 +4,7 @@ #define AOAC_DEVICE(DEV_NAME, DEV_ID, SX) \ PowerResource(DEV_NAME, SX, 0) { \ - OperationRegion (AOAC, SystemMemory, ACPIMMIO_AOAC_BASE + 0x40 + (DEV_ID << 1), 2) \ + OperationRegion (AOAC, SystemMemory, ACPIMMIO_BASE(AOAC) + 0x40 + (DEV_ID << 1), 2) \ Field (AOAC, ByteAcc, NoLock, Preserve) { \ /* \ * Target Device State \ diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c index 7c54d8d..38aac76 100644 --- a/src/soc/amd/stoneyridge/smbus_spd.c +++ b/src/soc/amd/stoneyridge/smbus_spd.c @@ -34,7 +34,7 @@ dev_addr = (SmbusSlaveAddress >> 1); /* Read the first SPD byte */ - error = do_smbus_read_byte(ACPIMMIO_SMBUS_BASE, dev_addr, 0); + error = do_smbus_read_byte(ACPIMMIO_BASE(SMBUS), dev_addr, 0); if (error < 0) { printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); return error; @@ -44,7 +44,7 @@ /* Read the remaining SPD bytes using do_smbus_recv_byte for speed */ for (index = 1 ; index < count ; index++) { - error = do_smbus_recv_byte(ACPIMMIO_SMBUS_BASE, dev_addr); + error = do_smbus_recv_byte(ACPIMMIO_BASE(SMBUS), dev_addr); if (error < 0) { printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); return error; -- To view, visit https://review.coreboot.org/c/coreboot/+/42894 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31f2d04d9fc8bdd9e270fb3cb48d71f215999a50 Gerrit-Change-Number: 42894 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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