coreboot-gerrit October 2020

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Change in coreboot[master]: [WIP] soc/amd/common: Avoid MMIO aliasing on SMBus
by Kyösti Mälkki (Code Review) 15 Dec '20

15 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42074 ) Change subject: [WIP] soc/amd/common: Avoid MMIO aliasing on SMBus ...................................................................... [WIP] soc/amd/common: Avoid MMIO aliasing on SMBus Change-Id: I5e0ebd7609c5c83d0e443ffba74dae68017d3ebc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/smbus/smbus.c M src/soc/amd/stoneyridge/southbridge.c 3 files changed, 20 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/42074/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index b95a347..ac48538 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -250,46 +250,6 @@ write32(acpimmio_acpi + reg, value); } -static inline uint8_t asf_read8(uint8_t reg) -{ - return read8(acpimmio_asf + reg); -} - -static inline uint16_t asf_read16(uint8_t reg) -{ - return read16(acpimmio_asf + reg); -} - -static inline void asf_write8(uint8_t reg, uint8_t value) -{ - write8(acpimmio_asf + reg, value); -} - -static inline void asf_write16(uint8_t reg, uint16_t value) -{ - write16(acpimmio_asf + reg, value); -} - -static inline uint8_t smbus_read8(uint8_t reg) -{ - return read8(acpimmio_smbus + reg); -} - -static inline uint16_t smbus_read16(uint8_t reg) -{ - return read16(acpimmio_smbus + reg); -} - -static inline void smbus_write8(uint8_t reg, uint8_t value) -{ - write8(acpimmio_smbus + reg, value); -} - -static inline void smbus_write16(uint8_t reg, uint16_t value) -{ - write16(acpimmio_smbus + reg, value); -} - static inline uint8_t iomux_read8(uint8_t reg) { return read8(acpimmio_iomux + reg); diff --git a/src/soc/amd/common/block/smbus/smbus.c b/src/soc/amd/common/block/smbus/smbus.c index b5db56b..f8bab62 100644 --- a/src/soc/amd/common/block/smbus/smbus.c +++ b/src/soc/amd/common/block/smbus/smbus.c @@ -3,7 +3,7 @@ #include <stdint.h> #include <console/console.h> #include <device/smbus_host.h> -#include <amdblocks/acpimmio.h> +#include <amdblocks/acpimmio_map.h> #include <soc/southbridge.h> /* @@ -12,37 +12,31 @@ */ #define SMBUS_TIMEOUT (100 * 1000 * 10) -static u8 controller_read8(uintptr_t base, u8 reg) +union reg_bank { + uint8_t reg8[0x100]; + uint16_t reg16[0x100 / sizeof(uint16_t)]; +}; + +static __always_inline u8 controller_read8(const u32 base, const u8 reg) { - switch (base) { - case ACPIMMIO_SMBUS_BASE: - return smbus_read8(reg); - case ACPIMMIO_ASF_BASE: - return asf_read8(reg); - default: - printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%lx\n", - base); - } - return 0xff; + volatile union reg_bank *controller = (void *)(uintptr_t)base; + return controller->reg8[reg]; } -static void controller_write8(uintptr_t base, u8 reg, u8 val) +static __always_inline void controller_write8(const u32 base, const u8 reg, const u8 val) { - switch (base) { - case ACPIMMIO_SMBUS_BASE: - smbus_write8(reg, val); - break; - case ACPIMMIO_ASF_BASE: - asf_write8(reg, val); - break; - default: - printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%lx\n", - base); - } + volatile union reg_bank *controller = (void *)(uintptr_t)base; + controller->reg8[reg] = val; } static int smbus_wait_until_ready(uintptr_t mmio) { + if ((mmio != (uintptr_t)acpimmio_smbus) && + (mmio != (uintptr_t)acpimmio_asf)) { + printk(BIOS_ERR, "Invalid SMBus or ASF base %#zx\n", mmio); + return -1; + } + u32 loops; loops = SMBUS_TIMEOUT; do { diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index e90fe1b..7bdc4a4 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -366,6 +366,7 @@ static void fch_smbus_init(void) { +#if 0 /* 400 kHz smbus speed. */ const uint8_t smbus_speed = (66000000 / (400000 * 4)); @@ -376,6 +377,7 @@ smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); asf_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); +#endif } /* Before console init */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e0ebd7609c5c83d0e443ffba74dae68017d3ebc Gerrit-Change-Number: 42074 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 26

Change in coreboot[master]: WIP: coreboot: Add anx7625 panel driver
by yongqiang niu (Code Review) 15 Dec '20

15 Dec '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46575 ) Change subject: WIP: coreboot: Add anx7625 panel driver ...................................................................... WIP: coreboot: Add anx7625 panel driver Add panel anx7625 to support display Signed-off-by: Huijuan Xie <huijuan.xie(a)mediatek.corp-partner.google.com> Change-Id: I045d2042b5649e36470500f266f108564b7063fa --- M src/mainboard/google/asurada/Makefile.inc A src/mainboard/google/asurada/panel.h A src/mainboard/google/asurada/panel_anx7625.c 3 files changed, 131 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/46575/1 diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc index d3f8ce6..2e5d86f 100644 --- a/src/mainboard/google/asurada/Makefile.inc +++ b/src/mainboard/google/asurada/Makefile.inc @@ -20,3 +20,5 @@ ramstage-y += chromeos.c ramstage-y += mainboard.c ramstage-y += reset.c + +ramstage-$(CONFIG_DRIVER_ANALOGIX_ANX7625) += panel_anx7625.c \ No newline at end of file diff --git a/src/mainboard/google/asurada/panel.h b/src/mainboard/google/asurada/panel.h new file mode 100644 index 0000000..648440b --- /dev/null +++ b/src/mainboard/google/asurada/panel.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_KUKUI_PANEL_H__ +#define __MAINBOARD_GOOGLE_KUKUI_PANEL_H__ + +#include <edid.h> +#include <soc/dsi.h> + +/* + * The data that to be serialized and put into CBFS. + * Note some fields, for example edid.mode.name, were actually pointers and + * cannot be really serialized. + */ +struct panel_serializable_data { + struct edid edid; /* edid info of this panel */ + enum lb_fb_orientation orientation; /* Panel orientation */ + u8 init[]; /* A packed array of lcm_init_command */ +}; + +struct panel_description { + const char *name; /* Panel name for constructing CBFS file name */ + struct panel_serializable_data *s; + void (*power_on)(void); /* Callback to turn on panel */ +}; + +/* Returns the panel description from given ID. */ +struct panel_description *get_panel_description(int panel_id); + +/* Loads panel serializable data from CBFS. */ +struct panel_description *get_panel_from_cbfs(struct panel_description *desc); + +#define INIT_DCS_CMD(...) \ + LCM_DCS_CMD, \ + sizeof((u8[]){__VA_ARGS__}), \ + __VA_ARGS__ + +#define INIT_GENERIC_CMD(...) \ + LCM_GENERIC_CMD, \ + sizeof((u8[]){__VA_ARGS__}), \ + __VA_ARGS__ + +#define INIT_DELAY_CMD(delay) \ + LCM_DELAY_CMD, \ + delay + +#define INIT_END_CMD \ + LCM_END_CMD + +/* GPIO names */ +#define GPIO_MIPIBRDG_INT_ODL GPIO(EINT6) /* 6 */ +#define GPIO_MIPIBRDG_PWREN GPIO(DSI_TE) /* 41 */ +#define GPIO_MIPIBRDG_RST_L_1V8 GPIO(LCM_RST) /* 42 */ +#define GPIO_MIPIBRDG_PP3300_EN GPIO(PERIPHERAL_EN1) /* 127 */ +#define GPIO_MIPIBRDG_PP1800_EN GPIO(PERIPHERAL_EN2) /* 128 */ +#define GPIO_MIPIBRDG_PP1000_EN GPIO(PERIPHERAL_EN3) /* 129 */ +#define GPIO_PP3300_PANEL GPIO(CAM_CLK3) /* 136 */ + +#endif /* __MAINBOARD_GOOGLE_KUKUI_PANEL_H__ */ diff --git a/src/mainboard/google/asurada/panel_anx7625.c b/src/mainboard/google/asurada/panel_anx7625.c new file mode 100644 index 0000000..0145859 --- /dev/null +++ b/src/mainboard/google/asurada/panel_anx7625.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <delay.h> +#include <drivers/analogix/anx7625/anx7625.h> +#include <edid.h> +#include <gpio.h> +#include <soc/i2c.h> + +#include "panel.h" + + +static void power_on_anx7625(void) +{ + /* Disable backlight before turning on bridge */ + gpio_output(GPIO(KPROW1), 0); + gpio_output(GPIO(DISP_PWM), 0); + gpio_output(GPIO_PP3300_PANEL, 1); + + /* Turn on bridge */ + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 0); + gpio_output(GPIO_MIPIBRDG_PP1000_EN, 1); + gpio_output(GPIO_MIPIBRDG_PP1800_EN, 1); + gpio_output(GPIO_MIPIBRDG_PP3300_EN, 1); + mdelay(2); + gpio_output(GPIO_MIPIBRDG_PWREN, 1); + mdelay(10); + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 1); +} + +static void dummy_power_on(void) +{ + /* The panel has been already powered on when getting panel information + * so we should do nothing here. + */ +} + +static struct panel_serializable_data anx7625_data = { + .orientation = LB_FB_ORIENTATION_NORMAL, + .init = { INIT_END_CMD }, +}; + +static struct panel_description anx7625_panel = { + .s = &anx7625_data, + .power_on = dummy_power_on, +}; + +struct panel_description *get_panel_description(int panel_id) +{ + /* To read panel EDID, we have to first power on anx7625. */ + power_on_anx7625(); + + u8 i2c_bus = 3; + mtk_i2c_bus_init(i2c_bus); + + if (anx7625_init(i2c_bus)) { + printk(BIOS_ERR, "Can't init ANX7625 bridge.\n"); + return NULL; + } + struct edid *edid = &anx7625_data.edid; + if (anx7625_dp_get_edid(i2c_bus, edid)) { + printk(BIOS_ERR, "Can't get panel's edid.\n"); + return NULL; + } + if (anx7625_dp_start(i2c_bus, edid) < 0) { + printk(BIOS_ERR, "Can't start display via ANX7625.\n"); + return NULL; + } + + return &anx7625_panel; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I045d2042b5649e36470500f266f108564b7063fa Gerrit-Change-Number: 46575 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 33

Change in coreboot[master]: WIP: coreboot: Add display code
by yongqiang niu (Code Review) 15 Dec '20

15 Dec '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46578 ) Change subject: WIP: coreboot: Add display code ...................................................................... WIP: coreboot: Add display code Add display init code to support display Signed-off-by: Huijuan Xie <huijuan.xie(a)mediatek.corp-partner.google.com> Change-Id: If730c42451f7b392285df686abc4ca252d8d42cf --- M src/mainboard/google/asurada/mainboard.c 1 file changed, 103 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/46578/1 diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index 677e917..30e98e8 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -1,16 +1,27 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <bl31.h> +#include <boardid.h> +#include <bootmode.h> #include <console/console.h> +#include <delay.h> #include <device/device.h> #include <device/mmio.h> +#include <edid.h> +#include <gpio.h> #include <lib.h> +#include <soc/ddp.h> +#include <soc/dsi.h> #include <soc/dpm.h> +#include <soc/gpio.h> #include <soc/gpio_common.h> +#include <soc/mtcmos.h> #include <soc/spm.h> #include <soc/usb.h> #include "gpio.h" +#include "panel.h" #include <arm-trusted-firmware/include/export/plat/mediatek/common/plat_params_exp.h> @@ -34,10 +45,102 @@ register_bl31_aux_param(&param_reset.h); } +/* Default implementation for boards without panels defined yet. */ +struct panel_description __weak *get_panel_description(int panel_id) +{ + printk(BIOS_ERR, "%s: ERROR: No panels defined for board: %s.\n", + __func__, CONFIG_MAINBOARD_PART_NUMBER); + return NULL; +} + +/* Set up backlight control pins as output pin and power-off by default */ +static void configure_panel_backlight(void) +{ + gpio_output(GPIO(KPROW1), 0); + gpio_output(GPIO(DISP_PWM), 0); +} + +static void power_on_panel(struct panel_description *panel) +{ + if (panel->power_on) { + panel->power_on(); + return; + } + + /* Default power sequence for most panels. */ + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 0); + mdelay(6); + gpio_output(GPIO_MIPIBRDG_RST_L_1V8, 1); + mdelay(6); +} + +static struct panel_description *get_active_panel(void) +{ + /* TODO(hungte) Create a dedicated panel_id() in board_id.c */ + int panel_id = sku_id() >> 4; + + struct panel_description *panel = get_panel_description(panel_id); + if (!panel) { + printk(BIOS_ERR, "%s: Panel %d is not supported.\n", + __func__, panel_id); + return NULL; + } + assert(panel->s); + + const struct edid *edid = &panel->s->edid; + const char *name = edid->ascii_string; + if (name[0] == '\0') + name = "unknown name"; + printk(BIOS_INFO, "%s: Found ID %d: '%s %s' %dx%d@%dHz\n", __func__, + panel_id, edid->manufacturer_name, name, edid->mode.ha, + edid->mode.va, edid->mode.refresh); + return panel; +} + +static bool configure_display(void) +{ + struct panel_description *panel = get_active_panel(); + if (!panel) + return false; + + mtcmos_display_power_on(); + mtcmos_protect_display_bus(); + configure_panel_backlight(); + power_on_panel(panel); + + struct edid *edid = &panel->s->edid; + edid_set_framebuffer_bits_per_pixel(edid, 32, 0); + mtk_ddp_init(); + u32 mipi_dsi_flags = (MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM); + if (CONFIG(DRIVER_ANALOGIX_ANX7625)) + mipi_dsi_flags |= MIPI_DSI_MODE_EOT_PACKET; + if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, edid, + panel->s->init) < 0) { + printk(BIOS_ERR, "%s: Failed in DSI init.\n", __func__); + return false; + } + mtk_ddp_mode_set(edid); + set_vbe_mode_info_valid(edid, 0); + set_vbe_framebuffer_orientation(panel->s->orientation); + return true; +} + static void mainboard_init(struct device *dev) { int i; + if (display_init_required()) { + printk(BIOS_INFO, "%s: Starting display init.\n", __func__); + if (!configure_display()) + printk(BIOS_ERR, "%s: Failed to init display.\n", + __func__); + } else { + printk(BIOS_INFO, "%s: Skipped display init.\n", __func__); + } + + /* HACK, set pinctrl for SD card */ for (i = 51; i <= 56; i++) gpio_set_mode((gpio_t){.id = i}, 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/46578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If730c42451f7b392285df686abc4ca252d8d42cf Gerrit-Change-Number: 46578 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

4 27

Change in coreboot[master]: cbfs: Enable CBFS mcache on (almost) all boards
by Julius Werner (Code Review) 14 Dec '20

14 Dec '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/38424 to review the following change. Change subject: cbfs: Enable CBFS mcache on (almost) all boards ...................................................................... cbfs: Enable CBFS mcache on (almost) all boards This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Only a few boards with notoriously little space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/x86/Kconfig M src/arch/x86/car.ld M src/cpu/ti/am335x/memlayout.ld M src/lib/Kconfig M src/mainboard/emulation/qemu-aarch64/memlayout.ld M src/mainboard/emulation/qemu-armv7/memlayout.ld M src/mainboard/emulation/qemu-power8/memlayout.ld M src/mainboard/emulation/qemu-riscv/memlayout.ld M src/mainboard/emulation/spike-riscv/memlayout.ld M src/mainboard/google/octopus/Kconfig M src/soc/cavium/cn81xx/include/soc/memlayout.ld M src/soc/mediatek/mt8173/include/soc/memlayout.ld M src/soc/mediatek/mt8183/include/soc/memlayout.ld M src/soc/nvidia/tegra124/include/soc/memlayout.ld M src/soc/nvidia/tegra210/include/soc/memlayout.ld M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld M src/soc/qualcomm/ipq806x/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/sc7180/include/soc/memlayout.ld M src/soc/qualcomm/sdm845/include/soc/memlayout.ld M src/soc/rockchip/rk3288/Kconfig M src/soc/rockchip/rk3399/include/soc/memlayout.ld M src/soc/samsung/exynos5250/include/soc/memlayout.ld M src/soc/samsung/exynos5420/include/soc/memlayout.ld M src/soc/sifive/fu540/include/soc/memlayout.ld 25 files changed, 51 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38424/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 1c55bdb..7cf049d 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -155,6 +155,13 @@ help Increase this value if preram cbmem console is getting truncated +config CBFS_MCACHE_SIZE + hex + depends on !NO_CBFS_MCACHE + default 0x2000 + help + Increase this value if you see CBFS mcache overflow warnings + config PC80_SYSTEM bool default y if ARCH_X86 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 2e29112..52e081a 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -60,6 +60,9 @@ #if !CONFIG(NO_FMAP_CACHE) FMAP_CACHE(., FMAP_SIZE) #endif +#if !CONFIG(NO_CBFS_MCACHE) + CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE) +#endif _car_ehci_dbg_info = .; /* Reserve sizeof(struct ehci_dbg_info). */ diff --git a/src/cpu/ti/am335x/memlayout.ld b/src/cpu/ti/am335x/memlayout.ld index f69a315..9bc7b75 100644 --- a/src/cpu/ti/am335x/memlayout.ld +++ b/src/cpu/ti/am335x/memlayout.ld @@ -19,7 +19,8 @@ { DRAM_START(0x40000000) BOOTBLOCK(0x402f0400, 20K) - ROMSTAGE(0x402f5400, 88K) + ROMSTAGE(0x402f5400, 80K) + CBFS_MCACHE(0x40309400, 8K) FMAP_CACHE(0x4030b400, 2K) STACK(0x4030be00, 4K) RAMSTAGE(0x80200000, 192K) diff --git a/src/lib/Kconfig b/src/lib/Kconfig index 26bf0be..4d2bf80 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -78,7 +78,6 @@ config NO_CBFS_MCACHE bool - default y help Disables the CBFS metadata cache. This means that your platform does not need to provide a CBFS_MCACHE section in memlayout and can save diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld index aba4205..544f89f 100644 --- a/src/mainboard/emulation/qemu-aarch64/memlayout.ld +++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld @@ -24,7 +24,8 @@ DRAM_START(0x40000000) BOOTBLOCK(0x60010000, 64K) - STACK(0x60020000, 62K) + STACK(0x60020000, 54K) + CBFS_MCACHE(0x6002D800, 8K) FMAP_CACHE(0x6002F800, 2K) ROMSTAGE(0x60030000, 128K) RAMSTAGE(0x60070000, 16M) diff --git a/src/mainboard/emulation/qemu-armv7/memlayout.ld b/src/mainboard/emulation/qemu-armv7/memlayout.ld index 2b33cb3..de09cbb 100644 --- a/src/mainboard/emulation/qemu-armv7/memlayout.ld +++ b/src/mainboard/emulation/qemu-armv7/memlayout.ld @@ -43,6 +43,7 @@ BOOTBLOCK(0x00000, 64K) FMAP_CACHE(0x10000, 2K) + CBFS_MCACHE(0x10800, 8K) DRAM_START(0x60000000) STACK(0x60000000, 64K) diff --git a/src/mainboard/emulation/qemu-power8/memlayout.ld b/src/mainboard/emulation/qemu-power8/memlayout.ld index c22d3e4..81fe7f4 100644 --- a/src/mainboard/emulation/qemu-power8/memlayout.ld +++ b/src/mainboard/emulation/qemu-power8/memlayout.ld @@ -27,5 +27,6 @@ STACK(0x40000, 0x3ff00) PRERAM_CBMEM_CONSOLE(0x80000, 8K) FMAP_CACHE(0x82000, 2K) + CBFS_MCACHE(0x82800, 8K) RAMSTAGE(0x100000, 16M) } diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index e53df38..7eb0f00 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -38,6 +38,7 @@ #endif PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K) FMAP_CACHE(STAGES_START + 136K, 2K) + CBFS_MCACHE(STAGES_START + 138K, 8K) RAMSTAGE(STAGES_START + 200K, 16M) STACK(STAGES_START + 200K + 16M, 4K) } diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index b6e4d9d..376b9b1 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -24,7 +24,8 @@ DRAM_START(START) BOOTBLOCK(START, 64K) STACK(START + 8M, 4K) - FMAP_CACHE(START + 8M + 4K, 2K) + FMAP_CACHE(START + 12M, 2K) + CBFS_CACHE(START + 14M, 8K) /* hole at (START + 8M + 6K, 58K) */ ROMSTAGE(START + 8M + 64K, 128K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 3139716..8a33b5f 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -23,6 +23,7 @@ select MAINBOARD_HAS_TPM2 select GOOGLE_SMBIOS_MAINBOARD_VERSION select NO_FMAP_CACHE + select NO_CBFS_MCACHE if BOARD_GOOGLE_BASEBOARD_OCTOPUS diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld index 1a0eb15..e78aa20 100644 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld @@ -34,7 +34,8 @@ PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 6K) FMAP_CACHE(BOOTROM_OFFSET + 0x7800, 2K) PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K) - BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) + BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 56K) + CBFS_MCACHE(BOOTROM_OFFSET + 0x2e000, 8K) VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K) VBOOT2_TPM_LOG(BOOTROM_OFFSET + 0x33000, 2K) VERSTAGE(BOOTROM_OFFSET + 0x33800, 50K) diff --git a/src/soc/mediatek/mt8173/include/soc/memlayout.ld b/src/soc/mediatek/mt8173/include/soc/memlayout.ld index 2358c39..2d364b5 100644 --- a/src/soc/mediatek/mt8173/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8173/include/soc/memlayout.ld @@ -43,7 +43,8 @@ FMAP_CACHE(0x00103800, 2K) PRERAM_CBMEM_CONSOLE(0x00104000, 12K) WATCHDOG_TOMBSTONE(0x00107000, 4) - PRERAM_CBFS_CACHE(0x00107004, 16K - 4) + PRERAM_CBFS_CACHE(0x00107004, 8K - 4) + CBFS_MCACHE(0x00109000, 8K) TIMESTAMP(0x0010B000, 4K) ROMSTAGE(0x0010C000, 92K) STACK(0x00124000, 16K) diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index 996d2ec..0d20e31 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -43,7 +43,8 @@ SRAM_L2C_START(0x00200000) OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00201000, 188K) - BOOTBLOCK(0x00230000, 64K) + BOOTBLOCK(0x00230000, 56K) + CBFS_MCACHE(0x0023e000, 8K) DRAM_INIT_CODE(0x00240000, 208K) PRERAM_CBFS_CACHE(0x00274000, 48K) SRAM_L2C_END(0x00280000) diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index 7e2cc7a..a342f6a 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -29,7 +29,8 @@ TTB(0x40000000, 16K + 32) PRERAM_CBMEM_CONSOLE(0x40004020, 6K - 32) FMAP_CACHE(0x40005800, 2K) - PRERAM_CBFS_CACHE(0x40006000, 14K) + CBFS_MCACHE(0x40006000, 8K) + PRERAM_CBFS_CACHE(0x40008000, 6K) VBOOT2_WORK(0x40009800, 12K) VBOOT2_TPM_LOG(0x4000D800, 2K) STACK(0x4000E000, 8K) diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld index b7268d1..44f0153 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld @@ -30,7 +30,8 @@ SRAM_START(0x40000000) PRERAM_CBMEM_CONSOLE(0x40000000, 2K) FMAP_CACHE(0x40000800, 2K) - PRERAM_CBFS_CACHE(0x40001000, 28K) + PRERAM_CBFS_CACHE(0x40001000, 20K) + CBFS_MCACHE(0x40006000, 8K) VBOOT2_WORK(0x40008000, 12K) VBOOT2_TPM_LOG(0x4000B000, 2K) #if ENV_ARM64 diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld index 6ff1018..76685cf 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld @@ -34,7 +34,8 @@ /* This includes bootblock image, can be reused after bootblock starts */ /* UBER_SBL(0x0A0C0000, 48K) */ - PRERAM_CBFS_CACHE(0x0A0C0000, 92K) + PRERAM_CBFS_CACHE(0x0A0C0000, 84K) + CBFS_MCACHE(0x0A0ED800, 8K) FMAP_CACHE(0x0A0EF800, 2K) TTB(0x0A0F0000, 16K) diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index 595d939..6e309c0 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -38,7 +38,8 @@ QCA_SHARED_RAM(2A03F000, 4K) */ STACK(0x2A040000, 16K) - PRERAM_CBFS_CACHE(0x2A044000, 91K) + PRERAM_CBFS_CACHE(0x2A044000, 83K) + CBFS_MCACHE(0x2A059000, 8K) FMAP_CACHE(0x2A05B000, 2K) TTB_SUBTABLES(0x2A05B800, 2K) TTB(0x2A05C000, 16K) diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index dd013b5..9d92949 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -38,7 +38,8 @@ STACK(0x8C4B000, 16K) TIMESTAMP(0x8C4F000, 1K) PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K) - PRERAM_CBFS_CACHE(0x8C57400, 70K) + PRERAM_CBFS_CACHE(0x8C57400, 62K) + CBFS_MCACHE(0x8C66C00, 8K) FMAP_CACHE(0x8C68C00, 2K) REGION(bsram_unused, 0x8C69400, 0xA1C00, 0x100) BSRAM_END(0x8D80000) diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index 7323119..838fda3 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -52,6 +52,7 @@ REGION(qclib_serial_log, 0x14852000, 4K, 4K) REGION(ddr_information, 0x14853000, 1K, 1K) FMAP_CACHE(0x14853400, 2K) + CBFS_MCACHE(0x14853C00, 8K) REGION(dcb, 0x14870000, 16K, 4K) REGION(pmic, 0x14874000, 44K, 4K) REGION(limits_cfg, 0x1487F000, 4K, 4K) diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld index c3a3b4c..5ea3e96 100644 --- a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld @@ -58,7 +58,8 @@ PRERAM_CBMEM_CONSOLE(0x14836400, 32K) PRERAM_CBFS_CACHE(0x1483E400, 70K) FMAP_CACHE(0x1484FC00, 2K) - REGION(bsram_unused, 0x14850400, 0x9DB00, 0x100) + CBFS_MCACHE(0x1485400, 8K) + REGION(bsram_unused, 0x14852400, 0x9BB00, 0x100) REGION(ddr_information, 0x148EDF00, 256, 256) REGION(limits_cfg, 0x148EE000, 4K, 4K) REGION(qclib_serial_log, 0x148EF000, 4K, 4K) diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 6a44ccd..e36a8e8 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -30,6 +30,7 @@ select HAVE_LINEAR_FRAMEBUFFER select NO_BOOTBLOCK_CONSOLE select NO_FMAP_CACHE + select NO_CBFS_MCACHE if SOC_ROCKCHIP_RK3288 diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index 4e46e2d..2c7be29 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -37,11 +37,12 @@ FMAP_CACHE(0xFF8C1400, 2K) TIMESTAMP(0xFF8C1C00, 1K) /* 0xFF8C2004 is the entry point address the masked ROM will jump to. */ - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4) - BOOTBLOCK(0xFF8D8000, 40K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 84K - 4) + BOOTBLOCK(0xFF8D7000, 40K) #endif - VBOOT2_WORK(0XFF8E2000, 12K) - TTB(0xFF8E5000, 24K) + CBFS_MCACHE(0xFF8E1000, 8K) + VBOOT2_WORK(0XFF8E3000, 12K) + TTB(0xFF8E6000, 20K) PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K) STACK(0xFF8ED000, 12K) SRAM_END(0xFF8F0000) diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld index 7e052f0..e97fcb0 100644 --- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld @@ -31,7 +31,8 @@ ROMSTAGE(0x2030000, 128K) /* 32K hole */ TTB(0x2058000, 16K) - PRERAM_CBFS_CACHE(0x205C000, 76K) + PRERAM_CBFS_CACHE(0x205C000, 68K) + CBFS_MCACHE(0x206D000, 8K) FMAP_CACHE(0x206F000, 2K) VBOOT2_TPM_LOG(0x206F800, 2K) VBOOT2_WORK(0x2070000, 12K) diff --git a/src/soc/samsung/exynos5420/include/soc/memlayout.ld b/src/soc/samsung/exynos5420/include/soc/memlayout.ld index ff781d2..e2e51c0 100644 --- a/src/soc/samsung/exynos5420/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5420/include/soc/memlayout.ld @@ -32,7 +32,8 @@ ROMSTAGE(0x2030000, 128K) /* 32K hole */ TTB(0x2058000, 16K) - PRERAM_CBFS_CACHE(0x205C000, 74K) + PRERAM_CBFS_CACHE(0x205C000, 66K) + CBFS_MCACHE(0x206C800, 8K) FMAP_CACHE(0x206E800, 2K) STACK(0x206F000, 16K) /* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't diff --git a/src/soc/sifive/fu540/include/soc/memlayout.ld b/src/soc/sifive/fu540/include/soc/memlayout.ld index 46c559c..cc4f900 100644 --- a/src/soc/sifive/fu540/include/soc/memlayout.ld +++ b/src/soc/sifive/fu540/include/soc/memlayout.ld @@ -26,7 +26,8 @@ L2LIM_START(FU540_L2LIM) BOOTBLOCK(FU540_L2LIM, 64K) CAR_STACK(FU540_L2LIM + 64K, 20K) - PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K) + PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 76K, 8K) + CBFS_MCACHE(FU540_L2LIM + 84K, 8K) FMAP_CACHE(FU540_L2LIM + 92K, 2K) ROMSTAGE(FU540_L2LIM + 128K, 128K) PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K) -- To view, visit https://review.coreboot.org/c/coreboot/+/38424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Gerrit-Change-Number: 38424 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

10 44

Change in coreboot[master]: soc/intel/xeon_sp: Configure DPR on all stacks
by Arthur Heymans (Code Review) 14 Dec '20

14 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46818 ) Change subject: soc/intel/xeon_sp: Configure DPR on all stacks ...................................................................... soc/intel/xeon_sp: Configure DPR on all stacks Configure DPR to span the region between TSEG_BASE and the cbmem_top. This region was already unavailable to the OS. Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/uncore.c 3 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/46818/1 diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index a28fac6..bbeee1f 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -79,6 +79,7 @@ #define VMD_FUNC_NUM 0x05 #define MMAP_VTD_CFG_REG_DEVID 0x2024 +#define MMAP_VTD_STACK_CFG_REG_DEVID 0x2034 #define VTD_DEV_NUM 0x5 #define VTD_FUNC_NUM 0x0 diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 32c316d..6523b6d 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -128,6 +128,7 @@ #define HPET0_FUNC_NUM 0x00 #define MMAP_VTD_CFG_REG_DEVID 0x2024 +#define MMAP_VTD_STACK_CFG_REG_DEVID 0x2034 #define VTD_DEV_NUM 0x5 #define VTD_FUNC_NUM 0x0 diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 332b9a4..c9ffeb6 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -11,6 +11,8 @@ #include <soc/ramstage.h> #include <soc/util.h> #include <fsp/util.h> +#include <security/intel/txt/txt_platform.h> +#include <soc/pci_devs.h> struct map_entry { uint32_t reg; @@ -88,6 +90,17 @@ } } +static void configure_dpr(struct device *dev) +{ + const uintptr_t cbmem_top_mb = ALIGN_UP((uintptr_t)cbmem_top(), MiB) / MiB; + union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; + + dpr.size = dpr.top - cbmem_top_mb; + dpr.lock = 1; + dpr.epm = 1; + pci_write_config32(dev, VTD_LTDPR, dpr.raw); +} + /* * Host Memory Map: * @@ -127,6 +140,8 @@ * | MEseg (relocatable) | 32, 64, 128 or 256 MB (0x78000000 - 0x7fffffff, 0x20000) * +--------------------------+ * | Tseg (relocatable) | N x 8MB (0x70000000 - 0x77ffffff, 0x20000) + * +--------------------------+ + * | DPR | * +--------------------------+ cbmem_top * | Reserved - CBMEM | (0x6fffe000 - 0x6fffffff, 0x2000) * +--------------------------+ @@ -199,6 +214,13 @@ LOG_MEM_RESOURCE("mmio_tseg", dev, index, base_kb, size_kb); reserved_ram_resource(dev, index++, base_kb, size_kb); + /* Reserve and set up DPR */ + configure_dpr(dev); + union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; + if (dpr.size) + reserved_ram_resource(dev, index++, (dpr.top - dpr.size) << 10, dpr.size << 10); + + /* Mark region between TSEG - TOLM (eg. MESEG) as reserved */ if (mc_values[TSEG_LIMIT_REG] < mc_values[TOLM_REG]) { base_kb = ((mc_values[TSEG_LIMIT_REG] + 1) >> 10); @@ -290,3 +312,25 @@ .vendor = PCI_VENDOR_ID_INTEL, .devices = mmapvtd_ids }; + +static void vtd_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + + configure_dpr(dev); +} + +static struct device_operations vtd_ops = { + .read_resources = vtd_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, +// .init = mmapvtd_init, + .ops_pci = &soc_pci_ops, +}; + +/* VTD devices on other stacks */ +static const struct pci_driver vtd_driver __pci_driver = { + .ops = &vtd_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = MMAP_VTD_STACK_CFG_REG_DEVID, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/46818 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b Gerrit-Change-Number: 46818 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: [WIP]drivers: Replace multiple fill_fb_framebuffer with single instance
by Patrick Rudolph (Code Review) 14 Dec '20

14 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39003 ) Change subject: [WIP]drivers: Replace multiple fill_fb_framebuffer with single instance ...................................................................... [WIP]drivers: Replace multiple fill_fb_framebuffer with single instance Replace all duplications of fill_fb_framebuffer and provide a single one. Should not change the current behaviour. TODO: Libgfxinit seems to expose one,too Change-Id: Ife507f7e7beaf59854e533551b4b87ea6980c1f4 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/oprom/realmode/x86.c M src/device/oprom/yabel/vbe.c M src/drivers/intel/fsp1_1/fsp_gop.c M src/drivers/intel/fsp2_0/graphics.c M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/xgi/common/xgi_coreboot.c M src/lib/Kconfig M src/lib/Makefile.inc 8 files changed, 111 insertions(+), 185 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/39003/1 diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 8ba0241..4c11e6f 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -23,6 +23,7 @@ #include <pc80/i8254.h> #include <string.h> #include <vbe.h> +#include <framebuffer_info.h> /* we use x86emu's register file representation */ #include <x86emu/regs.h> @@ -218,6 +219,7 @@ #if CONFIG(FRAMEBUFFER_SET_VESA_MODE) static vbe_mode_info_t mode_info; static int mode_info_valid; +static struct edid_fb_info *fb_info; static int vbe_mode_info_valid(void) { @@ -362,6 +364,28 @@ } vbe_set_mode(&mode_info); + + if (!vbe_mode_info_valid()) + return; + + if (!fb_info) { + fb_info = fb_new_framebuffer_info(); + } + if (fb_info) { + fb_fill_framebuffer_info_ex(fb_info, mode_info.vesa.phys_base_ptr, + le16_to_cpu(mode_info.vesa.x_resolution), + le16_to_cpu(mode_info.vesa.y_resolution), + le16_to_cpu(mode_info.vesa.bytes_per_scanline), + mode_info.vesa.bits_per_pixel, + mode_info.vesa.reserved_mask_pos, + mode_info.vesa.reserved_mask_size, + mode_info.vesa.red_mask_pos, + mode_info.vesa.red_mask_size, + mode_info.vesa.green_mask_pos, + mode_info.vesa.green_mask_size, + mode_info.vesa.blue_mask_pos, + mode_info.vesa.blue_mask_size); + } } void vbe_textmode_console(void) @@ -373,34 +397,6 @@ die("\nError: In %s function\n", __func__); } -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) -{ - if (!vbe_mode_info_valid()) - return -1; - - framebuffer->physical_address = mode_info.vesa.phys_base_ptr; - - framebuffer->x_resolution = le16_to_cpu(mode_info.vesa.x_resolution); - framebuffer->y_resolution = le16_to_cpu(mode_info.vesa.y_resolution); - framebuffer->bytes_per_line = - le16_to_cpu(mode_info.vesa.bytes_per_scanline); - framebuffer->bits_per_pixel = mode_info.vesa.bits_per_pixel; - - framebuffer->red_mask_pos = mode_info.vesa.red_mask_pos; - framebuffer->red_mask_size = mode_info.vesa.red_mask_size; - - framebuffer->green_mask_pos = mode_info.vesa.green_mask_pos; - framebuffer->green_mask_size = mode_info.vesa.green_mask_size; - - framebuffer->blue_mask_pos = mode_info.vesa.blue_mask_pos; - framebuffer->blue_mask_size = mode_info.vesa.blue_mask_size; - - framebuffer->reserved_mask_pos = mode_info.vesa.reserved_mask_pos; - framebuffer->reserved_mask_size = mode_info.vesa.reserved_mask_size; - - return 0; -} - #endif void run_bios(struct device *dev, unsigned long addr) diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index a3d736f..2c05338 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -162,6 +162,7 @@ } static int mode_info_valid; +static struct edid_fb_info *fb_info; static int vbe_mode_info_valid(void) { @@ -747,33 +748,28 @@ mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE; vbe_get_mode_info(&mode_info); vbe_set_mode(&mode_info); -} -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) -{ if (!vbe_mode_info_valid()) - return -1; + return; - framebuffer->physical_address = le32_to_cpu(mode_info.vesa.phys_base_ptr); - - framebuffer->x_resolution = le16_to_cpu(mode_info.vesa.x_resolution); - framebuffer->y_resolution = le16_to_cpu(mode_info.vesa.y_resolution); - framebuffer->bytes_per_line = le16_to_cpu(mode_info.vesa.bytes_per_scanline); - framebuffer->bits_per_pixel = mode_info.vesa.bits_per_pixel; - - framebuffer->red_mask_pos = mode_info.vesa.red_mask_pos; - framebuffer->red_mask_size = mode_info.vesa.red_mask_size; - - framebuffer->green_mask_pos = mode_info.vesa.green_mask_pos; - framebuffer->green_mask_size = mode_info.vesa.green_mask_size; - - framebuffer->blue_mask_pos = mode_info.vesa.blue_mask_pos; - framebuffer->blue_mask_size = mode_info.vesa.blue_mask_size; - - framebuffer->reserved_mask_pos = mode_info.vesa.reserved_mask_pos; - framebuffer->reserved_mask_size = mode_info.vesa.reserved_mask_size; - - return 0; + if (!fb_info) { + fb_info = fb_new_framebuffer_info(); + } + if (fb_info) { + fb_fill_framebuffer_info_ex(fb_info, mode_info.vesa.phys_base_ptr, + le16_to_cpu(mode_info.vesa.x_resolution), + le16_to_cpu(mode_info.vesa.y_resolution), + le16_to_cpu(mode_info.vesa.bytes_per_scanline), + mode_info.vesa.bits_per_pixel, + mode_info.vesa.reserved_mask_pos, + mode_info.vesa.reserved_mask_size, + mode_info.vesa.red_mask_pos, + mode_info.vesa.red_mask_size, + mode_info.vesa.green_mask_pos, + mode_info.vesa.green_mask_size, + mode_info.vesa.blue_mask_pos, + mode_info.vesa.blue_mask_size); + } } void vbe_textmode_console(void) diff --git a/src/drivers/intel/fsp1_1/fsp_gop.c b/src/drivers/intel/fsp1_1/fsp_gop.c index eb64151..9b555e6 100644 --- a/src/drivers/intel/fsp1_1/fsp_gop.c +++ b/src/drivers/intel/fsp1_1/fsp_gop.c @@ -12,10 +12,12 @@ */ #include <boot/coreboot_tables.h> +#include <bootstate.h> #include <console/console.h> +#include <framebuffer_info.h> #include <fsp/util.h> -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +static void fill_framebuffer_info(void *unused) { VOID *hob_list_ptr; hob_list_ptr = get_hob_list(); @@ -30,20 +32,15 @@ printk(BIOS_DEBUG, "FSP_DEBUG: Graphics Data HOB present\n"); vbt_gop = GET_GUID_HOB_DATA(vbt_hob); - framebuffer->physical_address = vbt_gop->FrameBufferBase; - framebuffer->x_resolution = vbt_gop->GraphicsMode.HorizontalResolution; - framebuffer->y_resolution = vbt_gop->GraphicsMode.VerticalResolution; - framebuffer->bytes_per_line = vbt_gop->GraphicsMode.PixelsPerScanLine - * 4; - framebuffer->bits_per_pixel = 32; - framebuffer->red_mask_pos = 16; - framebuffer->red_mask_size = 8; - framebuffer->green_mask_pos = 8; - framebuffer->green_mask_size = 8; - framebuffer->blue_mask_pos = 0; - framebuffer->blue_mask_size = 8; - framebuffer->reserved_mask_pos = 24; - framebuffer->reserved_mask_size = 8; + struct edid_fb_info *info = fb_new_framebuffer_info(); + if (!info) + return; - return 0; + fb_fill_framebuffer_info(info, vbt_gop->FrameBufferBase, + vbt_gop->GraphicsMode.HorizontalResolution, + vbt_gop->GraphicsMode.VerticalResolution, + vbt_gop->GraphicsMode.PixelsPerScanLine * 4, + 32); } + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, fill_framebuffer_info, NULL); diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index be7afdb..f35556f 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -17,6 +17,7 @@ #include <fsp/util.h> #include <soc/intel/common/vbt.h> #include <types.h> +#include <framebuffer_info.h> enum pixel_format { pixel_rgbx_8bpc = 0, @@ -58,48 +59,18 @@ [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} }, }; -enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +__weak uintptr_t fsp_soc_get_igd_bar(void) { - size_t size; - const struct hob_graphics_info *ginfo; - const struct fsp_framebuffer *fbinfo; - - ginfo = fsp_find_extension_hob_by_guid(fsp_graphics_info_guid, &size); - - if (!ginfo) { - printk(BIOS_ALERT, "Graphics hand-off block not found\n"); - return CB_ERR; - } - - if (ginfo->pixel_format >= ARRAY_SIZE(fsp_framebuffer_format_map)) { - printk(BIOS_ALERT, "FSP set unknown framebuffer format: %d\n", - ginfo->pixel_format); - return CB_ERR; - } - - fbinfo = fsp_framebuffer_format_map + ginfo->pixel_format; - - framebuffer->physical_address = ginfo->framebuffer_base; - framebuffer->x_resolution = ginfo->horizontal_resolution; - framebuffer->y_resolution = ginfo->vertical_resolution; - framebuffer->bytes_per_line = ginfo->pixels_per_scanline * 4; - framebuffer->bits_per_pixel = 32; - framebuffer->red_mask_pos = fbinfo->red.pos; - framebuffer->red_mask_size = fbinfo->red.size; - framebuffer->green_mask_pos = fbinfo->green.pos; - framebuffer->green_mask_size = fbinfo->green.size; - framebuffer->blue_mask_pos = fbinfo->blue.pos; - framebuffer->blue_mask_size = fbinfo->blue.size; - framebuffer->reserved_mask_pos = fbinfo->rsvd.pos; - framebuffer->reserved_mask_size = fbinfo->rsvd.pos; - - return CB_SUCCESS; + return 0; } -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +static void fill_framebuffer_info(void *unused) { + size_t size; enum cb_err ret; uintptr_t framebuffer_bar; + const struct hob_graphics_info *ginfo; + const struct fsp_framebuffer *fbinfo; /* Pci enumeration happens after silicon init. * After enumeration graphic framebuffer base may be relocated. @@ -109,24 +80,44 @@ if (!framebuffer_bar) { printk(BIOS_ALERT, "Framebuffer BAR invalid\n"); - return -1; - } - - ret = fsp_fill_lb_framebuffer(framebuffer); - if (ret != CB_SUCCESS) { - printk(BIOS_ALERT, "FSP did not return a valid framebuffer\n"); - return -1; + return; } /* Resource allocator can move the BAR around after FSP configures it */ - framebuffer->physical_address = framebuffer_bar; - printk(BIOS_DEBUG, "Graphics framebuffer located at 0x%llx\n", - framebuffer->physical_address); + printk(BIOS_DEBUG, "Graphics framebuffer located at 0x%llx\n", framebuffer_bar); - return 0; + ginfo = fsp_find_extension_hob_by_guid(fsp_graphics_info_guid, &size); + + if (!ginfo) { + printk(BIOS_ALERT, "Graphics hand-off block not found\n"); + return; + } + + if (ginfo->pixel_format >= ARRAY_SIZE(fsp_framebuffer_format_map)) { + printk(BIOS_ALERT, "FSP set unknown framebuffer format: %d\n", + ginfo->pixel_format); + return; + } + + fbinfo = fsp_framebuffer_format_map + ginfo->pixel_format; + + struct edid_fb_info *info = fb_new_framebuffer_info(); + if (!info) + return; + + fb_fill_framebuffer_info_ex(fb_info, ginfo->framebuffer_base, + ginfo->horizontal_resolution, + ginfo->vertical_resolution, + ginfo->pixels_per_scanline * 4, + 32, + fbinfo->rsvd.pos, + fbinfo->rsvd.size, + fbinfo->red.pos, + fbinfo->red.size, + fbinfo->green.pos, + fbinfo->green.size, + fbinfo->blue.pos, + fbinfo->blue.size); } -__weak uintptr_t fsp_soc_get_igd_bar(void) -{ - return 0; -} +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, fill_framebuffer_info, NULL); diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 303bafe..15e7390 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -76,7 +76,6 @@ void *fsp_get_hob_list_ptr(void); const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size); const void *fsp_find_nv_storage_data(size_t *size); -enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); int fsp_find_range_hob(struct range_entry *re, const uint8_t guid[16]); void fsp_display_fvi_version_hob(void); void fsp_find_reserved_memory(struct range_entry *re); diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c index d65e007..235cbe2 100644 --- a/src/drivers/xgi/common/xgi_coreboot.c +++ b/src/drivers/xgi/common/xgi_coreboot.c @@ -21,6 +21,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <pc80/vga.h> +#include <framebuffer_info.h> #include "xgi_coreboot.h" #include "vstruct.h" @@ -31,8 +32,7 @@ #include "vb_setmode.h" #include "XGI_main.c" -static int xgi_vbe_valid; -static struct lb_framebuffer xgi_fb; +static struct edid_fb_info *fb_info; int xgifb_probe(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info) { @@ -359,43 +359,16 @@ XGIbios_mode[xgifb_info->mode_idx].bpp, xgifb_info->refresh_rate); - /* Set LinuxBIOS framebuffer information */ - xgi_vbe_valid = 1; - xgi_fb.physical_address = xgifb_info->video_base; - xgi_fb.x_resolution = xgifb_info->video_width; - xgi_fb.y_resolution = xgifb_info->video_height; - xgi_fb.bytes_per_line = - xgifb_info->video_width * xgifb_info->video_bpp; - xgi_fb.bits_per_pixel = xgifb_info->video_bpp; - - xgi_fb.reserved_mask_pos = 0; - xgi_fb.reserved_mask_size = 0; - switch (xgifb_info->video_bpp) { - case 32: - case 24: - /* packed into 4-byte words */ - xgi_fb.reserved_mask_pos = 24; - xgi_fb.reserved_mask_size = 8; - xgi_fb.red_mask_pos = 16; - xgi_fb.red_mask_size = 8; - xgi_fb.green_mask_pos = 8; - xgi_fb.green_mask_size = 8; - xgi_fb.blue_mask_pos = 0; - xgi_fb.blue_mask_size = 8; - break; - case 16: - /* packed into 2-byte words */ - xgi_fb.red_mask_pos = 11; - xgi_fb.red_mask_size = 5; - xgi_fb.green_mask_pos = 5; - xgi_fb.green_mask_size = 6; - xgi_fb.blue_mask_pos = 0; - xgi_fb.blue_mask_size = 5; - break; - default: - printk(BIOS_SPEW, "%s: unsupported BPP %d\n", __func__, - xgifb_info->video_bpp); - xgi_vbe_valid = 0; + /* Set framebuffer information */ + if (!fb_info) { + fb_info = fb_new_framebuffer_info(); + } + if (fb_info) { + fb_fill_framebuffer_info(fb_info, xgifb_info->video_base, + xgifb_info->video_width, + xgifb_info->video_height, + xgifb_info->video_width * xgifb_info->video_bpp, + xgifb_info->video_bpp); } } else { /* @@ -415,22 +388,6 @@ return 0; } - -static int vbe_mode_info_valid(void) -{ - return xgi_vbe_valid; -} - -int fill_lb_framebuffer(struct lb_framebuffer *framebuffer) -{ - if (!vbe_mode_info_valid()) - return -1; - - *framebuffer = xgi_fb; - - return 0; -} - struct xgifb_video_info *xgifb_video_info_ptr; struct xgifb_video_info *pci_get_drvdata(struct pci_dev *pdev) { diff --git a/src/lib/Kconfig b/src/lib/Kconfig index dd9974a..d831975 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -5,14 +5,6 @@ implementation. This activates a stub that logs the missing board reset and halts execution. -config NO_EDID_FILL_FB - bool - default y if !MAINBOARD_DO_NATIVE_VGA_INIT - help - Don't include default fill_lb_framebuffer() implementation. Select - this if your drivers uses MAINBOARD_DO_NATIVE_VGA_INIT but provides - its own fill_lb_framebuffer() implementation. - config RAMSTAGE_ADA bool help diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 2333f64..a1fb8c2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -134,9 +134,7 @@ ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-$(CONFIG_COVERAGE) += libgcov.c ramstage-y += edid.c -ifneq ($(CONFIG_NO_EDID_FILL_FB),y) ramstage-y += edid_fill_fb.c -endif ramstage-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c -- To view, visit https://review.coreboot.org/c/coreboot/+/39003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife507f7e7beaf59854e533551b4b87ea6980c1f4 Gerrit-Change-Number: 39003 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

10 68

Change in coreboot[master]: [NOTFORMERGE]: drivers/pc80/tpm: Probe for tpm multiple times
by Patrick Rudolph (Code Review) 14 Dec '20

14 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42510 ) Change subject: [NOTFORMERGE]: drivers/pc80/tpm: Probe for tpm multiple times ...................................................................... [NOTFORMERGE]: drivers/pc80/tpm: Probe for tpm multiple times Change-Id: Icdd675c0978173755d9ee18c20d8c314c1537a7a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/pc80/tpm/tis.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/42510/1 diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 185df34..ef556fe 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -393,7 +393,11 @@ if (vendor_dev_id) return 0; /* Already probed. */ - didvid = tpm_read_did_vid(0); + for (i = 0; i < 10000; i++) { + didvid = tpm_read_did_vid(0); + if (didvid && didvid != 0xffffffff) + break; + } if (!didvid || (didvid == 0xffffffff)) { printf("%s: No TPM device found\n", __FUNCTION__); return TPM_DRIVER_ERR; -- To view, visit https://review.coreboot.org/c/coreboot/+/42510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdd675c0978173755d9ee18c20d8c314c1537a7a Gerrit-Change-Number: 42510 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: WIP: coreboot: Enable ANALOGIX_ANX7625
by yongqiang niu (Code Review) 14 Dec '20

14 Dec '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46576 ) Change subject: WIP: coreboot: Enable ANALOGIX_ANX7625 ...................................................................... WIP: coreboot: Enable ANALOGIX_ANX7625 Enable ANALOGIX_ANX7625 to support display in coreboot Signed-off-by: Huijuan Xie <huijuan.xie(a)mediatek.corp-partner.google.com> Change-Id: I837e56ba4e98cc94c33484e79c4d5ff45a62becd --- M src/mainboard/google/asurada/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46576/1 diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig index 7c93815..3a825b6 100644 --- a/src/mainboard/google/asurada/Kconfig +++ b/src/mainboard/google/asurada/Kconfig @@ -27,6 +27,7 @@ select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER + select DRIVER_ANALOGIX_ANX7625 if BOARD_GOOGLE_ASURADA config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/46576 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I837e56ba4e98cc94c33484e79c4d5ff45a62becd Gerrit-Change-Number: 46576 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

5 13

Change in coreboot[master]: WIP: soc/mediatek/mt8192: Add display controller driver
by yongqiang niu (Code Review) 14 Dec '20

14 Dec '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46577 ) Change subject: WIP: soc/mediatek/mt8192: Add display controller driver ...................................................................... WIP: soc/mediatek/mt8192: Add display controller driver The MT8192 SOC has a DISP (display controller) that supports overlay, read/write DMA, ... etc. The output of DISP goes to display interface DSI, DPI or DBI directly. BUG=b:80501386,b:155713214 BRANCH=none TEST=Boots correctly on asurada Signed-off-by: Yongqiang Niu <yongqiang.niu(a)mediatek.com> Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/ddp.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/ddp.h 4 files changed, 485 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/46577/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index b2a8a9e..119d999 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -59,6 +59,7 @@ ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c usb.c +ramstage-y += ../common/ddp.c ddp.c ramstage-y += ../common/dsi.c dsi.c MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192 diff --git a/src/soc/mediatek/mt8192/ddp.c b/src/soc/mediatek/mt8192/ddp.c new file mode 100644 index 0000000..0d5eab5 --- /dev/null +++ b/src/soc/mediatek/mt8192/ddp.c @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <edid.h> +#include <soc/addressmap.h> +#include <soc/ddp.h> + +static void disp_config_main_path_connection(void) +{ + /* ovl0->ovl0_2l */ + write32(&mmsys_cfg->mmsys_ovl_mout_en, + (DISP_OVL0_GO_BG | DISP_OVL0_2L_GO_BLEND)); + write32(&mmsys_cfg->ovl0_2l_mout_en, OVL0_MOUT_EN_DISP_RDMA0); + write32(&mmsys_cfg->rdma0_sel_in, RDMA0_SEL_IN_OVL0_2L); + write32(&mmsys_cfg->rdma0_sout_sel, RDMA0_SOUT_COLOR0); + write32(&mmsys_cfg->ccorr0_sout_sel, CCORR0_SOUT_AAL0); + write32(&mmsys_cfg->aal0_sel_in, AAL0_SEL_IN_CCORR0); + write32(&mmsys_cfg->dither0_mout_en, DITHER0_MOUT_DSI0); + write32(&mmsys_cfg->dsi0_sel_in, DSI0_SEL_IN_DITHER0); +} + +static void disp_config_main_path_mutex(void) +{ + write32(&disp_mutex->mutex[0].mod, MUTEX_MOD_MAIN_PATH); + + /* Clock source from DSI0 */ + write32(&disp_mutex->mutex[0].ctl, + MUTEX_SOF_DSI0 | (MUTEX_SOF_DSI0 << 6)); + write32(&disp_mutex->mutex[0].en, BIT(0)); +} + +static void ovl_bgclr_in_sel(u32 idx) +{ + setbits32(&disp_ovl[idx]->datapath_con, BIT(2)); +} + +static void ovl_layer_smi_id_en(u32 idx) +{ + printk(BIOS_INFO, "%s\n", __func__); + + setbits32(&disp_ovl[idx]->datapath_con, BIT(0)); +} + +static void ccorr_config(u32 width, u32 height) +{ + struct disp_ccorr_regs *const regs = disp_ccorr; + int enable_relay = 0; + + printk(BIOS_INFO, "%s\n", __func__); + + write32(&regs->size, width << 16 | height); + + if (enable_relay) { + setbits32(&regs->cfg, PQ_RELAY_MODE); + clrbits32(&regs->cfg, PQ_ENGINE_EN); + } else { + clrbits32(&regs->cfg, PQ_RELAY_MODE); + setbits32(&regs->cfg, PQ_ENGINE_EN); + } + + write32(&regs->en, PQ_EN); +} + +static void aal_config(u32 width, u32 height) +{ + struct disp_aal_regs *const regs = disp_aal; + int enable_relay = 1; + + printk(BIOS_INFO, "%s\n", __func__); + + write32(&regs->size, width << 16 | height); + write32(&regs->output_size, width << 16 | height); + + if (enable_relay) { + setbits32(&regs->cfg, PQ_RELAY_MODE); + clrbits32(&regs->cfg, PQ_ENGINE_EN); + } else { + clrbits32(&regs->cfg, PQ_RELAY_MODE); + setbits32(&regs->cfg, PQ_ENGINE_EN); + } + + write32(&regs->en, PQ_EN); +} + +static void gamma_config(u32 width, u32 height) +{ + struct disp_gamma_regs *const regs = disp_gamma; + int enable_relay = 0; + + printk(BIOS_INFO, "%s\n", __func__); + + write32(&regs->size, width << 16 | height); + + if (enable_relay) + setbits32(&regs->cfg, PQ_RELAY_MODE); + else + clrbits32(&regs->cfg, PQ_RELAY_MODE); + + write32(&regs->en, PQ_EN); +} + +static void postmask_config(u32 width, u32 height) +{ + struct disp_postmask_regs *const regs = disp_postmask; + int enable_relay = 1; + + printk(BIOS_INFO, "%s\n", __func__); + + write32(&regs->size, width << 16 | height); + + if (enable_relay) + setbits32(&regs->cfg, PQ_RELAY_MODE); + else + clrbits32(&regs->cfg, PQ_RELAY_MODE); + + write32(&regs->en, PQ_EN); +} + +static void dither_config(u32 width, u32 height) +{ + struct disp_dither_regs *const regs = disp_dither; + int enable_relay = 1; + + printk(BIOS_INFO, "%s\n", __func__); + + write32(&regs->size, width << 16 | height); + + if (enable_relay) + setbits32(&regs->cfg, PQ_RELAY_MODE); + else + clrbits32(&regs->cfg, PQ_RELAY_MODE); + + write32(&regs->en, PQ_EN); +} + + +static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh) +{ + u32 idx = 0; + u32 pixel_clk = width * height * vrefresh; + + printk(BIOS_INFO, "%s\n", __func__); + + for (idx = 0; idx < MAIN_PATH_OVL_NR; idx++) { + ovl_set_roi(idx, width, height, idx ? 0 : 0xff0000ff); + ovl_layer_smi_id_en(idx); + } + + rdma_config(width, height, pixel_clk, 5 * KiB); + color_start(width, height); + ccorr_config(width, height); + aal_config(width, height); + gamma_config(width, height); + postmask_config(width, height); + dither_config(width, height); + disp_config_main_path_connection(); + disp_config_main_path_mutex(); +} + +static void disp_clock_on(void) +{ + clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL); + + clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_ALL); + + clrbits32(&mmsys_cfg->mmsys_cg_con2, CG_CON2_DISP_ALL); +} + +void mtk_ddp_init(void) +{ + disp_clock_on(); + /* Turn off M4U port. */ + write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_DISP_POSTMASK0), 0); + write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0_HDR), 0); + write32((void *)(SMI_LARB0 + SMI_LARB_L0_OVL_RDMA0), 0); +} + +void mtk_ddp_mode_set(const struct edid *edid) +{ + u32 fmt = OVL_INFMT_RGBA8888; + u32 bpp = edid->framebuffer_bits_per_pixel / 8; + u32 width = edid->mode.ha; + u32 height = edid->mode.va; + u32 vrefresh = edid->mode.refresh; + + printk(BIOS_INFO, "%s display resolution: %dx%d@%d bpp %d\n", + __func__, width, height, vrefresh, bpp); + + if (!vrefresh) { + vrefresh = 60; + printk(BIOS_INFO, "%s invalid vrefresh %d\n", + __func__, vrefresh); + } + + main_disp_path_setup(width, height, vrefresh); + rdma_start(); + ovl_layer_config(fmt, bpp, width, height); + ovl_bgclr_in_sel(1); +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index eac4a9a..198beaa 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -65,6 +65,19 @@ MSDC0_BASE = IO_PHYS + 0x01F60000, DEVAPC_INFRA_AO_BASE = IO_PHYS + 0x00030000, MIPITX_BASE = IO_PHYS + 0x01E50000, + MMSYS_BASE = IO_PHYS + 0x04000000, + DISP_MUTEX_BASE = IO_PHYS + 0x04001000, + SMI_BASE = IO_PHYS + 0x04002000, + SMI_LARB0 = IO_PHYS + 0x04003000, + DISP_OVL0_BASE = IO_PHYS + 0x04005000, /* ovl0 */ + DISP_OVL1_BASE = IO_PHYS + 0x04006000, /* ovl0_2l */ + DISP_RDMA0_BASE = IO_PHYS + 0x04007000, + DISP_COLOR0_BASE = IO_PHYS + 0x04009000, + DISP_CCORR0_BASE = IO_PHYS + 0x0400A000, + DISP_AAL0_BASE = IO_PHYS + 0x0400B000, + DISP_GAMMA0_BASE = IO_PHYS + 0x0400C000, + DISP_POSTMASK0_BASE = IO_PHYS + 0x0400D000, + DISP_DITHER0_BASE = IO_PHYS + 0x0400E000, DSI0_BASE = IO_PHYS + 0x04010000, }; diff --git a/src/soc/mediatek/mt8192/include/soc/ddp.h b/src/soc/mediatek/mt8192/include/soc/ddp.h new file mode 100644 index 0000000..18b2e27 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/ddp.h @@ -0,0 +1,272 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MT8183_SOC_DDP_H_ +#define _MT8183_SOC_DDP_H_ + +#include <soc/addressmap.h> +#include <soc/ddp_common.h> +#include <types.h> + +#define MAIN_PATH_OVL_NR 2 + +struct mmsys_cfg_regs { + u32 reserved_0x000[64]; /* 0x000 */ + u32 mmsys_cg_con0; /* 0x100 */ + u32 mmsys_cg_set0; /* 0x104 */ + u32 mmsys_cg_clr0; /* 0x108 */ + u32 reserved_0x10C; /* 0x10C */ + u32 mmsys_cg_con1; /* 0x110 */ + u32 mmsys_cg_set1; /* 0x114 */ + u32 mmsys_cg_clr1; /* 0x118 */ + u32 reserved_0x11C[33]; /* 0x11C */ + u32 mmsys_cg_con2; /* 0x1A0 */ + u32 mmsys_cg_set2; /* 0x1A4 */ + u32 mmsys_cg_clr2; /* 0x1A8 */ + u32 reserved_0x1AC[853]; /* 0x1AC */ + u32 reserved_0xF00; /* 0xF00 */ + u32 mmsys_ovl_mout_en; /* 0xF04 */ + u32 reserved_0xF08; /* 0xF08 */ + u32 reserved_0xF0C; /* 0xF0C */ + u32 reserved_0xF10; /* 0xF10 */ + u32 reserved_0xF14; /* 0xF14 */ + u32 ovl0_2l_mout_en; /* 0xF18 */ + u32 ovl0_mout_en; /* 0xF1C */ + u32 reserved_0xF20; /* 0xF20 */ + u32 reserved_0xF24; /* 0xF24 */ + u32 reserved_0xF28; /* 0xF28 */ + u32 rdma0_sel_in; /* 0xF2C */ + u32 rdma0_sout_sel; /* 0xF30 */ + u32 ccorr0_sout_sel; /* 0xF34 */ + u32 aal0_sel_in; /* 0xF38 */ + u32 dither0_mout_en; /* 0xF3C*/ + u32 dsi0_sel_in; /* 0xF40*/ +}; + +check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100); +check_member(mmsys_cfg_regs, mmsys_cg_con1, 0x110); +check_member(mmsys_cfg_regs, mmsys_cg_con2, 0x1A0); +check_member(mmsys_cfg_regs, mmsys_ovl_mout_en, 0xF04); +check_member(mmsys_cfg_regs, ovl0_2l_mout_en, 0xF18); +check_member(mmsys_cfg_regs, dsi0_sel_in, 0xF40); +static struct mmsys_cfg_regs *const mmsys_cfg = + (void *)MMSYS_BASE; + + +/* DISP_REG_CONFIG_MMSYS_CG_CON0 + Configures free-run clock gating 0 + 0: Enable clock + 1: Clock gating */ +enum { + CG_CON0_DISP_MUTEX0 = BIT(0), + CG_CON0_DISPSYS_CONFIG = BIT(1), + CG_CON0_DISP_OVL0 = BIT(2), + CG_CON0_DISP_RDMA0 = BIT(3), + CG_CON0_DISP_OVL0_2L = BIT(4), + CG_CON0_DISP_AAL0 = BIT(8), + CG_CON0_DISP_CCORR0 = BIT(9), + CG_CON0_DISP_DITHER0 = BIT(10), + CG_CON0_SMI_INFRA = BIT(11), + CG_CON0_DISP_GAMMA0 = BIT(12), + CG_CON0_DISP_POSTMASK0 = BIT(13), + CG_CON0_DISP_DSI0 = BIT(15), + CG_CON0_DISP_COLOR0 = BIT(16), + CG_CON0_SMI_COMMON = BIT(17), + + CG_CON0_SMI_GALS = BIT(27), + CG_CON0_DISP_ALL = CG_CON0_SMI_INFRA | + CG_CON0_SMI_COMMON | + CG_CON0_SMI_GALS | + CG_CON0_DISP_MUTEX0 | + CG_CON0_DISPSYS_CONFIG | + CG_CON0_DISP_OVL0 | + CG_CON0_DISP_RDMA0 | + CG_CON0_DISP_OVL0_2L | + CG_CON0_DISP_AAL0 | + CG_CON0_DISP_CCORR0 | + CG_CON0_DISP_DITHER0 | + CG_CON0_DISP_GAMMA0 | + CG_CON0_DISP_POSTMASK0 | + CG_CON0_DISP_DSI0 | + CG_CON0_DISP_COLOR0, + CG_CON0_ALL = 0xffffffff +}; + +/* DISP_REG_CONFIG_MMSYS_CG_CON1 + Configures free-run clock gating 1 + 0: Enable clock + 1: Clock gating */ +enum { + CG_CON1_SMI_IOMMU = BIT(0), + CG_CON1_DISP_ALL = CG_CON1_SMI_IOMMU, + CG_CON1_ALL = 0xffffffff +}; + +enum { + CG_CON2_DSI_DSI0 = BIT(0), + CG_CON2_DPI_DPI0 = BIT(8), + CG_CON2_MM_26MHZ = BIT(24), + CG_CON2_DISP_ALL = CG_CON2_DSI_DSI0 | + CG_CON2_MM_26MHZ, + CG_CON2_ALL = 0xffffffff +}; + + +enum { + DISP_OVL0_GO_BLEND = BIT(0), + DISP_OVL0_GO_BG = BIT(1), + DISP_OVL0_2L_GO_BLEND = BIT(2), + DISP_OVL0_2L_GO_BG = BIT(3), + OVL0_MOUT_EN_DISP_RDMA0 = BIT(0), + DITHER0_MOUT_DSI0 = BIT(0), +}; + +enum { + RDMA0_SEL_IN_OVL0_2L = 0x3, + RDMA0_SOUT_COLOR0 = 0x1, + CCORR0_SOUT_AAL0 = 0x1, + AAL0_SEL_IN_CCORR0 = 0x1, + DSI0_SEL_IN_DITHER0 = 0x1, +}; + +struct disp_mutex_regs { + u32 inten; + u32 intsta; + u32 reserved0[6]; + struct { + u32 en; + u32 dummy; + u32 rst; + u32 ctl; + u32 mod; + u32 reserved[3]; + } mutex[12]; +}; + +static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE; + +enum { + MUTEX_MOD_DISP_OVL0 = BIT(0), + MUTEX_MOD_DISP_OVL0_2L = BIT(1), + MUTEX_MOD_DISP_RDMA0 = BIT(2), + MUTEX_MOD_DISP_COLOR0 = BIT(4), + MUTEX_MOD_DISP_CCORR0 = BIT(5), + MUTEX_MOD_DISP_AAL0 = BIT(6), + MUTEX_MOD_DISP_GAMMA0 = BIT(7), + MUTEX_MOD_DISP_POSTMASK0 = BIT(8), + MUTEX_MOD_DISP_DITHER0 = BIT(9), + MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | + MUTEX_MOD_DISP_OVL0_2L | + MUTEX_MOD_DISP_RDMA0 | + MUTEX_MOD_DISP_COLOR0 | + MUTEX_MOD_DISP_CCORR0 | + MUTEX_MOD_DISP_AAL0 | + MUTEX_MOD_DISP_GAMMA0 | + MUTEX_MOD_DISP_POSTMASK0 | + MUTEX_MOD_DISP_DITHER0, +}; + +enum { + MUTEX_SOF_SINGLE_MODE = 0, + MUTEX_SOF_DSI0 = 1, + MUTEX_SOF_DPI0 = 2, +}; + +struct disp_ccorr_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[27]; + u32 shadow; +}; +check_member(disp_ccorr_regs, shadow, 0xA0); + +struct disp_gamma_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; +}; +check_member(disp_gamma_regs, size, 0x30); + +struct disp_aal_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[47]; + u32 shadow; + u32 reserved3[249]; + u32 output_size; +}; +check_member(disp_aal_regs, shadow, 0xF0); +check_member(disp_aal_regs, output_size, 0x4D8); + +struct disp_postmask_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 reserved0[4]; + u32 cfg; + u32 reserved1[3]; + u32 size; +}; +check_member(disp_postmask_regs, size, 0x30); + +struct disp_dither_regs { + u32 en; + u32 reset; + u32 inten; + u32 intsta; + u32 status; + u32 reserved0[3]; + u32 cfg; + u32 reserved1[3]; + u32 size; + u32 reserved2[51]; + u32 shadow; +}; +check_member(disp_dither_regs, shadow, 0x100); + +enum { + PQ_EN = BIT(0), + PQ_RELAY_MODE = BIT(0), + PQ_ENGINE_EN = BIT(1), +}; + +static struct disp_ccorr_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE; + +static struct disp_aal_regs *const disp_aal = (void *)DISP_AAL0_BASE; + +static struct disp_gamma_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE; + +static struct disp_dither_regs *const disp_dither = (void *)DISP_DITHER0_BASE; + +static struct disp_postmask_regs *const disp_postmask = (void *)DISP_POSTMASK0_BASE; + +enum { + SMI_LARB_PORT_L0_DISP_POSTMASK0 = 0x380, + SMI_LARB_PORT_L0_OVL_RDMA0_HDR = 0x384, + SMI_LARB_L0_OVL_RDMA0 = 0x388, +}; + +void mtk_ddp_init(void); +void mtk_ddp_mode_set(const struct edid *edid); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ad13175b8304beed9965d609ea3bd721311f154 Gerrit-Change-Number: 46577 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: WIP: coreboot: Add dsi file
by yongqiang niu (Code Review) 14 Dec '20

14 Dec '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46574 ) Change subject: WIP: coreboot: Add dsi file ...................................................................... WIP: coreboot: Add dsi file Add dsi APIs for coreboot display Signed-off-by: Huijuan Xie <huijuan.xie(a)mediatek.corp-partner.google.com> Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dsi.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dsi.h 4 files changed, 129 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/46574/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 04d57dc..b2a8a9e 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -59,6 +59,8 @@ ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c usb.c +ramstage-y += ../common/dsi.c dsi.c + MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192 cbfs-files-y += dpm.dm diff --git a/src/soc/mediatek/mt8192/dsi.c b/src/soc/mediatek/mt8192/dsi.c new file mode 100644 index 0000000..9f54f49 --- /dev/null +++ b/src/soc/mediatek/mt8192/dsi.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <device/mmio.h> +#include <delay.h> +#include <soc/dsi.h> +#include <soc/pll.h> + +void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes) +{ + unsigned int txdiv0, txdiv1; + u64 pcw; + + if (data_rate >= 2000 * MHz) { + txdiv0 = 0; + txdiv1 = 0; + } else if (data_rate >= 1000 * MHz) { + txdiv0 = 1; + txdiv1 = 0; + } else if (data_rate >= 500 * MHz) { + txdiv0 = 2; + txdiv1 = 0; + } else if (data_rate > 250 * MHz) { + /* (data_rate == 250MHz) is a special case that should go to the + else-block below (txdiv0 = 4) */ + txdiv0 = 3; + txdiv1 = 0; + } else { + /* MIN = 125 */ + assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ * MHz); + txdiv0 = 4; + txdiv1 = 0; + } + + clrbits32(&mipi_tx->pll_con4, BIT(11) | BIT(10)); + setbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON); + udelay(30); + clrbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN); + + pcw = (u64)data_rate * (1 << txdiv0) * (1 << txdiv1); + pcw <<= 24; + pcw /= CLK26M_HZ; + + write32(&mipi_tx->pll_con0, pcw); + clrsetbits32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8); + udelay(30); + setbits32(&mipi_tx->pll_con1, RG_DSI_PLL_EN); + + /* BG_LPF_EN / BG_CORE_EN */ + write32(&mipi_tx->lane_con, 0x3fff0180); + udelay(40); + write32(&mipi_tx->lane_con, 0x3fff00c0); + + /* Switch OFF each Lane */ + clrbits32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN); + + setbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN); +} + +void mtk_dsi_reset(void) +{ + write32(&dsi0->dsi_force_commit, + DSI_FORCE_COMMIT_USE_MMSYS | DSI_FORCE_COMMIT_ALWAYS); + write32(&dsi0->dsi_con_ctrl, 1); + write32(&dsi0->dsi_con_ctrl, 0); +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 3fd2bca..eac4a9a 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -64,6 +64,8 @@ MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, MSDC0_BASE = IO_PHYS + 0x01F60000, DEVAPC_INFRA_AO_BASE = IO_PHYS + 0x00030000, + MIPITX_BASE = IO_PHYS + 0x01E50000, + DSI0_BASE = IO_PHYS + 0x04010000, }; #endif diff --git a/src/soc/mediatek/mt8192/include/soc/dsi.h b/src/soc/mediatek/mt8192/include/soc/dsi.h new file mode 100644 index 0000000..4535d90 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dsi.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8183_DSI_H +#define SOC_MEDIATEK_MT8183_DSI_H + +#include <soc/dsi_common.h> + +/* DSI features */ +#define MTK_DSI_MIPI_RATIO_NUMERATOR 100 +#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100 +#define MTK_DSI_DATA_RATE_MIN_MHZ 125 +#define MTK_DSI_HAVE_SIZE_CON 1 +#define PIXEL_STREAM_CUSTOM_HEADER 0xb + +/* MIPITX is SOC specific and cannot live in common. */ + +/* MIPITX_REG */ +struct mipi_tx_regs { + u32 reserved0[3]; + u32 lane_con; + u32 reserved1[6]; + u32 pll_pwr; + u32 pll_con0; + u32 pll_con1; + u32 pll_con2; + u32 pll_con3; + u32 pll_con4; + u32 reserved2[65]; + u32 d2_sw_ctl_en; + u32 reserved3[63]; + u32 d0_sw_ctl_en; + u32 reserved4[56]; + u32 ck_ckmode_en; + u32 reserved5[6]; + u32 ck_sw_ctl_en; + u32 reserved6[63]; + u32 d1_sw_ctl_en; + u32 reserved7[63]; + u32 d3_sw_ctl_en; +}; + +check_member(mipi_tx_regs, pll_con4, 0x3c); +check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544); +static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE; + +/* Register values */ +#define DSI_CK_CKMODE_EN BIT(0) +#define DSI_SW_CTL_EN BIT(0) +#define AD_DSI_PLL_SDM_PWR_ON BIT(0) +#define AD_DSI_PLL_SDM_ISO_EN BIT(1) + +#define RG_DSI_PLL_EN BIT(4) +#define RG_DSI_PLL_POSDIV (0x7 << 8) + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/46574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I067db08f5600aeee216f482fec49ab75f75a602a Gerrit-Change-Number: 46574 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit October 2020