coreboot-gerrit October 2020

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Change in libgfxinit[master]: gma: Export backlight control interface
by Nico Huber (Code Review) 21 Dec '20

21 Dec '20

Hello Angel Pons, I'd like you to do a code review. Please visit https://review.coreboot.org/c/libgfxinit/+/43668 to review the following change. Change subject: gma: Export backlight control interface ...................................................................... gma: Export backlight control interface Change-Id: I5a157d7849124fd3b4cca8f9de1d605092fd3c5e Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M common/hw-gfx-gma.adb M common/hw-gfx-gma.ads 2 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/68/43668/1 diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 9157bbe..fae40ed 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -388,6 +388,40 @@ ---------------------------------------------------------------------------- + procedure Backlight_On (Port : Active_Port_Type) + with + Refined_Global => (In_Out => Registers.Register_State) + is + begin + Panel.Backlight_On (Config_Helpers.To_Panel (Port)); + end Backlight_On; + + procedure Backlight_Off (Port : Active_Port_Type) + with + Refined_Global => (In_Out => Registers.Register_State) + is + begin + Panel.Backlight_Off (Config_Helpers.To_Panel (Port)); + end Backlight_Off; + + procedure Set_Brightness (Port : Active_Port_Type; Level : Word32) + with + Refined_Global => (In_Out => Registers.Register_State) + is + begin + Panel.Set_Backlight (Config_Helpers.To_Panel (Port), Level); + end Set_Brightness; + + procedure Get_Max_Brightness (Port : Active_Port_Type; Level : out Word32) + with + Refined_Global => (In_Out => Registers.Register_State) + is + begin + Panel.Get_Max_Backlight (Config_Helpers.To_Panel (Port), Level); + end Get_Max_Brightness; + + ---------------------------------------------------------------------------- + procedure Initialize (Write_Delay : in Word64 := 0; Clean_State : in Boolean := False; diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 1215fc5..747d2f1 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -161,6 +161,24 @@ ---------------------------------------------------------------------------- + procedure Backlight_On (Port : Active_Port_Type) + with + Global => (In_Out => Device_State); + + procedure Backlight_Off (Port : Active_Port_Type) + with + Global => (In_Out => Device_State); + + procedure Set_Brightness (Port : Active_Port_Type; Level : Word32) + with + Global => (In_Out => Device_State); + + procedure Get_Max_Brightness (Port : Active_Port_Type; Level : out Word32) + with + Global => (In_Out => Device_State); + + ---------------------------------------------------------------------------- + procedure Write_GTT (GTT_Page : GTT_Range; Device_Address : GTT_Address_Type; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/43668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I5a157d7849124fd3b4cca8f9de1d605092fd3c5e Gerrit-Change-Number: 43668 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/tpm: Implement full PPI
by Patrick Rudolph (Code Review) 21 Dec '20

21 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45568 ) Change subject: drivers/tpm: Implement full PPI ...................................................................... drivers/tpm: Implement full PPI Implement the ACPI PPI interface as described in "TCG PC Client Physical Presence Interface Specification" Version 1.3. Add a new Kconfig that allows to use the full PPI instead of the stub version compiled in. This doesn't add code to execute the PPI request, as that's up to the payload with graphical UI support. Tested on GNU/Linux 5.6 using the sysfs interface at: /sys/class/tpm/tpm0/ppi/ Change-Id: Ifffe1d9b715e2c37568e1b009e86c298025c89ac Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/commonlib/include/commonlib/cbmem_id.h M src/drivers/tpm/Kconfig M src/drivers/tpm/Makefile.inc A src/drivers/tpm/ppi.c M src/drivers/tpm/tpm_ppi.h 5 files changed, 732 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/45568/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index ac271a0..38d0aee 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -55,6 +55,7 @@ #define CBMEM_ID_TCPA_TCG_LOG 0x54445041 #define CBMEM_ID_TIMESTAMP 0x54494d45 #define CBMEM_ID_TPM2_TCG_LOG 0x54504d32 +#define CBMEM_ID_TPM_PPI 0x54505049 #define CBMEM_ID_VBOOT_HANDOFF 0x780074f0 /* deprecated */ #define CBMEM_ID_VBOOT_SEL_REG 0x780074f1 /* deprecated */ #define CBMEM_ID_VBOOT_WORKBUF 0x78007343 diff --git a/src/drivers/tpm/Kconfig b/src/drivers/tpm/Kconfig index 8508210..d3d343c 100644 --- a/src/drivers/tpm/Kconfig +++ b/src/drivers/tpm/Kconfig @@ -5,3 +5,14 @@ help This driver automatically initializes the TPM if vboot is not used. The TPM driver init is done during the ramstage chip init phase. + +config TPM_PPI + bool "TPM: Generate ACPI code for physical presence interface" + depends on TPM1 || TPM2 + depends on HAVE_ACPI_TABLES + depends on !CHROMEOS + default y if PAYLOAD_TIANOCORE || PAYLOAD_SEABIOS + help + This driver automatically generates ACPI tables for the Physical + Presence Interface defined by the Tcg. If not activated only a Stub + will be generated without any functionality. diff --git a/src/drivers/tpm/Makefile.inc b/src/drivers/tpm/Makefile.inc index 5fc4632..af6e5a21 100644 --- a/src/drivers/tpm/Makefile.inc +++ b/src/drivers/tpm/Makefile.inc @@ -1,3 +1,7 @@ ramstage-$(CONFIG_TPM_INIT) += tpm.c +ifeq ($(CONFIG_TPM_PPI),y) +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ppi.c +else ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ppi_stub.c +endif diff --git a/src/drivers/tpm/ppi.c b/src/drivers/tpm/ppi.c new file mode 100644 index 0000000..7665973 --- /dev/null +++ b/src/drivers/tpm/ppi.c @@ -0,0 +1,624 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> +#include <stddef.h> +#include <acpi/acpi.h> +#include <acpi/acpigen.h> +#include <acpi/acpi_device.h> +#include <cbmem.h> +#include <console/console.h> + +#include "tpm_ppi.h" + +/* This file contains PPI functions only, but no ACPI code! */ + +static void set_package_element_op(const char *package_name, unsigned int element, + uint8_t src_op) +{ + acpigen_write_store(); + acpigen_emit_byte(src_op); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring(package_name); + acpigen_write_integer(element); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ +} + +static void set_package_element_name(const char *package_name, unsigned int element, + const char *src) +{ + acpigen_write_store(); + acpigen_emit_namestring(src); + acpigen_emit_byte(INDEX_OP); + acpigen_emit_namestring(package_name); + acpigen_write_integer(element); + acpigen_emit_byte(ZERO_OP); /* Ignore Index() Destination */ +} + +/* PPI function is passed in src_op. Converted to Local2. Clobbers Local1 and Local2 */ +static void verify_supported_ppi(uint8_t src_op) +{ + /* + * Old OS incorrectly pass a Buffer instead of a Package. + * See Tcg Physical Presence Interface Specification Chapter 8.1.2 for details. + */ + + /* If (ObjectType(Arg3) == Package) */ + acpigen_write_store(); + acpigen_emit_byte(OBJ_TYPE_OP); + acpigen_emit_byte(src_op); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 4); + acpigen_get_package_op_element(src_op, 0, LOCAL2_OP); + acpigen_pop_len(); + + /* If (ObjectType(Arg3) == Buffer) */ + acpigen_write_store(); + acpigen_emit_byte(OBJ_TYPE_OP); + acpigen_emit_byte(src_op); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 3); + acpigen_write_to_integer(src_op, LOCAL2_OP); + acpigen_pop_len(); + + /* Check if it's a valid PPI function */ + acpigen_write_store(); + acpigen_emit_namestring("^FSUP"); + acpigen_emit_byte(LOCAL2_OP); + acpigen_emit_byte(CONFIG(TPM1) ? ONE_OP : ZERO_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 0); + + /* + * Note: Must fake success for 1-4, 6-13, 15-16, 19-20 + * see "Trusted Execution Environment ACPI Profile" + * + * Even if not available, the TPM 1.2 PPI must be advertised as + * supported. Tests showed that Windows relies on it, even when + * a TPM2.0 is present! + * The functions aren't actually used when a TPM2.0 is present... + * Without this the Windows TPM 2.0 stack refuses to work. + */ + + /* + * Check if we have TPM1.2 but a TPM2 PPI function was called + * or if we have TPM2.0 but a TPM1.2 PPI function was called. + */ + acpigen_write_store(); + acpigen_emit_namestring("^FSUP"); + acpigen_emit_byte(LOCAL2_OP); + acpigen_emit_byte(CONFIG(TPM1) ? ZERO_OP : ONE_OP); + acpigen_emit_byte(LOCAL1_OP); + + acpigen_write_if_lequal_op_int(LOCAL1_OP, 1); + acpigen_write_return_integer(0); /* Fake Success, as per TPM spec */ + acpigen_pop_len(); + acpigen_write_return_integer(1); /* Not supported */ + + acpigen_pop_len(); +} + +/* TPM PPI functions */ + +static void tpm_ppi_func0_cb(void *arg) +{ + /* Functions 1-8. */ + u8 buf[] = {0xff, 0x01}; + acpigen_write_return_byte_buffer(buf, 2); +} + + /* + * PPI 1.0: 2.1.1 Get Physical Presence Interface Version + * + * Arg2 (Integer): Function Index = 1 + * Arg3 (Package): Arguments = Empty Package + * + * Returns: Type: String + */ +static void tpm_ppi_func1_cb(void *arg) +{ + if (CONFIG(TPM2)) + /* Interface version: 1.3 */ + acpigen_write_return_string("1.3"); + else + /* Interface version: 1.2 */ + acpigen_write_return_string("1.2"); +} + +/* + * Submit TPM Operation Request to Pre-OS Environment [Windows optional] + * PPI 1.0: 2.1.3 Submit TPM Operation Request to Pre-OS Environment + * + * Supported Revisions: 1 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 2 + * Arg3 (Package): Arguments = Package: Type: Integer + * Operation Value of the Request + * + * Returns: Type: Integer + * 0: Success + * 1: Operation Value of the Request Not Supported + * 2: General Failure + */ +static void tpm_ppi_func2_cb(void *arg) +{ + /* Revision 1 */ + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + + /* Local2 = ConvertAndVerify(Arg3) */ + verify_supported_ppi(ARG3_OP); + + acpigen_write_store_op_to_namestr(LOCAL2_OP, "^CMDR"); + acpigen_write_store_op_to_namestr(ZERO_OP, "^OARG"); + acpigen_write_store_op_to_namestr(ZERO_OP, "^USER"); + + acpigen_write_return_integer (0); /* Success */ + acpigen_pop_len(); + + acpigen_write_return_integer(2); /* General Failure */ +} + +/* + * PPI 1.0: 2.1.4 Get Pending TPM Operation Requested By the OS + * + * Supported Revisions: 1, 2 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 3 + * Arg3 (Package): Empty package + * + * Returns: Type: Package(Integer, Integer, Integer (optional)) + * Integer 1: + * 0: Success + * 1: General Failure + * Integer 2: + * Pending TPM operation requested by OS + * Integer 3: + * Pending TPM operation argument requested by OS + */ +static void tpm_ppi_func3_cb(void *arg) +{ + /* ^TPM3 [0] = One */ + set_package_element_op("^TPM3", 0, ONE_OP); + + /* ^TPM2 [0] = One */ + set_package_element_op("^TPM2", 0, ONE_OP); + + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + + /* Revision 1 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + + /* ^TPM2 [0] = Zero */ + set_package_element_op("^TPM2", 0, ZERO_OP); + + /* ^TPM2 [1] = ^CMDR */ + set_package_element_name("^TPM2", 1, "^CMDR"); + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("^TPM2"); + acpigen_pop_len(); + + /* + * A return value of {0, 23, 1} indicates that operation 23 + * with argument 1 is pending. + */ + + /* Revision 2 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 2); + + /* ^TPM3 [0] = Zero */ + set_package_element_op("^TPM3", 0, ZERO_OP); + + /* ^TPM3 [1] = ^CMDR */ + set_package_element_name("^TPM3", 1, "^CMDR"); + + /* ^TPM3 [2] = ^OARG */ + set_package_element_name("^TPM3", 2, "^OARG"); + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("^TPM3"); + acpigen_pop_len(); + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("^TPM3"); +} + +/* + * PPI 1.0: 2.1.5 Get Platform-Specific Action to Transition to Pre-OS Environment + * + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 4 + * Arg3 (Package): Empty package + * + * Returns: Type: Integer + * 0: None + * 1: Shutdown + * 2: Reboot + * 3: Vendor specific + */ +static void tpm_ppi_func4_cb(void *arg) +{ + /* Pre-OS transition method: reboot. */ + acpigen_write_return_byte(2); +} + +/* + * PPI 1.0: 2.1.6 Return TPM Operation Response to OS Environment + * + * Supported Revisions: 1 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 5 + * Arg3 (Package): Empty package + * + * Returns: Type: Package(Integer, Integer, Integer) + * Integer 1: + * 0: Success + * 1: General Failure + * Integer 2: + * Most recent TPM operation requested by OS + * Integer 3: + * Response to most recent TPM operation requested by OS + */ +static void tpm_ppi_func5_cb(void *arg) +{ + /* ^TPM3 [0] = One */ + set_package_element_op("^TPM3", 0, ONE_OP); + + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + + /* Revision 1 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + + /* ^TPM3 [0] = Zero */ + set_package_element_op("^TPM3", 0, ZERO_OP); + + /* ^TPM3 [1] = ^LCMD */ + set_package_element_name("^TPM3", 1, "^LCMD"); + + /* ^TPM3 [2] = ^RESU */ + set_package_element_name("^TPM3", 2, "^RESU"); + + acpigen_pop_len(); + + acpigen_emit_byte(RETURN_OP); + acpigen_emit_namestring("^TPM3"); +} + +/* + * PPI 1.2: 2.1.6 Submit preferred user language [Windows optional] + * + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 5 + * Arg3 (Package): Empty package + */ +static void tpm_ppi_func6_cb(void *arg) +{ + /* + * Set preferred user language: deprecated and must return 3 aka + * "not implemented". + */ + acpigen_write_return_byte(3); +} + +/* + * PPI 1.2: 2.1.7 Submit TPM Operation Request to Pre-OS Environment 2 + * + * Supported Revisions: 1, 2 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 7 + * Arg3 (Package): Integer + * + * Returns: Type: Integer + * 0: Success + * 1: Not implemented + * 2: General Failure + * 3: Blocked by current BIOS settings + */ +static void tpm_ppi_func7_cb(void *arg) +{ + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + + /* Local2 = ConvertAndVerify(Arg3) */ + verify_supported_ppi(ARG3_OP); + + /* If (ObjectType(Arg3) == Buffer) */ + acpigen_write_store(); + acpigen_emit_byte(OBJ_TYPE_OP); + acpigen_emit_byte(ARG3_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 3); + + /* Enforce use of Revision 1 that doesn't take an optional argument. */ + + /* Local0 = One */ + acpigen_write_store(); + acpigen_emit_byte(ONE_OP); + acpigen_emit_byte(LOCAL0_OP); + + acpigen_pop_len(); + + // FIXME: Only advertise supported functions + + /* Revision 1 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + + /* ^CMDR = Local2 */ + acpigen_write_store_op_to_namestr(LOCAL2_OP, "^CMDR"); + + /* ^OARG = Zero */ + acpigen_write_store_op_to_namestr(ZERO_OP, "^OARG"); + + acpigen_write_return_byte(0); /* Success */ + acpigen_pop_len(); + + /* Revision 2 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 2); + /* ^CMDR = Local2 */ + acpigen_write_store_op_to_namestr(LOCAL2_OP, "^CMDR"); + + /* ^OARG = Arg3 [1] */ + acpigen_get_package_op_element(ARG3_OP, 1, LOCAL3_OP); + acpigen_write_store(); + acpigen_emit_byte(LOCAL3_OP); + acpigen_emit_namestring("^OARG"); + + acpigen_write_return_byte(0); /* Success */ + acpigen_pop_len(); + + acpigen_write_return_byte(2); /* General failure */ +} + +/* + * PPI 1.2: 2.1.8 Get User Confirmation Status for Operation + * + * Returns if a command is supported and allowed by firmware + * Supported Revisions: 1 + * Arg1 (Integer): Revision + * Arg2 (Integer): Function Index = 7 + * Arg3 (Package): Integer + * + * Returns: Type: Integer + * 0: Not implemented + * 1: BIOS only + * 2: Blocked for OS by BIOS settings + * 3: Allowed and physical present user required + * 4: Allowed and physical present user not required + */ +static void tpm_ppi_func8_cb(void *arg) +{ + acpigen_write_to_integer(ARG1_OP, LOCAL0_OP); + + /* Revision 1 */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 1); + acpigen_get_package_op_element(ARG3_OP, 0, LOCAL2_OP); + + /* Check if it's a valid PPI function */ + acpigen_write_store(); + acpigen_emit_namestring("^FSUP"); + acpigen_emit_byte(LOCAL2_OP); + acpigen_emit_byte(CONFIG(TPM1) ? ONE_OP : ZERO_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_write_if_lequal_op_int(LOCAL1_OP, 0); + acpigen_write_return_byte(0); /* Not implemented */ + acpigen_pop_len(); + + // FIXME: Only advertise supported functions + + if (CONFIG(TPM1)) { + /* + * Some functions do not require PP depending on configuration. + * Those aren't listed here, so the 'required PP' is always set for those. + */ + static const u32 tpm1_funcs[] = { + TPM_NOOP, + //FIXME + }; + for (size_t i = 0; i < ARRAY_SIZE(tpm1_funcs); i++) { + acpigen_write_if_lequal_op_int(LOCAL2_OP, tpm1_funcs[i]); + acpigen_write_return_integer(4); /* Supported, requires no PP */ + acpigen_pop_len(); /* Pop : If */ + } + } else if (CONFIG(TPM2)) { + /* + * Some functions do not require PP depending on configuration. + * Those aren't listed here, so the 'required PP' is always set for those. + */ + static const u32 tpm2_funcs[] = { + TPM2_NOOP, + TPM2_SET_PP_REQUIRED_FOR_CLEAR_TRUE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_TRUE, + TPM2_SET_PP_REQUIRED_FOR_TURN_ON_TRUE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_TRUE, + TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_TRUE, + TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_TRUE, + TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_TRUE, + }; + for (size_t i = 0; i < ARRAY_SIZE(tpm2_funcs); i++) { + acpigen_write_if_lequal_op_int(LOCAL2_OP, tpm2_funcs[i]); + acpigen_write_return_integer(4); /* Supported, requires no PP */ + acpigen_pop_len(); /* Pop : If */ + } + } + acpigen_write_return_integer(3); /* Supported, requires PP */ + + acpigen_pop_len(); + + acpigen_write_return_byte(0); /* Not implemented */ +} + +static void (*tpm_ppi_callbacks[])(void *) = { + tpm_ppi_func0_cb, + tpm_ppi_func1_cb, + tpm_ppi_func2_cb, + tpm_ppi_func3_cb, + tpm_ppi_func4_cb, + tpm_ppi_func5_cb, + tpm_ppi_func6_cb, + tpm_ppi_func7_cb, + tpm_ppi_func8_cb, +}; + +static void tpm_mci_func0_cb(void *arg) +{ + /* Function 1. */ + acpigen_write_return_singleton_buffer(0x3); +} +static void tpm_mci_func1_cb(void *arg) +{ + /* Just return success. */ + acpigen_write_return_byte(0); +} + +static void (*tpm_mci_callbacks[])(void *) = { + tpm_mci_func0_cb, + tpm_mci_func1_cb, +}; + +void tpm_ppi_acpi_fill_ssdt(const struct device *dev) +{ + u32 arg; + struct cb_tpm_ppi_payload_handshake *ppib; + + static const struct fieldlist list[] = { + FIELDLIST_NAMESTR("CMDR", 32),// The command requested by OS. 0 for NOP + FIELDLIST_NAMESTR("OARG", 32),// The command optional argument requested by OS + FIELDLIST_NAMESTR("LCMD", 32),// The last command requested by OS. + // Copied by firmware on command execution + FIELDLIST_NAMESTR("RESU", 32),// Result of the last operation (TPM error code) + }; + + /* + * On hot reset/ACPI S3 the contents are preserved. + */ + ppib = (void *)cbmem_add(CBMEM_ID_TPM_PPI, sizeof(*ppib)); + if (!ppib) { + printk(BIOS_ERR, "PPI: Failed to add CBMEM\n"); + return; + } + + /* Physical Presence OpRegion */ + struct opregion opreg = OPREGION("PPOP", SYSTEMMEMORY, (uintptr_t)ppib, + sizeof(*ppib)); + + acpigen_write_opregion(&opreg); + acpigen_write_field(opreg.name, list, ARRAY_SIZE(list), + FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); + + acpigen_write_name("TPM2"); + acpigen_write_package(2); + acpigen_write_dword(0); + acpigen_write_dword(0); + acpigen_pop_len(); /* Package */ + + acpigen_write_name("TPM3"); + acpigen_write_package(3); + acpigen_write_dword(0); + acpigen_write_dword(0); + acpigen_write_dword(0); + acpigen_pop_len(); /* Package */ + + /* + * Returns One if the PPI spec supports this functions. + * That doesn't necessarily mean that the firmware implemtents it, or the + * TPM can execute the function. + * + * Arg0: Integer PPI function + * Arg1: Integer TPMversion (0: TPM2, 1: TPM1.2) + */ + acpigen_write_method("FSUP", 2); + + acpigen_write_to_integer(ARG0_OP, LOCAL0_OP); + acpigen_write_to_integer(ARG1_OP, LOCAL1_OP); + acpigen_write_if(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_integer(0x80); + acpigen_write_return_integer(0); + acpigen_pop_len(); /* If */ + + acpigen_write_if_lequal_op_int(LOCAL1_OP, 1); + static const u32 tpm1_funcs[] = { + TPM_NOOP, + TPM_ENABLE, + TPM_DISABLE, + TPM_ACTIVATE, + TPM_DEACTIVATE, + TPM_CLEAR, + TPM_ENABLE_ACTIVATE, + TPM_DEACTIVATE_DISABLE, + TPM_SETOWNERINSTALL_TRUE, + TPM_SETOWNERINSTALL_FALSE, + TPM_ENABLE_ACTIVATE_SETOWNERINSTALL_TRUE, + TPM_SETOWNERINSTALL_FALSE_DEACTIVATE_DISABLE, + TPM_CLEAR_ENABLE_ACTIVATE, + TPM_SET_NOPPIPROVISION_FALSE, + TPM_SET_NOPPIPROVISION_TRUE, + TPM_ENABLE_ACTIVE_CLEAR, + TPM_ENABLE_ACTIVE_CLEAR_ENABLE_ACTIVE, + }; + for (size_t i = 0; i < ARRAY_SIZE(tpm1_funcs); i++) { + acpigen_write_if_lequal_op_int(LOCAL0_OP, tpm1_funcs[i]); + acpigen_write_return_integer(1); + acpigen_pop_len(); /* Pop : If */ + } + acpigen_pop_len(); /* If */ + + acpigen_write_if_lequal_op_int(LOCAL1_OP, 0); + static const u32 tpm2_funcs[] = { + TPM2_NOOP, + TPM2_ENABLE, + TPM2_DISABLE, + TPM2_CLEAR, + TPM2_CLEAR_ENABLE_ACTIVE, + TPM2_SET_PP_REQUIRED_FOR_CLEAR_TRUE, + TPM2_SET_PP_REQUIRED_FOR_CLEAR_FALSE, + TPM2_ENABLE_CLEAR, + TPM2_ENABLE_CLEAR2, + TPM2_SET_PCR_BANKS, + TPM2_CHANGE_EPS, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_FALSE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_TRUE, + TPM2_SET_PP_REQUIRED_FOR_TURN_ON_FALSE, + TPM2_SET_PP_REQUIRED_FOR_TURN_ON_TRUE, + TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_FALSE, + TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_TRUE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_FALSE, + TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_TRUE, + TPM2_LOG_ALL_DIGEST, + TPM2_DISABLE_ENDORSMENT_ENABLE_STORAGE_HISTORY, + TPM2_ENABLE_BLOCK_SID, + TPM2_DISABLE_BLOCK_SID, + TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_TRUE, + TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_FALSE, + TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_TRUE, + TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_FALSE, + }; + + for (size_t i = 0; i < ARRAY_SIZE(tpm2_funcs); i++) { + acpigen_write_if_lequal_op_int(LOCAL0_OP, tpm2_funcs[i]); + acpigen_write_return_integer(1); + acpigen_pop_len(); /* Pop : If */ + } + acpigen_pop_len(); /* If */ + + acpigen_write_return_integer(0); + acpigen_pop_len(); /* Method */ + + /* + * _DSM method + */ + struct dsm_uuid ids[] = { + /* Physical presence interface. + * This is used to submit commands like "Clear TPM" to + * be run at next reboot provided that user confirms + * them. + */ + DSM_UUID(TPM_PPI_UUID, &tpm_ppi_callbacks[0], + ARRAY_SIZE(tpm_ppi_callbacks), (void *) &arg), + /* Memory clearing on boot: just a dummy. */ + DSM_UUID(TPM_MCI_UUID, &tpm_mci_callbacks[0], + ARRAY_SIZE(tpm_mci_callbacks), (void *) &arg), + }; + + acpigen_write_dsm_uuid_arr(ids, ARRAY_SIZE(ids)); +} diff --git a/src/drivers/tpm/tpm_ppi.h b/src/drivers/tpm/tpm_ppi.h index 4bacbe5..4a61a38 100644 --- a/src/drivers/tpm/tpm_ppi.h +++ b/src/drivers/tpm/tpm_ppi.h @@ -18,4 +18,96 @@ /* TCG Memory Clear Interface */ #define TPM_MCI_UUID "376054ed-cc13-4675-901c-4756d7f2d45d" +/* + * Physical Presence Interface Specification Version 1.30 Revision 00.52 + * Table 1 Physical Presence Interface Operation Summary for TPM 1.2 + */ +#define TPM_NOOP 0 +#define TPM_ENABLE 1 +#define TPM_DISABLE 2 +#define TPM_ACTIVATE 3 +#define TPM_DEACTIVATE 4 +#define TPM_CLEAR 5 +#define TPM_ENABLE_ACTIVATE 6 +#define TPM_DEACTIVATE_DISABLE 7 +#define TPM_SETOWNERINSTALL_TRUE 8 +#define TPM_SETOWNERINSTALL_FALSE 9 +#define TPM_ENABLE_ACTIVATE_SETOWNERINSTALL_TRUE 10 +#define TPM_SETOWNERINSTALL_FALSE_DEACTIVATE_DISABLE 11 +#define TPM_CLEAR_ENABLE_ACTIVATE 14 +#define TPM_SET_NOPPIPROVISION_FALSE 15 +#define TPM_SET_NOPPIPROVISION_TRUE 16 +#define TPM_SET_NOPPICLEAR_FALSE 17 +#define TPM_SET_NOPPICLEAR_TRUE 18 +#define TPM_SET_NOPPIMAINTAINANCE_FALSE 19 +#define TPM_SET_NOPPIMAINTAINANCE_TRUE 20 +#define TPM_ENABLE_ACTIVE_CLEAR 21 +#define TPM_ENABLE_ACTIVE_CLEAR_ENABLE_ACTIVE 22 + +/* + * Physical Presence Interface Specification Version 1.30 Revision 00.52 + * Table 2 Physical Presence Interface Operation Summary for TPM 2.0 + */ +#define TPM2_NOOP 0 +#define TPM2_ENABLE 1 +#define TPM2_DISABLE 2 +#define TPM2_CLEAR 5 +#define TPM2_CLEAR_ENABLE_ACTIVE 14 +#define TPM2_SET_PP_REQUIRED_FOR_CLEAR_TRUE 17 +#define TPM2_SET_PP_REQUIRED_FOR_CLEAR_FALSE 18 +#define TPM2_ENABLE_CLEAR 21 +#define TPM2_ENABLE_CLEAR2 22 +#define TPM2_SET_PCR_BANKS 23 +#define TPM2_CHANGE_EPS 24 +#define TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_FALSE 25 +#define TPM2_SET_PP_REQUIRED_FOR_CHANGE_PCRS_TRUE 26 +#define TPM2_SET_PP_REQUIRED_FOR_TURN_ON_FALSE 27 +#define TPM2_SET_PP_REQUIRED_FOR_TURN_ON_TRUE 28 +#define TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_FALSE 29 +#define TPM2_SET_PP_REQUIRED_FOR_TURN_OFF_TRUE 30 +#define TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_FALSE 31 +#define TPM2_SET_PP_REQUIRED_FOR_CHANGE_EPS_TRUE 32 +#define TPM2_LOG_ALL_DIGEST 33 +#define TPM2_DISABLE_ENDORSMENT_ENABLE_STORAGE_HISTORY 34 +#define TPM2_ENABLE_BLOCK_SID 96 +#define TPM2_DISABLE_BLOCK_SID 97 +#define TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_TRUE 98 +#define TPM2_SET_PP_REQUIRED_FOR_ENABLE_BLOCK_SID_FALSE 99 +#define TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_TRUE 100 +#define TPM2_SET_PP_REQUIRED_FOR_DISABLE_BLOCK_SID_FALSE 101 + +/* TCG Physical Presence Interface */ +#define TPM_PPI_UUID "3dddfaa6-361b-4eb4-a424-8d10089d1653" +/* TCG Memory Clear Interface */ +#define TPM_MCI_UUID "376054ed-cc13-4675-901c-4756d7f2d45d" + +struct cb_tpm_ppi_payload_handshake { +#if 0 + //FIXME: filled by firmware that executes the PPI + /* + * Bitmask of supported PPI operations that doesn't require physical presence. + * To be set by firmware. + */ + u64 supported_functions1; + u64 supported_functions2; + /* + * Bitmask of supported PPI operations that require physical presence + * (due to user configuration). To be set by firmware. + */ + u64 supported_functions_pp1; + u64 supported_functions_pp2; +#endif + /* To be executed by firmware if user_fb_done and ppi_supported and + * user_fb_result is set. */ + u32 request; + /* To be executed by firmware if user_fb_done and ppi_supported and + * user_fb_result is set. */ + u32 request_argument; + /* Cleared on cold boot. Copy of request once firmware 'executed' the + * command. */ + u32 last_request; + /* Result of the requested command. Can also be a failure. */ + u32 last_result; +} __packed; + #endif /* _TPM_PPI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifffe1d9b715e2c37568e1b009e86c298025c89ac Gerrit-Change-Number: 45568 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 18

Change in coreboot[master]: drivers/tpm/ppi_stub: Fix interface version
by Patrick Rudolph (Code Review) 21 Dec '20

21 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45569 ) Change subject: drivers/tpm/ppi_stub: Fix interface version ...................................................................... drivers/tpm/ppi_stub: Fix interface version The latest version defined by Tcg is 1.3. Change-Id: Idb12e2212d6d38c720c8fe989678724c871af6ef Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/tpm/ppi_stub.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/45569/1 diff --git a/src/drivers/tpm/ppi_stub.c b/src/drivers/tpm/ppi_stub.c index a4b8f57..a5d0252 100644 --- a/src/drivers/tpm/ppi_stub.c +++ b/src/drivers/tpm/ppi_stub.c @@ -20,7 +20,7 @@ { if (CONFIG(TPM2)) /* Interface version: 2.0 */ - acpigen_write_return_string("2.0"); + acpigen_write_return_string("1.3"); else /* Interface version: 1.2 */ acpigen_write_return_string("1.2"); -- To view, visit https://review.coreboot.org/c/coreboot/+/45569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb12e2212d6d38c720c8fe989678724c871af6ef Gerrit-Change-Number: 45569 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: drivers/ipmi: Avoid NULL pointer dereference
by Harshit Sharma (Code Review) 20 Dec '20

20 Dec '20

Harshit Sharma has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41654 ) Change subject: drivers/ipmi: Avoid NULL pointer dereference ...................................................................... drivers/ipmi: Avoid NULL pointer dereference There are multiple instances where NULL pointer conf could be dereferenced. This patch fixes those issues. Found-by: Coverity Scan #1407751, #1428709, #1428710, #1428714 Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com> Change-Id: I2d1cfe3f9b55288eeb55ab8785d857993e3989c0 --- M src/drivers/ipmi/ipmi_kcs_ops.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/41654/1 diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 0b90fb2..e43f3a5 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -84,6 +84,9 @@ if (dev->chip_info) conf = dev->chip_info; + if (!conf) + return; + /* Get IPMI version for ACPI and SMBIOS */ if (conf && conf->wait_for_bmc && conf->bmc_boot_timeout) { struct stopwatch sw; @@ -200,6 +203,9 @@ if (dev->chip_info) conf = dev->chip_info; + if (!conf) + return 0; + if (conf) { if (conf->have_gpe) gpe_interrupt = conf->gpe_interrupt; @@ -234,6 +240,9 @@ if (dev->chip_info) conf = dev->chip_info; + if (!conf) + return; + /* Use command to pass UID to ipmi_write_acpi_tables */ conf->uid = uid_cnt++; -- To view, visit https://review.coreboot.org/c/coreboot/+/41654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d1cfe3f9b55288eeb55ab8785d857993e3989c0 Gerrit-Change-Number: 41654 Gerrit-PatchSet: 1 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: soc/mediatek/mt8192: add pmif driver support for romstage
by Yidi Lin (Code Review) 18 Dec '20

18 Dec '20

Hello hsin-hsiung wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46396 to review the following change. Change subject: soc/mediatek/mt8192: add pmif driver support for romstage ...................................................................... soc/mediatek/mt8192: add pmif driver support for romstage Add pmif driver support for romstage. TEST=Boots correctly on asurada p0. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> Change-Id: I141bc30b034714657b743f3453b2782b4d8d4e43 --- M src/soc/mediatek/mt8192/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/46396/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 9542aa4..e7ff25d 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -32,6 +32,7 @@ romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c romstage-y += ../common/uart.c +romstage-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c ramstage-y += auxadc.c ramstage-y += flash_controller.c -- To view, visit https://review.coreboot.org/c/coreboot/+/46396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I141bc30b034714657b743f3453b2782b4d8d4e43 Gerrit-Change-Number: 46396 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/mediatek/mt8192: add 6359p driver support for romstage
by Yidi Lin (Code Review) 18 Dec '20

18 Dec '20

Hello hsin-hsiung wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46397 to review the following change. Change subject: soc/mediatek/mt8192: add 6359p driver support for romstage ...................................................................... soc/mediatek/mt8192: add 6359p driver support for romstage Add 6359p driver support for romstage. TEST=Boots correctly on asurada p0. Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> Change-Id: I46bca69836d41e7c35b196d91d9fbdbdb7d71df7 --- M src/mainboard/google/asurada/romstage.c M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/mt6359p.h M src/soc/mediatek/mt8192/mt6359p.c 4 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/46397/1 diff --git a/src/mainboard/google/asurada/romstage.c b/src/mainboard/google/asurada/romstage.c index 3d03bd4..bd5cd74 100644 --- a/src/mainboard/google/asurada/romstage.c +++ b/src/mainboard/google/asurada/romstage.c @@ -6,6 +6,7 @@ #include <soc/dramc_param.h> #include <soc/emi.h> #include <soc/mmu_operations.h> +#include <soc/mt6359p.h> /* This must be defined in chromeos.fmd in same name and size. */ #define CALIBRATION_REGION "RW_DDR_TRAINING" @@ -43,6 +44,7 @@ void platform_romstage_main(void) { + mt6359p_romstage_init(); mt_mem_init(&dparam_ops); mtk_mmu_after_dram(); } diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index e7ff25d..657aa8e 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -33,6 +33,7 @@ romstage-y += ../common/timer.c romstage-y += ../common/uart.c romstage-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c +romstage-y += mt6359p.c ramstage-y += auxadc.c ramstage-y += flash_controller.c diff --git a/src/soc/mediatek/mt8192/include/soc/mt6359p.h b/src/soc/mediatek/mt8192/include/soc/mt6359p.h index ce7ef24..c0f01a0 100644 --- a/src/soc/mediatek/mt8192/include/soc/mt6359p.h +++ b/src/soc/mediatek/mt8192/include/soc/mt6359p.h @@ -41,6 +41,7 @@ #define VM18_VOL_REG_SHIFT 8 void mt6359p_init(void); +void mt6359p_romstage_init(void); void mt6359p_buck_set_voltage(u32 buck_id, u32 buck_uv); u32 mt6359p_buck_get_voltage(u32 buck_id); void mt6359p_set_vm18_voltage(u32 vm18_uv); diff --git a/src/soc/mediatek/mt8192/mt6359p.c b/src/soc/mediatek/mt8192/mt6359p.c index c70485d..2eb3f60 100644 --- a/src/soc/mediatek/mt8192/mt6359p.c +++ b/src/soc/mediatek/mt8192/mt6359p.c @@ -457,3 +457,12 @@ pmic_lp_setting(); pmic_wk_vs2_voter_setting(); } + +void mt6359p_romstage_init(void) +{ + if (pmif_arb == NULL) { + pmif_arb = get_pmif_controller(PMIF_SPI, 0); + if (pmif_arb == NULL) + die("ERROR - Failed to get pmif controller\n"); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46bca69836d41e7c35b196d91d9fbdbdb7d71df7 Gerrit-Change-Number: 46397 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: soc/mediatek/mt8192: Set BL31 platform mt8192
by Yidi Lin (Code Review) 17 Dec '20

17 Dec '20

Hello CK HU, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46383 to review the following change. Change subject: soc/mediatek/mt8192: Set BL31 platform mt8192 ...................................................................... soc/mediatek/mt8192: Set BL31 platform mt8192 Change-Id: I80d4a339b4a75647f55a699af447dcd362aab7b5 Signed-off-by: CK Hu <ck.hu(a)mediatek.com> --- M src/soc/mediatek/mt8192/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/46383/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 20acd24..8bc7b74 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -49,6 +49,8 @@ cbfs-files-y += $(DRAM_CBFS) endif +BL31_MAKEARGS += PLAT=mt8192 + CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include -- To view, visit https://review.coreboot.org/c/coreboot/+/46383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80d4a339b4a75647f55a699af447dcd362aab7b5 Gerrit-Change-Number: 46383 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: autoport: Add a license header to non-empty asl files
by Iru Cai (vimacs) (Code Review) 17 Dec '20

17 Dec '20

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45464 to review the following change. Change subject: autoport: Add a license header to non-empty asl files ...................................................................... autoport: Add a license header to non-empty asl files Change-Id: I8078d8babf24feabb22856ee820ab45b7d466f62 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/autoport/ec_fixme.go M util/autoport/ec_lenovo.go M util/autoport/ec_none.go M util/autoport/main.go 4 files changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/45464/1 diff --git a/util/autoport/ec_fixme.go b/util/autoport/ec_fixme.go index f5d039c..54f78ab 100644 --- a/util/autoport/ec_fixme.go +++ b/util/autoport/ec_fixme.go @@ -19,6 +19,7 @@ SouthBridge.EnableGPE(SouthBridge.DecodeGPE(sbGPE)) } + Add_gpl(ap) ap.WriteString( `Method(_WAK, 1) { @@ -64,6 +65,7 @@ defer si.Close() if hasKeyboard { + Add_gpl(si) si.WriteString("#include <drivers/pc80/pc/ps2_controller.asl>\n") MainboardInit += fmt.Sprintf("\tpc_keyboard_init(NO_AUX_DEVICE);\n") MainboardIncludes = append(MainboardIncludes, "pc80/keyboard.h") @@ -72,6 +74,7 @@ ec := Create(ctx, "acpi/ec.asl") defer ec.Close() + Add_gpl(ec) ec.WriteString(`Device(EC) { Name (_HID, EISAID("PNP0C09")) diff --git a/util/autoport/ec_lenovo.go b/util/autoport/ec_lenovo.go index 6851d6d..763ac26 100644 --- a/util/autoport/ec_lenovo.go +++ b/util/autoport/ec_lenovo.go @@ -39,6 +39,7 @@ Value: "1", }, GPEDefine) + Add_gpl(ap) ap.WriteString( `Method(_WAK, 1) { @@ -57,6 +58,7 @@ si := Create(ctx, "acpi/superio.asl") defer si.Close() + Add_gpl(si) si.WriteString("#include <drivers/pc80/pc/ps2_controller.asl>\n") /* FIXME:XX Move this to ec/lenovo. */ @@ -163,6 +165,7 @@ ec := Create(ctx, "acpi/ec.asl") defer ec.Close() + Add_gpl(ec) ec.WriteString("#include <ec/lenovo/h8/acpi/ec.asl>\n") KconfigBool["EC_LENOVO_PMH7"] = true diff --git a/util/autoport/ec_none.go b/util/autoport/ec_none.go index eb2b87c..bcb61bf 100644 --- a/util/autoport/ec_none.go +++ b/util/autoport/ec_none.go @@ -4,6 +4,7 @@ ap := Create(ctx, "acpi/platform.asl") defer ap.Close() + Add_gpl(ap) ap.WriteString( `Method(_WAK, 1) { diff --git a/util/autoport/main.go b/util/autoport/main.go index 1a9050a..e8436bd 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -825,9 +825,9 @@ dsdt.WriteString("#define " + define.Key + " " + define.Value + "\n") } + Add_gpl(dsdt) dsdt.WriteString( ` - #include <acpi/acpi.h> DefinitionBlock( -- To view, visit https://review.coreboot.org/c/coreboot/+/45464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8078d8babf24feabb22856ee820ab45b7d466f62 Gerrit-Change-Number: 45464 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: [WIP]drivers: Replace set_vbe_mode_info_valid
by Patrick Rudolph (Code Review) 17 Dec '20

17 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39004 ) Change subject: [WIP]drivers: Replace set_vbe_mode_info_valid ...................................................................... [WIP]drivers: Replace set_vbe_mode_info_valid Replace set_vbe_mode_info_valid with fb_fill_framebuffer_info, as it doesn't need a complete edid struct s paramter. The platforms doesn't read an EDID anyway. Change-Id: I95d1d62385a201c68c6c2527c023ad2292a235c5 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/aspeed/common/ast_mode_corebootfb.c M src/drivers/emulation/qemu/bochs.c M src/drivers/emulation/qemu/cirrus.c M src/mainboard/emulation/qemu-armv7/mainboard.c M src/soc/nvidia/tegra210/dc.c 5 files changed, 33 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/39004/1 diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index 2ec85ac..fed7754 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -30,6 +30,7 @@ */ #include <edid.h> +#include <framebuffer_info.h> #include "ast_drv.h" @@ -247,7 +248,12 @@ ast_hide_cursor(&crtc); /* Advertise new mode */ - set_vbe_mode_info_valid(&edid, fb.mmio_addr); + struct edid_fb_info *info = fb_new_framebuffer_info(); + if (info) { + fb_fill_framebuffer_info(info, fb.mmio_addr, edid.x_resolution, + edid.y_resolution, edid.bytes_per_line, + edid.framebuffer_bits_per_pixel); + } /* Clear display */ memset((void *)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution); diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index d9e4ce1..959d431 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -12,7 +12,6 @@ */ #include <stdint.h> -#include <edid.h> #include <arch/io.h> #include <console/console.h> #include <device/device.h> @@ -20,6 +19,7 @@ #include <device/pci_ops.h> #include <pc80/vga.h> #include <pc80/vga_io.h> +#include <framebuffer_info.h> /* VGA init. We use the Bochs VESA VBE extensions */ #define VBE_DISPI_IOPORT_INDEX 0x01CE @@ -65,7 +65,6 @@ static void bochs_init_linear_fb(struct device *dev) { - struct edid edid; int id, mem, bar; u32 addr; @@ -112,13 +111,11 @@ outb(0x20, 0x3c0); /* disable blanking */ - /* setup coreboot framebuffer */ - edid.mode.ha = width; - edid.mode.va = height; - edid.panel_bits_per_color = 8; - edid.panel_bits_per_pixel = 24; - edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); - set_vbe_mode_info_valid(&edid, addr); + /* Advertise new mode */ + struct edid_fb_info *info = fb_new_framebuffer_info(); + if (info) { + fb_fill_framebuffer_info(info, addr, width, height, 4 * width, 24); + } } static void bochs_init_text_mode(struct device *dev) diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index 6b1968c..8f048f9 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -13,13 +13,13 @@ */ #include <stdint.h> -#include <edid.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> #include <pc80/vga.h> #include <pc80/vga_io.h> +#include <framebuffer_info.h> static int width = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES; static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES; @@ -311,14 +311,10 @@ vga_sr_write (CIRRUS_SR_EXTENDED_MODE, sr_ext); write_hidden_dac (hidden_dac); - - struct edid edid; - edid.mode.ha = width; - edid.mode.va = height; - edid.panel_bits_per_color = 8; - edid.panel_bits_per_pixel = 24; - edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); - set_vbe_mode_info_valid(&edid, addr); + struct edid_fb_info *info = fb_new_framebuffer_info(); + if (info) { + fb_fill_framebuffer_info(info, addr, width, height, 4 * width, 24); + } } static void cirrus_init_text_mode(struct device *dev) diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c index 338cff9..22340b2 100644 --- a/src/mainboard/emulation/qemu-armv7/mainboard.c +++ b/src/mainboard/emulation/qemu-armv7/mainboard.c @@ -18,15 +18,14 @@ #include <device/device.h> #include <cbmem.h> #include <halt.h> -#include <edid.h> #include <device/mmio.h> #include <ramdetect.h> #include <symbols.h> +#include <framebuffer_info.h> static void init_gfx(void) { uint32_t *pl111; - struct edid edid; /* width is at most 4096 */ /* height is at most 1024 */ int width = 800, height = 600; @@ -42,12 +41,10 @@ write32(pl111 + 10, 0xff); write32(pl111 + 6, (5 << 1) | 0x801); - edid.framebuffer_bits_per_pixel = 32; - edid.bytes_per_line = width * 4; - edid.x_resolution = width; - edid.y_resolution = height; - - set_vbe_mode_info_valid(&edid, framebuffer); + struct edid_fb_info *info = fb_new_framebuffer_info(); + if (info) { + fb_fill_framebuffer_info(info, framebuffer, width, height, 4 * width, 32); + } } static void mainboard_enable(struct device *dev) diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c index 46443cf..b4e3378 100644 --- a/src/soc/nvidia/tegra210/dc.c +++ b/src/soc/nvidia/tegra210/dc.c @@ -16,10 +16,10 @@ #include <console/console.h> #include <device/mmio.h> #include <stdint.h> -#include <edid.h> #include <device/device.h> #include <soc/nvidia/tegra/dc.h> #include <soc/display.h> +#include <framebuffer_info.h> #include "chip.h" @@ -226,19 +226,13 @@ void pass_mode_info_to_payload( struct soc_nvidia_tegra210_config *config) { - struct edid edid; - - edid.mode.va = config->display_yres; - edid.mode.ha = config->display_xres; - edid_set_framebuffer_bits_per_pixel(&edid, - config->framebuffer_bits_per_pixel, 64); - - printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n " - " x_res x y_res: %d x %d, size: %d\n", - __func__, edid.bytes_per_line, - edid.framebuffer_bits_per_pixel, - edid.x_resolution, edid.y_resolution, - (edid.bytes_per_line * edid.y_resolution)); - - set_vbe_mode_info_valid(&edid, 0); + struct edid_fb_info *info = fb_new_framebuffer_info(); + if (info) { + uint32_t bytes_per_line = ALIGN_UP(config->display_xres * + DIV_ROUND_UP(config->framebuffer_bits_per_pixel, 8), 64); + //FIXME: Why not config->framebuffer_base? + fb_fill_framebuffer_info(info, 0, + config->display_xres, config->display_yres, + bytes_per_line, config->framebuffer_bits_per_pixel); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/39004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95d1d62385a201c68c6c2527c023ad2292a235c5 Gerrit-Change-Number: 39004 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: Do the dramc pinmux selection
by CK HU (Code Review) 16 Dec '20

16 Dec '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44701 to review the following change. Change subject: soc/mediatek/mt8192: Do the dramc pinmux selection ...................................................................... soc/mediatek/mt8192: Do the dramc pinmux selection Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I7bc1971646a65db8eef5eb5223c919645c6e8ed9 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c 1 file changed, 100 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/44701/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 9b1216c..08f3ea4 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -6,8 +6,108 @@ #include <string.h> #include <timer.h> +const u8 mrr_o1_pinmux_mapping[PINMUX_MAX][CHANNEL_MAX][DQ_DATA_WIDTH] = { + [PINMUX_DSC] = { + [CHANNEL_A] = {0, 1, 7, 6, 4, 5, 2, 3, 9, 8, 11, 10, 14, 15, 13, 12}, + [CHANNEL_B] = {1, 0, 5, 6, 3, 2, 7, 4, 8, 9, 11, 10, 12, 14, 13, 15}, + }, + [PINMUX_LPBK] = { + }, + [PINMUX_EMCP] = { + [CHANNEL_A] = {1, 0, 3, 2, 4, 7, 6, 5,8, 9, 10, 14, 11, 15, 13, 12}, + [CHANNEL_B] = {0, 1, 4, 7, 3, 5, 6, 2,9, 8, 10, 12, 11, 14, 13, 15} + }, +}; + +static void set_rank_info_to_conf(const struct ddr_cali *cali) +{ + u8 value = ((cali->emi_config->cona_val >> 17) & 0x1) ? 0 : 1; + + SET32_BITFIELDS(&ch[0].ao.sa_reserve, + SA_RESERVE_MODE_RK0, cali->cbt_mode[RANK_0], + SA_RESERVE_MODE_RK1, cali->cbt_mode[RANK_1], + SA_RESERVE_SINGLE_RANK, value); +} + +static void get_dram_pinmux_sel(struct ddr_cali *cali) +{ + u32 value = (read32(&mtk_gpio->dram_pinmux_trapping) >> 19) & 0x1; + + if (value) + cali->pinmux_type = PINMUX_DSC; + else + cali->pinmux_type = PINMUX_EMCP; +} + +static void set_MRR_pinmux_mapping(const struct ddr_cali *cali) +{ + const u8 *map; + u32 bc_bak = dramc_get_broadcast(); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + map = mrr_o1_pinmux_mapping[get_pinmux_type(cali)][chn]; + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux1, + MRR_BIT_MUX1_MRR_BIT0_SEL, map[0], + MRR_BIT_MUX1_MRR_BIT1_SEL, map[1], + MRR_BIT_MUX1_MRR_BIT2_SEL, map[2], + MRR_BIT_MUX1_MRR_BIT3_SEL, map[3]); + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux2, + MRR_BIT_MUX2_MRR_BIT4_SEL, map[4], + MRR_BIT_MUX2_MRR_BIT5_SEL, map[5], + MRR_BIT_MUX2_MRR_BIT6_SEL, map[6], + MRR_BIT_MUX2_MRR_BIT7_SEL, map[7]); + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux3, + MRR_BIT_MUX3_MRR_BIT8_SEL, map[8], + MRR_BIT_MUX3_MRR_BIT9_SEL, map[9], + MRR_BIT_MUX3_MRR_BIT10_SEL, map[10], + MRR_BIT_MUX3_MRR_BIT11_SEL, map[11]); + SET32_BITFIELDS(&ch[chn].ao.mrr_bit_mux4, + MRR_BIT_MUX4_MRR_BIT12_SEL, map[12], + MRR_BIT_MUX4_MRR_BIT13_SEL, map[13], + MRR_BIT_MUX4_MRR_BIT14_SEL, map[14], + MRR_BIT_MUX4_MRR_BIT15_SEL, map[15]); + } + dramc_set_broadcast(bc_bak); +} + +static void set_dqO1_pinmux_mapping(const struct ddr_cali *cali) +{ + const u8 *map; + u32 bc_bak = dramc_get_broadcast(); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + map = mrr_o1_pinmux_mapping[get_pinmux_type(cali)][chn]; + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dq_se_pinmux_ctrl0, + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ0, map[0], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ1, map[1], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ2, map[2], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ3, map[3], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ4, map[4], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ5, map[5], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ6, map[6], + MISC_DQ_SE_PINMUX_CTRL0_DQ_PINMUX_SEL_DQ7, map[7]); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dq_se_pinmux_ctrl1, + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ8, map[8], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ9, map[9], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ10, map[10], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ11, map[11], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ12, map[12], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ13, map[13], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ14, map[14], + MISC_DQ_SE_PINMUX_CTRL1_DQ_PINMUX_SEL_DQ15, map[15]); + } + + dramc_set_broadcast(bc_bak); +} + void global_option_init(struct ddr_cali *cali) { + set_rank_info_to_conf(cali); + get_dram_pinmux_sel(cali); + set_MRR_pinmux_mapping(cali); + set_dqO1_pinmux_mapping(cali); } void dfs_init_for_calibration(const struct ddr_cali *cali) -- To view, visit https://review.coreboot.org/c/coreboot/+/44701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bc1971646a65db8eef5eb5223c919645c6e8ed9 Gerrit-Change-Number: 44701 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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