coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

1 participants
3474 discussions

Change in coreboot[master]: soc/amd/common: Refactor ACPIMMIO posted writes
by Kyösti Mälkki (Code Review) 12 Dec '20

12 Dec '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42825 ) Change subject: soc/amd/common: Refactor ACPIMMIO posted writes ...................................................................... soc/amd/common: Refactor ACPIMMIO posted writes Change-Id: Ic1a5c17c789dd79fea8f348d1a9d32d4301ced88 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/picasso/i2c.c M src/soc/amd/stoneyridge/i2c.c 3 files changed, 8 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/42825/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 2775b52..8546da9 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -369,12 +369,6 @@ write32(gpio_ctrl_ptr(gpio_num), value); } -static inline void gpio_write32_rb(uint8_t gpio_num, uint32_t value) -{ - write32(gpio_ctrl_ptr(gpio_num), value); - read32(gpio_ctrl_ptr(gpio_num)); -} - /* GPIO bank 0 */ static inline uint8_t gpio0_read8(uint8_t reg) { diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 881278f..61a4f8a 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -161,9 +161,11 @@ static void restore_i2c_pin_registers(uint8_t gpio, struct soc_amd_i2c_save *save_table) { + /* Write and flush posted writes. */ iomux_write8(gpio, save_table->mux_value); - iomux_read8(gpio); - gpio_write32_rb(gpio, save_table->control_value); + iomux_read8(0); + gpio_write32(gpio, save_table->control_value); + gpio_read32(0); } /* Slaves to be reset are controlled by devicetree register i2c_scl_reset */ diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index 0327028..cd42cda 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -144,9 +144,11 @@ static void restore_i2c_pin_registers(uint8_t gpio, struct soc_amd_i2c_save *save_table) { + /* Write and flush posted writes. */ iomux_write8(gpio, save_table->mux_value); - iomux_read8(gpio); - gpio_write32_rb(gpio, save_table->control_value); + iomux_read8(0); + gpio_write32(gpio, save_table->control_value); + gpio_read32(0); } /* Slaves to be reset are controlled by devicetree register i2c_scl_reset */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1a5c17c789dd79fea8f348d1a9d32d4301ced88 Gerrit-Change-Number: 42825 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: [TESTONLY] Revert "src/amd/common: Exclude biosram from psp_verstage"
by Kyösti Mälkki (Code Review) 12 Dec '20

12 Dec '20

Hello build bot (Jenkins), Raul Rangel, Martin Roth, Patrick Georgi, Julius Werner, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43067 to review the following change. Change subject: [TESTONLY] Revert "src/amd/common: Exclude biosram from psp_verstage" ...................................................................... [TESTONLY] Revert "src/amd/common: Exclude biosram from psp_verstage" This reverts commit f38af663d2c2c854859715803da249e6c24032db. I just want to see where the build fails. Change-Id: I0a995301404b67224be6addbeebf984c4b5c47d5 --- M src/soc/amd/common/block/acpimmio/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/43067/1 diff --git a/src/soc/amd/common/block/acpimmio/Makefile.inc b/src/soc/amd/common/block/acpimmio/Makefile.inc index 553d9e2..69253b9 100644 --- a/src/soc/amd/common/block/acpimmio/Makefile.inc +++ b/src/soc/amd/common/block/acpimmio/Makefile.inc @@ -6,7 +6,7 @@ smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c -verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c +verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c -- To view, visit https://review.coreboot.org/c/coreboot/+/43067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a995301404b67224be6addbeebf984c4b5c47d5 Gerrit-Change-Number: 43067 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()
by Julius Werner (Code Review) 12 Dec '20

12 Dec '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39306 to review the following change. Change subject: cbfs: Introduce cbfs_ro_map() and cbfs_ro_load() ...................................................................... cbfs: Introduce cbfs_ro_map() and cbfs_ro_load() This patch introduces two new CBFS API functions which are equivalent to cbfs_map() and cbfs_load(), respectively, with the difference that they always operate on the read-only CBFS region ("COREBOOT" FMAP section). Use it to replace some of the simple cases that needed to use cbfs_locate_file_in_region(). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I9c55b022b6502a333a9805ab0e4891dd7b97ef7f --- M src/drivers/pc80/rtc/option.c M src/include/cbfs.h M src/lib/cbfs.c M src/northbridge/intel/haswell/raminit.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/quark/romstage/romstage.c 6 files changed, 60 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/39306/1 diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index 4789b15..1f9abb5 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -60,36 +60,28 @@ return CB_SUCCESS; } -static enum cb_err locate_cmos_layout(struct region_device *rdev) +static struct cmos_option_table *get_cmos_layout(struct region_device *rdev) { - uint32_t cbfs_type = CBFS_COMPONENT_CMOS_LAYOUT; - MAYBE_STATIC_BSS struct cbfsf fh = {}; + MAYBE_STATIC_BSS struct cmos_option_table ct = NULL; /* * In case VBOOT is enabled and this function is called from SMM, * we have multiple CMOS layout files and to locate them we'd need to * include VBOOT into SMM... * - * Support only one CMOS layout in the 'COREBOOT' region for now. + * Support only one CMOS layout in the RO CBFS for now. */ - if (!region_device_sz(&(fh.data))) { - if (cbfs_locate_file_in_region(&fh, "COREBOOT", "cmos_layout.bin", - &cbfs_type)) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " - "Options are disabled\n"); - return CB_CMOS_LAYOUT_NOT_FOUND; - } - } - - cbfs_file_data(rdev, &fh); - - return CB_SUCCESS; + if (!ct) + ct = cbfs_ro_map("cmos_layout.bin", NULL); + if (!ct) + printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " + "Options are disabled\n"); + return ct; } enum cb_err cmos_get_option(void *dest, const char *name) { struct cmos_option_table *ct; - struct region_device rdev; struct cmos_entries *ce; size_t namelen; int found = 0; @@ -97,16 +89,9 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { + ct = get_cmos_layout(); + if (!ct) return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - return CB_CMOS_LAYOUT_NOT_FOUND; - } /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -119,19 +104,15 @@ } if (!found) { printk(BIOS_DEBUG, "No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); return CB_CMOS_OPTION_NOT_FOUND; } - if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { - rdev_munmap(&rdev, ct); + if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) return CB_CMOS_CHECKSUM_INVALID; - } - if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); +} + if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } - rdev_munmap(&rdev, ct); +} return CB_SUCCESS; } @@ -179,7 +160,6 @@ enum cb_err cmos_set_option(const char *name, void *value) { struct cmos_option_table *ct; - struct region_device rdev; struct cmos_entries *ce; unsigned long length; size_t namelen; @@ -188,16 +168,9 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { + ct = get_cmos_layout(); + if (!ct) return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - return CB_CMOS_LAYOUT_NOT_FOUND; - } /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -210,7 +183,6 @@ } if (!found) { printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); return CB_CMOS_OPTION_NOT_FOUND; } @@ -219,18 +191,13 @@ length = MAX(strlen((const char *)value) * 8, ce->length - 8); /* make sure the string is null terminated */ if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}) - != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } } - if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) return CB_CMOS_ACCESS_ERROR; - } - rdev_munmap(&rdev, ct); return CB_SUCCESS; } diff --git a/src/include/cbfs.h b/src/include/cbfs.h index cc61b16..8cd5713 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -36,9 +36,12 @@ NOTE: Since this may return a direct pointer to memory-mapped hardware, compressed files are NOT transparently decompressed (unlike cbfs_load()). */ void *cbfs_map(const char *name, size_t *size); -/* Removes a mapping previously allocated with cbfs_map(). Should try to unmap - mappings in strict LIFO order where possible, since mapping backends often - don't support more complicated cases. */ +/* Like cbfs_map(), except that it will always read from the read-only CBFS + ("COREBOOT" FMAP region), even when CONFIG_VBOOT is enabled. */ +void *cbfs_ro_map(const char *name, size_t *size); +/* Removes a previously allocated CBFS mapping. Should try to unmap mappings in + strict LIFO order where possible, since mapping backends often don't support + more complicated cases. */ int cbfs_unmap(void *mapping); /* Locate file in a specific region of fmap. Return 0 on success. < 0 on error*/ int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name, @@ -47,6 +50,9 @@ success or 0 on error. File will get decompressed as necessary. Same decompression requirements as cbfs_load_and_decompress(). */ size_t cbfs_load(const char *name, void *buf, size_t buf_size); +/* Like cbfs_load(), except that it will always read from the read-only CBFS + ("COREBOOT" FMAP region), even when CONFIG_VBOOT is enabled. */ +size_t cbfs_ro_load(const char *name, void *buf, size_t buf_size); /* Load |in_size| bytes from |rdev| at |offset| to the |buffer_size| bytes * large |buffer|, decompressing it according to |compression| in the process. * Returns the decompressed file size, or 0 on error. diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index c3660aa..ba50c34 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -79,9 +79,9 @@ return 0; } -void *cbfs_map(const char *name, size_t *size) +static void *_cbfs_map(const char *name, size_t *size, bool force_ro) { - const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(force_ro); union cbfs_mdata mdata; size_t data_offset; @@ -96,6 +96,16 @@ return rdev_mmap(&cbd->rdev, data_offset, data_size); } +void *cbfs_map(const char *name, size_t *size) +{ + return _cbfs_map(name, size, false); +} + +void *cbfs_ro_map(const char *name, size_t *size) +{ + return _cbfs_map(name, size, true); +} + int cbfs_unmap(void *mapping) { /* This works because munmap() only works on the root rdev and never @@ -215,7 +225,8 @@ return prog_entry(&stage); } -size_t cbfs_load(const char *name, void *buf, size_t buf_size) +static size_t _cbfs_load(const char *name, void *buf, size_t buf_size, + bool force_ro) { const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); union cbfs_mdata mdata; @@ -238,6 +249,16 @@ compression); } +size_t cbfs_load(const char *name, void *buf, size_t buf_size) +{ + return _cbfs_load(name, buf, buf_size, false); +} + +size_t cbfs_ro_load(const char *name, void *buf, size_t buf_size) +{ + return _cbfs_load(name, buf, buf_size, true); +} + size_t cbfs_prog_stage_section(struct prog *pstage, uintptr_t *base) { struct cbfs_stage stage; diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 8267833..00211bd 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -118,8 +118,6 @@ void sdram_initialize(struct pei_data *pei_data) { unsigned long entry; - uint32_t type = CBFS_TYPE_MRC; - struct cbfsf f; printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); @@ -144,12 +142,11 @@ /* * Locate and call UEFI System Agent binary. The binary needs to be at * a fixed offset in the flash and can therefore only reside in the - * COREBOOT fmap region + * COREBOOT fmap region. We don't care about leaking the mapping. */ - if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) + entry = (unsigned long)cbfs_ro_map("mrc.bin", NULL); + if (!entry) die("mrc.bin not found!"); - /* We don't care about leaking the mapping */ - entry = (unsigned long)rdev_mmap_full(&f.data); if (entry) { int rv; asm volatile ( diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 3759c1f..bcf7148 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -43,8 +43,6 @@ struct memory_info *mem_info; pei_wrapper_entry_t entry; int ret; - struct cbfsf f; - uint32_t type = CBFS_TYPE_MRC; broadwell_fill_pei_data(pei_data); @@ -76,15 +74,10 @@ pei_data->saved_data_size = 0; } - /* Determine if mrc.bin is in the cbfs. */ - if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) - die("mrc.bin not found!"); /* We don't care about leaking the mapping */ - entry = (pei_wrapper_entry_t)rdev_mmap_full(&f.data); - if (entry == NULL) { - printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); - return; - } + entry = cbfs_ro_map("mrc.bin", NULL); + if (entry == NULL) + die("mrc.bin not found!"); printk(BIOS_DEBUG, "Starting Memory Reference Code\n"); diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 4ac580e..3e08663 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -63,29 +63,16 @@ void *locate_rmu_file(size_t *rmu_file_len) { - struct cbfsf fh; size_t fsize; void *rmu_data; - uint32_t type; /* Locate the rmu.bin file in the read-only region of the flash */ - type = CBFS_TYPE_RAW; - if (cbfs_locate_file_in_region(&fh, "COREBOOT", "rmu.bin", &type)) + rmu_data = cbfs_ro_map("rmu.bin", &fsize); + if (!rmu_data) return NULL; - /* Get the file size */ - fsize = region_device_sz(&fh.data); if (rmu_file_len != NULL) *rmu_file_len = fsize; - /* Get the data address */ - rmu_data = rdev_mmap(&fh.data, 0, fsize); - - /* Since the SPI flash is directly mapped into memory, we do not need - * the mapping provided by the rdev service. Unmap the file to prevent - * a memory leak. Return/leak the SPI flash address for the rmu.bin - * file data which will be directly accessed by FSP MemoryInit. - */ - rdev_munmap(&fh.data, rmu_data); return rmu_data; } -- To view, visit https://review.coreboot.org/c/coreboot/+/39306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c55b022b6502a333a9805ab0e4891dd7b97ef7f Gerrit-Change-Number: 39306 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: sb/intel/bd82x6x: Only check device ID in `intel_me_finalize_smm`
by Angel Pons (Code Review) 11 Dec '20

11 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45258 ) Change subject: sb/intel/bd82x6x: Only check device ID in `intel_me_finalize_smm` ...................................................................... sb/intel/bd82x6x: Only check device ID in `intel_me_finalize_smm` There's no need to compare the vendor ID. Change-Id: I4368f2615e5ce72430992f1f5581908c90c970f0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/45258/1 diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index c51cca6..3876b02 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -168,16 +168,16 @@ void intel_me_finalize_smm(void) { - u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); + u16 did = pci_read_config16(PCH_ME_DEV, PCI_DEVICE_ID); switch (did) { - case 0x1c3a8086: + case 0x1c3a: intel_me7_finalize_smm(); break; - case 0x1e3a8086: + case 0x1e3a: intel_me8_finalize_smm(); break; default: - printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); + printk(BIOS_ERR, "No finalize handler for ME %04x.\n", did); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/45258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4368f2615e5ce72430992f1f5581908c90c970f0 Gerrit-Change-Number: 45258 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/volteer/var/voxel: change speaker smart amplifier to ALC1011
by Sheng-Liang Pan (Code Review) 11 Dec '20

11 Dec '20

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43549 ) Change subject: mb/google/volteer/var/voxel: change speaker smart amplifier to ALC1011 ...................................................................... mb/google/volteer/var/voxel: change speaker smart amplifier to ALC1011 voxel change amp to ALC1011 adding ALC1011 amp acpi info into devicetree BUG=b:160550394 BRANCH=None TEST=build and verify ALC1011 can be recognized. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: If3e7b829000a61a27f6a45a2688bb434e57f479a --- M src/mainboard/google/volteer/Kconfig.name M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/variants/voxel/overridetree.cb 3 files changed, 15 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/43549/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 06bbc58..a3ece12 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -37,6 +37,8 @@ bool "-> Voxel" select BOARD_GOOGLE_BASEBOARD_VOLTEER select SOC_INTEL_CSE_LITE_SKU + select CHROMEOS_DSM_CALIB + select DRIVERS_I2C_RT1011 config BOARD_GOOGLE_DELBIN bool "-> Delbin" diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c index 61e20f4..6cbde24 100644 --- a/src/mainboard/google/volteer/fw_config.c +++ b/src/mainboard/google/volteer/fw_config.c @@ -72,7 +72,8 @@ gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); } if (fw_config_probe(FW_CONFIG(AUDIO, MAX98357_ALC5682I_I2S)) || - fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S))) { + fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S)) || + fw_config_probe(FW_CONFIG(AUDIO, RT1011_ALC5682I_I2S))) { printk(BIOS_INFO, "Configure GPIOs for I2S audio.\n"); gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 2219de0..8838705 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -12,24 +12,23 @@ register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" device i2c 1a on + probe AUDIO RT1011_ALC5682I_I2S end end - chip drivers/i2c/max98373 - register "vmon_slot_no" = "0" - register "imon_slot_no" = "1" + chip drivers/i2c/rt1011 + register "desc" = ""RT1011 Woofer Left Speaker Amp"" register "uid" = "0" - register "desc" = ""Right Speaker Amp"" - register "name" = ""MAXR"" - device i2c 31 on + register "name" = ""RTWL"" + device i2c 38 on + probe AUDIO RT1011_ALC5682I_I2S end end - chip drivers/i2c/max98373 - register "vmon_slot_no" = "2" - register "imon_slot_no" = "3" + chip drivers/i2c/rt1011 + register "desc" = ""RT1011 Woofer Right Speaker Amp"" register "uid" = "1" - register "desc" = ""Left Speaker Amp"" - register "name" = ""MAXL"" - device i2c 32 on + register "name" = ""RTWR"" + device i2c 39 on + probe AUDIO RT1011_ALC5682I_I2S end end end # I2C #0 0xA0E8 -- To view, visit https://review.coreboot.org/c/coreboot/+/43549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3e7b829000a61a27f6a45a2688bb434e57f479a Gerrit-Change-Number: 43549 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: sb/intel/bd82x6x: Make me_common.c a compilation unit
by Angel Pons (Code Review) 10 Dec '20

10 Dec '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42019 ) Change subject: sb/intel/bd82x6x: Make me_common.c a compilation unit ...................................................................... sb/intel/bd82x6x: Make me_common.c a compilation unit We need to make most things non-static so that the code builds. Change-Id: I17e561abf2378632f72d0aa9f0057cb1bee23514 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/Makefile.inc M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_common.c 5 files changed, 47 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/42019/1 diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 9e34e96..cf9bf50 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -15,6 +15,7 @@ ramstage-y += usb_xhci.c ramstage-y += me.c ramstage-y += me_8.x.c +ramstage-y += me_common.c ramstage-y += smbus.c ramstage-y += ../common/pciehp.c @@ -24,7 +25,7 @@ ramstage-$(CONFIG_ELOG) += elog.c -smm-y += smihandler.c me.c me_8.x.c pch.c +smm-y += smihandler.c me.c me_8.x.c pch.c me_common.c romstage-y += early_smbus.c me_status.c romstage-y += early_rcba.c diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 515f984..d2a3480 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -28,9 +28,6 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif -/* FIXME: For verification purposes only */ -#include "me_common.c" - /* Get ME firmware version */ static int __unused mkhi_get_fw_version(void) { diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 5aaf661..a55a1f2 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -221,6 +221,34 @@ ME_FIRMWARE_UPDATE_BIOS_PATH, } me_bios_path; +/* Defined in me_common.c for both ramstage and smm */ +const char *const me_get_bios_path_string(int path); + +void mei_read_dword_ptr(void *ptr, int offset); +void mei_write_dword_ptr(void *ptr, int offset); + +#ifndef __SIMPLE_DEVICE__ +void pci_read_dword_ptr(struct device *dev, void *ptr, int offset); +#endif + +void read_host_csr(struct mei_csr *csr); +void write_host_csr(struct mei_csr *csr); + +void read_me_csr(struct mei_csr *csr); + +void write_cb(u32 dword); +u32 read_cb(void); + +int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, + void *req_data, void *rsp_data, int rsp_bytes); + +int mkhi_end_of_post(void); +void update_mei_base_address(void); +bool is_mei_base_address_valid(void); +int intel_mei_setup(struct device *dev); +int intel_me_extend_valid(struct device *dev); +void intel_me_hide(struct device *dev); + /* Defined in me_status.c for both romstage and ramstage */ void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index fcf4dd3..1a331e9 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -28,9 +28,6 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif -/* FIXME: For verification purposes only */ -#include "me_common.c" - static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index 790b870..83e7fe6 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -25,7 +25,7 @@ [ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update", }; -static inline const char *const me_get_bios_path_string(int path) +const char *const me_get_bios_path_string(int path) { return me_bios_path_values[path]; } @@ -70,14 +70,14 @@ * ME/MEI access helpers using memcpy to avoid aliasing. */ -static inline void mei_read_dword_ptr(void *ptr, int offset) +void mei_read_dword_ptr(void *ptr, int offset) { u32 dword = read32(mei_base_address + (offset / sizeof(u32))); memcpy(ptr, &dword, sizeof(dword)); mei_dump(ptr, dword, offset, "READ"); } -static inline void mei_write_dword_ptr(void *ptr, int offset) +void mei_write_dword_ptr(void *ptr, int offset) { u32 dword = 0; memcpy(&dword, ptr, sizeof(dword)); @@ -86,7 +86,7 @@ } #ifndef __SIMPLE_DEVICE__ -static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) +void pci_read_dword_ptr(struct device *dev, void *ptr, int offset) { u32 dword = pci_read_config32(dev, offset); memcpy(ptr, &dword, sizeof(dword)); @@ -94,28 +94,28 @@ } #endif -static inline void read_host_csr(struct mei_csr *csr) +void read_host_csr(struct mei_csr *csr) { mei_read_dword_ptr(csr, MEI_H_CSR); } -static inline void write_host_csr(struct mei_csr *csr) +void write_host_csr(struct mei_csr *csr) { mei_write_dword_ptr(csr, MEI_H_CSR); } -static inline void read_me_csr(struct mei_csr *csr) +void read_me_csr(struct mei_csr *csr) { mei_read_dword_ptr(csr, MEI_ME_CSR_HA); } -static inline void write_cb(u32 dword) +void write_cb(u32 dword) { write32(mei_base_address + (MEI_H_CB_WW / sizeof(u32)), dword); mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); } -static inline u32 read_cb(void) +u32 read_cb(void) { u32 dword = read32(mei_base_address + (MEI_ME_CB_RW / sizeof(u32))); mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); @@ -310,8 +310,8 @@ return mei_wait_for_me_ready(); } -static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, - void *req_data, void *rsp_data, int rsp_bytes) +int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, + void *req_data, void *rsp_data, int rsp_bytes) { if (mei_send_msg(mei, mkhi, req_data) < 0) return -1; @@ -321,7 +321,7 @@ } /* Send END OF POST message to the ME */ -static int __unused mkhi_end_of_post(void) +int mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -351,12 +351,12 @@ #ifdef __SIMPLE_DEVICE__ -static inline void update_mei_base_address(void) +void update_mei_base_address(void) { mei_base_address = (u32 *)(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); } -static inline bool is_mei_base_address_valid(void) +bool is_mei_base_address_valid(void) { return mei_base_address && mei_base_address != (u32 *)0xfffffff0; } @@ -364,7 +364,7 @@ #else /* Prepare ME for MEI messages */ -static int intel_mei_setup(struct device *dev) +int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; @@ -391,7 +391,7 @@ } /* Read the Extend register hash of ME firmware */ -static int intel_me_extend_valid(struct device *dev) +int intel_me_extend_valid(struct device *dev) { struct me_heres status; u32 extend[8] = {0}; @@ -438,7 +438,7 @@ } /* Hide the ME virtual PCI devices */ -static void intel_me_hide(struct device *dev) +void intel_me_hide(struct device *dev) { dev->enabled = 0; pch_enable(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/42019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17e561abf2378632f72d0aa9f0057cb1bee23514 Gerrit-Change-Number: 42019 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: [TEST] mb/google/dedede: change temp thresholds
by Sumeet R Pawnikar (Code Review) 10 Dec '20

10 Dec '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44132 ) Change subject: [TEST] mb/google/dedede: change temp thresholds ...................................................................... [TEST] mb/google/dedede: change temp thresholds Change temp thersholds to avoid system shutdown during stress test. Change-Id: I11a2c7542577a08fbb67224c6024cc26a0cf48de Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/44132/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index d0609ef..d115ef7 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -171,13 +171,13 @@ device pci 02.0 on end # Integrated Graphics Device device pci 04.0 on chip drivers/intel/dptf - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 90, 10000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000)" - register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000)" + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 80, 10000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 60000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 45, 15000)" - register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN)" - register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN)" + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 115, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 100, SHUTDOWN)" + register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 110, SHUTDOWN)" register "controls.power_limits.pl1" = "{ .min_power = 3000, -- To view, visit https://review.coreboot.org/c/coreboot/+/44132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11a2c7542577a08fbb67224c6024cc26a0cf48de Gerrit-Change-Number: 44132 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: [TEST]: drawcia: set PL1 to higher value
by Sumeet R Pawnikar (Code Review) 10 Dec '20

10 Dec '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44803 ) Change subject: [TEST]: drawcia: set PL1 to higher value ...................................................................... [TEST]: drawcia: set PL1 to higher value Set PL1 to higher value Change-Id: Ibc0b2d2cedc68ab367bf0947034e048fbbfc0841 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/44803/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index ee95332..15e09db 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -40,7 +40,7 @@ }" register "power_limits_config" = "{ - .tdp_pl1_override = 6, + .tdp_pl1_override = 8, .tdp_pl2_override = 15, }" @@ -69,12 +69,12 @@ register "controls.power_limits.pl1" = "{ .min_power = 4800, - .max_power = 6000, + .max_power = 8000, .time_window_min = 1 * MSECS_PER_SEC, .time_window_max = 1 * MSECS_PER_SEC, .granularity = 200,}" register "controls.power_limits.pl2" = "{ - .min_power = 6000, + .min_power = 8000, .max_power = 15000, .time_window_min = 1 * MSECS_PER_SEC, .time_window_max = 1 * MSECS_PER_SEC, -- To view, visit https://review.coreboot.org/c/coreboot/+/44803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc0b2d2cedc68ab367bf0947034e048fbbfc0841 Gerrit-Change-Number: 44803 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/mediatek/mt8192: Add dpm loader
by Yidi Lin (Code Review) 10 Dec '20

10 Dec '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46393 to review the following change. Change subject: soc/mediatek/mt8192: Add dpm loader ...................................................................... soc/mediatek/mt8192: Add dpm loader BUG=none TEST=Boots correctly on Asurada Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I16b341ad63940b45b886c4a7fd733c1970624e40 --- M src/mainboard/google/asurada/mainboard.c M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dpm.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/dpm.h 5 files changed, 136 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/46393/1 diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index 7b3ef22..677e917 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -5,6 +5,7 @@ #include <device/device.h> #include <device/mmio.h> #include <lib.h> +#include <soc/dpm.h> #include <soc/gpio_common.h> #include <soc/spm.h> #include <soc/usb.h> @@ -79,6 +80,9 @@ register_reset_to_bl31(); + if (dpm_init()) + printk(BIOS_ERR, "dpm init fail, system can't do DVFS switch\n"); + if (spm_init()) printk(BIOS_ERR, "spm init fail, system suspend may stuck\n"); } diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 59d105c..5fc90a8 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -37,6 +37,7 @@ ramstage-y += ../common/gpio.c gpio.c ramstage-y += emi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += dpm.c ramstage-y += spm.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c @@ -48,6 +49,16 @@ MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192 +cbfs-files-y += dpm.dm +dpm.dm-file := $(MT8192_BLOB_DIR)/dpm.dm +dpm.dm-type := raw +dpm.dm-compression := $(CBFS_COMPRESS_FLAG) + +cbfs-files-y += dpm.pm +dpm.pm-file := $(MT8192_BLOB_DIR)/dpm.pm +dpm.pm-type := raw +dpm.pm-compression := $(CBFS_COMPRESS_FLAG) + cbfs-files-y += spm_firmware.bin spm_firmware.bin-file := $(MT8192_BLOB_DIR)/spm_firmware.bin spm_firmware.bin-type := raw diff --git a/src/soc/mediatek/mt8192/dpm.c b/src/soc/mediatek/mt8192/dpm.c new file mode 100644 index 0000000..7e018b5 --- /dev/null +++ b/src/soc/mediatek/mt8192/dpm.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <cbfs.h> +#include <console/console.h> +#include <delay.h> +#include <device/mmio.h> +#include <soc/dpm.h> +#include <timer.h> + +#define DM_BUF_SIZE (2 * KiB) +#define PM_BUF_SIZE (20 * KiB) + +static u8 dpm_dm_bin[DM_BUF_SIZE] __aligned(8); +static u8 dpm_pm_bin[PM_BUF_SIZE] __aligned(8); +static void *dpm_pm_reg = (void *)DPM_PM_SRAM_BASE; +static void *dpm_dm_reg = (void *)DPM_DM_SRAM_BASE; + +static int dpm_load_firmware(void) +{ + const char *dm_file_name = "dpm.dm"; + const char *pm_file_name = "dpm.pm"; + size_t dm_file_size, pm_file_size; + + dm_file_size = cbfs_boot_load_file(dm_file_name, dpm_dm_bin, + sizeof(dpm_dm_bin), CBFS_TYPE_RAW); + if (dm_file_size == 0) { + printk(BIOS_ERR, "binary %s not found\n", dm_file_name); + return -1; + } + + pm_file_size = cbfs_boot_load_file(pm_file_name, dpm_pm_bin, + sizeof(dpm_pm_bin), CBFS_TYPE_RAW); + if (pm_file_size == 0) { + printk(BIOS_ERR, "binary %s not found\n", pm_file_name); + return -2; + } + printk(BIOS_INFO, "dm_file_size:%d, pm_file_size:%d\n", + (int)dm_file_size, (int)pm_file_size); + + /* config DPM SRAM layout */ + write32(&mtk_dpm->sw_rstn, read32(&mtk_dpm->sw_rstn) | 0x10000000); + + /* copy PM DM to DPM_SRAM */ + memcpy(dpm_pm_reg, dpm_pm_bin, pm_file_size); + memcpy(dpm_dm_reg, dpm_dm_bin, dm_file_size); + + /* write bootargs */ + write32(&mtk_dpm->twam_window_len, 0x0); + write32(&mtk_dpm->twam_mon_type, 0x0); + + /* free RST */ + write32(&mtk_dpm->sw_rstn, read32(&mtk_dpm->sw_rstn) | 0x1); + + return 0; +} + +int dpm_init(void) +{ + struct stopwatch sw; + stopwatch_init(&sw); + + if (dpm_load_firmware()) { + printk(BIOS_ERR, "DPM: firmware is not ready\n"); + return -1; + } + + printk(BIOS_INFO, "DPM: load finish in %ld msecs\n", + stopwatch_duration_msecs(&sw)); + + return 0; +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h old mode 100755 new mode 100644 index 9864e5b..5f49fe5 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -29,6 +29,9 @@ PMICSPI_MST_BASE = IO_PHYS + 0x00028000, SPMI_MST_BASE = IO_PHYS + 0x00029000, AUXADC_BASE = IO_PHYS + 0x01001000, + DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, + DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, + DPM_CFG_BASE = IO_PHYS + 0x00940000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, SPI1_BASE = IO_PHYS + 0x01010000, diff --git a/src/soc/mediatek/mt8192/include/soc/dpm.h b/src/soc/mediatek/mt8192/include/soc/dpm.h new file mode 100644 index 0000000..5763dab --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dpm.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_DPM_H__ +#define __SOC_MEDIATEK_MT8192_DPM_H__ + +#include <soc/addressmap.h> +#include <stdint.h> +#include <types.h> + +#define DPM_DM_OFFSET 0x8000 /* 32KB */ + +struct dpm_regs { + u32 sw_rstn; + u32 rsvd_0[3072]; + u32 mclk_div; + u32 rsvd_1[3071]; + u32 twam_window_len; + u32 twam_mon_type; + u32 rsvd_2[1022]; + u32 low_power_cfg_0; + u32 low_power_cfg_1; + u32 rsvd_3[1]; + u32 fsm_out_ctrl_0; + u32 rsvd_4[8]; + u32 fsm_cfg_1; + u32 low_power_cfg_3; + u32 dfd_dbug_0; + u32 rsvd_5[28]; + u32 status_4; +}; + +check_member(dpm_regs, mclk_div, 0x3004); +check_member(dpm_regs, twam_window_len, 0x6004); +check_member(dpm_regs, low_power_cfg_0, 0x7004); +check_member(dpm_regs, low_power_cfg_1, 0x7008); +check_member(dpm_regs, fsm_out_ctrl_0, 0x7010); +check_member(dpm_regs, fsm_cfg_1, 0x7034); +check_member(dpm_regs, low_power_cfg_3, 0x7038); +check_member(dpm_regs, dfd_dbug_0, 0x703C); +check_member(dpm_regs, status_4, 0x70B0);; + +int dpm_init(void); + +#define mtk_dpm ((struct dpm_regs *)DPM_CFG_BASE) + +#endif /* __SOC_MEDIATEK_MT8192_DPM_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16b341ad63940b45b886c4a7fd733c1970624e40 Gerrit-Change-Number: 46393 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 47

Change in coreboot[master]: soc/mediatek/mt8192: Load MCUPM firmware and boot up MCUPM.
by Yidi Lin (Code Review) 10 Dec '20

10 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46392 ) Change subject: soc/mediatek/mt8192: Load MCUPM firmware and boot up MCUPM. ...................................................................... soc/mediatek/mt8192: Load MCUPM firmware and boot up MCUPM. Change-Id: I50bea1942507b4a40df9730b4e1bf98980d74277 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/mcupm.h M src/soc/mediatek/mt8192/include/soc/memlayout.ld A src/soc/mediatek/mt8192/mcupm.c M src/soc/mediatek/mt8192/soc.c 6 files changed, 57 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/46392/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 9bb9cfd..59d105c 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c +ramstage-y += mcupm.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c usb.c @@ -52,6 +53,11 @@ spm_firmware.bin-type := raw spm_firmware.bin-compression := $(CBFS_COMPRESS_FLAG) +cbfs-files-y += mcupm.bin +mcupm.bin-file := $(MT8192_BLOB_DIR)/mcupm.bin +mcupm.bin-type := raw +mcupm.bin-compression := $(CBFS_COMPRESS_FLAG) + DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram $(DRAM_CBFS)-file := $(MT8192_BLOB_DIR)/dram.elf $(DRAM_CBFS)-type := stage diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 9760c88..9864e5b 100755 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -5,6 +5,8 @@ enum { MCUSYS_BASE = 0x0C530000, + MCUPM_SRAM_BASE = 0x0C540000, + MCUPM_CFG_BASE = 0x0C560000, IO_PHYS = 0x10000000, }; diff --git a/src/soc/mediatek/mt8192/include/soc/mcupm.h b/src/soc/mediatek/mt8192/include/soc/mcupm.h new file mode 100644 index 0000000..dcb8c4a --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/mcupm.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_MCUPM_H +#define SOC_MEDIATEK_MT8192_MCUPM_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8192_mcupm_regs { + u32 sw_rstn; +}; +static struct mt8192_mcupm_regs *const mt8192_mcupm = (void *)MCUPM_CFG_BASE; +void mcupm_init(void); +#endif /* SOC_MEDIATEK_MT8192_MCUPM_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index df9d376..3bef5b1 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -37,7 +37,7 @@ DRAM_START(0x40000000) POSTRAM_CBFS_CACHE(0x40000000, 2M) - RAMSTAGE(0x40200000, 256K) + RAMSTAGE(0x40200000, 512K) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8192/mcupm.c b/src/soc/mediatek/mt8192/mcupm.c new file mode 100644 index 0000000..88efc85 --- /dev/null +++ b/src/soc/mediatek/mt8192/mcupm.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/barrier.h> +#include <cbfs.h> +#include <console/console.h> +#include <device/mmio.h> +#include <soc/mcupm.h> +#include <string.h> + +#define BUF_SIZE (128 * KiB) +static uint8_t mcupm_bin[BUF_SIZE] __aligned(8); + +void mcupm_init(void) +{ + const char *file_name = "mcupm.bin"; + size_t fw_size = cbfs_boot_load_file(file_name, + mcupm_bin, + sizeof(mcupm_bin), + CBFS_TYPE_RAW); + + if (fw_size == 0) { + die("MCUPM file :mcupm.bin not found."); + } + + write32(&mt8192_mcupm->sw_rstn, 0x0); + write32((void *)(0x0C55FAA0), 0x0); + memcpy((void *)MCUPM_SRAM_BASE, mcupm_bin, fw_size); + /* Memory barrier to ensure that all fw code is loaded + before we release the reset pin. */ + mb(); + write32(&mt8192_mcupm->sw_rstn, 0x1); +} diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index 6978406..6deb833 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -4,6 +4,7 @@ #include <soc/emi.h> #include <soc/mmu_operations.h> #include <symbols.h> +#include <soc/mcupm.h> static void soc_read_resources(struct device *dev) { @@ -13,6 +14,7 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + mcupm_init(); } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/46392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50bea1942507b4a40df9730b4e1bf98980d74277 Gerrit-Change-Number: 46392 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 28

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2020