coreboot-gerrit October 2020

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Change in coreboot[master]: cbfs: Port cbfs_load() and cbfs_map() to new API
by Julius Werner (Code Review) 02 Dec '20

02 Dec '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39305 to review the following change. Change subject: cbfs: Port cbfs_load() and cbfs_map() to new API ...................................................................... cbfs: Port cbfs_load() and cbfs_map() to new API This patch adapts cbfs_load() and cbfs_map() to use the new CBFS API directly, rather than through cbfs_boot_locate(). For cbfs_load() this means that attribute metadata does not need to be read twice. Change-Id: I754cc34b1c1471129e15475aa0f1891e02439a02 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/bsd/cbfs_private.c M src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h M src/lib/cbfs.c 3 files changed, 43 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/39305/1 diff --git a/src/commonlib/bsd/cbfs_private.c b/src/commonlib/bsd/cbfs_private.c index 85a75ab..7e309ec 100644 --- a/src/commonlib/bsd/cbfs_private.c +++ b/src/commonlib/bsd/cbfs_private.c @@ -155,3 +155,21 @@ }; return cbfs_walk(dev, lookup_walker, &args, master_hash, 0); } + +void *cbfs_find_attr(union cbfs_mdata *mdata, uint32_t attr_tag) +{ + uint32_t offset = be32toh(mdata->h.attributes_offset); + uint32_t end = be32toh(mdata->h.offset); + + if (!offset) + return NULL; + + while (offset < end) { + struct cbfs_file_attribute *attr = (void *)mdata + offset; + if (be32toh(attr->tag) == attr_tag) + return attr; + offset += be32toh(attr->len); + } + + return NULL; +} diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h index df97009..4962cef 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h @@ -112,4 +112,7 @@ /* Returns the amount of bytes actually used by the CBFS metadata cache in |mcache|. */ size_t cbfs_mcache_real_size(const void *mcache, size_t mcache_size); +/* Finds a CBFS attribute in a metadata block. Attribute returned as-is (still big-endian). */ +void *cbfs_find_attr(union cbfs_mdata *mdata, uint32_t attr_tag); + #endif /* _COMMONLIB_BSD_CBFS_PRIVATE_H_ */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index bece4d0..c3660aa 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -81,18 +81,19 @@ void *cbfs_map(const char *name, size_t *size) { - struct cbfsf fh; - size_t fsize; + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + union cbfs_mdata mdata; + size_t data_offset; - if (cbfs_boot_locate(&fh, name, NULL)) + if (cbfs_boot_lookup(cbd, name, &mdata, &data_offset)) return NULL; - fsize = region_device_sz(&fh.data); + size_t data_size = be32toh(mdata.h.len); if (size != NULL) - *size = fsize; + *size = data_size; - return rdev_mmap(&fh.data, 0, fsize); + return rdev_mmap(&cbd->rdev, data_offset, data_size); } int cbfs_unmap(void *mapping) @@ -216,21 +217,25 @@ size_t cbfs_load(const char *name, void *buf, size_t buf_size) { - struct cbfsf fh; - uint32_t compression_algo; - size_t decompressed_size; + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + union cbfs_mdata mdata; + size_t data_offset; - if (cbfs_boot_locate(&fh, name, NULL) < 0) + if (cbfs_boot_lookup(cbd, name, &mdata, &data_offset)) return 0; - if (cbfsf_decompression_info(&fh, &compression_algo, - &decompressed_size) - < 0 - || decompressed_size > buf_size) - return 0; + uint32_t compression = CBFS_COMPRESS_NONE; + struct cbfs_file_attr_compression *attr = + cbfs_find_attr(&mdata, CBFS_FILE_ATTR_TAG_COMPRESSION); + if (attr) { + compression = be32toh(attr->compression); + if (buf_size < be32toh(attr->decompressed_size)) + return 0; + } - return cbfs_load_and_decompress(&fh.data, 0, region_device_sz(&fh.data), - buf, buf_size, compression_algo); + return cbfs_load_and_decompress(&cbd->rdev, data_offset, + be32toh(mdata.h.len), buf, buf_size, + compression); } size_t cbfs_prog_stage_section(struct prog *pstage, uintptr_t *base) -- To view, visit https://review.coreboot.org/c/coreboot/+/39305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I754cc34b1c1471129e15475aa0f1891e02439a02 Gerrit-Change-Number: 39305 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: cbfs: Move more stuff into cbfs_boot_lookup()
by Julius Werner (Code Review) 02 Dec '20

02 Dec '20

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39327 to review the following change. Change subject: cbfs: Move more stuff into cbfs_boot_lookup() ...................................................................... cbfs: Move more stuff into cbfs_boot_lookup() cbfs_boot_locate() is supposed to be deprecated eventually, after slowly migrating all APIs to bypass it. That means common features (like RO-fallback or measurement) need to be moved to the new cbfs_boot_lookup(). Signed-off-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I4bc9b7cbc42a4211d806a3e3389abab7f589a25a --- M src/lib/cbfs.c M src/security/vboot/vboot_crtm.c M src/security/vboot/vboot_crtm.h 3 files changed, 34 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/39327/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 39db97a..ef29299 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -31,40 +31,47 @@ #include <security/vboot/vboot_crtm.h> #include <security/vboot/vboot_common.h> -static cb_err_t cbfs_boot_lookup(const struct cbfs_boot_device *cbd, - const char *name, union cbfs_mdata *mdata, size_t *data_offset) +static cb_err_t cbfs_boot_lookup(struct region_device *rdev, const char *name, + union cbfs_mdata *mdata, size_t *data_offset, bool force_ro) { + cb_err_t err; + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(force_ro); + if (!cbd || rdev_chain_full(rdev, &cbd->rdev)) + return CB_ERR; + if (CONFIG(NO_CBFS_MCACHE)) - return cbfs_lookup(&cbd->rdev, name, mdata, data_offset, NULL); + err = cbfs_lookup(rdev, name, mdata, data_offset, NULL); else - return cbfs_mcache_lookup(&cbd->rdev, - cbd->mcache, cbd->mcache_size, - name, mdata, data_offset, NULL); + err = cbfs_mcache_lookup(rdev, cbd->mcache, cbd->mcache_size, + name, mdata, data_offset, NULL); + + if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && !force_ro && + err == CB_CBFS_NOT_FOUND) { + printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n", + name); + return cbfs_boot_lookup(rdev, name, mdata, data_offset, true); + } + if (err) + return err; + + if (vboot_measure_cbfs_hook(rdev, name, be32toh(mdata->h.type))) + return CB_ERR; + + return CB_SUCCESS; } int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) { - const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); - if (!cbd) - return -1; - + struct region_device rdev; union cbfs_mdata mdata; size_t data_offset; - cb_err_t err = cbfs_boot_lookup(cbd, name, &mdata, &data_offset); - if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && err == CB_CBFS_NOT_FOUND) { - printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n", - name); - if (!(cbd = cbfs_get_boot_device(true))) - return -1; - err = cbfs_boot_lookup(cbd, name, &mdata, &data_offset); - } - if (err) + if (cbfs_boot_lookup(&rdev, name, &mdata, &data_offset, false)) return -1; size_t msize = be32toh(mdata.h.offset); - if (rdev_chain(&fh->metadata, &cbd->rdev, data_offset - msize, msize) || - rdev_chain(&fh->data, &cbd->rdev, data_offset, be32toh(mdata.h.len))) + if (rdev_chain(&fh->metadata, &rdev, data_offset - msize, msize) || + rdev_chain(&fh->data, &rdev, data_offset, be32toh(mdata.h.len))) return -1; if (type) { if (!*type) @@ -73,9 +80,6 @@ return -1; } - if (vboot_measure_cbfs_hook(fh, name)) - return -1; - return 0; } diff --git a/src/security/vboot/vboot_crtm.c b/src/security/vboot/vboot_crtm.c index f68ab0a4..75c5662 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/vboot/vboot_crtm.c @@ -157,19 +157,16 @@ return false; } -uint32_t vboot_measure_cbfs_hook(struct cbfsf *fh, const char *name) +uint32_t vboot_measure_cbfs_hook(struct region_device *rdev, const char *name, + uint32_t cbfs_type) { uint32_t pcr_index; - uint32_t cbfs_type; struct region_device rdev; char tcpa_metadata[TCPA_PCR_HASH_NAME]; if (!vboot_logic_executed()) return 0; - cbfsf_file_type(fh, &cbfs_type); - cbfs_file_data(&rdev, fh); - switch (cbfs_type) { case CBFS_TYPE_MRC: case CBFS_TYPE_MRC_CACHE: diff --git a/src/security/vboot/vboot_crtm.h b/src/security/vboot/vboot_crtm.h index 64cb4f2..8e6c076 100644 --- a/src/security/vboot/vboot_crtm.h +++ b/src/security/vboot/vboot_crtm.h @@ -49,13 +49,14 @@ #if CONFIG(VBOOT_MEASURED_BOOT) /* * Measures cbfs data via hook (cbfs) - * fh is the cbfs file handle to measure + * rdev covers the file data (not metadata) * return 0 if successful, else an error */ -uint32_t vboot_measure_cbfs_hook(struct cbfsf *fh, const char *name); +uint32_t vboot_measure_cbfs_hook(struct region_device *rdev, const char *name, + uint32_t cbfs_type); #else -#define vboot_measure_cbfs_hook(fh, name) 0 +#define vboot_measure_cbfs_hook(rdev, name, cbfs_type) 0 #endif #endif /* __VBOOT_VBOOT_CRTM_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/39327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bc9b7cbc42a4211d806a3e3389abab7f589a25a Gerrit-Change-Number: 39327 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: AMD AGESA DDR3 XMP support: scripts for applying the not-merged-yet p...
by Mike Banon (Code Review) 02 Dec '20

02 Dec '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40495 ) Change subject: AMD AGESA DDR3 XMP support: scripts for applying the not-merged-yet patches ...................................................................... AMD AGESA DDR3 XMP support: scripts for applying the not-merged-yet patches These scripts will help you to securely and conveniently apply five changes CB:40484, CB:40485, CB:40490, CB:40488, CB:40489 to add the DDR3 XMP support. Save to ./coreboot/ then run ./get_xmp_patches.sh , ./check... and ./apply... Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ibcb04871e5d969eee1cfd49d21962ae4bbcc4e5d --- A apply_xmp_patches.sh A check_xmp_patches.sh A get_xmp_patches.sh A sha256sums_xmp_correct.txt 4 files changed, 85 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/40495/1 diff --git a/apply_xmp_patches.sh b/apply_xmp_patches.sh new file mode 100755 index 0000000..4320ee2 --- /dev/null +++ b/apply_xmp_patches.sh @@ -0,0 +1,27 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/40484 +### nb/amd/agesa: read 256 bytes to SPD buffer instead of 128 +### +patch -p1 < "./b8b7fb7.diff" +### +### https://review.coreboot.org/c/coreboot/+/40485 +### vc/amd/agesa/f15tn: add 933 MHz to GfxMemClockFrequencyDefinitionTable +### +patch -p1 < "./a81f3eb.diff" +### +### https://review.coreboot.org/c/coreboot/+/40490 +### vc/amd/agesa/f15tn: add DDR1866_FREQUENCY to DdrMaxRateTab table +### +patch -p1 < "./bf4bd85.diff" +### +### https://review.coreboot.org/c/coreboot/+/40488 +### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles +### +patch -p1 < "./3b9288e.diff" +### +### https://review.coreboot.org/c/coreboot/+/40489 +### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile +### +patch -p1 < "./413db53.diff" +### diff --git a/check_xmp_patches.sh b/check_xmp_patches.sh new file mode 100755 index 0000000..88a0375 --- /dev/null +++ b/check_xmp_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +rm -f "./sha256sums_xmp_my.txt" +sha256sum "./b8b7fb7.diff" > "./sha256sums_xmp_my.txt" +sha256sum "./a81f3eb.diff" >> "./sha256sums_xmp_my.txt" +sha256sum "./bf4bd85.diff" >> "./sha256sums_xmp_my.txt" +sha256sum "./3b9288e.diff" >> "./sha256sums_xmp_my.txt" +sha256sum "./413db53.diff" >> "./sha256sums_xmp_my.txt" +if cmp -s "./sha256sums_xmp_my.txt" "./sha256sums_xmp_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_xmp_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_xmp_my.txt and ./sha256sums_xmp_correct.txt" + exit 1 +fi +# diff --git a/get_xmp_patches.sh b/get_xmp_patches.sh new file mode 100755 index 0000000..34eba96 --- /dev/null +++ b/get_xmp_patches.sh @@ -0,0 +1,37 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/40484 +### nb/amd/agesa: read 256 bytes to SPD buffer instead of 128 +### +rm -f "./b8b7fb7.diff" +wget "https://review.coreboot.org/changes/40484/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./b8b7fb7.diff" +### +### https://review.coreboot.org/c/coreboot/+/40485 +### vc/amd/agesa/f15tn: add 933 MHz to GfxMemClockFrequencyDefinitionTable +### +rm -f "./a81f3eb.diff" +wget "https://review.coreboot.org/changes/40485/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./a81f3eb.diff" +### +### https://review.coreboot.org/c/coreboot/+/40490 +### vc/amd/agesa/f15tn: add DDR1866_FREQUENCY to DdrMaxRateTab table +### +rm -f "./bf4bd85.diff" +wget "https://review.coreboot.org/changes/40490/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./bf4bd85.diff" +### +### https://review.coreboot.org/c/coreboot/+/40488 +### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles +### +rm -f "./3b9288e.diff" +wget "https://review.coreboot.org/changes/40488/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./3b9288e.diff" +### +### https://review.coreboot.org/c/coreboot/+/40489 +### vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile +### +rm -f "./413db53.diff" +wget "https://review.coreboot.org/changes/40489/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./413db53.diff" +### diff --git a/sha256sums_xmp_correct.txt b/sha256sums_xmp_correct.txt new file mode 100644 index 0000000..e3ccb04 --- /dev/null +++ b/sha256sums_xmp_correct.txt @@ -0,0 +1,5 @@ +0b19e790c27cc4344f5427e2af62b3d8f5c729c49a528709689e4c1536e55daf ./b8b7fb7.diff +0f5816d40a56e5fe3201e539c2f6cae51a03ae606085731f3c70eb7f2a007bd5 ./a81f3eb.diff +6749bbe5a8a33b0a32d214e32ffba4b6d7df740c73fd674c344653041e5103aa ./bf4bd85.diff +4579e9a7f3454e4909789b56d2fd6422129e31185a363cf6cd13485907b82b1d ./3b9288e.diff +d5161276160d1cf4d77a5252cb7f9855d2ff5de00dedea28790627d9a144b556 ./413db53.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/40495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibcb04871e5d969eee1cfd49d21962ae4bbcc4e5d Gerrit-Change-Number: 40495 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile
by Mike Banon (Code Review) 02 Dec '20

02 Dec '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40489 ) Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile ...................................................................... vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support a custom memory profile The ability to set up a custom memory profile is useful if you don't like the XMP memory profiles (if they exist) of your RAM sticks, or want to try some overclocking. Read SPD data will be overriden by your custom values. Took Crucial BLT8G3D1869DT1TX0 XMP 1 (1866MHz 9-9-9-27) as an example. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I1238ff00ef0efd11ea807794827476c30ac98065 --- M src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 10 files changed, 337 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/40489/1 diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig index 817c4b3..461b04d 100644 --- a/src/vendorcode/amd/agesa/Kconfig +++ b/src/vendorcode/amd/agesa/Kconfig @@ -38,6 +38,119 @@ help XMP 2 memory profile. Check that it exists on ALL of your RAM sticks! +config CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM + bool "CUSTOM" + help + Custom memory profile. Use the XMP SPD values as the base, if available. + +if CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM + +config CUSTOM_SPD_DIVIDENT + int "[10]: Medium Timebase (MTB) Dividend" + default 1 + range 1 255 + +config CUSTOM_SPD_DIVISOR + int "[11]: Medium Timebase (MTB) Divisor" + default 14 + range 1 255 + +config CUSTOM_SPD_TCK + int "[12]: SDRAM Minimum Cycle Time, tCK" + default 15 + range 1 255 + +config CUSTOM_SPD_CASLO + int "[14]: CAS Latencies Supported, Lower Byte" + default 124 + range 0 255 + +config CUSTOM_SPD_CASHI + int "[15]: CAS Latencies Supported, Higher Byte" + default 0 + range 0 255 + +config CUSTOM_SPD_TAA + int "[16]: Min CAS Latency Time, tAA" + default 132 + range 1 255 + +config CUSTOM_SPD_TWR + int "[17]: Min Write Recovery Time, tWR" + default 210 + range 1 255 + +config CUSTOM_SPD_TRCD + int "[18]: Min RAS# to CAS# Delay Time, tRCD" + default 132 + range 1 255 + +config CUSTOM_SPD_TRRD + int "[19]: Min Row Active to Row Active Delay Time, tRRD" + default 84 + range 1 255 + +config CUSTOM_SPD_TRP + int "[20]: Min Row Precharge Delay Time, tRP" + default 132 + range 1 255 + +config CUSTOM_SPD_UPPER_TRC + int "[21][7:4]: Min Active to Active/Refresh Delay, UPPER tRC" + default 2 + range 0 16 + +config CUSTOM_SPD_UPPER_TRAS + int "[21][3:0]: Min Active to Precharge Delay Time, UPPER tRAS" + default 1 + range 0 16 + +config CUSTOM_SPD_TRAS + int "[22]: Min Active to Precharge Delay Time, LOWER tRAS" + default 138 + range 1 255 + +config CUSTOM_SPD_TRC + int "[23]: Min Active to Active/Refresh Delay, LOWER tRC" + default 181 + range 1 255 + +if CPU_AMD_AGESA_FAMILY16_KB + +config CUSTOM_SPD_TRFC_LO + int "[24]: Min Refresh Recovery Delay Time, LOWER tRFC" + default 56 + range 1 255 + +config CUSTOM_SPD_TRFC_HI + int "[25]: Min Refresh Recovery Delay Time, UPPER tRFC" + default 14 + range 0 255 + +endif + +config CUSTOM_SPD_TWTR + int "[26]: Min Internal Write to Read Command Delay, tWTR" + default 105 + range 1 255 + +config CUSTOM_SPD_TRTP + int "[27]: Min Internal Read to Precharge Command Delay, tRTP" + default 105 + range 1 255 + +config CUSTOM_SPD_UPPER_TFAW + int "[28][3:0]: Min Four Activate Window Delay, UPPER tFAW" + default 1 + range 0 16 + +config CUSTOM_SPD_TFAW + int "[29]: Min Four Activate Window Delay Time, tFAW" + default 164 + range 1 255 + +endif + endchoice endif diff --git a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h index 86fe800..e38e675 100644 --- a/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/PlatformInstall.h @@ -798,6 +798,11 @@ #define CFG_DQS_TRAINING_CONTROL TRUE #endif +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) + #undef BLDCFG_IGNORE_SPD_CHECKSUM + #define BLDCFG_IGNORE_SPD_CHECKSUM TRUE +#endif + #ifdef BLDCFG_IGNORE_SPD_CHECKSUM #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM #else diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c index 392b7fc..cf3942b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmflow.c @@ -64,6 +64,7 @@ #include "mm.h" #include "mn.h" #include "mt.h" +#include "mtspd3.h" #include "mu.h" #include "heapManager.h" #include "Filecode.h" @@ -101,6 +102,16 @@ IN OUT MEM_DATA_STRUCT *MemPtr ); +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ); + +#endif + /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * @@ -293,6 +304,60 @@ return Retval; } +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function modifies a SPD buffer with the custom SPD values set up in coreboot's config. + * + * @param[in,out] *Buffer - Pointer to the UINT8 + * + */ + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ) +{ + UINT16 Offset; + // + // Modify a SPD buffer. + // + Buffer[SPD_DIVIDENT] = CONFIG_CUSTOM_SPD_DIVIDENT; + Buffer[SPD_DIVISOR] = CONFIG_CUSTOM_SPD_DIVISOR; + Buffer[SPD_TCK] = CONFIG_CUSTOM_SPD_TCK; + Buffer[SPD_CASLO] = CONFIG_CUSTOM_SPD_CASLO; + Buffer[SPD_CASHI] = CONFIG_CUSTOM_SPD_CASHI; + Buffer[SPD_TAA] = CONFIG_CUSTOM_SPD_TAA; + Buffer[SPD_TWR] = CONFIG_CUSTOM_SPD_TWR; + Buffer[SPD_TRCD] = CONFIG_CUSTOM_SPD_TRCD; + Buffer[SPD_TRRD] = CONFIG_CUSTOM_SPD_TRRD; + Buffer[SPD_TRP] = CONFIG_CUSTOM_SPD_TRP; + // + // SPD_UPPER_TRC and SPD_UPPER_TRAS are the same index but different bits: + // SPD_UPPER_TRC - [7:4], SPD_UPPER_TRAS - [3:0]. + // + Buffer[SPD_UPPER_TRAS] = (CONFIG_CUSTOM_SPD_UPPER_TRC << 4) + CONFIG_CUSTOM_SPD_UPPER_TRAS; + Buffer[SPD_TRAS] = CONFIG_CUSTOM_SPD_TRAS; + Buffer[SPD_TRC] = CONFIG_CUSTOM_SPD_TRC; + Buffer[SPD_TWTR] = CONFIG_CUSTOM_SPD_TWTR; + Buffer[SPD_TRTP] = CONFIG_CUSTOM_SPD_TRTP; + Buffer[SPD_UPPER_TFAW] = CONFIG_CUSTOM_SPD_UPPER_TFAW; + Buffer[SPD_TFAW] = CONFIG_CUSTOM_SPD_TFAW; + // + // Print a SPD buffer. + // + printk(BIOS_SPEW, "***** SPD BUFFER *****\n"); + for (Offset = 0; Offset < 256; Offset++) { + printk(BIOS_SPEW, "Buffer[%d] = 0x%02X\n", Offset, Buffer[Offset]); + } + printk(BIOS_SPEW, "**********************\n"); +} + +#endif /* -----------------------------------------------------------------------------*/ /** @@ -369,6 +434,9 @@ if (AgesaStatus == AGESA_SUCCESS) { DimmSPDPtr->DimmPresent = TRUE; IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); + #if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + AgesaCustomMemoryProfileSPD(SpdParam.Buffer); + #endif } else { DimmSPDPtr->DimmPresent = FALSE; } diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h index c7f490d..2797f80 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,7 +95,7 @@ #define SPD_FTB 9 -#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) || CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 diff --git a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h index 70c2135..82ebab7 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h @@ -2027,6 +2027,11 @@ #define CFG_DQS_TRAINING_CONTROL TRUE #endif +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) + #undef BLDCFG_IGNORE_SPD_CHECKSUM + #define BLDCFG_IGNORE_SPD_CHECKSUM TRUE +#endif + #ifdef BLDCFG_IGNORE_SPD_CHECKSUM #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM #else diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c index f2e5848..1030d7a 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmflow.c @@ -62,6 +62,7 @@ #include "mm.h" #include "mn.h" #include "mt.h" +#include "mtspd3.h" #include "mu.h" #include "heapManager.h" #include "Filecode.h" @@ -99,6 +100,16 @@ IN OUT MEM_DATA_STRUCT *MemPtr ); +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ); + +#endif + /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * @@ -302,6 +313,60 @@ return Retval; } +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function modifies a SPD buffer with the custom SPD values set up in coreboot's config. + * + * @param[in,out] *Buffer - Pointer to the UINT8 + * + */ + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ) +{ + UINT16 Offset; + // + // Modify a SPD buffer. + // + Buffer[SPD_DIVIDENT] = CONFIG_CUSTOM_SPD_DIVIDENT; + Buffer[SPD_DIVISOR] = CONFIG_CUSTOM_SPD_DIVISOR; + Buffer[SPD_TCK] = CONFIG_CUSTOM_SPD_TCK; + Buffer[SPD_CASLO] = CONFIG_CUSTOM_SPD_CASLO; + Buffer[SPD_CASHI] = CONFIG_CUSTOM_SPD_CASHI; + Buffer[SPD_TAA] = CONFIG_CUSTOM_SPD_TAA; + Buffer[SPD_TWR] = CONFIG_CUSTOM_SPD_TWR; + Buffer[SPD_TRCD] = CONFIG_CUSTOM_SPD_TRCD; + Buffer[SPD_TRRD] = CONFIG_CUSTOM_SPD_TRRD; + Buffer[SPD_TRP] = CONFIG_CUSTOM_SPD_TRP; + // + // SPD_UPPER_TRC and SPD_UPPER_TRAS are the same index but different bits: + // SPD_UPPER_TRC - [7:4], SPD_UPPER_TRAS - [3:0]. + // + Buffer[SPD_UPPER_TRAS] = (CONFIG_CUSTOM_SPD_UPPER_TRC << 4) + CONFIG_CUSTOM_SPD_UPPER_TRAS; + Buffer[SPD_TRAS] = CONFIG_CUSTOM_SPD_TRAS; + Buffer[SPD_TRC] = CONFIG_CUSTOM_SPD_TRC; + Buffer[SPD_TWTR] = CONFIG_CUSTOM_SPD_TWTR; + Buffer[SPD_TRTP] = CONFIG_CUSTOM_SPD_TRTP; + Buffer[SPD_UPPER_TFAW] = CONFIG_CUSTOM_SPD_UPPER_TFAW; + Buffer[SPD_TFAW] = CONFIG_CUSTOM_SPD_TFAW; + // + // Print a SPD buffer. + // + printk(BIOS_SPEW, "***** SPD BUFFER *****\n"); + for (Offset = 0; Offset < 256; Offset++) { + printk(BIOS_SPEW, "Buffer[%d] = 0x%02X\n", Offset, Buffer[Offset]); + } + printk(BIOS_SPEW, "**********************\n"); +} + +#endif /* -----------------------------------------------------------------------------*/ /** @@ -378,6 +443,9 @@ if (AgesaStatus == AGESA_SUCCESS) { DimmSPDPtr->DimmPresent = TRUE; IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); + #if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + AgesaCustomMemoryProfileSPD(SpdParam.Buffer); + #endif } else { DimmSPDPtr->DimmPresent = FALSE; } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h index bbe5c12..ede7067 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h @@ -94,7 +94,7 @@ #define SPD_FTB 9 -#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) || CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 diff --git a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h index 90c4e3f..4349e4e 100644 --- a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h @@ -996,6 +996,11 @@ #define CFG_DQS_TRAINING_CONTROL TRUE #endif +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) + #undef BLDCFG_IGNORE_SPD_CHECKSUM + #define BLDCFG_IGNORE_SPD_CHECKSUM TRUE +#endif + #ifdef BLDCFG_IGNORE_SPD_CHECKSUM #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM #else diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c index d497aec..dfc1e35 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmflow.c @@ -62,6 +62,7 @@ #include "mm.h" #include "mn.h" #include "mt.h" +#include "mtspd3.h" #include "mu.h" #include "heapManager.h" #include "Filecode.h" @@ -99,6 +100,16 @@ IN OUT MEM_DATA_STRUCT *MemPtr ); +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ); + +#endif + /*---------------------------------------------------------------------------- * EXPORTED FUNCTIONS * @@ -314,6 +325,62 @@ return Retval; } +#if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + +/* -----------------------------------------------------------------------------*/ +/** + * + * + * This function modifies a SPD buffer with the custom SPD values set up in coreboot's config. + * + * @param[in,out] *Buffer - Pointer to the UINT8 + * + */ + +VOID +STATIC +AgesaCustomMemoryProfileSPD ( + IN OUT UINT8 *Buffer + ) +{ + UINT16 Offset; + // + // Modify a SPD buffer. + // + Buffer[SPD_DIVIDENT] = CONFIG_CUSTOM_SPD_DIVIDENT; + Buffer[SPD_DIVISOR] = CONFIG_CUSTOM_SPD_DIVISOR; + Buffer[SPD_TCK] = CONFIG_CUSTOM_SPD_TCK; + Buffer[SPD_CASLO] = CONFIG_CUSTOM_SPD_CASLO; + Buffer[SPD_CASHI] = CONFIG_CUSTOM_SPD_CASHI; + Buffer[SPD_TAA] = CONFIG_CUSTOM_SPD_TAA; + Buffer[SPD_TWR] = CONFIG_CUSTOM_SPD_TWR; + Buffer[SPD_TRCD] = CONFIG_CUSTOM_SPD_TRCD; + Buffer[SPD_TRRD] = CONFIG_CUSTOM_SPD_TRRD; + Buffer[SPD_TRP] = CONFIG_CUSTOM_SPD_TRP; + // + // SPD_UPPER_TRC and SPD_UPPER_TRAS are the same index but different bits: + // SPD_UPPER_TRC - [7:4], SPD_UPPER_TRAS - [3:0]. + // + Buffer[SPD_UPPER_TRAS] = (CONFIG_CUSTOM_SPD_UPPER_TRC << 4) + CONFIG_CUSTOM_SPD_UPPER_TRAS; + Buffer[SPD_TRAS] = CONFIG_CUSTOM_SPD_TRAS; + Buffer[SPD_TRC] = CONFIG_CUSTOM_SPD_TRC; + Buffer[SPD_TRFC_LO] = CONFIG_CUSTOM_SPD_TRFC_LO; + Buffer[SPD_TRFC_HI] = CONFIG_CUSTOM_SPD_TRFC_HI; + Buffer[SPD_TWTR] = CONFIG_CUSTOM_SPD_TWTR; + Buffer[SPD_TRTP] = CONFIG_CUSTOM_SPD_TRTP; + Buffer[SPD_UPPER_TFAW] = CONFIG_CUSTOM_SPD_UPPER_TFAW; + Buffer[SPD_TFAW] = CONFIG_CUSTOM_SPD_TFAW; + // + // Print a SPD buffer. + // + printk(BIOS_SPEW, "***** SPD BUFFER *****\n"); + for (Offset = 0; Offset < 256; Offset++) { + printk(BIOS_SPEW, "Buffer[%d] = 0x%02X\n", Offset, Buffer[Offset]); + } + printk(BIOS_SPEW, "**********************\n"); +} + +#endif /* -----------------------------------------------------------------------------*/ /** @@ -390,6 +457,9 @@ if (AgesaStatus == AGESA_SUCCESS) { DimmSPDPtr->DimmPresent = TRUE; IDS_HDT_CONSOLE (MEM_FLOW, "SPD Socket %d Channel %d Dimm %d: %08x\n", Socket, Channel, Dimm, SpdParam.Buffer); + #if (CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM)) + AgesaCustomMemoryProfileSPD(SpdParam.Buffer); + #endif } else { DimmSPDPtr->DimmPresent = FALSE; } diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h index bc608a5..472add0 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,7 +95,7 @@ #define SPD_FTB 9 -#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) || CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM) #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 -- To view, visit https://review.coreboot.org/c/coreboot/+/40489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1238ff00ef0efd11ea807794827476c30ac98065 Gerrit-Change-Number: 40489 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles
by Mike Banon (Code Review) 02 Dec '20

02 Dec '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40488 ) Change subject: vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles ...................................................................... vc/amd/agesa/f.../Proc/Mem/Tech/DDR3: Support XMP memory profiles XMP memory profiles support which has been tested on f15tn (ASUS A88XM-E) and f16kb (ASUS AM1I-A) with Crucial BLT8G3D1869DT1TX0, XMP 1 profile. Added using the datasheets from https://github.com/mikebdp2/ddr3spd : JEDEC_DDR3_SPD_4_01_02_11R24.pdf and Intel_XMP_Spec_Rev1.1.pdf (whole PDFs) Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I584416e3376afdf377a11783e55c5e9ff41e6b0d --- M src/vendorcode/amd/Kconfig A src/vendorcode/amd/agesa/Kconfig M src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h 5 files changed, 245 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/40488/1 diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig index 3e3a0e9..7f85852 100644 --- a/src/vendorcode/amd/Kconfig +++ b/src/vendorcode/amd/Kconfig @@ -42,6 +42,10 @@ endchoice +if CPU_AMD_AGESA_OPENSOURCE +source "src/vendorcode/amd/agesa/Kconfig" +endif + if CPU_AMD_AGESA_BINARY_PI source "src/vendorcode/amd/pi/Kconfig" endif diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig new file mode 100644 index 0000000..817c4b3 --- /dev/null +++ b/src/vendorcode/amd/agesa/Kconfig @@ -0,0 +1,43 @@ +# +# This file is part of the coreboot project. +# +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if CPU_AMD_AGESA_FAMILY14 || CPU_AMD_AGESA_FAMILY15_TN || CPU_AMD_AGESA_FAMILY16_KB + +choice + prompt "DDR3 memory profile" + default CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + help + Choose the DDR3 memory profile to use for your RAM sticks, i.e. XMP 1. + XMP support is experimental, and your PC will fail booting if you choose + a profile which does not exist on ANY of your RAM sticks! If in doubt, + check their SPD Data using a coreboot's great fork of memtest86+ 5.01. + +config CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC + bool "JEDEC" + help + JEDEC memory profile, standard and stable. Is guaranteed to be working. + +config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 + bool "XMP 1" + help + XMP 1 memory profile. Check that it exists on ALL of your RAM sticks! + +config CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 + bool "XMP 2" + help + XMP 2 memory profile. Check that it exists on ALL of your RAM sticks! + +endchoice + +endif diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h index 3b37429..c7f490d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,6 +95,8 @@ #define SPD_FTB 9 +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 @@ -103,18 +105,70 @@ #define SPD_CASHI 15 #define SPD_TAA 16 -#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 +#define SPD_UPPER_TRC 21 /* bits 7:4 */ +#define SPD_UPPER_TRAS 21 /* bits 3:0 */ +#define SPD_TRAS 22 +#define SPD_TRC 23 #define SPD_TWTR 26 #define SPD_TRTP 27 -#define SPD_TRC 23 -#define SPD_UPPER_TRC 21 /* bit 7:4 */ -#define SPD_UPPER_TRAS 21 /* bit 3:0 */ +#define SPD_UPPER_TFAW 28 /* bits 3:0 */ #define SPD_TFAW 29 -#define SPD_UPPER_TFAW 28 /* bit 3:0 */ + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1) + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bits 7:4 */ +#define SPD_UPPER_TRAS 194 /* bits 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bits 3:0 */ +#define SPD_TFAW 204 + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2) + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bits 7:4 */ +#define SPD_UPPER_TRAS 229 /* bits 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bits 3:0 */ +#define SPD_TFAW 239 + +#endif #define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h index ab46e4a..bbe5c12 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtspd3.h @@ -94,6 +94,8 @@ #define SPD_FTB 9 +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 @@ -102,18 +104,70 @@ #define SPD_CASHI 15 #define SPD_TAA 16 -#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 +#define SPD_UPPER_TRC 21 /* bits 7:4 */ +#define SPD_UPPER_TRAS 21 /* bits 3:0 */ +#define SPD_TRAS 22 +#define SPD_TRC 23 #define SPD_TWTR 26 #define SPD_TRTP 27 -#define SPD_TRC 23 -#define SPD_UPPER_TRC 21 /* bit 7:4 */ -#define SPD_UPPER_TRAS 21 /* bit 3:0 */ +#define SPD_UPPER_TFAW 28 /* bits 3:0 */ #define SPD_TFAW 29 -#define SPD_UPPER_TFAW 28 /* bit 3:0 */ + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1) + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bits 7:4 */ +#define SPD_UPPER_TRAS 194 /* bits 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bits 3:0 */ +#define SPD_TFAW 204 + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2) + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bits 7:4 */ +#define SPD_UPPER_TRAS 229 /* bits 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bits 3:0 */ +#define SPD_TFAW 239 + +#endif #define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h index bf13c7f..bc608a5 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/DDR3/mtspd3.h @@ -95,6 +95,8 @@ #define SPD_FTB 9 +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC) + #define SPD_DIVIDENT 10 #define SPD_DIVISOR 11 @@ -103,18 +105,82 @@ #define SPD_CASHI 15 #define SPD_TAA 16 -#define SPD_TRP 20 -#define SPD_TRRD 19 -#define SPD_TRCD 18 -#define SPD_TRAS 22 #define SPD_TWR 17 +#define SPD_TRCD 18 +#define SPD_TRRD 19 +#define SPD_TRP 20 +#define SPD_UPPER_TRC 21 /* bits 7:4 */ +#define SPD_UPPER_TRAS 21 /* bits 3:0 */ +#define SPD_TRAS 22 +#define SPD_TRC 23 + +#define SPD_TRFC_LO 24 +#define SPD_TRFC_HI 25 + #define SPD_TWTR 26 #define SPD_TRTP 27 -#define SPD_TRC 23 -#define SPD_UPPER_TRC 21 /* bit 7:4 */ -#define SPD_UPPER_TRAS 21 /* bit 3:0 */ +#define SPD_UPPER_TFAW 28 /* bits 3:0 */ #define SPD_TFAW 29 -#define SPD_UPPER_TFAW 28 /* bit 3:0 */ + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1) + +#define SPD_DIVIDENT 180 +#define SPD_DIVISOR 181 + +#define SPD_TCK 186 +#define SPD_CASLO 188 +#define SPD_CASHI 189 +#define SPD_TAA 187 + +#define SPD_TWR 193 +#define SPD_TRCD 192 +#define SPD_TRRD 202 +#define SPD_TRP 191 +#define SPD_UPPER_TRC 194 /* bits 7:4 */ +#define SPD_UPPER_TRAS 194 /* bits 3:0 */ +#define SPD_TRAS 195 +#define SPD_TRC 196 + +#define SPD_TRFC_LO 199 +#define SPD_TRFC_HI 200 + +#define SPD_TWTR 205 +#define SPD_TRTP 201 +#define SPD_UPPER_TFAW 203 /* bits 3:0 */ +#define SPD_TFAW 204 + +#endif + +#if CONFIG(CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2) + +#define SPD_DIVIDENT 182 +#define SPD_DIVISOR 183 + +#define SPD_TCK 221 +#define SPD_CASLO 223 +#define SPD_CASHI 224 +#define SPD_TAA 222 + +#define SPD_TWR 228 +#define SPD_TRCD 227 +#define SPD_TRRD 237 +#define SPD_TRP 226 +#define SPD_UPPER_TRC 229 /* bits 7:4 */ +#define SPD_UPPER_TRAS 229 /* bits 3:0 */ +#define SPD_TRAS 230 +#define SPD_TRC 231 + +#define SPD_TRFC_LO 234 +#define SPD_TRFC_HI 235 + +#define SPD_TWTR 240 +#define SPD_TRTP 236 +#define SPD_UPPER_TFAW 238 /* bits 3:0 */ +#define SPD_TFAW 239 + +#endif #define SPD_TCK_FTB 34 #define SPD_TAA_FTB 35 @@ -122,9 +188,6 @@ #define SPD_TRP_FTB 37 #define SPD_TRC_FTB 38 -#define SPD_TRFC_LO 24 -#define SPD_TRFC_HI 25 - /*----------------------------- * Jedec DDR II related equates *----------------------------- -- To view, visit https://review.coreboot.org/c/coreboot/+/40488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I584416e3376afdf377a11783e55c5e9ff41e6b0d Gerrit-Change-Number: 40488 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

6 14

Change in coreboot[master]: [WIP] soc/amd/picasso: add FSP binary location
by Felix Held (Code Review) 02 Dec '20

02 Dec '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42472 ) Change subject: [WIP] soc/amd/picasso: add FSP binary location ...................................................................... [WIP] soc/amd/picasso: add FSP binary location Since the blobs haven't landed yet, it is expected that this breaks the Jenkins build. Change-Id: Ib2241cc90c7113e0c3de4409e08b9ae1f4c2f51e Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/Kconfig 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/42472/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index dd5731d..bf809f8 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -60,6 +60,20 @@ string default "src/soc/amd/picasso/memlayout.ld" +config FSP_M_FILE + string "FSP-M (memory init) binary path and filename" + depends on ADD_FSP_BINARIES + default "3rdparty/amd_blobs/picasso/PICASSO_M.fd" + help + The path and filename of the FSP-M binary for this platform. + +config FSP_S_FILE + string "FSP-S (silicon init) binary path and filename" + depends on ADD_FSP_BINARIES + default "3rdparty/amd_blobs/picasso/PICASSO_S.fd" + help + The path and filename of the FSP-S binary for this platform. + config EARLY_RESERVED_DRAM_BASE hex default 0x2000000 -- To view, visit https://review.coreboot.org/c/coreboot/+/42472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2241cc90c7113e0c3de4409e08b9ae1f4c2f51e Gerrit-Change-Number: 42472 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: WIP: soc/mediatek/mt8192: add i2c driver support
by yongqiang niu (Code Review) 02 Dec '20

02 Dec '20

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46573 ) Change subject: WIP: soc/mediatek/mt8192: add i2c driver support ...................................................................... WIP: soc/mediatek/mt8192: add i2c driver support Add i2c controller driver code TEST=Boots correctly on MT8192P1 Signed-off-by: jg_daolongzhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Change-Id: Ib8ece265687d37bafe2f0de63459ea0fabab8a11 --- M src/soc/mediatek/common/i2c.c M src/soc/mediatek/common/include/soc/i2c_common.h M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/i2c.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/i2c.h 6 files changed, 247 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/46573/1 diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c index 87925ba..931e36d 100644 --- a/src/soc/mediatek/common/i2c.c +++ b/src/soc/mediatek/common/i2c.c @@ -47,6 +47,7 @@ { uint32_t ret_code = I2C_OK; uint16_t status; + uint16_t dma_sync = 0; uint32_t time_out_val = 0; uint8_t addr; uint32_t write_len = 0; @@ -62,6 +63,12 @@ addr = seg[0].slave; + if (mtk_i2c_bus_controller[bus].mt_i2c_flag == I2C_APDMA_ASYNC) { + dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE; + if (mode == I2C_WRITE_READ_MODE) + dma_sync |= I2C_DMA_DIR_CHANGE; + } + switch (mode) { case I2C_WRITE_MODE: assert(seg[0].len > 0 && seg[0].len <= 255); @@ -113,7 +120,7 @@ write32(&regs->slave_addr, addr << 1); /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CON_TX); + write32(&dma_regs->dma_con, I2C_DMA_CON_TX | dma_sync); write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); write32(&dma_regs->dma_tx_len, write_len); break; @@ -132,7 +139,7 @@ write32(&regs->slave_addr, (addr << 1 | 0x1)); /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CON_RX); + write32(&dma_regs->dma_con, I2C_DMA_CON_RX | dma_sync); write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); write32(&dma_regs->dma_rx_len, read_len); break; @@ -154,7 +161,7 @@ write32(&regs->slave_addr, addr << 1); /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CLR_FLAG); + write32(&dma_regs->dma_con, I2C_DMA_CLR_FLAG | dma_sync); write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); write32(&dma_regs->dma_tx_len, write_len); write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); diff --git a/src/soc/mediatek/common/include/soc/i2c_common.h b/src/soc/mediatek/common/include/soc/i2c_common.h index 0100e26..198a2b57 100644 --- a/src/soc/mediatek/common/include/soc/i2c_common.h +++ b/src/soc/mediatek/common/include/soc/i2c_common.h @@ -38,6 +38,9 @@ I2C_DMA_INT_FLAG_NONE = 0x0, I2C_DMA_CLR_FLAG = 0x0, I2C_DMA_FLUSH_FLAG = 0x1, + I2C_DMA_ASYNC_MODE = 0x0004, + I2C_DMA_SKIP_CONFIG = 0x0010, + I2C_DMA_DIR_CHANGE = 0x0200, }; enum { @@ -46,6 +49,11 @@ I2C_CONTROL_MASK = (0x3f << 1) }; +enum { + I2C_APDMA_NOASYNC = 0, + I2C_APDMA_ASYNC = 1, +}; + /* Register mask */ enum { I2C_HS_NACKERR = (1 << 2), @@ -80,6 +88,7 @@ struct mtk_i2c { struct mt_i2c_regs *i2c_regs; struct mt_i2c_dma_regs *i2c_dma_regs; + uint32_t mt_i2c_flag; }; extern struct mtk_i2c mtk_i2c_bus_controller[]; diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index d695824..04d57dc 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -5,6 +5,7 @@ bootblock-y += bootblock.c bootblock-y += flash_controller.c bootblock-y += ../common/gpio.c gpio.c +bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -19,6 +20,7 @@ verstage-y += auxadc.c verstage-y += flash_controller.c verstage-y += ../common/gpio.c gpio.c +verstage-y += ../common/i2c.c i2c.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c verstage-y += ../common/timer.c verstage-y += ../common/uart.c @@ -30,6 +32,7 @@ romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c +romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/mmu_operations.c romstage-y += memory.c dramc_param.c ../common/memory_test.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c @@ -41,6 +44,7 @@ ramstage-y += auxadc.c ramstage-y += flash_controller.c ramstage-y += ../common/gpio.c gpio.c +ramstage-y += ../common/i2c.c i2c.c ramstage-y += emi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c ramstage-y += dpm.c diff --git a/src/soc/mediatek/mt8192/i2c.c b/src/soc/mediatek/mt8192/i2c.c new file mode 100644 index 0000000..6b9c1ea --- /dev/null +++ b/src/soc/mediatek/mt8192/i2c.c @@ -0,0 +1,176 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <device/mmio.h> +#include <soc/pll.h> +#include <soc/i2c.h> +#include <soc/gpio.h> + +#define I2C_CLK_HZ (UNIVPLL_HZ / 20) +struct mtk_i2c mtk_i2c_bus_controller[] = { + /* i2c0 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x250000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c1 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x70000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x80), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c2 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x71000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x100), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c3 setting */ + { + .i2c_regs = (void *)(I2C_BASE), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x280), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c4 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x72000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x300), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c5 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x150000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x480), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c6 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x251000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x500), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c7 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x50000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x580), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c8 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x51000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x700), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, + + /* i2c9 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x52000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x880), + .mt_i2c_flag = I2C_APDMA_ASYNC, + }, +}; + +#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller) + +struct pad_func { + gpio_t gpio; + u8 func; +}; + +#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} + +static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = { + { + PAD_FUNC(SDA0, SDA0), + PAD_FUNC(SCL0, SCL0), + }, + { + PAD_FUNC(SDA1, SDA1), + PAD_FUNC(SCL1, SCL1), + }, + { + PAD_FUNC(SDA2, SDA2), + PAD_FUNC(SCL2, SCL2), + }, + { + PAD_FUNC(SDA3, SDA3), + PAD_FUNC(SCL3, SCL3), + }, + { + PAD_FUNC(SDA4, SDA4), + PAD_FUNC(SCL4, SCL4), + }, + { + PAD_FUNC(SDA5, SDA5), + PAD_FUNC(SCL5, SCL5), + }, + { + PAD_FUNC(SDA6, SDA6), + PAD_FUNC(SCL6, SCL6), + }, + { + PAD_FUNC(SDA7, SDA7), + PAD_FUNC(SCL7, SCL7), + }, + { + PAD_FUNC(SDA8, SDA8), + PAD_FUNC(SCL8, SCL8), + }, + { + PAD_FUNC(SDA9, SDA9), + PAD_FUNC(SCL9, SCL9), + }, +}; + +static void mtk_i2c_set_gpio_pinmux(uint8_t bus) +{ + assert(bus < I2C_BUS_NUMBER); + + const struct pad_func *ptr = i2c_funcs[bus]; + for (size_t i = 0; i < 2; i++) { + gpio_set_mode(ptr[i].gpio, ptr[i].func); + gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + } +} + +static void mtk_i2c_speed_init(uint8_t bus) +{ + uint8_t step_div; + const uint8_t clock_div = 5; + const uint8_t sample_div = 1; + uint32_t i2c_freq; + + assert(bus < ARRAY_SIZE(mtk_i2c_bus_controller)); + + /* Calculate i2c frequency */ + step_div = DIV_ROUND_UP(I2C_CLK_HZ, + (400 * KHz * sample_div * 2) * clock_div); + i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2 * clock_div); + assert(sample_div < 8 && step_div < 64 && i2c_freq <= 400 * KHz && + i2c_freq >= 380 * KHz); + + /* Init i2c bus Timing register */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->timing, + (sample_div - 1) << 8 | (step_div - 1)); + write32(&mtk_i2c_bus_controller[bus].i2c_regs->ltiming, + (sample_div - 1) << 6 | (step_div - 1)); + + /* Init i2c bus clock_div register */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->clock_div, + clock_div - 1); +} + +void mtk_i2c_bus_init(uint8_t bus) +{ + mtk_i2c_speed_init(bus); + mtk_i2c_set_gpio_pinmux(bus); +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index 85eac5b..3fd2bca 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -29,6 +29,7 @@ PMIF_SPMI_BASE = IO_PHYS + 0x00027000, PMICSPI_MST_BASE = IO_PHYS + 0x00028000, SPMI_MST_BASE = IO_PHYS + 0x00029000, + I2C_DMA_BASE = IO_PHYS + 0x00217080, EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, @@ -50,6 +51,7 @@ UFSHCI_BASE = IO_PHYS + 0x01270000, EFUSEC_BASE = IO_PHYS + 0x01C10000, IOCFG_RM_BASE = IO_PHYS + 0x01C20000, + I2C_BASE = IO_PHYS + 0x01CB0000, IOCFG_BM_BASE = IO_PHYS + 0x01D10000, IOCFG_BL_BASE = IO_PHYS + 0x01D30000, IOCFG_BR_BASE = IO_PHYS + 0x01D40000, diff --git a/src/soc/mediatek/mt8192/include/soc/i2c.h b/src/soc/mediatek/mt8192/include/soc/i2c.h new file mode 100644 index 0000000..72a9af1 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/i2c.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_I2C_H +#define SOC_MEDIATEK_MT8192_I2C_H + +#include <soc/i2c_common.h> + +/* I2C Register */ +struct mt_i2c_regs { + uint32_t data_port; + uint32_t slave_addr; + uint32_t intr_mask; + uint32_t intr_stat; + uint32_t control; + uint32_t transfer_len; + uint32_t transac_len; + uint32_t delay_len; + uint32_t timing; + uint32_t start; + uint32_t ext_conf; + uint32_t ltiming; + uint32_t hs; + uint32_t io_config; + uint32_t fifo_addr_clr; + uint32_t reserved0[2]; + uint32_t transfer_aux_len; + uint32_t clock_div; + uint32_t time_out; + uint32_t softreset; + uint32_t reserved1[36]; + uint32_t debug_stat; + uint32_t debug_ctrl; + uint32_t reserved2[2]; + uint32_t fifo_stat; + uint32_t fifo_thresh; + uint32_t reserved3[932]; + uint32_t multi_dma; + uint32_t reserved4[2]; + uint32_t rollback; +}; + +check_member(mt_i2c_regs, multi_dma, 0xf8c); + +void mtk_i2c_bus_init(uint8_t bus); + +#endif /* SOC_MEDIATEK_MT8192_I2C_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8ece265687d37bafe2f0de63459ea0fabab8a11 Gerrit-Change-Number: 46573 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: soc/intel/elkhartlake: Update Kconfig
by Lean Sheng Tan (Code Review) 02 Dec '20

02 Dec '20

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45078 ) Change subject: soc/intel/elkhartlake: Update Kconfig ...................................................................... soc/intel/elkhartlake: Update Kconfig Update Kconfig: 1. use FSP2.1 instead of 2.2 2. remove HECI_DISABLE_USING_SMM config 3. update CAR related stack & ram size 4. update FSP heap size 5. set IED region size = 0 as it is not used 6. update SMM TSEG size 7. update RP & I2c max device #s 8. update UART base address Signed-off-by: Tan, Lean Sheng <lean.sheng.tan(a)intel.com> Change-Id: I6a44d357d71be706f402a6b2a4f2d4e7c0eeb4a9 --- M src/soc/intel/elkhartlake/Kconfig 1 file changed, 11 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/45078/1 diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 166bda0..b5462ff 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -32,7 +32,7 @@ select PARALLEL_MP select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED - select PLATFORM_USES_FSP2_2 + select PLATFORM_USES_FSP2_1 select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select PMC_GLOBAL_RESET_ENABLE_LOCK @@ -61,29 +61,27 @@ select UDELAY_TSC select UDK_202005_BINDING select DISPLAY_FSP_VERSION_INFO - select HECI_DISABLE_USING_SMM config DCACHE_RAM_BASE default 0xfef00000 config DCACHE_RAM_SIZE - default 0x80000 + default 0xc0000 help The size of the cache-as-ram region required during bootblock and/or romstage. config DCACHE_BSP_STACK_SIZE hex - default 0x30400 + default 0x30000 help The amount of anticipated stack usage in CAR by bootblock and - other stages. In the case of FSP_USES_CB_STACK default value - will be sum of FSP-M stack requirement(192 KiB) and CB romstage - stack requirement(~1KiB). + other stages. In the case of FSP_USES_CB_STACK default value will be + sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). config FSP_TEMP_RAM_SIZE hex - default 0x20000 + default 0x40000 help The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know @@ -95,7 +93,7 @@ config IED_REGION_SIZE hex - default 0x400000 + default 0x0 config HEAP_SIZE hex @@ -103,7 +101,7 @@ config MAX_ROOT_PORTS int - default 8 + default 7 config MAX_PCIE_CLOCKS int @@ -111,7 +109,7 @@ config SMM_TSEG_SIZE hex - default 0x800000 + default 0x1000000 config SMM_RESERVED_SIZE hex @@ -145,7 +143,7 @@ config SOC_INTEL_I2C_DEV_MAX int - default 6 + default 8 config SOC_INTEL_UART_DEV_MAX int @@ -153,7 +151,7 @@ config CONSOLE_UART_BASE_ADDRESS hex - default 0xfe032000 + default 0xfe042000 depends on INTEL_LPSS_UART_FOR_CONSOLE # Clock divider parameters for 115200 baud rate -- To view, visit https://review.coreboot.org/c/coreboot/+/45078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a44d357d71be706f402a6b2a4f2d4e7c0eeb4a9 Gerrit-Change-Number: 45078 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: soc/intel/skylake: Map VBIOS IDs
by Paul Menzel (Code Review) 02 Dec '20

02 Dec '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43853 ) Change subject: soc/intel/skylake: Map VBIOS IDs ...................................................................... soc/intel/skylake: Map VBIOS IDs The extracted VBIOS Option ROM ships the same ID for several generations, not matching the ID on the hardware resulting in a mismatch, and coreboot does not run the Option ROM. PCI ROM image, vendor ID 8086, device ID 0406, ID mismatch: vendor ID 8086, device ID 5916 Add the appropriate mappings. TEST=coreboot runs the ROM on the TUXEDO Book BU1406. Change-Id: Ia167d91627a7ff1b329ea75f150b3ce95c0acccb Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M src/soc/intel/skylake/graphics.c 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/43853/1 diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 4ecf67a..f95ca6c 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -3,11 +3,13 @@ #include <commonlib/helpers.h> #include <console/console.h> #include <device/mmio.h> +#include <device/pci_rom.h> #include <device/resource.h> #include <drivers/intel/gma/i915.h> #include <drivers/intel/gma/i915_reg.h> #include <intelblocks/graphics.h> #include <soc/ramstage.h> +#include <soc/systemagent.h> #include <types.h> void graphics_soc_init(struct device *dev) @@ -76,3 +78,21 @@ struct soc_intel_skylake_config *chip = device->chip_info; return &chip->gfx; } + +/* + * Some VGA option roms are used for several chipsets but they only have one PCI ID in their + * header. If we encounter such an option rom, we need to do the mapping ourselves. + */ +u32 map_oprom_vendev(u32 vendev) +{ + u32 new_vendev = vendev; + + switch (vendev) { + case 0x80865916: /* PCI_DEVICE_ID_INTEL_KBL_GT2_SULTM */ + case 0x80865917: /* PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR */ + new_vendev = SA_IGD_OPROM_VENDEV; + break; + } + + return new_vendev; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/43853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia167d91627a7ff1b329ea75f150b3ce95c0acccb Gerrit-Change-Number: 43853 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: arch/x86/car.ld: Check for out of bound on no-XIP stages
by Arthur Heymans (Code Review) 02 Dec '20

02 Dec '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36623 ) Change subject: arch/x86/car.ld: Check for out of bound on no-XIP stages ...................................................................... arch/x86/car.ld: Check for out of bound on no-XIP stages Check that stages running in CAR have their start and end in CAR. Change-Id: I292aacce564c23d9ae21aa46c5e2f8784fa6a609 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/car.ld 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/36623/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 6ccbd8c..e68beb3 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -119,4 +119,9 @@ #endif #if CONFIG(C_ENVIRONMENT_BOOTBLOCK) _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured"); +#if CONFIG(NO_XIP_EARLY_STAGES) && (ENV_ROMSTAGE || ENV_VERSTAGE) +_bogus4 = ASSERT(_eprogram <= _car_region_end, "Stage end too high !"); +_bogus5 = ASSERT(_program >= _car_unallocated_start, "Stage start too low!"); +#endif + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/36623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I292aacce564c23d9ae21aa46c5e2f8784fa6a609 Gerrit-Change-Number: 36623 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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