coreboot-gerrit October 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/mediatek/mt8192: Implement dramc base settings for each frequency
by CK HU (Code Review) 29 Dec '20

29 Dec '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44707 to review the following change. Change subject: soc/mediatek/mt8192: Implement dramc base settings for each frequency ...................................................................... soc/mediatek/mt8192: Implement dramc base settings for each frequency Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I50d5aebaf249ab7292fad7a0046099239c8b403c --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c 1 file changed, 2,926 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/44707/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 21a5808..5ca000f 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -110,6 +110,2902 @@ set_dqO1_pinmux_mapping(cali); } +static void sv_algorithm_assistance_lp4_800(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rdsel_track, + SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 0x0e, + SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 0x1, + SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 0x0, + SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 0xff5, + SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 0x00b); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rdat, + MISC_SHU_RDAT_DATLAT, 0x0e, + MISC_SHU_RDAT_DATLAT_DSEL, 0x0e, + MISC_SHU_RDAT_DATLAT_DSEL_PHY, 0x0e); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl, + MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 0x1, + MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 0x2, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 0x1, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 0x0, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 0x1, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 0x0, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 0x3, + MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 0x1, + MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 0x1, + MISC_SHU_RANKCTL_RANKINCTL_STB, 0x4, + MISC_SHU_RANKCTL_RANKINCTL, 0x4, + MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 0x4, + MISC_SHU_RANKCTL_RANKINCTL_PHY, 0x6); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x4, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x4, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x4); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, 0x6); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, 0x6); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x6, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x8, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x0b); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x7, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x9, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x1f); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x6, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x8, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x0b); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x7, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x9, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x1f); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl, + MISC_SHU_ODTCTRL_RODTEN, 0x1, + MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 0x0, + MISC_SHU_ODTCTRL_RODT_LAT, 0x4, + MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 0x0, + MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 0x0, + MISC_SHU_ODTCTRL_FIXRODT, 0x0, + MISC_SHU_ODTCTRL_RODTEN_OPT, 0x1, + MISC_SHU_ODTCTRL_RODTE2, 0x1, + MISC_SHU_ODTCTRL_RODTE, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMRANKRXDVS_B0, 0x0, + SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 0x0, + SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0, + SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMRODTEN_B0, 0x1, + SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0, + SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 0x0, + SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMRANKRXDVS_B1, 0x0, + SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 0x0, + SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0, + SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMRODTEN_B1, 0x1, + SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0, + SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 0x0, + SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rx_pipe_ctrl, + SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x1, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x1, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x2, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x2, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x1, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x1, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x2, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x2, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_rx_cg_set0, + SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0x0, + SHU_RX_CG_SET0_READ_START_EXTEND3, 0x0, + SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 0x1, + SHU_RX_CG_SET0_READ_START_EXTEND2, 0x1, + SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 0x1, + SHU_RX_CG_SET0_READ_START_EXTEND1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rank_sel_stb, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 0x5, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqscal, + MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, + MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, + MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, + MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqscal, + MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, + MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, + MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, + MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_ini_uipi, + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x0b, + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x06); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_ini_uipi, + SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x0b, + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x06); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_ini_uipi, + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x1f, + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x07); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_ini_uipi, + SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x1f, + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x07); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_next_ini_uipi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x0b, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x06, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_next_ini_uipi, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x0b, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x06, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_next_ini_uipi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x1f, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x07, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x09); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_next_ini_uipi, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x1f, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x07, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x09); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x18, + SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x18, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, + SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, + SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x18, + SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x18, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, + SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, + SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x18, + SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x18, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, + SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, + SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x18, + SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x18, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, + SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, + SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_dcm_ctrl0, + SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 0x1, + SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 0x3, + SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 0x6, + SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 0x2, + SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 0x5, + SHU_DCM_CTRL0_FASTWAKE2, 0x0, + SHU_DCM_CTRL0_FASTWAKE, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_aphy_tx_picg_ctrl, + SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 0x3, + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 0x0, + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 0x3, + SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 0x2, + SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_aphy_tx_picg_ctrl, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x0, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_aphy_tx_picg_ctrl, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x0, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_new_xrw2w_ctrl, + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 0x2, + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 0x2, + SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs0, + SHU_SELPH_DQS0_TXDLY_DQS0, 0x4, + SHU_SELPH_DQS0_TXDLY_DQS1, 0x4, + SHU_SELPH_DQS0_TXDLY_DQS2, 0x1, + SHU_SELPH_DQS0_TXDLY_DQS3, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 0x3, + SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 0x3, + SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x3, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x3, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq1, + SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x3, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x3, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_DQ0, 0x1, + SHURK_SELPH_DQ2_DLY_DQ1, 0x1, + SHURK_SELPH_DQ2_DLY_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_DQ3, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x2, + SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x2, + SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq3, + SHURK_SELPH_DQ3_DLY_DQM0, 0x1, + SHURK_SELPH_DQ3_DLY_DQM1, 0x1, + SHURK_SELPH_DQ3_DLY_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_DQM3, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x2, + SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x2, + SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x3, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x3, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq1, + SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x3, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x3, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_DQ0, 0x1, + SHURK_SELPH_DQ2_DLY_DQ1, 0x1, + SHURK_SELPH_DQ2_DLY_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_DQ3, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x2, + SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x2, + SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq3, + SHURK_SELPH_DQ3_DLY_DQM0, 0x1, + SHURK_SELPH_DQ3_DLY_DQM1, 0x1, + SHURK_SELPH_DQ3_DLY_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_DQM3, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x2, + SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x2, + SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal1, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x018, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x018); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal2, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x018, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x018); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal5, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x018, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x018); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal1, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x018, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x018); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal2, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x018, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x018); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal5, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x018, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x018); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_pi, + SHURK_PI_RK0_ARPI_DQ_B1, 0x18, + SHURK_PI_RK0_ARPI_DQ_B0, 0x18, + SHURK_PI_RK0_ARPI_DQM_B1, 0x18, + SHURK_PI_RK0_ARPI_DQM_B0, 0x18); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_pi, + SHURK_PI_RK0_ARPI_DQ_B1, 0x18, + SHURK_PI_RK0_ARPI_DQ_B0, 0x18, + SHURK_PI_RK0_ARPI_DQM_B1, 0x18, + SHURK_PI_RK0_ARPI_DQM_B0, 0x18); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x30, + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x30, + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x30, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x30); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x30, + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x30, + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x30, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x30); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x30, + SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, + SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x0c, + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x0c, + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x0c, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x0c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x0c, + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x0c, + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x0c, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x0c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x0c, + SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, + SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x10, + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x10, + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x10, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x10); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x10, + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x10, + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x10, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x10); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x10, + SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, + SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x20, + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x20, + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x20, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x20); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x20, + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x20, + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x20, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x20); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x20, + SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, + SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_tx_rankctl, + SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, 0x1, + SHU_TX_RANKCTL_TXRANKINCTL, 0x1, + SHU_TX_RANKCTL_TXRANKINCTL_ROOT, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating0, + SHU_AC_DERATING0_ACDERATEEN, 0x1, + SHU_AC_DERATING0_TRRD_DERATE, 0x2, + SHU_AC_DERATING0_TRCD_DERATE, 0x4); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating1, + SHU_AC_DERATING1_TRPAB_DERATE, 0x3, + SHU_AC_DERATING1_TRP_DERATE, 0x2, + SHU_AC_DERATING1_TRAS_DERATE, 0x01, + SHU_AC_DERATING1_TRC_DERATE, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_sref_ctrl, + SHU_SREF_CTRL_CKEHCMD, 0x3, + SHU_SREF_CTRL_SREF_CK_DLY, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_hmr4_dvfs_ctrl0, + SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0x32, + SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x000); + SET32_BITFIELDS(&ch[0].ao.shu_actim_xrt, + SHU_ACTIM_XRT_XRTR2R, 0x05, + SHU_ACTIM_XRT_XRTR2W, 0x0a, + SHU_ACTIM_XRT_XRTW2R, 0x6, + SHU_ACTIM_XRT_XRTW2W, 0x09); + SET32_BITFIELDS(&ch[0].ao.shu_actim0, + SHU_ACTIM0_TWTR, 0x0a, + SHU_ACTIM0_TWR, 0x0c, + SHU_ACTIM0_TRRD, 0x1, + SHU_ACTIM0_TRCD, 0x4, + SHU_ACTIM0_CKELCKCNT, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_actim1, + SHU_ACTIM1_TRPAB, 0x3, + SHU_ACTIM1_TMRWCKEL, 0x7, + SHU_ACTIM1_TRP, 0x2, + SHU_ACTIM1_TRAS, 0x01, + SHU_ACTIM1_TRC, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_actim2, + SHU_ACTIM2_TXP, 0x0, + SHU_ACTIM2_TMRRI, 0x07, + SHU_ACTIM2_TRTP, 0x3, + SHU_ACTIM2_TR2W, 0x0a, + SHU_ACTIM2_TFAW, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_actim3, + SHU_ACTIM3_TRFCPB, 0x1a, + SHU_ACTIM3_MANTMRR, 0x8, + SHU_ACTIM3_TR2MRR, 0x8, + SHU_ACTIM3_TRFC, 0x40, + SHU_ACTIM3_TWTR_L, 0x25); + SET32_BITFIELDS(&ch[0].ao.shu_actim4, + SHU_ACTIM4_TXREFCNT, 0x04e, + SHU_ACTIM4_TMRR2MRW, 0x0f, + SHU_ACTIM4_TMRR2W, 0x0c, + SHU_ACTIM4_TZQCS, 0x10); + SET32_BITFIELDS(&ch[0].ao.shu_actim5, + SHU_ACTIM5_TR2PD, 0x10, + SHU_ACTIM5_TWTPD, 0x0f, + SHU_ACTIM5_TPBR2PBR, 0x15, + SHU_ACTIM5_TPBR2ACT, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_actim6, + SHU_ACTIM6_TZQLAT2, 0x06, + SHU_ACTIM6_TMRD, 0x6, + SHU_ACTIM6_TMRW, 0x5, + SHU_ACTIM6_TW2MRW, 0x0d, + SHU_ACTIM6_TR2MRW, 0x11); + SET32_BITFIELDS(&ch[0].ao.shu_ckectrl, + SHU_CKECTRL_TPDE_05T, 0x0, + SHU_CKECTRL_TPDX_05T, 0x0, + SHU_CKECTRL_TPDE, 0x3, + SHU_CKECTRL_TPDX, 0x3, + SHU_CKECTRL_TCKEPRD, 0x2, + SHU_CKECTRL_TCKESRX, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_misc, + SHU_MISC_REQQUE_MAXCNT, 0x2, + SHU_MISC_DCMDLYREF, 0x7, + SHU_MISC_DAREFEN, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq8, + SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 0x0031, + SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq8, + SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 0x0031, + SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq5, + SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 0x0e, + SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 0x0, + SHU_B0_DQ5_RG_ARPI_FB_B0, 0x00, + SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 0x0, + SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 0x0, + SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 0x7, + SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq5, + SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 0x0e, + SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 0x0, + SHU_B1_DQ5_RG_ARPI_FB_B1, 0x00, + SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 0x0, + SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 0x0, + SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 0x7, + SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly0, + SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x75, + SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x75, + SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x75, + SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly1, + SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x75, + SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x75, + SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x75, + SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly2, + SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x75, + SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x75, + SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x75, + SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly3, + SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x75, + SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x75, + SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x75, + SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly4, + SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x75, + SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly5, + SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x17e, + SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x17e); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly0, + SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x74, + SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x74, + SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x74, + SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly1, + SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x74, + SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x74, + SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x74, + SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly2, + SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x74, + SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x74, + SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x74, + SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly3, + SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x74, + SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x74, + SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x74, + SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly4, + SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x74, + SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly5, + SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x17d, + SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x17d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly0, + SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x75, + SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x75, + SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x75, + SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly1, + SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x75, + SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x75, + SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x75, + SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly2, + SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x75, + SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x75, + SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x75, + SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly3, + SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x75, + SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x75, + SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x75, + SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly4, + SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x75, + SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x75); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly5, + SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x17e, + SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x17e); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly0, + SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x74, + SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x74, + SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x74, + SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly1, + SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x74, + SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x74, + SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x74, + SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly2, + SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x74, + SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x74, + SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x74, + SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly3, + SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x74, + SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x74, + SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x74, + SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly4, + SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x74, + SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x74); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly5, + SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x17d, + SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x17d); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0x1, + B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0x0, + B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 0x0, + B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 0x1, + B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 0x0, + B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 0x00, + B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 0x0, + B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 0x0, + B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 0x0, + B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0x1, + B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0x0, + B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 0x0, + B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 0x1, + B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 0x0, + B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 0x00, + B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 0x0, + B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 0x0, + B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 0x0, + B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq4, + B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 0x03, + B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 0x03, + B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 0x35, + B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 0x35); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq4, + B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 0x03, + B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 0x03, + B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 0x35, + B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 0x35); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, + B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 0x0e, + B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 0x1, + B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, + B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 0x0e, + B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 0x1, + B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0x0); +} + +static void sv_algorithm_assistance_lp4_1600(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rdsel_track, + SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 0x09, + SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 0x1, + SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 0x0, + SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 0xfeb, + SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 0x015); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rdat, + MISC_SHU_RDAT_DATLAT, 0x09, + MISC_SHU_RDAT_DATLAT_DSEL, 0x09, + MISC_SHU_RDAT_DATLAT_DSEL_PHY, 0x09); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl, + MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 0x1, + MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 0x2, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 0x2, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 0x0, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 0x1, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 0x0, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 0x0, + MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 0x1, + MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 0x1, + MISC_SHU_RANKCTL_RANKINCTL_STB, 0x1, + MISC_SHU_RANKCTL_RANKINCTL, 0x0, + MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 0x0, + MISC_SHU_RANKCTL_RANKINCTL_PHY, 0x3); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x2, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x2, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x2); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, 0x2); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, 0x2); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x9, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0xd, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x0b); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0xc, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x11); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x9, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0xd, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x0b); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0xc, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x11); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl, + MISC_SHU_ODTCTRL_RODTEN, 0x1, + MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 0x0, + MISC_SHU_ODTCTRL_RODT_LAT, 0x1, + MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 0x0, + MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 0x0, + MISC_SHU_ODTCTRL_FIXRODT, 0x0, + MISC_SHU_ODTCTRL_RODTEN_OPT, 0x1, + MISC_SHU_ODTCTRL_RODTE2, 0x1, + MISC_SHU_ODTCTRL_RODTE, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMRANKRXDVS_B0, 0x0, + SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 0x0, + SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0, + SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 0x0, + SHU_B0_DQ7_R_DMRODTEN_B0, 0x1, + SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0, + SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 0x0, + SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMRANKRXDVS_B1, 0x0, + SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 0x0, + SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0, + SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMRODTEN_B1, 0x1, + SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0, + SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 0x0, + SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rx_pipe_ctrl, + SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x4, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x4, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x7, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x7, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x4, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x4, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x7, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x7, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_rx_cg_set0, + SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0x0, + SHU_RX_CG_SET0_READ_START_EXTEND3, 0x0, + SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 0x0, + SHU_RX_CG_SET0_READ_START_EXTEND2, 0x0, + SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 0x1, + SHU_RX_CG_SET0_READ_START_EXTEND1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rank_sel_stb, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqscal, + MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, + MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, + MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, + MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqscal, + MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, + MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, + MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, + MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_ini_uipi, + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x0b, + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x09); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_ini_uipi, + SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x0b, + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x09); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_ini_uipi, + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x11, + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x0c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_ini_uipi, + SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x11, + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x0c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_next_ini_uipi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x0b, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x09, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x0d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_next_ini_uipi, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x0b, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x09, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x0d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_next_ini_uipi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x11, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x0c, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x10); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_next_ini_uipi, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x11, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x0c, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x10); + SET32_BITFIELDS(&ch[0].phy_ao.ca_rk[0].shu_r0_ca_cmd0, + SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 0x0, + SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 0x0, + SHU_R0_CA_CMD0_RG_ARPI_CS, 0x00, + SHU_R0_CA_CMD0_RG_ARPI_CMD, 0x20, + SHU_R0_CA_CMD0_RG_ARPI_CLK, 0x00, + SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 0x0, + SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x19, + SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x19, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, + SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, + SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x1f, + SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x1f, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, + SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, + SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.ca_rk[1].shu_r0_ca_cmd0, + SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 0x0, + SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 0x0, + SHU_R0_CA_CMD0_RG_ARPI_CS, 0x00, + SHU_R0_CA_CMD0_RG_ARPI_CMD, 0x20, + SHU_R0_CA_CMD0_RG_ARPI_CLK, 0x00, + SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 0x0, + SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x13, + SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x13, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, + SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, + SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x12, + SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x12, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, + SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, + SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_dcm_ctrl0, + SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 0x1, + SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 0x3, + SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 0x5, + SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 0x2, + SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 0x4, + SHU_DCM_CTRL0_FASTWAKE2, 0x0, + SHU_DCM_CTRL0_FASTWAKE, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_aphy_tx_picg_ctrl, + SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 0x3, + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 0x1, + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 0x0, + SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 0x2, + SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_aphy_tx_picg_ctrl, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x1, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_aphy_tx_picg_ctrl, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x1, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_new_xrw2w_ctrl, + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 0x0, + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 0x0, + SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs0, + SHU_SELPH_DQS0_TXDLY_DQS0, 0x2, + SHU_SELPH_DQS0_TXDLY_DQS1, 0x2, + SHU_SELPH_DQS0_TXDLY_DQS2, 0x1, + SHU_SELPH_DQS0_TXDLY_DQS3, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs1, + SHU_SELPH_DQS1_DLY_DQS0, 0x1, + SHU_SELPH_DQS1_DLY_DQS1, 0x1, + SHU_SELPH_DQS1_DLY_DQS2, 0x1, + SHU_SELPH_DQS1_DLY_DQS3, 0x1, + SHU_SELPH_DQS1_DLY_OEN_DQS0, 0x6, + SHU_SELPH_DQS1_DLY_OEN_DQS1, 0x6, + SHU_SELPH_DQS1_DLY_OEN_DQS2, 0x1, + SHU_SELPH_DQS1_DLY_OEN_DQS3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_DQ0, 0x2, + SHURK_SELPH_DQ0_TXDLY_DQ1, 0x2, + SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq1, + SHURK_SELPH_DQ1_TXDLY_DQM0, 0x2, + SHURK_SELPH_DQ1_TXDLY_DQM1, 0x2, + SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_DQ0, 0x1, + SHURK_SELPH_DQ2_DLY_DQ1, 0x1, + SHURK_SELPH_DQ2_DLY_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_DQ3, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x6, + SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x6, + SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq3, + SHURK_SELPH_DQ3_DLY_DQM0, 0x1, + SHURK_SELPH_DQ3_DLY_DQM1, 0x1, + SHURK_SELPH_DQ3_DLY_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_DQM3, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x6, + SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x6, + SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_DQ0, 0x2, + SHURK_SELPH_DQ0_TXDLY_DQ1, 0x2, + SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq1, + SHURK_SELPH_DQ1_TXDLY_DQM0, 0x2, + SHURK_SELPH_DQ1_TXDLY_DQM1, 0x2, + SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_DQ0, 0x2, + SHURK_SELPH_DQ2_DLY_DQ1, 0x2, + SHURK_SELPH_DQ2_DLY_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_DQ3, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x7, + SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x7, + SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq3, + SHURK_SELPH_DQ3_DLY_DQM0, 0x2, + SHURK_SELPH_DQ3_DLY_DQM1, 0x2, + SHURK_SELPH_DQ3_DLY_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_DQM3, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x7, + SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x7, + SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal1, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x019, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x01f); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal2, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x019, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x01f); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal5, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x019, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x01f); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal1, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x013, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x012); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal2, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x013, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x012); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal5, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x013, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x012); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_pi, + SHURK_PI_RK0_ARPI_DQ_B1, 0x1f, + SHURK_PI_RK0_ARPI_DQ_B0, 0x19, + SHURK_PI_RK0_ARPI_DQM_B1, 0x1f, + SHURK_PI_RK0_ARPI_DQM_B0, 0x19); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_pi, + SHURK_PI_RK0_ARPI_DQ_B1, 0x12, + SHURK_PI_RK0_ARPI_DQ_B0, 0x13, + SHURK_PI_RK0_ARPI_DQM_B1, 0x12, + SHURK_PI_RK0_ARPI_DQM_B0, 0x13); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x3c, + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x3c, + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x3c, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x3c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x3c, + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x3c, + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x3c, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x3c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x3c, + SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, + SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x08, + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x08, + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x08, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x08, + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x08, + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x08, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x08, + SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, + SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating0, + SHU_AC_DERATING0_ACDERATEEN, 0x0, + SHU_AC_DERATING0_TRRD_DERATE, 0x1, + SHU_AC_DERATING0_TRCD_DERATE, 0x4); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating1, + SHU_AC_DERATING1_TRPAB_DERATE, 0x3, + SHU_AC_DERATING1_TRP_DERATE, 0x2, + SHU_AC_DERATING1_TRAS_DERATE, 0x00, + SHU_AC_DERATING1_TRC_DERATE, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating_05t, + SHU_AC_DERATING_05T_TRC_05T_DERATE, 0x0, + SHU_AC_DERATING_05T_TRCD_05T_DERATE, 0x0, + SHU_AC_DERATING_05T_TRP_05T_DERATE, 0x1, + SHU_AC_DERATING_05T_TRPAB_05T_DERATE, 0x1, + SHU_AC_DERATING_05T_TRAS_05T_DERATE, 0x1, + SHU_AC_DERATING_05T_TRRD_05T_DERATE, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_sref_ctrl, + SHU_SREF_CTRL_CKEHCMD, 0x3, + SHU_SREF_CTRL_SREF_CK_DLY, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_hmr4_dvfs_ctrl0, + SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0x32, + SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x000); + SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TRC_05T, 0x0, + SHU_AC_TIME_05T_TRFCPB_05T, 0x0, + SHU_AC_TIME_05T_TRFC_05T, 0x0, + SHU_AC_TIME_05T_TPBR2PBR_05T, 0x0, + SHU_AC_TIME_05T_TXP_05T, 0x0, + SHU_AC_TIME_05T_TRTP_05T, 0x1, + SHU_AC_TIME_05T_TRCD_05T, 0x0, + SHU_AC_TIME_05T_TRP_05T, 0x1, + SHU_AC_TIME_05T_TRPAB_05T, 0x0, + SHU_AC_TIME_05T_TRAS_05T, 0x0, + SHU_AC_TIME_05T_TWR_M05T, 0x1, + SHU_AC_TIME_05T_TRRD_05T, 0x0, + SHU_AC_TIME_05T_TFAW_05T, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TCKEPRD_05T, 0x0, + SHU_AC_TIME_05T_TR2PD_05T, 0x0, + SHU_AC_TIME_05T_TWTPD_M05T, 0x1, + SHU_AC_TIME_05T_TMRRI_05T, 0x1, + SHU_AC_TIME_05T_TMRWCKEL_05T, 0x0, + SHU_AC_TIME_05T_BGTRRD_05T, 0x0, + SHU_AC_TIME_05T_BGTCCD_05T, 0x0, + SHU_AC_TIME_05T_BGTWTR_M05T, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TR2W_05T, 0x0, + SHU_AC_TIME_05T_TWTR_M05T, 0x1, + SHU_AC_TIME_05T_XRTR2W_05T, 0x0, + SHU_AC_TIME_05T_TMRD_05T, 0x1, + SHU_AC_TIME_05T_TMRW_05T, 0x1, + SHU_AC_TIME_05T_TMRR2MRW_05T, 0x1, + SHU_AC_TIME_05T_TW2MRW_05T, 0x1, + SHU_AC_TIME_05T_TR2MRW_05T, 0x0, + SHU_AC_TIME_05T_TPBR2ACT_05T, 0x1, + SHU_AC_TIME_05T_XRTW2R_M05T, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_actim_xrt, + SHU_ACTIM_XRT_XRTR2R, 0x03, + SHU_ACTIM_XRT_XRTR2W, 0x03, + SHU_ACTIM_XRT_XRTW2R, 0x3, + SHU_ACTIM_XRT_XRTW2W, 0x04); + SET32_BITFIELDS(&ch[0].ao.shu_actim0, + SHU_ACTIM0_TWTR, 0x04, + SHU_ACTIM0_TWR, 0x07, + SHU_ACTIM0_TRRD, 0x1, + SHU_ACTIM0_TRCD, 0x4, + SHU_ACTIM0_CKELCKCNT, 0x2); + SET32_BITFIELDS(&ch[0].ao.shu_actim1, + SHU_ACTIM1_TRPAB, 0x3, + SHU_ACTIM1_TMRWCKEL, 0x4, + SHU_ACTIM1_TRP, 0x2, + SHU_ACTIM1_TRAS, 0x00, + SHU_ACTIM1_TRC, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_actim2, + SHU_ACTIM2_TXP, 0x0, + SHU_ACTIM2_TMRRI, 0x05, + SHU_ACTIM2_TRTP, 0x0, + SHU_ACTIM2_TR2W, 0x03, + SHU_ACTIM2_TFAW, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_actim3, + SHU_ACTIM3_TRFCPB, 0x1a, + SHU_ACTIM3_MANTMRR, 0x4, + SHU_ACTIM3_TR2MRR, 0x4, + SHU_ACTIM3_TRFC, 0x40, + SHU_ACTIM3_TWTR_L, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_actim4, + SHU_ACTIM4_TXREFCNT, 0x04e, + SHU_ACTIM4_TMRR2MRW, 0x07, + SHU_ACTIM4_TMRR2W, 0x05, + SHU_ACTIM4_TZQCS, 0x10); + SET32_BITFIELDS(&ch[0].ao.shu_actim5, + SHU_ACTIM5_TR2PD, 0x08, + SHU_ACTIM5_TWTPD, 0x09, + SHU_ACTIM5_TPBR2PBR, 0x0b, + SHU_ACTIM5_TPBR2ACT, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_actim6, + SHU_ACTIM6_TZQLAT2, 0x06, + SHU_ACTIM6_TMRD, 0x3, + SHU_ACTIM6_TMRW, 0x2, + SHU_ACTIM6_TW2MRW, 0x06, + SHU_ACTIM6_TR2MRW, 0x09); + SET32_BITFIELDS(&ch[0].ao.shu_ckectrl, + SHU_CKECTRL_TPDE_05T, 0x1, + SHU_CKECTRL_TPDX_05T, 0x0, + SHU_CKECTRL_TPDE, 0x1, + SHU_CKECTRL_TPDX, 0x1, + SHU_CKECTRL_TCKEPRD, 0x1, + SHU_CKECTRL_TCKESRX, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_misc, + SHU_MISC_REQQUE_MAXCNT, 0x2, + SHU_MISC_DCMDLYREF, 0x7, + SHU_MISC_DAREFEN, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq8, + SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 0x0063, + SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq8, + SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 0x0063, + SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq5, + SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 0x0e, + SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 0x0, + SHU_B0_DQ5_RG_ARPI_FB_B0, 0x00, + SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 0x0, + SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 0x0, + SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 0x5, + SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq5, + SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 0x0e, + SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 0x0, + SHU_B1_DQ5_RG_ARPI_FB_B1, 0x00, + SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 0x0, + SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 0x0, + SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 0x5, + SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly0, + SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x64, + SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x64, + SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x64, + SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly1, + SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x64, + SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x64, + SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x64, + SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly2, + SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x64, + SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x64, + SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x64, + SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly3, + SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x64, + SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x64, + SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x64, + SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly4, + SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x64, + SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly5, + SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x0da, + SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x0da); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly0, + SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x63, + SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x63, + SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x63, + SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly1, + SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x63, + SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x63, + SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x63, + SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly2, + SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x63, + SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x63, + SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x63, + SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly3, + SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x63, + SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x63, + SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x63, + SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly4, + SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x63, + SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly5, + SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x0d9, + SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x0d9); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly0, + SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x64, + SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x64, + SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x64, + SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly1, + SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x64, + SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x64, + SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x64, + SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly2, + SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x64, + SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x64, + SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x64, + SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly3, + SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x64, + SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x64, + SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x64, + SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly4, + SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x64, + SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x64); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly5, + SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x0da, + SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x0da); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly0, + SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x63, + SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x63, + SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x63, + SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly1, + SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x63, + SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x63, + SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x63, + SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly2, + SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x63, + SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x63, + SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x63, + SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly3, + SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x63, + SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x63, + SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x63, + SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly4, + SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x63, + SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x63); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly5, + SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x0d9, + SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x0d9); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0x1, + B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0x0, + B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 0x0, + B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 0x1, + B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 0x0, + B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 0x00, + B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 0x0, + B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 0x0, + B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 0x0, + B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0x1, + B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0x0, + B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 0x0, + B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 0x1, + B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 0x0, + B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 0x00, + B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 0x0, + B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 0x0, + B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 0x0, + B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq4, + B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 0x6e, + B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 0x6e, + B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 0x24, + B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 0x24); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq4, + B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 0x6e, + B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 0x6e, + B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 0x24, + B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 0x24); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, + B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 0x0e, + B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 0x1, + B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, + B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 0x0e, + B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 0x1, + B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0x0); +} + +static void sv_algorithm_assistance_lp4_3733(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rdsel_track, + SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 0x0f, + SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 0x1, + SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 0x0, + SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 0xfd0, + SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 0x030); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rdat, + MISC_SHU_RDAT_DATLAT, 0x0f, + MISC_SHU_RDAT_DATLAT_DSEL, 0x0f, + MISC_SHU_RDAT_DATLAT_DSEL_PHY, 0x0f); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl, + MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 0x1, + MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 0x2, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 0x2, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 0x1, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 0x1, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 0x2, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 0x4, + MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 0x1, + MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 0x1, + MISC_SHU_RANKCTL_RANKINCTL_STB, 0x6, + MISC_SHU_RANKCTL_RANKINCTL, 0x5, + MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 0x5, + MISC_SHU_RANKCTL_RANKINCTL_PHY, 0x8); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x2, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x2, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x2); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, 0x7); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, 0x7); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x0, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x4, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x1, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x0f); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x7, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0xb, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x1, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x1c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x0, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x4, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x1, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x0f); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x7, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0xb, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x1, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x1c); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl, + MISC_SHU_ODTCTRL_RODTEN, 0x1, + MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 0x0, + MISC_SHU_ODTCTRL_RODT_LAT, 0x7, + MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 0x0, + MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 0x0, + MISC_SHU_ODTCTRL_FIXRODT, 0x0, + MISC_SHU_ODTCTRL_RODTEN_OPT, 0x1, + MISC_SHU_ODTCTRL_RODTE2, 0x1, + MISC_SHU_ODTCTRL_RODTE, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMRANKRXDVS_B0, 0x0, + SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 0x0, + SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0, + SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMRODTEN_B0, 0x1, + SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0, + SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 0x0, + SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMRANKRXDVS_B1, 0x0, + SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 0x0, + SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0, + SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMRODTEN_B1, 0x1, + SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0, + SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 0x0, + SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rx_pipe_ctrl, + SHU_MISC_RX_PIPE_CTRL_RX_PIPE_BYPASS_EN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x3, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x3, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x2, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x2, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x1, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x3, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x3, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x2, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x2, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x1, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_rx_cg_set0, + SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0x0, + SHU_RX_CG_SET0_READ_START_EXTEND3, 0x0, + SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 0x1, + SHU_RX_CG_SET0_READ_START_EXTEND2, 0x1, + SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 0x1, + SHU_RX_CG_SET0_READ_START_EXTEND1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rank_sel_stb, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 0x6, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 0x2, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqscal, + MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, + MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, + MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, + MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqscal, + MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, + MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, + MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, + MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_ini_uipi, + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x0f, + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x10); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_ini_uipi, + SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x0f, + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x10); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_ini_uipi, + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x1c, + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x17); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_ini_uipi, + SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x1c, + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x17); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_next_ini_uipi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x0f, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x10, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x14); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_next_ini_uipi, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x0f, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x10, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x14); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_next_ini_uipi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x1c, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x17, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x1b); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_next_ini_uipi, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x1c, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x17, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x1b); + SET32_BITFIELDS(&ch[0].phy_ao.ca_rk[0].shu_r0_ca_cmd0, + SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 0x0, + SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 0x0, + SHU_R0_CA_CMD0_RG_ARPI_CS, 0x00, + SHU_R0_CA_CMD0_RG_ARPI_CMD, 0x20, + SHU_R0_CA_CMD0_RG_ARPI_CLK, 0x00, + SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 0x0, + SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x11, + SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x11, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, + SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, + SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x12, + SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x12, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, + SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, + SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.ca_rk[1].shu_r0_ca_cmd0, + SHU_R0_CA_CMD0_RG_RX_ARCLK_R_DLY_DUTY, 0x0, + SHU_R0_CA_CMD0_RG_RX_ARCLK_F_DLY_DUTY, 0x0, + SHU_R0_CA_CMD0_RG_ARPI_CS, 0x00, + SHU_R0_CA_CMD0_RG_ARPI_CMD, 0x20, + SHU_R0_CA_CMD0_RG_ARPI_CLK, 0x00, + SHU_R0_CA_CMD0_DA_ARPI_DDR400_0D5UI_RK0_CA, 0x0, + SHU_R0_CA_CMD0_DA_RX_ARDQSIEN_0D5UI_RK0_CA, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x16, + SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x16, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, + SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, + SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x21, + SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x21, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, + SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, + SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_dcm_ctrl0, + SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 0x1, + SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 0x3, + SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 0x5, + SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 0x2, + SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 0x4, + SHU_DCM_CTRL0_FASTWAKE2, 0x0, + SHU_DCM_CTRL0_FASTWAKE, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_aphy_tx_picg_ctrl, + SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 0x3, + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 0x3, + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 0x2, + SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 0x2, + SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_aphy_tx_picg_ctrl, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x3, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_aphy_tx_picg_ctrl, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x3, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_new_xrw2w_ctrl, + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 0x3, + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 0x3, + SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs0, + SHU_SELPH_DQS0_TXDLY_DQS0, 0x4, + SHU_SELPH_DQS0_TXDLY_DQS1, 0x4, + SHU_SELPH_DQS0_TXDLY_DQS2, 0x1, + SHU_SELPH_DQS0_TXDLY_DQS3, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 0x3, + SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 0x3, + SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs1, + SHU_SELPH_DQS1_DLY_DQS0, 0x1, + SHU_SELPH_DQS1_DLY_DQS1, 0x1, + SHU_SELPH_DQS1_DLY_DQS2, 0x1, + SHU_SELPH_DQS1_DLY_DQS3, 0x1, + SHU_SELPH_DQS1_DLY_OEN_DQS0, 0x6, + SHU_SELPH_DQS1_DLY_OEN_DQS1, 0x6, + SHU_SELPH_DQS1_DLY_OEN_DQS2, 0x1, + SHU_SELPH_DQS1_DLY_OEN_DQS3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x3, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x3, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq1, + SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x3, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x3, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_DQ0, 0x2, + SHURK_SELPH_DQ2_DLY_DQ1, 0x2, + SHURK_SELPH_DQ2_DLY_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_DQ3, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x7, + SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x7, + SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq3, + SHURK_SELPH_DQ3_DLY_DQM0, 0x2, + SHURK_SELPH_DQ3_DLY_DQM1, 0x2, + SHURK_SELPH_DQ3_DLY_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_DQM3, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x7, + SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x7, + SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x4, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x4, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq1, + SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x4, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x4, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_DQ0, 0x3, + SHURK_SELPH_DQ2_DLY_DQ1, 0x3, + SHURK_SELPH_DQ2_DLY_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_DQ3, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x0, + SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x0, + SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq3, + SHURK_SELPH_DQ3_DLY_DQM0, 0x3, + SHURK_SELPH_DQ3_DLY_DQM1, 0x3, + SHURK_SELPH_DQ3_DLY_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_DQM3, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x0, + SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x0, + SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal1, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x011, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x012); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal2, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x011, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x012); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal5, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x011, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x012); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal1, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x016, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x021); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal2, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x016, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x021); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal5, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x016, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x021); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_pi, + SHURK_PI_RK0_ARPI_DQ_B1, 0x12, + SHURK_PI_RK0_ARPI_DQ_B0, 0x11, + SHURK_PI_RK0_ARPI_DQM_B1, 0x12, + SHURK_PI_RK0_ARPI_DQM_B0, 0x11); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_pi, + SHURK_PI_RK0_ARPI_DQ_B1, 0x21, + SHURK_PI_RK0_ARPI_DQ_B0, 0x16, + SHURK_PI_RK0_ARPI_DQM_B1, 0x21, + SHURK_PI_RK0_ARPI_DQM_B0, 0x16); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x08, + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x08, + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x08, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x08, + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x08, + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x08, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x08, + SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, + SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x04, + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x04, + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x04, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x04); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x04, + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x04, + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x04, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x04); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x04, + SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, + SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x34, + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x34, + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x34, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x34); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x34, + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x34, + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x34, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x34); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x34, + SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, + SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x08, + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x08, + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x08, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x08, + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x08, + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x08, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x08, + SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, + SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_tx_rankctl, + SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, 0x2, + SHU_TX_RANKCTL_TXRANKINCTL, 0x2, + SHU_TX_RANKCTL_TXRANKINCTL_ROOT, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating0, + SHU_AC_DERATING0_ACDERATEEN, 0x0, + SHU_AC_DERATING0_TRRD_DERATE, 0x5, + SHU_AC_DERATING0_TRCD_DERATE, 0x9); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating1, + SHU_AC_DERATING1_TRPAB_DERATE, 0x9, + SHU_AC_DERATING1_TRP_DERATE, 0x8, + SHU_AC_DERATING1_TRAS_DERATE, 0x0c, + SHU_AC_DERATING1_TRC_DERATE, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating_05t, + SHU_AC_DERATING_05T_TRC_05T_DERATE, 0x0, + SHU_AC_DERATING_05T_TRCD_05T_DERATE, 0x1, + SHU_AC_DERATING_05T_TRP_05T_DERATE, 0x0, + SHU_AC_DERATING_05T_TRPAB_05T_DERATE, 0x1, + SHU_AC_DERATING_05T_TRAS_05T_DERATE, 0x0, + SHU_AC_DERATING_05T_TRRD_05T_DERATE, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_sref_ctrl, + SHU_SREF_CTRL_CKEHCMD, 0x3, + SHU_SREF_CTRL_SREF_CK_DLY, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_hmr4_dvfs_ctrl0, + SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0x75, + SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x000); + SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TRC_05T, 0x0, + SHU_AC_TIME_05T_TRFCPB_05T, 0x0, + SHU_AC_TIME_05T_TRFC_05T, 0x1, + SHU_AC_TIME_05T_TPBR2PBR_05T, 0x0, + SHU_AC_TIME_05T_TXP_05T, 0x1, + SHU_AC_TIME_05T_TRTP_05T, 0x0, + SHU_AC_TIME_05T_TRCD_05T, 0x1, + SHU_AC_TIME_05T_TRP_05T, 0x0, + SHU_AC_TIME_05T_TRPAB_05T, 0x1, + SHU_AC_TIME_05T_TRAS_05T, 0x1, + SHU_AC_TIME_05T_TWR_M05T, 0x1, + SHU_AC_TIME_05T_TRRD_05T, 0x0, + SHU_AC_TIME_05T_TFAW_05T, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TCKEPRD_05T, 0x0, + SHU_AC_TIME_05T_TR2PD_05T, 0x0, + SHU_AC_TIME_05T_TWTPD_M05T, 0x1, + SHU_AC_TIME_05T_TMRRI_05T, 0x0, + SHU_AC_TIME_05T_TMRWCKEL_05T, 0x0, + SHU_AC_TIME_05T_BGTRRD_05T, 0x0, + SHU_AC_TIME_05T_BGTCCD_05T, 0x0, + SHU_AC_TIME_05T_BGTWTR_M05T, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TR2W_05T, 0x0, + SHU_AC_TIME_05T_TWTR_M05T, 0x0, + SHU_AC_TIME_05T_XRTR2W_05T, 0x0, + SHU_AC_TIME_05T_TMRD_05T, 0x1, + SHU_AC_TIME_05T_TMRW_05T, 0x0, + SHU_AC_TIME_05T_TMRR2MRW_05T, 0x1, + SHU_AC_TIME_05T_TW2MRW_05T, 0x0, + SHU_AC_TIME_05T_TR2MRW_05T, 0x1, + SHU_AC_TIME_05T_TPBR2ACT_05T, 0x1, + SHU_AC_TIME_05T_XRTW2R_M05T, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_actim_xrt, + SHU_ACTIM_XRT_XRTR2R, 0x03, + SHU_ACTIM_XRT_XRTR2W, 0x08, + SHU_ACTIM_XRT_XRTW2R, 0x1, + SHU_ACTIM_XRT_XRTW2W, 0x05); + SET32_BITFIELDS(&ch[0].ao.shu_actim0, + SHU_ACTIM0_TWTR, 0x08, + SHU_ACTIM0_TWR, 0x0d, + SHU_ACTIM0_TRRD, 0x4, + SHU_ACTIM0_TRCD, 0x8, + SHU_ACTIM0_CKELCKCNT, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_actim1, + SHU_ACTIM1_TRPAB, 0x8, + SHU_ACTIM1_TMRWCKEL, 0x8, + SHU_ACTIM1_TRP, 0x7, + SHU_ACTIM1_TRAS, 0x0b, + SHU_ACTIM1_TRC, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_actim2, + SHU_ACTIM2_TXP, 0x0, + SHU_ACTIM2_TMRRI, 0x0c, + SHU_ACTIM2_TRTP, 0x2, + SHU_ACTIM2_TR2W, 0x09, + SHU_ACTIM2_TFAW, 0x0b); + SET32_BITFIELDS(&ch[0].ao.shu_actim3, + SHU_ACTIM3_TRFCPB, 0x4d, + SHU_ACTIM3_MANTMRR, 0x4, + SHU_ACTIM3_TR2MRR, 0x4, + SHU_ACTIM3_TRFC, 0xa5, + SHU_ACTIM3_TWTR_L, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_actim4, + SHU_ACTIM4_TXREFCNT, 0x0b5, + SHU_ACTIM4_TMRR2MRW, 0x0d, + SHU_ACTIM4_TMRR2W, 0x0c, + SHU_ACTIM4_TZQCS, 0x28); + SET32_BITFIELDS(&ch[0].ao.shu_actim5, + SHU_ACTIM5_TR2PD, 0x0e, + SHU_ACTIM5_TWTPD, 0x10, + SHU_ACTIM5_TPBR2PBR, 0x23, + SHU_ACTIM5_TPBR2ACT, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_actim6, + SHU_ACTIM6_TZQLAT2, 0x0e, + SHU_ACTIM6_TMRD, 0x7, + SHU_ACTIM6_TMRW, 0x5, + SHU_ACTIM6_TW2MRW, 0x0a, + SHU_ACTIM6_TR2MRW, 0x10); + SET32_BITFIELDS(&ch[0].ao.shu_ckectrl, + SHU_CKECTRL_TPDE_05T, 0x1, + SHU_CKECTRL_TPDX_05T, 0x0, + SHU_CKECTRL_TPDE, 0x1, + SHU_CKECTRL_TPDX, 0x1, + SHU_CKECTRL_TCKEPRD, 0x3, + SHU_CKECTRL_TCKESRX, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_misc, + SHU_MISC_REQQUE_MAXCNT, 0x2, + SHU_MISC_DCMDLYREF, 0x7, + SHU_MISC_DAREFEN, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq8, + SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 0x00e7, + SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq8, + SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 0x00e7, + SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq5, + SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 0x0e, + SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 0x0, + SHU_B0_DQ5_RG_ARPI_FB_B0, 0x00, + SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 0x0, + SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 0x0, + SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 0x4, + SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq5, + SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 0x0e, + SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 0x0, + SHU_B1_DQ5_RG_ARPI_FB_B1, 0x00, + SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 0x0, + SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 0x0, + SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 0x4, + SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly0, + SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly1, + SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly2, + SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly3, + SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly4, + SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x6d, + SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly5, + SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x061, + SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x061); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly0, + SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly1, + SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly2, + SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly3, + SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly4, + SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x6c, + SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly5, + SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x060, + SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x060); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly0, + SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly1, + SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly2, + SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly3, + SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly4, + SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x6d, + SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x6d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly5, + SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x061, + SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x061); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly0, + SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly1, + SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly2, + SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly3, + SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly4, + SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0x6c, + SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0x6c); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly5, + SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x060, + SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x060); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0x1, + B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0x0, + B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 0x0, + B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 0x1, + B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 0x0, + B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 0x00, + B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 0x0, + B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 0x0, + B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 0x0, + B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0x1, + B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0x0, + B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 0x0, + B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 0x1, + B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 0x0, + B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 0x00, + B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 0x0, + B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 0x0, + B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 0x0, + B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq4, + B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 0x75, + B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 0x75, + B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 0x2d, + B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 0x2d); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq4, + B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 0x75, + B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 0x75, + B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 0x2d, + B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 0x2d); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, + B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 0x0e, + B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 0x1, + B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, + B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 0x0e, + B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 0x1, + B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0x0); +} + +static void sv_algorithm_assistance_lp4_4266(void) +{ + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rdsel_track, + SHU_MISC_RDSEL_TRACK_DMDATLAT_I, 0x10, + SHU_MISC_RDSEL_TRACK_RDSEL_HWSAVE_MSK, 0x1, + SHU_MISC_RDSEL_TRACK_RDSEL_TRACK_EN, 0x0, + SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_NEG, 0xfcb, + SHU_MISC_RDSEL_TRACK_SHU_GW_THRD_POS, 0x035); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rdat, + MISC_SHU_RDAT_DATLAT, 0x10, + MISC_SHU_RDAT_DATLAT_DSEL, 0x0f, + MISC_SHU_RDAT_DATLAT_DSEL_PHY, 0x0f); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_phy_rx_ctrl, + MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPDLAT_EN, 0x1, + MISC_SHU_PHY_RX_CTRL_RANK_RXDLY_UPD_OFFSET, 0x2, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_PRE_OFFSET, 0x2, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_HEAD, 0x1, + MISC_SHU_PHY_RX_CTRL_RX_IN_GATE_EN_TAIL, 0x1, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_HEAD, 0x2, + MISC_SHU_PHY_RX_CTRL_RX_IN_BUFF_EN_TAIL, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rankctl, + MISC_SHU_RANKCTL_RANKINCTL_RXDLY, 0x4, + MISC_SHU_RANKCTL_RANK_RXDLY_OPT, 0x1, + MISC_SHU_RANKCTL_RANKSEL_SELPH_FRUN, 0x1, + MISC_SHU_RANKCTL_RANKINCTL_STB, 0x6, + MISC_SHU_RANKCTL_RANKINCTL, 0x5, + MISC_SHU_RANKCTL_RANKINCTL_ROOT1, 0x5, + MISC_SHU_RANKCTL_RANKINCTL_PHY, 0x8); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_rank_sel_lat, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B0, 0x2, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_B1, 0x2, + MISC_SHU_RANK_SEL_LAT_RANK_SEL_LAT_CA, 0x2); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, 0x7); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqsctl, + MISC_SHU_RK_DQSCTL_DQSINCTL, 0x7); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x1, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0x5, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x1, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x01); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_dqsien_mck_ui_dly, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B0, 0x9, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B0, 0xd, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B0, 0x1, + SHU_RK_B0_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B0, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B0_DQSIEN_PI_DLY_DQSIEN_PI_B0, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x1, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0x5, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x1, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x01); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_dqsien_mck_ui_dly, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P0_B1, 0x9, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_UI_P1_B1, 0xd, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P0_B1, 0x1, + SHU_RK_B1_DQSIEN_MCK_UI_DLY_DQSIEN_MCK_P1_B1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_dqsien_pi_dly, + SHU_RK_B1_DQSIEN_PI_DLY_DQSIEN_PI_B1, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.misc_shu_odtctrl, + MISC_SHU_ODTCTRL_RODTEN, 0x1, + MISC_SHU_ODTCTRL_RODTENSTB_SELPH_CG_IG, 0x0, + MISC_SHU_ODTCTRL_RODT_LAT, 0x7, + MISC_SHU_ODTCTRL_RODTEN_SELPH_FRUN, 0x0, + MISC_SHU_ODTCTRL_RODTDLY_LAT_OPT, 0x0, + MISC_SHU_ODTCTRL_FIXRODT, 0x0, + MISC_SHU_ODTCTRL_RODTEN_OPT, 0x1, + MISC_SHU_ODTCTRL_RODTE2, 0x1, + MISC_SHU_ODTCTRL_RODTE, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMRANKRXDVS_B0, 0x0, + SHU_B0_DQ7_R_DMDQMDBI_EYE_SHU_B0, 0x0, + SHU_B0_DQ7_R_DMDQMDBI_SHU_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_DQM_FLAGSEL_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B0, 0x0, + SHU_B0_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B0, 0x0, + SHU_B0_DQ7_R_DMRXTRACK_DQM_EN_B0, 0x0, + SHU_B0_DQ7_R_DMRODTEN_B0, 0x1, + SHU_B0_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq7, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B0, 0x0, + SHU_B0_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B0, 0x0, + SHU_B0_DQ7_R_LP4Y_SDN_MODE_DQS0, 0x0, + SHU_B0_DQ7_R_DMRXRANK_DQ_EN_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQ_LAT_B0, 0x2, + SHU_B0_DQ7_R_DMRXRANK_DQS_EN_B0, 0x1, + SHU_B0_DQ7_R_DMRXRANK_DQS_LAT_B0, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMRANKRXDVS_B1, 0x0, + SHU_B1_DQ7_R_DMDQMDBI_EYE_SHU_B1, 0x0, + SHU_B1_DQ7_R_DMDQMDBI_SHU_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_DQM_FLAGSEL_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_FLAG_OPT_B1, 0x0, + SHU_B1_DQ7_R_DMRXDVS_PBYTE_DQM_EN_B1, 0x0, + SHU_B1_DQ7_R_DMRXTRACK_DQM_EN_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq7, + SHU_B1_DQ7_R_DMRODTEN_B1, 0x1, + SHU_B1_DQ7_R_DMARPI_CG_FB2DLL_DCM_EN_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQ_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQS_NEW_B1, 0x0, + SHU_B1_DQ7_R_DMTX_ARPI_CG_DQM_NEW_B1, 0x0, + SHU_B1_DQ7_R_LP4Y_SDN_MODE_DQS1, 0x0, + SHU_B1_DQ7_R_DMRXRANK_DQ_EN_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQ_LAT_B1, 0x2, + SHU_B1_DQ7_R_DMRXRANK_DQS_EN_B1, 0x1, + SHU_B1_DQ7_R_DMRXRANK_DQS_LAT_B1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x4, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x4, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x0, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B0, 0x4, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B0, 0x4, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B0, 0x1, + SHU_RK_B0_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x4, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x4, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x0, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_rk_b0_rodten_mck_ui_dly, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P0_B1, 0x4, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_UI_P1_B1, 0x4, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P0_B1, 0x1, + SHU_RK_B1_RODTEN_MCK_UI_DLY_RODTEN_MCK_P1_B1, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_rx_cg_set0, + SHU_RX_CG_SET0_DLE_LAST_EXTEND3, 0x0, + SHU_RX_CG_SET0_READ_START_EXTEND3, 0x0, + SHU_RX_CG_SET0_DLE_LAST_EXTEND2, 0x1, + SHU_RX_CG_SET0_READ_START_EXTEND2, 0x1, + SHU_RX_CG_SET0_DLE_LAST_EXTEND1, 0x1, + SHU_RX_CG_SET0_READ_START_EXTEND1, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.shu_misc_rank_sel_stb, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_EN_B23, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_SERMODE, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_TRACK, 0x1, + SHU_MISC_RANK_SEL_STB_RANK_SEL_RXDLY_TRACK, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_PHASE_EN, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_PHSINCTL, 0x6, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_PLUS, 0x0, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_UI_MINUS, 0x2, + SHU_MISC_RANK_SEL_STB_RANK_SEL_STB_MCK_MINUS, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[0].misc_shu_rk_dqscal, + MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, + MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, + MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, + MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.misc_rk[1].misc_shu_rk_dqscal, + MISC_SHU_RK_DQSCAL_DQSIENLLMT, 0x60, + MISC_SHU_RK_DQSCAL_DQSIENLLMTEN, 0x1, + MISC_SHU_RK_DQSCAL_DQSIENHLMT, 0x3f, + MISC_SHU_RK_DQSCAL_DQSIENHLMTEN, 0x1); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_ini_uipi, + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x01, + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x11); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_ini_uipi, + SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x01, + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x11); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_ini_uipi, + SHU_R0_B0_INI_UIPI_CURR_INI_PI_B0, 0x08, + SHU_R0_B0_INI_UIPI_CURR_INI_UI_B0, 0x19); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_ini_uipi, + SHU_R0_B1_INI_UIPI_CURR_INI_PI_B1, 0x08, + SHU_R0_B1_INI_UIPI_CURR_INI_UI_B1, 0x19); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_next_ini_uipi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x01, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x11, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x15); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_next_ini_uipi, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x01, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x11, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x15); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_next_ini_uipi, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_PI_B0, 0x08, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_B0, 0x19, + SHU_R0_B0_NEXT_INI_UIPI_NEXT_INI_UI_P1_B0, 0x1d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_next_ini_uipi, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_PI_B1, 0x08, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_B1, 0x19, + SHU_R0_B1_NEXT_INI_UIPI_NEXT_INI_UI_P1_B1, 0x1d); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x13, + SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x13, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x00, + SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, + SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x16, + SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x16, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x00, + SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, + SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_dq0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_R_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_RG_RX_ARDQS0_F_DLY_DUTY, 0x0, + SHU_R0_B0_DQ0_SW_ARPI_DQ_B0, 0x2b, + SHU_R0_B0_DQ0_SW_ARPI_DQM_B0, 0x2b, + SHU_R0_B0_DQ0_ARPI_PBYTE_B0, 0x01, + SHU_R0_B0_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B0, 0x0, + SHU_R0_B0_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_dq0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_R_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_RG_RX_ARDQS1_F_DLY_DUTY, 0x0, + SHU_R0_B1_DQ0_SW_ARPI_DQ_B1, 0x2b, + SHU_R0_B1_DQ0_SW_ARPI_DQM_B1, 0x2b, + SHU_R0_B1_DQ0_ARPI_PBYTE_B1, 0x01, + SHU_R0_B1_DQ0_DA_ARPI_DDR400_0D5UI_RK0_B1, 0x0, + SHU_R0_B1_DQ0_DA_RX_ARDQSIEN_0D5UI_RK0_B1, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_dcm_ctrl0, + SHU_DCM_CTRL0_DDRPHY_CLK_EN_OPT, 0x1, + SHU_DCM_CTRL0_DPHY_CMD_CLKEN_EXTCNT, 0x3, + SHU_DCM_CTRL0_DDRPHY_CLK_DYN_GATING_SEL, 0x5, + SHU_DCM_CTRL0_APHYPI_CKCGL_CNT, 0x2, + SHU_DCM_CTRL0_APHYPI_CKCGH_CNT, 0x4, + SHU_DCM_CTRL0_FASTWAKE2, 0x0, + SHU_DCM_CTRL0_FASTWAKE, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_aphy_tx_picg_ctrl, + SHU_APHY_TX_PICG_CTRL_TX_PICG_CNT, 0x3, + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P1, 0x3, + SHU_APHY_TX_PICG_CTRL_TX_DQS_SEL_P0, 0x3, + SHU_APHY_TX_PICG_CTRL_DPHY_TX_DCM_EXTCNT, 0x2, + SHU_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_OPT, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_aphy_tx_picg_ctrl, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x4, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_aphy_tx_picg_ctrl, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P1, 0x4, + SHURK_APHY_TX_PICG_CTRL_TX_DQ_RK_SEL_P0, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_new_xrw2w_ctrl, + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B0, 0x2, + SHU_NEW_XRW2W_CTRL_TX_PI_UPDCTL_B1, 0x2, + SHU_NEW_XRW2W_CTRL_TXPI_UPD_MODE, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs0, + SHU_SELPH_DQS0_TXDLY_DQS0, 0x4, + SHU_SELPH_DQS0_TXDLY_DQS1, 0x4, + SHU_SELPH_DQS0_TXDLY_DQS2, 0x1, + SHU_SELPH_DQS0_TXDLY_DQS3, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS0, 0x4, + SHU_SELPH_DQS0_TXDLY_OEN_DQS1, 0x4, + SHU_SELPH_DQS0_TXDLY_OEN_DQS2, 0x1, + SHU_SELPH_DQS0_TXDLY_OEN_DQS3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_selph_dqs1, + SHU_SELPH_DQS1_DLY_DQS0, 0x5, + SHU_SELPH_DQS1_DLY_DQS1, 0x5, + SHU_SELPH_DQS1_DLY_DQS2, 0x1, + SHU_SELPH_DQS1_DLY_DQS3, 0x1, + SHU_SELPH_DQS1_DLY_OEN_DQS0, 0x2, + SHU_SELPH_DQS1_DLY_OEN_DQS1, 0x2, + SHU_SELPH_DQS1_DLY_OEN_DQS2, 0x1, + SHU_SELPH_DQS1_DLY_OEN_DQS3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x4, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x4, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq1, + SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x4, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x4, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_DQ0, 0x6, + SHURK_SELPH_DQ2_DLY_DQ1, 0x6, + SHURK_SELPH_DQ2_DLY_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_DQ3, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x3, + SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x3, + SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_selph_dq3, + SHURK_SELPH_DQ3_DLY_DQM0, 0x6, + SHURK_SELPH_DQ3_DLY_DQM1, 0x6, + SHURK_SELPH_DQ3_DLY_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_DQM3, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x3, + SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x3, + SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq0, + SHURK_SELPH_DQ0_TXDLY_DQ0, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ1, 0x4, + SHURK_SELPH_DQ0_TXDLY_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_DQ3, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ0, 0x4, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ1, 0x4, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ0_TXDLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq1, + SHURK_SELPH_DQ1_TXDLY_DQM0, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM1, 0x4, + SHURK_SELPH_DQ1_TXDLY_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_DQM3, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM0, 0x4, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM1, 0x4, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ1_TXDLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq2, + SHURK_SELPH_DQ2_DLY_DQ0, 0x7, + SHURK_SELPH_DQ2_DLY_DQ1, 0x7, + SHURK_SELPH_DQ2_DLY_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_DQ3, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ0, 0x4, + SHURK_SELPH_DQ2_DLY_OEN_DQ1, 0x4, + SHURK_SELPH_DQ2_DLY_OEN_DQ2, 0x1, + SHURK_SELPH_DQ2_DLY_OEN_DQ3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_selph_dq3, + SHURK_SELPH_DQ3_DLY_DQM0, 0x7, + SHURK_SELPH_DQ3_DLY_DQM1, 0x7, + SHURK_SELPH_DQ3_DLY_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_DQM3, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM0, 0x4, + SHURK_SELPH_DQ3_DLY_OEN_DQM1, 0x4, + SHURK_SELPH_DQ3_DLY_OEN_DQM2, 0x1, + SHURK_SELPH_DQ3_DLY_OEN_DQM3, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal1, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x013, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x016); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal2, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x013, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x016); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_dqs2dq_cal5, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x013, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x016); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal1, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ0, 0x02b, + SHURK_DQS2DQ_CAL1_BOOT_ORIG_UI_RK0_DQ1, 0x02b); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal2, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ0, 0x02b, + SHURK_DQS2DQ_CAL2_BOOT_TARG_UI_RK0_DQ1, 0x02b); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_dqs2dq_cal5, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM0, 0x02b, + SHURK_DQS2DQ_CAL5_BOOT_TARG_UI_RK0_DQM1, 0x02b); + SET32_BITFIELDS(&ch[0].ao.shu_rk[0].shurk_pi, + SHURK_PI_RK0_ARPI_DQ_B1, 0x16, + SHURK_PI_RK0_ARPI_DQ_B0, 0x13, + SHURK_PI_RK0_ARPI_DQM_B1, 0x16, + SHURK_PI_RK0_ARPI_DQM_B0, 0x13); + SET32_BITFIELDS(&ch[0].ao.shu_rk[1].shurk_pi, + SHURK_PI_RK0_ARPI_DQ_B1, 0x2b, + SHURK_PI_RK0_ARPI_DQ_B0, 0x2b, + SHURK_PI_RK0_ARPI_DQM_B1, 0x2b, + SHURK_PI_RK0_ARPI_DQM_B0, 0x2b); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x10, + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x10, + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x10, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x10); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x10, + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x10, + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x10, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x10); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x10, + SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, + SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x04, + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x04, + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x04, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x04); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x04, + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x04, + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x04, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x04); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x04, + SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, + SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0x08, + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0x08, + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0x08, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0x08, + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0x08, + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0x08, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x08, + SHU_R0_B0_TXDLY3_TX_ARWCK_DLY_B0, 0x00, + SHU_R0_B0_TXDLY3_TX_ARWCKB_DLY_B0, 0x00); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0x08, + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0x08, + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0x08, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0x08, + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0x08, + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0x08, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0x08); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x08, + SHU_R0_B1_TXDLY3_TX_ARWCK_DLY_B1, 0x00, + SHU_R0_B1_TXDLY3_TX_ARWCKB_DLY_B1, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_tx_rankctl, + SHU_TX_RANKCTL_TXRANKINCTL_TXDLY, 0x1, + SHU_TX_RANKCTL_TXRANKINCTL, 0x1, + SHU_TX_RANKCTL_TXRANKINCTL_ROOT, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating0, + SHU_AC_DERATING0_ACDERATEEN, 0x0, + SHU_AC_DERATING0_TRRD_DERATE, 0x5, + SHU_AC_DERATING0_TRCD_DERATE, 0xb); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating1, + SHU_AC_DERATING1_TRPAB_DERATE, 0xb, + SHU_AC_DERATING1_TRP_DERATE, 0x9, + SHU_AC_DERATING1_TRAS_DERATE, 0x0f, + SHU_AC_DERATING1_TRC_DERATE, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_ac_derating_05t, + SHU_AC_DERATING_05T_TRC_05T_DERATE, 0x0, + SHU_AC_DERATING_05T_TRCD_05T_DERATE, 0x0, + SHU_AC_DERATING_05T_TRP_05T_DERATE, 0x1, + SHU_AC_DERATING_05T_TRPAB_05T_DERATE, 0x0, + SHU_AC_DERATING_05T_TRAS_05T_DERATE, 0x0, + SHU_AC_DERATING_05T_TRRD_05T_DERATE, 0x1); + SET32_BITFIELDS(&ch[0].ao.shu_sref_ctrl, + SHU_SREF_CTRL_CKEHCMD, 0x3, + SHU_SREF_CTRL_SREF_CK_DLY, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_hmr4_dvfs_ctrl0, + SHU_HMR4_DVFS_CTRL0_FSPCHG_PRDCNT, 0x86, + SHU_HMR4_DVFS_CTRL0_REFRCNT, 0x000); + SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TRC_05T, 0x0, + SHU_AC_TIME_05T_TRFCPB_05T, 0x1, + SHU_AC_TIME_05T_TRFC_05T, 0x0, + SHU_AC_TIME_05T_TPBR2PBR_05T, 0x0, + SHU_AC_TIME_05T_TXP_05T, 0x0, + SHU_AC_TIME_05T_TRTP_05T, 0x1, + SHU_AC_TIME_05T_TRCD_05T, 0x0, + SHU_AC_TIME_05T_TRP_05T, 0x1, + SHU_AC_TIME_05T_TRPAB_05T, 0x0, + SHU_AC_TIME_05T_TRAS_05T, 0x0, + SHU_AC_TIME_05T_TWR_M05T, 0x0, + SHU_AC_TIME_05T_TRRD_05T, 0x0, + SHU_AC_TIME_05T_TFAW_05T, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TCKEPRD_05T, 0x0, + SHU_AC_TIME_05T_TR2PD_05T, 0x1, + SHU_AC_TIME_05T_TWTPD_M05T, 0x0, + SHU_AC_TIME_05T_TMRRI_05T, 0x0, + SHU_AC_TIME_05T_TMRWCKEL_05T, 0x1, + SHU_AC_TIME_05T_BGTRRD_05T, 0x0, + SHU_AC_TIME_05T_BGTCCD_05T, 0x0, + SHU_AC_TIME_05T_BGTWTR_M05T, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TR2W_05T, 0x0, + SHU_AC_TIME_05T_TWTR_M05T, 0x1, + SHU_AC_TIME_05T_XRTR2W_05T, 0x0, + SHU_AC_TIME_05T_TMRD_05T, 0x0, + SHU_AC_TIME_05T_TMRW_05T, 0x1, + SHU_AC_TIME_05T_TMRR2MRW_05T, 0x0, + SHU_AC_TIME_05T_TW2MRW_05T, 0x0, + SHU_AC_TIME_05T_TR2MRW_05T, 0x0, + SHU_AC_TIME_05T_TPBR2ACT_05T, 0x0, + SHU_AC_TIME_05T_XRTW2R_M05T, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_actim_xrt, + SHU_ACTIM_XRT_XRTR2R, 0x03, + SHU_ACTIM_XRT_XRTR2W, 0x08, + SHU_ACTIM_XRT_XRTW2R, 0x1, + SHU_ACTIM_XRT_XRTW2W, 0x05); + SET32_BITFIELDS(&ch[0].ao.shu_actim0, + SHU_ACTIM0_TWTR, 0x0a, + SHU_ACTIM0_TWR, 0x0f, + SHU_ACTIM0_TRRD, 0x3, + SHU_ACTIM0_TRCD, 0xa, + SHU_ACTIM0_CKELCKCNT, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_actim1, + SHU_ACTIM1_TRPAB, 0xa, + SHU_ACTIM1_TMRWCKEL, 0x8, + SHU_ACTIM1_TRP, 0x8, + SHU_ACTIM1_TRAS, 0x0e, + SHU_ACTIM1_TRC, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_actim2, + SHU_ACTIM2_TXP, 0x1, + SHU_ACTIM2_TMRRI, 0x0e, + SHU_ACTIM2_TRTP, 0x2, + SHU_ACTIM2_TR2W, 0x09, + SHU_ACTIM2_TFAW, 0x08); + SET32_BITFIELDS(&ch[0].ao.shu_actim3, + SHU_ACTIM3_TRFCPB, 0x59, + SHU_ACTIM3_MANTMRR, 0x4, + SHU_ACTIM3_TR2MRR, 0x4, + SHU_ACTIM3_TRFC, 0xbf, + SHU_ACTIM3_TWTR_L, 0x00); + SET32_BITFIELDS(&ch[0].ao.shu_actim4, + SHU_ACTIM4_TXREFCNT, 0x0cf, + SHU_ACTIM4_TMRR2MRW, 0x0f, + SHU_ACTIM4_TMRR2W, 0x0b, + SHU_ACTIM4_TZQCS, 0x2e); + SET32_BITFIELDS(&ch[0].ao.shu_actim5, + SHU_ACTIM5_TR2PD, 0x0f, + SHU_ACTIM5_TWTPD, 0x12, + SHU_ACTIM5_TPBR2PBR, 0x29, + SHU_ACTIM5_TPBR2ACT, 0x0); + SET32_BITFIELDS(&ch[0].ao.shu_actim6, + SHU_ACTIM6_TZQLAT2, 0x10, + SHU_ACTIM6_TMRD, 0x8, + SHU_ACTIM6_TMRW, 0x5, + SHU_ACTIM6_TW2MRW, 0x0b, + SHU_ACTIM6_TR2MRW, 0x12); + SET32_BITFIELDS(&ch[0].ao.shu_ckectrl, + SHU_CKECTRL_TPDE_05T, 0x1, + SHU_CKECTRL_TPDX_05T, 0x0, + SHU_CKECTRL_TPDE, 0x1, + SHU_CKECTRL_TPDX, 0x1, + SHU_CKECTRL_TCKEPRD, 0x3, + SHU_CKECTRL_TCKESRX, 0x3); + SET32_BITFIELDS(&ch[0].ao.shu_misc, + SHU_MISC_REQQUE_MAXCNT, 0x2, + SHU_MISC_DCMDLYREF, 0x7, + SHU_MISC_DAREFEN, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq8, + SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B0, 0x0100, + SHU_B0_DQ8_R_DMRXDVS_UPD_FORCE_EN_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_RMRODTEN_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_RMRX_TOPHY_CG_IG_B0, 0x1, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRXDLY_CG_IG_B0, 0x1, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_PIPE_CG_IG_B0, 0x0, + SHU_B0_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq8, + SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_CYC_B1, 0x0100, + SHU_B1_DQ8_R_DMRXDVS_UPD_FORCE_EN_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_RXDLY_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_RMRODTEN_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_RMRX_TOPHY_CG_IG_B1, 0x1, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRXDVS_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRXDLY_CG_IG_B1, 0x1, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_SYNC_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_FLAG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMDQSIEN_RDSEL_TOG_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_PIPE_CG_IG_B1, 0x0, + SHU_B1_DQ8_R_DMRANK_CHG_PIPE_CG_IG_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].shu_b0_dq5, + SHU_B0_DQ5_RG_RX_ARDQ_VREF_SEL_B0, 0x0e, + SHU_B0_DQ5_RG_RX_ARDQ_VREF_BYPASS_B0, 0x0, + SHU_B0_DQ5_RG_ARPI_FB_B0, 0x00, + SHU_B0_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B0, 0x0, + SHU_B0_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B0, 0x0, + SHU_B0_DQ5_RG_RX_ARDQS0_DVS_DLY_B0, 0x3, + SHU_B0_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].shu_b0_dq5, + SHU_B1_DQ5_RG_RX_ARDQ_VREF_SEL_B1, 0x0e, + SHU_B1_DQ5_RG_RX_ARDQ_VREF_BYPASS_B1, 0x0, + SHU_B1_DQ5_RG_ARPI_FB_B1, 0x00, + SHU_B1_DQ5_RG_RX_ARDQS0_DQSIEN_DLY_B1, 0x0, + SHU_B1_DQ5_RG_RX_ARDQS_DQSIEN_RB_DLY_B1, 0x0, + SHU_B1_DQ5_RG_RX_ARDQS0_DVS_DLY_B1, 0x3, + SHU_B1_DQ5_RG_RX_ARDQ_FIFO_DQSI_DLY_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly0, + SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x54, + SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x54, + SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x54, + SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x54); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly1, + SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x54, + SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x54, + SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x54, + SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x54); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly2, + SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x54, + SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x54, + SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x54, + SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x54); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly3, + SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x54, + SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x54, + SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x54, + SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x54); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly4, + SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x54, + SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x54); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[0].shu_r0_b0_rxdly5, + SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x04a, + SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x04a); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly0, + SHU_R0_B0_RXDLY0_RX_ARDQ0_R_DLY_B0, 0x46, + SHU_R0_B0_RXDLY0_RX_ARDQ0_F_DLY_B0, 0x46, + SHU_R0_B0_RXDLY0_RX_ARDQ1_R_DLY_B0, 0x46, + SHU_R0_B0_RXDLY0_RX_ARDQ1_F_DLY_B0, 0x46); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly1, + SHU_R0_B0_RXDLY1_RX_ARDQ2_R_DLY_B0, 0x46, + SHU_R0_B0_RXDLY1_RX_ARDQ2_F_DLY_B0, 0x46, + SHU_R0_B0_RXDLY1_RX_ARDQ3_R_DLY_B0, 0x46, + SHU_R0_B0_RXDLY1_RX_ARDQ3_F_DLY_B0, 0x46); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly2, + SHU_R0_B0_RXDLY2_RX_ARDQ4_R_DLY_B0, 0x46, + SHU_R0_B0_RXDLY2_RX_ARDQ4_F_DLY_B0, 0x46, + SHU_R0_B0_RXDLY2_RX_ARDQ5_R_DLY_B0, 0x46, + SHU_R0_B0_RXDLY2_RX_ARDQ5_F_DLY_B0, 0x46); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly3, + SHU_R0_B0_RXDLY3_RX_ARDQ6_R_DLY_B0, 0x46, + SHU_R0_B0_RXDLY3_RX_ARDQ6_F_DLY_B0, 0x46, + SHU_R0_B0_RXDLY3_RX_ARDQ7_R_DLY_B0, 0x46, + SHU_R0_B0_RXDLY3_RX_ARDQ7_F_DLY_B0, 0x46); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly4, + SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0, 0x46, + SHU_R0_B0_RXDLY4_RX_ARDQM0_F_DLY_B0, 0x46); + SET32_BITFIELDS(&ch[0].phy_ao.byte[0].rk[1].shu_r0_b0_rxdly5, + SHU_R0_B0_RXDLY5_RX_ARDQS0_R_DLY_B0, 0x038, + SHU_R0_B0_RXDLY5_RX_ARDQS0_F_DLY_B0, 0x038); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly0, + SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0xcd); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly1, + SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0xcd); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly2, + SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0xcd); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly3, + SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0xcd); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly4, + SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0xcd, + SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0xcd); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[0].shu_r0_b0_rxdly5, + SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x0bd, + SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x0bd); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly0, + SHU_R0_B1_RXDLY0_RX_ARDQ0_R_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY0_RX_ARDQ0_F_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY0_RX_ARDQ1_R_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY0_RX_ARDQ1_F_DLY_B1, 0xfe); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly1, + SHU_R0_B1_RXDLY1_RX_ARDQ2_R_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY1_RX_ARDQ2_F_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY1_RX_ARDQ3_R_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY1_RX_ARDQ3_F_DLY_B1, 0xfe); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly2, + SHU_R0_B1_RXDLY2_RX_ARDQ4_R_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY2_RX_ARDQ4_F_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY2_RX_ARDQ5_R_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY2_RX_ARDQ5_F_DLY_B1, 0xfe); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly3, + SHU_R0_B1_RXDLY3_RX_ARDQ6_R_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY3_RX_ARDQ6_F_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY3_RX_ARDQ7_R_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY3_RX_ARDQ7_F_DLY_B1, 0xfe); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly4, + SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1, 0xfe, + SHU_R0_B1_RXDLY4_RX_ARDQM0_F_DLY_B1, 0xfe); + SET32_BITFIELDS(&ch[0].phy_ao.byte[1].rk[1].shu_r0_b0_rxdly5, + SHU_R0_B1_RXDLY5_RX_ARDQS0_R_DLY_B1, 0x0f4, + SHU_R0_B1_RXDLY5_RX_ARDQS0_F_DLY_B1, 0x0f4); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq9, + B0_DQ9_RG_RX_ARDQ_STBEN_RESETB_B0, 0x1, + B0_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B0, 0x0, + B0_DQ9_RG_RX_ARDQS0_DQSIENMODE_B0, 0x0, + B0_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B0, 0x1, + B0_DQ9_R_DMRXFIFO_STBENCMP_EN_B0, 0x0, + B0_DQ9_R_IN_GATE_EN_LOW_OPT_B0, 0x00, + B0_DQ9_R_DMDQSIEN_VALID_LAT_B0, 0x0, + B0_DQ9_R_DMDQSIEN_RDSEL_LAT_B0, 0x0, + B0_DQ9_R_DMRXDVS_VALID_LAT_B0, 0x0, + B0_DQ9_R_DMRXDVS_RDSEL_LAT_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq9, + B1_DQ9_RG_RX_ARDQ_STBEN_RESETB_B1, 0x1, + B1_DQ9_RG_RX_ARDQS0_STBEN_RESETB_B1, 0x0, + B1_DQ9_RG_RX_ARDQS0_DQSIENMODE_B1, 0x0, + B1_DQ9_R_DMRXDVS_R_F_DLY_RK_OPT_B1, 0x1, + B1_DQ9_R_DMRXFIFO_STBENCMP_EN_B1, 0x0, + B1_DQ9_R_IN_GATE_EN_LOW_OPT_B1, 0x00, + B1_DQ9_R_DMDQSIEN_VALID_LAT_B1, 0x0, + B1_DQ9_R_DMDQSIEN_RDSEL_LAT_B1, 0x0, + B1_DQ9_R_DMRXDVS_VALID_LAT_B1, 0x0, + B1_DQ9_R_DMRXDVS_RDSEL_LAT_B1, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq4, + B0_DQ4_RG_RX_ARDQS_EYE_R_DLY_B0, 0x5a, + B0_DQ4_RG_RX_ARDQS_EYE_F_DLY_B0, 0x5a, + B0_DQ4_RG_RX_ARDQ_EYE_R_DLY_B0, 0x14, + B0_DQ4_RG_RX_ARDQ_EYE_F_DLY_B0, 0x14); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq4, + B1_DQ4_RG_RX_ARDQS_EYE_R_DLY_B1, 0x53, + B1_DQ4_RG_RX_ARDQS_EYE_F_DLY_B1, 0x53, + B1_DQ4_RG_RX_ARDQ_EYE_R_DLY_B1, 0x0d, + B1_DQ4_RG_RX_ARDQ_EYE_F_DLY_B1, 0x0d); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[0].b0_dq5, + B0_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B0, 0x0e, + B0_DQ5_RG_RX_ARDQ_VREF_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_SEL_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_EN_B0, 0x0, + B0_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B0, 0x1, + B0_DQ5_RG_RX_ARDQS0_DVS_EN_B0, 0x0); + SET32_BITFIELDS(&ch[0].phy_ao.dvs_b[1].b0_dq5, + B1_DQ5_RG_RX_ARDQ_EYE_VREF_SEL_B1, 0x0e, + B1_DQ5_RG_RX_ARDQ_VREF_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_VREF_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_SEL_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_EN_B1, 0x0, + B1_DQ5_RG_RX_ARDQ_EYE_STBEN_RESETB_B1, 0x1, + B1_DQ5_RG_RX_ARDQS0_DVS_EN_B1, 0x0); +} + static u32 get_write_latency_by_mr(u8 mr_wl) { u32 write_latency = 0; @@ -189,6 +3085,35 @@ } } +static void dramc_setting(const struct ddr_cali *cali) +{ + dram_freq_grp freq_group = cali->freq_group; + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + switch (freq_group) { + case DDRFREQ_400: + sv_algorithm_assistance_lp4_800(); + break; + case DDRFREQ_600: + case DDRFREQ_800: + case DDRFREQ_933: + case DDRFREQ_1200: + sv_algorithm_assistance_lp4_1600(); + break; + case DDRFREQ_1600: + sv_algorithm_assistance_lp4_3733(); + break; + case DDRFREQ_2133: + sv_algorithm_assistance_lp4_4266(); + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); +} + void cke_fix_onoff(const struct ddr_cali *cali, u8 chn, u8 rank, int option) { u8 cke_on = 0, cke_off = 0; @@ -297,6 +3222,7 @@ static void dramc_init(const struct ddr_cali *cali) { + dramc_setting(cali); dramc_reset_delay_chain_before_calibration(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50d5aebaf249ab7292fad7a0046099239c8b403c Gerrit-Change-Number: 44707 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: drivers/libgfxinit: Add Comet Lake to supported platforms
by Felix Singer (Code Review) 28 Dec '20

28 Dec '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40720 ) Change subject: drivers/libgfxinit: Add Comet Lake to supported platforms ...................................................................... drivers/libgfxinit: Add Comet Lake to supported platforms Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Change-Id: I002ade555c0544e4ef738c1ad45ee3d8aa38e03e --- M src/drivers/intel/gma/Kconfig 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/40720/1 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index acc25fe..051cdd4 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -86,7 +86,7 @@ || NORTHBRIDGE_INTEL_HASWELL \ || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE \ || SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE \ - || SOC_INTEL_WHISKEYLAKE + || SOC_INTEL_WHISKEYLAKE || SOC_INTEL_COMETLAKE depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID select RAMSTAGE_LIBHWBASE @@ -113,7 +113,8 @@ string default "Broxton" if SOC_INTEL_APOLLOLAKE default "Skylake" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE || \ - SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE + SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE || \ + SOC_INTEL_COMETLAKE default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL default "Ironlake" if NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X -- To view, visit https://review.coreboot.org/c/coreboot/+/40720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I002ade555c0544e4ef738c1ad45ee3d8aa38e03e Gerrit-Change-Number: 40720 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: soc/mediatek/mt8192: add rtc MT6359P driver
by Yidi Lin (Code Review) 28 Dec '20

28 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46395 ) Change subject: soc/mediatek/mt8192: add rtc MT6359P driver ...................................................................... soc/mediatek/mt8192: add rtc MT6359P driver Add rtc MT6359P driver. TEST=boot asurada Signed-off-by: Yuchen Huang <yuchen.huang(a)mediatek.corp-partner.google.com> Change-Id: I57d6738fdec148c7458b2024a0a8225415ca2f3e --- M src/soc/mediatek/common/include/soc/rtc_common.h M src/soc/mediatek/common/rtc.c M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/bootblock.c A src/soc/mediatek/mt8192/include/soc/rtc.h A src/soc/mediatek/mt8192/rtc.c 6 files changed, 694 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/46395/1 diff --git a/src/soc/mediatek/common/include/soc/rtc_common.h b/src/soc/mediatek/common/include/soc/rtc_common.h old mode 100644 new mode 100755 index 5159f37..19dc3cd --- a/src/soc/mediatek/common/include/soc/rtc_common.h +++ b/src/soc/mediatek/common/include/soc/rtc_common.h @@ -102,26 +102,4 @@ int rtc_reg_init(void); void rtc_boot_common(void); -static inline s32 rtc_read(u16 addr, u16 *rdata) -{ - s32 ret; - - ret = pwrap_read(addr, rdata); - if (ret < 0) - rtc_info("pwrap_read fail: ret=%d\n", ret); - - return ret; -} - -static inline s32 rtc_write(u16 addr, u16 wdata) -{ - s32 ret; - - ret = pwrap_write(addr, wdata); - if (ret < 0) - rtc_info("pwrap_write fail: ret=%d\n", ret); - - return ret; -} - #endif /* SOC_MEDIATEK_RTC_COMMON_H */ diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c old mode 100644 new mode 100755 index 0925f7f..d0b90f7 --- a/src/soc/mediatek/common/rtc.c +++ b/src/soc/mediatek/common/rtc.c @@ -2,7 +2,7 @@ #include <soc/rtc_common.h> #include <soc/rtc.h> -#include <soc/pmic_wrap.h> +#include <soc/pmif.h> #include <timer.h> /* ensure rtc write success */ @@ -164,8 +164,8 @@ switch (rtc_check_state()) { case RTC_STATE_REBOOT: - pwrap_write_field(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, - 0xFFFF, 0); + rtc_read(RTC_BBPU, &bbpu); + rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); rtc_write_trigger(); rtc_osc_init(); break; @@ -176,6 +176,7 @@ default: if (rtc_init(0)) rtc_init(1); + rtc_info("RTC_STATE_INIT\n"); break; } diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc old mode 100644 new mode 100755 index 5fc90a8..9542aa4 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -11,6 +11,7 @@ bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c bootblock-y += pmif.c pmif_clk.c pmif_spi.c pmif_spmi.c +bootblock-y += ../common/rtc.c rtc.c bootblock-y += mt6315.c bootblock-y += mt6359p.c diff --git a/src/soc/mediatek/mt8192/bootblock.c b/src/soc/mediatek/mt8192/bootblock.c old mode 100644 new mode 100755 index 7987b1c..5bb85ba --- a/src/soc/mediatek/mt8192/bootblock.c +++ b/src/soc/mediatek/mt8192/bootblock.c @@ -7,6 +7,7 @@ #include <soc/pll.h> #include <soc/pmif.h> #include <soc/wdt.h> +#include <soc/rtc.h> void bootblock_soc_init(void) { @@ -16,4 +17,5 @@ mtk_pmif_init(); mt6359p_init(); mt6315_init(); + rtc_boot(); } diff --git a/src/soc/mediatek/mt8192/include/soc/rtc.h b/src/soc/mediatek/mt8192/include/soc/rtc.h new file mode 100755 index 0000000..b1be85c --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/rtc.h @@ -0,0 +1,220 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef SOC_MEDIATEK_MT8192_RTC_H +#define SOC_MEDIATEK_MT8192_RTC_H + +#include <soc/rtc_common.h> + +/* RTC registers */ +enum { + RTC_BBPU = 0x0588, + RTC_IRQ_STA = 0x058A, + RTC_IRQ_EN = 0x058C, + RTC_CII_EN = 0x058E +}; + +enum { + RTC_TC_SEC = 0x0592, + RTC_TC_MIN = 0x0594, + RTC_TC_HOU = 0x0596, + RTC_TC_DOM = 0x0598, + RTC_TC_DOW = 0x059A, + RTC_TC_MTH = 0x059C, + RTC_TC_YEA = 0x059E +}; + +enum { + RTC_AL_SEC = 0x05A0, + RTC_AL_MIN = 0x05A2, + RTC_AL_HOU = 0x05A4, + RTC_AL_DOM = 0x05A6, + RTC_AL_DOW = 0x05A8, + RTC_AL_MTH = 0x05AA, + RTC_AL_YEA = 0x05AC, + RTC_AL_MASK = 0x0590 +}; + +enum { + RTC_OSC32CON = 0x05AE, + RTC_CON = 0x05C4, + RTC_WRTGR = 0x05C2 +}; + +enum { + RTC_POWERKEY1 = 0x05B0, + RTC_POWERKEY2 = 0x05B2 +}; + +enum { + RTC_PDN1 = 0x05B4, + RTC_PDN2 = 0x05B6, + RTC_SPAR0 = 0x05B8, + RTC_SPAR1 = 0x05BA, + RTC_PROT = 0x05BC, + RTC_DIFF = 0x05BE, + RTC_CALI = 0x05C0 +}; + +enum { + RTC_BBPU_ENABLE_ALARM = 1U << 0, + RTC_BBPU_SPAR_SW = 1U << 1, + RTC_BBPU_RESET_SPAR = 1U << 2, + RTC_BBPU_RESET_ALARM = 1U << 3, + RTC_BBPU_CLRPKY = 1U << 4, + RTC_BBPU_RELOAD = 1U << 5, + RTC_BBPU_CBUSY = 1U << 6, + RTC_CBUSY_TIMEOUT_US = 1000000 +}; + +enum { + RTC_CON_VBAT_LPSTA_RAW = 1U << 0, + RTC_CON_EOSC32_LPEN = 1U << 1, + RTC_CON_XOSC32_LPEN = 1U << 2, + RTC_CON_LPRST = 1U << 3, + RTC_CON_CDBO = 1U << 4, + RTC_CON_F32KOB = 1U << 5, + RTC_CON_GPO = 1U << 6, + RTC_CON_GOE = 1U << 7, + RTC_CON_GSR = 1U << 8, + RTC_CON_GSMT = 1U << 9, + RTC_CON_GPEN = 1U << 10, + RTC_CON_GPU = 1U << 11, + RTC_CON_GE4 = 1U << 12, + RTC_CON_GE8 = 1U << 13, + RTC_CON_GPI = 1U << 14, + RTC_CON_LPSTA_RAW = 1U << 15 +}; + +enum { + RTC_XOSCCALI_MASK = 0x1F << 0, + RTC_XOSC32_ENB = 1U << 5, + RTC_EMB_HW_MODE = 0U << 6, + RTC_EMB_K_EOSC32_MODE = 1U << 6, + RTC_EMB_SW_DCXO_MODE = 2U << 6, + RTC_EMB_SW_EOSC32_MODE = 3U << 6, + RTC_EMBCK_SEL_MODE_MASK = 3U << 6, + RTC_EMBCK_SRC_SEL = 1U << 8, + RTC_EMBCK_SEL_OPTION = 1U << 9, + RTC_GPS_CKOUT_EN = 1U << 10, + RTC_REG_XOSC32_ENB = 1U << 15 +}; + +enum { + RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13, + RTC_LPD_OPT_EOSC_LPD = 1U << 13, + RTC_LPD_OPT_XOSC_LPD = 2U << 13, + RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13, + RTC_LPD_OPT_MASK = 3U << 13 +}; + +/* PMIC TOP Register Definition */ +enum { + PMIC_RG_SCK_TOP_CON0 = 0x050C +}; + +/* PMIC TOP Register Definition */ +enum { + PMIC_RG_TOP_CKPDN_CON0 = 0x010C, + PMIC_RG_TOP_CKPDN_CON0_SET = 0x010E, + PMIC_RG_TOP_CKPDN_CON0_CLR = 0x0110, + PMIC_RG_TOP_CKPDN_CON1 = 0x0112, + PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114, + PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116, + PMIC_RG_TOP_CKSEL_CON0 = 0x0118, + PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A, + PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C +}; + +enum { + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT = 10, + PMIC_RG_FQMTR_CK_PDN_SHIFT = 11 +}; + +/* PMIC DCXO Register Definition */ +enum { + PMIC_RG_DCXO_CW00 = 0x0788, + PMIC_RG_DCXO_CW00_SET = 0x078A, + PMIC_RG_DCXO_CW00_CLR = 0x078C, + PMIC_RG_DCXO_CW02 = 0x0790, + PMIC_RG_DCXO_CW08 = 0x079C, + PMIC_RG_DCXO_CW09 = 0x079E, + PMIC_RG_DCXO_CW09_SET = 0x07A0, + PMIC_RG_DCXO_CW09_CLR = 0x07A2, + PMIC_RG_DCXO_CW12 = 0x07A8 +}; + +/* PMIC Frequency Meter Definition */ +enum { + PMIC_RG_FQMTR_CKSEL = 0x0118, + PMIC_RG_FQMTR_RST = 0x013A, + PMIC_RG_FQMTR_CON0 = 0x0546, + PMIC_RG_FQMTR_WINSET = 0x0548, + PMIC_RG_FQMTR_DATA = 0x054A, + FQMTR_TIMEOUT_US = 8000 +}; + +enum { + PMIC_FQMTR_FIX_CLK_26M = 0U << 0, + PMIC_FQMTR_FIX_CLK_XOSC_32K_DET = 1U << 0, + PMIC_FQMTR_FIX_CLK_EOSC_32K = 2U << 0, + PMIC_FQMTR_FIX_CLK_RTC_32K = 3U << 0, + PMIC_FQMTR_FIX_CLK_DCXO1M_CK = 4U << 0, + PMIC_FQMTR_FIX_CLK_TCK_SEC = 5U << 0, + PMIC_FQMTR_FIX_CLK_PMU_32K = 6U << 0, + PMIC_FQMTR_CKSEL_MASK = 7U << 0 +}; + +enum { + PMIC_FQMTR_RST_SHIFT = 8 +}; + +enum { + PMIC_FQMTR_CON0_XOSC32_CK = 0U << 0, + PMIC_FQMTR_CON0_DCXO_F32K_CK = 1U << 0, + PMIC_FQMTR_CON0_EOSC32_CK = 2U << 0, + PMIC_FQMTR_CON0_XOSC32_CK_DETECTON = 3U << 0, + PMIC_FQMTR_CON0_FQM26M_CK = 4U << 0, + PMIC_FQMTR_CON0_FQM32k_CK = 5U << 0, + PMIC_FQMTR_CON0_TEST_CK = 6U << 0, + PMIC_FQMTR_CON0_TCKSEL_MASK = 7U << 0, + PMIC_FQMTR_CON0_BUSY = 1U << 3, + PMIC_FQMTR_CON0_DCXO26M_EN = 1U << 4, + PMIC_FQMTR_CON0_FQMTR_EN = 1U << 15 +}; + +enum { + RTC_FQMTR_LOW_BASE = 794 - 2, + RTC_FQMTR_HIGH_BASE = 794 + 2 +}; + +enum { + RTC_XOSCCALI_START = 0x00, + RTC_XOSCCALI_END = 0x1f +}; + +enum { + RTC_TC_MTH_MASK = 0xf +}; + +int rtc_read(u16 addr, u16 *rdata); +int rtc_write(u16 addr, u16 wdata); +void rtc_write_field(u16 reg, u16 val, u16 mask, u16 shift); +void rtc_bbpu_power_on(void); +void rtc_osc_init(void); +int rtc_init(u8 recover); +void rtc_boot(void); +void mt6359_dcxo_disable_unused(void); +#endif /* SOC_MEDIATEK_MT8192_RTC_H */ + diff --git a/src/soc/mediatek/mt8192/rtc.c b/src/soc/mediatek/mt8192/rtc.c new file mode 100755 index 0000000..a8e28b5 --- /dev/null +++ b/src/soc/mediatek/mt8192/rtc.c @@ -0,0 +1,467 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <delay.h> +#include <halt.h> +#include <soc/mt6359p.h> +#include <soc/pmif.h> +#include <soc/rtc_common.h> +#include <soc/rtc.h> +#include <timer.h> + +#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8)) + +static struct pmif *pmif_arb = NULL; + +int rtc_read(u16 addr, u16 *rdata) +{ + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPI, 0); + return pmif_arb->read_cmd(pmif_arb, 0, (unsigned int)addr, (unsigned int *)rdata); +} + +int rtc_write(u16 addr, u16 wdata) +{ + if (pmif_arb == NULL) + pmif_arb = get_pmif_controller(PMIF_SPI, 0); + return pmif_arb->write_cmd(pmif_arb, 0, (unsigned int)addr, (unsigned int)wdata); +} + +void rtc_write_field(u16 reg, u16 val, u16 mask, u16 shift) +{ + u16 old, new; + + rtc_read(reg, &old); + new = old & ~(mask << shift); + new |= (val << shift); + rtc_write(reg, new); +} + +/* initialize rtc setting of using dcxo clock */ +static int rtc_enable_dcxo(void) +{ + if (!rtc_writeif_unlock()) { /* Unlock for reload */ + rtc_info("rtc_writeif_unlock() failed\n"); + return 0; + } + + u16 bbpu, con, osc32con, sec; + + rtc_read(RTC_BBPU, &bbpu); + rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + rtc_write_trigger(); + rtc_read(RTC_OSC32CON, &osc32con); + osc32con &= ~(RTC_EMBCK_SRC_SEL | RTC_EMBCK_SEL_MODE_MASK + | RTC_GPS_CKOUT_EN); + osc32con |= RTC_XOSC32_ENB | RTC_REG_XOSC32_ENB + | RTC_EMB_K_EOSC32_MODE | RTC_EMBCK_SEL_OPTION; + + if (!rtc_xosc_write(osc32con)) { + rtc_info("rtc_xosc_write() failed\n"); + return 0; + } + + rtc_read(RTC_CON, &con); + rtc_read(RTC_OSC32CON, &osc32con); + rtc_read(RTC_AL_SEC, &sec); + rtc_info("con=0x%x, osc32con=0x%x, sec=0x%x\n", con, osc32con, sec); + return 1; +} + +/* initialize rtc related gpio */ +static int rtc_gpio_init(void) +{ + u16 con; + + /* GPI mode and pull down */ + rtc_read(RTC_CON, &con); + con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_EOSC32_LPEN + | RTC_CON_XOSC32_LPEN); + con |= (RTC_CON_GPEN | RTC_CON_GOE); + con &= ~(RTC_CON_F32KOB); + con &= ~RTC_CON_GPU; + rtc_write(RTC_CON, con); + + return rtc_write_trigger(); +} + +static u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size) +{ + u16 bbpu, osc32con; + u16 fqmtr_busy, fqmtr_data, fqmtr_rst, fqmtr_tcksel; + struct stopwatch sw; + + if (val) { + rtc_read(RTC_BBPU, &bbpu); + rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + rtc_write_trigger(); + rtc_read(RTC_OSC32CON, &osc32con); + rtc_xosc_write((osc32con & ~RTC_XOSCCALI_MASK) | + (val & RTC_XOSCCALI_MASK)); + } + + /* enable FQMTR clock */ + rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1, + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT); + rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_CLR, 1, 1, + PMIC_RG_FQMTR_CK_PDN_SHIFT); + /* FQMTR reset */ + rtc_write_field(PMIC_RG_FQMTR_RST, 1, 1, PMIC_FQMTR_RST_SHIFT); + + do { + rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data); + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy); + } while (fqmtr_data && (fqmtr_busy & PMIC_FQMTR_CON0_BUSY)); + + rtc_read(PMIC_RG_FQMTR_RST, &fqmtr_rst); + /* FQMTR normal */ + rtc_write_field(PMIC_RG_FQMTR_RST, 0, 1, PMIC_FQMTR_RST_SHIFT); + /* set frequency meter window value (0=1X32K(fixed clock)) */ + rtc_write(PMIC_RG_FQMTR_WINSET, window_size); + /* enable 26M and set test clock source */ + rtc_write(PMIC_RG_FQMTR_CON0, PMIC_FQMTR_CON0_DCXO26M_EN | measure_src); + /* enable 26M -> delay 100us -> enable FQMTR */ + udelay(100); + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + /* enable FQMTR */ + rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel | PMIC_FQMTR_CON0_FQMTR_EN); + udelay(100); + stopwatch_init_usecs_expire(&sw, FQMTR_TIMEOUT_US); + /* FQMTR read until ready */ + do { + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_busy); + if (stopwatch_expired(&sw)) { + rtc_info("get frequency time out !!\n"); + return 0; + } + } while (fqmtr_busy & PMIC_FQMTR_CON0_BUSY); + + /* read data should be closed to 26M/32k = 794 */ + rtc_read(PMIC_RG_FQMTR_DATA, &fqmtr_data); + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + /* disable FQMTR */ + rtc_write(PMIC_RG_FQMTR_CON0, fqmtr_tcksel & ~PMIC_FQMTR_CON0_FQMTR_EN); + /* disable FQMTR -> delay 100us -> disable 26M */ + udelay(100); + /* disable 26M */ + rtc_read(PMIC_RG_FQMTR_CON0, &fqmtr_tcksel); + rtc_write(PMIC_RG_FQMTR_CON0, + fqmtr_tcksel & ~PMIC_FQMTR_CON0_DCXO26M_EN); + rtc_info("input=0x%x, output=%d\n", val, fqmtr_data); + /* disable FQMTR clock */ + rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1, + PMIC_RG_FQMTR_32K_CK_PDN_SHIFT); + rtc_write_field(PMIC_RG_TOP_CKPDN_CON0_SET, 1, 1, + PMIC_RG_FQMTR_CK_PDN_SHIFT); + return fqmtr_data; +} + +/* 32k clock calibration */ +static u16 rtc_eosc_cali(void) +{ + u16 middle, diff1, diff2, cksel; + u16 val = 0; + u16 left = RTC_XOSCCALI_START, right = RTC_XOSCCALI_END; + + rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel); + cksel &= ~PMIC_FQMTR_CKSEL_MASK; + /* select EOSC_32 as fixed clock */ + rtc_write(PMIC_RG_FQMTR_CKSEL, cksel | PMIC_FQMTR_FIX_CLK_EOSC_32K); + rtc_read(PMIC_RG_FQMTR_CKSEL, &cksel); + rtc_info("PMIC_RG_FQMTR_CKSEL=0x%x\n", cksel); + + while (left <= right) { + middle = (right + left) / 2; + if (middle == left) + break; + /* select 26M as target clock */ + val = rtc_get_frequency_meter(middle, PMIC_FQMTR_CON0_FQM26M_CK, 0); + if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) + break; + if (val > RTC_FQMTR_HIGH_BASE) + right = middle; + else + left = middle; + } + + if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) + return middle; + + val = rtc_get_frequency_meter(left, PMIC_FQMTR_CON0_FQM26M_CK, 0); + + if (val > RTC_FQMTR_LOW_BASE) + diff1 = val - RTC_FQMTR_LOW_BASE; + else + diff1 = RTC_FQMTR_LOW_BASE - val; + + val = rtc_get_frequency_meter(right, PMIC_FQMTR_CON0_FQM26M_CK, 0); + + if (val > RTC_FQMTR_LOW_BASE) + diff2 = val - RTC_FQMTR_LOW_BASE; + else + diff2 = RTC_FQMTR_LOW_BASE - val; + + if (diff1 < diff2) + return left; + else + return right; +} + +void rtc_osc_init(void) +{ + u16 osc32con; + + /* enable 32K export */ + rtc_gpio_init(); + /* Calibrate eosc32 for powerdown clock */ + rtc_read(RTC_OSC32CON, &osc32con); + rtc_info("osc32con val = 0x%x\n", osc32con); + osc32con &= ~RTC_XOSCCALI_MASK; + osc32con |= rtc_eosc_cali() & RTC_XOSCCALI_MASK; + rtc_xosc_write(osc32con); + rtc_info("EOSC32 cali val = 0x%x\n", osc32con); +} + +/* enable lpd subroutine */ +static int rtc_lpen(u16 con) +{ + con &= ~RTC_CON_LPRST; + rtc_write(RTC_CON, con); + + if (!rtc_write_trigger()) + return 0; + + con |= RTC_CON_LPRST; + rtc_write(RTC_CON, con); + + if (!rtc_write_trigger()) + return 0; + + con &= ~RTC_CON_LPRST; + rtc_write(RTC_CON, con); + + if (!rtc_write_trigger()) + return 0; + + return 1; +} + +/* low power detect setting */ +static int rtc_lpd_init(void) +{ + u16 con, sec; + + /* disable both XOSC & EOSC LPD */ + rtc_read(RTC_AL_SEC, &sec); + sec |= RTC_LPD_OPT_F32K_CK_ALIVE; + rtc_write(RTC_AL_SEC, sec); + + if (!rtc_write_trigger()) + return 0; + + /* init XOSC32 to detect 32k clock stop */ + rtc_read(RTC_CON, &con); + con |= RTC_CON_XOSC32_LPEN; + + if (!rtc_lpen(con)) + return 0; + + /* init EOSC32 to detect rtc low power */ + rtc_read(RTC_CON, &con); + con |= RTC_CON_EOSC32_LPEN; + + if (!rtc_lpen(con)) + return 0; + + rtc_read(RTC_CON, &con); + con &= ~RTC_CON_XOSC32_LPEN; + rtc_write(RTC_CON, con); + /*Enable RTC_LPD_OPT: EOSC LPD*/ + rtc_read(RTC_AL_SEC, &sec); + sec &= ~RTC_LPD_OPT_MASK; + sec |= RTC_LPD_OPT_EOSC_LPD; + rtc_write(RTC_AL_SEC, sec); + + if (!rtc_write_trigger()) + return 0; + + return 1; +} + +static bool rtc_hw_init(void) +{ + u16 bbpu; + + rtc_read(RTC_BBPU, &bbpu); + rtc_write(RTC_BBPU, (bbpu | RTC_BBPU_KEY | RTC_BBPU_RESET_ALARM | RTC_BBPU_RESET_SPAR) & (~RTC_BBPU_SPAR_SW)); + rtc_write_trigger(); + udelay(500); + + rtc_read(RTC_BBPU, &bbpu); + rtc_write(RTC_BBPU, bbpu | RTC_BBPU_KEY | RTC_BBPU_RELOAD); + rtc_write_trigger(); + rtc_read(RTC_BBPU, &bbpu); + + if (bbpu & RTC_BBPU_RESET_ALARM || bbpu & RTC_BBPU_RESET_SPAR) { + rtc_info("timeout\n"); + return false; + } + return true; +} + +/* write powerkeys to enable rtc functions */ +static int rtc_powerkey_init(void) +{ + rtc_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY); + rtc_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY); + return rtc_write_trigger(); +} + +/* rtc init check */ +int rtc_init(u8 recover) +{ + int ret; + + rtc_info("recovery: %d\n", recover); + + /* write powerkeys to enable rtc functions */ + if (!rtc_powerkey_init()) { + ret = -RTC_STATUS_POWERKEY_INIT_FAIL; + goto err; + } + + /* write interface unlock need to be set after powerkey match */ + if (!rtc_writeif_unlock()) { + ret = -RTC_STATUS_WRITEIF_UNLOCK_FAIL; + goto err; + } + + //rtc_osc_init(); + + if (recover) + mdelay(20); + + if (!rtc_gpio_init()) { + ret = -RTC_STATUS_GPIO_INIT_FAIL; + goto err; + } + + if (!rtc_hw_init()) { + ret = -RTC_STATUS_HW_INIT_FAIL; + goto err; + } + + if (!rtc_reg_init()) { + ret = -RTC_STATUS_REG_INIT_FAIL; + goto err; + } + + if (!rtc_lpd_init()) { + ret = -RTC_STATUS_LPD_INIT_FAIL; + goto err; + } + /* After lpd init, powerkeys need to be written again to enable + * low power detect function. + */ + if (!rtc_powerkey_init()) { + ret = -RTC_STATUS_POWERKEY_INIT_FAIL; + goto err; + } + return RTC_STATUS_OK; +err: + rtc_info("init fail: ret=%d\n", ret); + return ret; +} + +/* enable rtc bbpu */ +void rtc_bbpu_power_on(void) +{ + u16 bbpu; + int ret; + + /* pull powerhold high, control by pmic */ + rtc_write_field(PMIC_PWRHOLD, 1, 0x1, 0); + bbpu = RTC_BBPU_KEY | RTC_BBPU_ENABLE_ALARM; + rtc_write(RTC_BBPU, bbpu); + ret = rtc_write_trigger(); + rtc_info("rtc_write_trigger=%d\n", ret); + rtc_read(RTC_BBPU, &bbpu); + rtc_info("done BBPU=%#x\n", bbpu); +} + +void poweroff(void) +{ + u16 bbpu; + + if (!rtc_writeif_unlock()) + rtc_info("rtc_writeif_unlock() failed\n"); + /* pull PWRBB low */ + bbpu = RTC_BBPU_KEY | RTC_BBPU_ENABLE_ALARM; + rtc_write(RTC_BBPU, bbpu); + rtc_write_field(PMIC_PWRHOLD, 0, 0x1, 0); + halt(); +} + +static void dcxo_init(void) +{ + u16 tmp; + + rtc_read(PMIC_RG_DCXO_CW00, &tmp); + rtc_info("CW00,0x%x:0x%x\n", PMIC_RG_DCXO_CW00, tmp); + rtc_read(PMIC_RG_DCXO_CW09, &tmp); + rtc_info("CW09,0x%x:0x%x\n", PMIC_RG_DCXO_CW09, tmp); + rtc_read(PMIC_RG_DCXO_CW08, &tmp); + rtc_info("CW08,0x%x:0x%x\n", PMIC_RG_DCXO_CW08, tmp); + /* 26M enable control */ + /* Enable clock buffer XO_SOC */ + rtc_write_field(PMIC_RG_DCXO_CW00, 0x4005, 0xFFFF, 0); + rtc_read(PMIC_RG_DCXO_CW00, &tmp); + rtc_info("CW0,0x%x:0x%x\n", PMIC_RG_DCXO_CW00, tmp); + rtc_write_field(PMIC_RG_DCXO_CW09_CLR, 0x3f, 0x3f, 9); + rtc_read(PMIC_RG_DCXO_CW09, &tmp); + rtc_info("PMIC_RG_DCXO_CW09,0x%x:0x%x\n", PMIC_RG_DCXO_CW09, tmp); + /* Mode and buffer controlled by srclken0 */ + rtc_write_field(PMIC_RG_DCXO_CW08, 0x1, 0x1, 2); + rtc_read(PMIC_RG_DCXO_CW08, &tmp); + rtc_info("PMIC_RG_DCXO_CW08,0x%x:0x%x\n", PMIC_RG_DCXO_CW08, tmp); +} + +void mt6359_dcxo_disable_unused(void) +{ + /* Disable HW BBLPM arbiter */ + //rtc_write_field(PMIC_RG_DCXO_CW12, 0x0, 0x1, 0); + rtc_write_field(PMIC_RG_DCXO_CW12, 0x2, 0x3, 0); +} + +/* the rtc boot flow entry */ +void rtc_boot(void) +{ + u16 tmp; + + /* dcxo clock init settings */ + dcxo_init(); + /* dcxo 32k init settings */ + rtc_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0); + rtc_read(PMIC_RG_SCK_TOP_CON0, &tmp); + rtc_info("PMIC_RG_SCK_TOP_CON0,0x%x:0x%x\n", PMIC_RG_SCK_TOP_CON0, tmp); + rtc_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0); + rtc_read(PMIC_RG_SCK_TOP_CON0, &tmp); + rtc_info("PMIC_RG_SCK_TOP_CON0,0x%x:0x%x\n", PMIC_RG_SCK_TOP_CON0, tmp); + /* use dcxo 32K clock */ + if (!rtc_enable_dcxo()) + rtc_info("rtc_enable_dcxo() failed\n"); + rtc_boot_common(); + rtc_bbpu_power_on(); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/46395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57d6738fdec148c7458b2024a0a8225415ca2f3e Gerrit-Change-Number: 46395 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: devapc: add basic dapc drivers
by Yidi Lin (Code Review) 28 Dec '20

28 Dec '20

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46402 ) Change subject: soc/mediatek/mt8192: devapc: add basic dapc drivers ...................................................................... soc/mediatek/mt8192: devapc: add basic dapc drivers Add basic dapc drivers: 1. init dapc 2. set CPUEB to secure sideband Change-Id: I2ad47c86b88047c76854a6f8a67b251b6a9d4013 Signed-off-by: Nina Wu <nina-cm.wu(a)mediatek.com> --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/devapc.c M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/devapc.h M src/soc/mediatek/mt8192/soc.c 5 files changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/46402/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 5609a06..4ce5e6a 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -47,6 +47,7 @@ ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c +ramstage-y += devapc.c ramstage-y += mcupm.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8192/devapc.c b/src/soc/mediatek/mt8192/devapc.c new file mode 100644 index 0000000..96a2a01 --- /dev/null +++ b/src/soc/mediatek/mt8192/devapc.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <soc/devapc.h> + +static unsigned long devapc_ao_base = (unsigned long)DEVAPC_INFRA_AO_BASE; + +static void master_sec_init(void) +{ + unsigned int val = 0; + + SET32_BITFIELDS(&val, CPU_EB_SEC, 1); + + write32((void*)MAS_SEC, val); + + if (read32((const void*)MAS_SEC) != val) + printk(BIOS_ERR, "[DEVAPC] %s: FAILED to set INFRA MAS_SEC\n", __func__); + else + printk(BIOS_INFO, "[DEVAPC] %s: INFRA MAS_SEC is set to 0x%x\n", __func__, val); +} + +void dapc_init(void) +{ + /* Init dapc */ + write32((void*)AO_APC_CON, 0x1); + + /* Init master sideband */ + master_sec_init(); +} diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index bd9b755..19728a3 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -60,6 +60,7 @@ IOCFG_TL_BASE = IO_PHYS + 0x01F30000, MSDC0_TOP_BASE = IO_PHYS + 0x01F50000, MSDC0_BASE = IO_PHYS + 0x01F60000, + DEVAPC_INFRA_AO_BASE = IO_PHYS + 0x00030000, }; #endif diff --git a/src/soc/mediatek/mt8192/include/soc/devapc.h b/src/soc/mediatek/mt8192/include/soc/devapc.h new file mode 100644 index 0000000..0cd67d3 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/devapc.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_DEVAPC_H +#define SOC_MEDIATEK_MT8192_DEVAPC_H + +#include <device/mmio.h> +#include <soc/addressmap.h> + +void dapc_init(void); + +enum devapc_ao_offset { + OFF_AO_APC_CON = 0x0F00, + OFF_MAS_SEC_0 = 0x0A00, +}; + +#define AO_APC_CON (devapc_ao_base + (unsigned long)OFF_AO_APC_CON) +#define MAS_SEC (devapc_ao_base + (unsigned long)OFF_MAS_SEC_0) + +DEFINE_BIT(CPU_EB_SEC, 4) + +#endif /* SOC_MEDIATEK_MT8192_DEVAPC_H */ diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c index 6deb833..ba153f2 100644 --- a/src/soc/mediatek/mt8192/soc.c +++ b/src/soc/mediatek/mt8192/soc.c @@ -4,6 +4,7 @@ #include <soc/emi.h> #include <soc/mmu_operations.h> #include <symbols.h> +#include <soc/devapc.h> #include <soc/mcupm.h> static void soc_read_resources(struct device *dev) @@ -14,6 +15,7 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + dapc_init(); mcupm_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ad47c86b88047c76854a6f8a67b251b6a9d4013 Gerrit-Change-Number: 46402 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 58

Change in coreboot[master]: soc/mediatek/mt8192: Do dramc before calibration pre-settings
by CK HU (Code Review) 28 Dec '20

28 Dec '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44706 to review the following change. Change subject: soc/mediatek/mt8192: Do dramc before calibration pre-settings ...................................................................... soc/mediatek/mt8192: Do dramc before calibration pre-settings Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9 --- M src/soc/mediatek/mt8192/dramc_pi_basic_api.c M src/soc/mediatek/mt8192/emi.c 2 files changed, 278 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/44706/1 diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c index 08f3ea4..21a5808 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -110,6 +110,273 @@ set_dqO1_pinmux_mapping(cali); } +static u32 get_write_latency_by_mr(u8 mr_wl) +{ + u32 write_latency = 0; + + switch(mr_wl) { + case 0: + write_latency = 4; + break; + case 1: + write_latency = 6; + break; + case 2: + write_latency = 8; + break; + case 3: + write_latency = 10; + break; + case 4: + write_latency = 12; + break; + case 5: + write_latency = 14; + break; + case 6: + write_latency = 16; + break; + case 7: + write_latency = 18; + break; + default: + dramc_info("error: unexpected mr_wl:%x\n", mr_wl); + break; + } + + dramc_info("mr_wl:%x map to WriteLatency:%d\n", mr_wl, write_latency); + return write_latency; +} + +static void tx_path_algorithm(const struct ddr_cali *cali) +{ + u8 write_latency = 0, ckr = 1, wl_mr; + u8 dqs_total_ui = 0; + u8 dqs_oe_total_ui = 0; + u8 dqs_mck, dqs_ui; + u8 dqs_oe_mck, dqs_oe_ui; + u8 small_ui_to_large; + u8 tx_dq_oe_shift = 0; + + wl_mr = (cali->mr_value->mr02[get_fsp(cali)] & 0x3f) >> 3; + small_ui_to_large = get_mck2ui_div_shift(cali); + write_latency = get_write_latency_by_mr(wl_mr); + dqs_total_ui = write_latency * ckr * 2 + 1; + tx_dq_oe_shift = 3; + + dqs_oe_total_ui = dqs_total_ui - tx_dq_oe_shift; + dqs_ui = dqs_total_ui - ((dqs_total_ui >> small_ui_to_large) << small_ui_to_large); + dqs_mck = (dqs_total_ui >> small_ui_to_large); + dqs_oe_ui = dqs_oe_total_ui - ((dqs_oe_total_ui >> small_ui_to_large) + << small_ui_to_large); + dqs_oe_mck = (dqs_oe_total_ui >> small_ui_to_large); + dramc_dbg("[TX_path_calculate] write_latency=%d, DQS_TotalUI=%d\n", + write_latency, dqs_total_ui); + dramc_dbg("[TX_path_calculate] DQS = (%d,%d) DQS_OE = (%d,%d)\n", + dqs_mck, dqs_ui, dqs_oe_mck, dqs_oe_ui); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.shu_selph_dqs0, + SHU_SELPH_DQS0_TXDLY_DQS0, dqs_mck, + SHU_SELPH_DQS0_TXDLY_DQS1, dqs_mck, + SHU_SELPH_DQS0_TXDLY_OEN_DQS0, dqs_oe_mck, + SHU_SELPH_DQS0_TXDLY_OEN_DQS1, dqs_oe_mck); + SET32_BITFIELDS(&ch[chn].ao.shu_selph_dqs1, + SHU_SELPH_DQS1_DLY_DQS0, dqs_ui, + SHU_SELPH_DQS1_DLY_DQS1, dqs_ui, + SHU_SELPH_DQS1_DLY_OEN_DQS0, dqs_oe_ui, + SHU_SELPH_DQS1_DLY_OEN_DQS1, dqs_oe_ui); + } +} + +void cke_fix_onoff(const struct ddr_cali *cali, u8 chn, u8 rank, int option) +{ + u8 cke_on = 0, cke_off = 0; + bool set_rank1 = (rank == RANK_MAX) && (cali->support_ranks == DUAL_RANK_DDR); + + if (option != CKE_DYNAMIC) { + cke_on = option; + cke_off = (1 - option); + } + + if (rank == RANK_0 || rank == RANK_MAX) { + SET32_BITFIELDS(&ch[chn].ao.ckectrl, + CKECTRL_CKEFIXOFF, cke_off, + CKECTRL_CKEFIXON, cke_on); + } + if (rank == RANK_1 || set_rank1) { + SET32_BITFIELDS(&ch[chn].ao.ckectrl, + CKECTRL_CKE1FIXOFF, cke_off, + CKECTRL_CKE1FIXON, cke_on); + } +} + +static void set_cke2rank_independent(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.rkcfg, RKCFG_CKE2RANK, 0); + SET32_BITFIELDS(&ch[chn].ao.ckectrl, + CKECTRL_CKE2RANK_OPT3, 0, + CKECTRL_CKE2RANK_OPT, 0, + CKECTRL_CKE2RANK_OPT2, 1, + CKECTRL_CKE2RANK_OPT5, 0, + CKECTRL_CKE2RANK_OPT6, 0, + CKECTRL_CKE2RANK_OPT7, 1, + CKECTRL_CKE2RANK_OPT8, 0, + CKECTRL_CKETIMER_SEL, 0, + CKECTRL_FASTWAKE_SEL, 1, + CKECTRL_CKEWAKE_SEL, 0); + SET32_BITFIELDS(&ch[chn].ao.shu_dcm_ctrl0, + SHU_DCM_CTRL0_FASTWAKE, 1, + SHU_DCM_CTRL0_FASTWAKE2, 1); + SET32_BITFIELDS(&ch[chn].ao.actiming_ctrl, ACTIMING_CTRL_CLKWITRFC, 0); + } +} + +static void dramc_hw_gating_onoff(bool is_on) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.misc_dvfsctl2, + MISC_DVFSCTL2_R_DVFS_OPTION, is_on, + MISC_DVFSCTL2_R_DVFS_PARK_N, is_on); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_stbcal2, + MISC_STBCAL2_STB_GERRSTOP, is_on); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_STBCALEN, is_on); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_stbcal, + MISC_SHU_STBCAL_STB_SELPHCALEN, is_on); + } +} + +static void dramc_reset_delay_chain_before_calibration(void) +{ + u32 bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + + for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].phy_ao.ca_rk[rk].shu_r0_ca_txdly0, + SHU_R0_CA_TXDLY0_TX_ARCA0_DLY, 0, + SHU_R0_CA_TXDLY0_TX_ARCA1_DLY, 0, + SHU_R0_CA_TXDLY0_TX_ARCA2_DLY, 0, + SHU_R0_CA_TXDLY0_TX_ARCA3_DLY, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.ca_rk[rk].shu_r0_ca_txdly1, + SHU_R0_CA_TXDLY1_TX_ARCA4_DLY, 0, + SHU_R0_CA_TXDLY1_TX_ARCA5_DLY, 0, + SHU_R0_CA_TXDLY1_TX_ARCA6_DLY, 0, + SHU_R0_CA_TXDLY1_TX_ARCA7_DLY, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rk].shu_r0_b0_txdly0, + SHU_R0_B0_TXDLY0_TX_ARDQ0_DLY_B0, 0, + SHU_R0_B0_TXDLY0_TX_ARDQ1_DLY_B0, 0, + SHU_R0_B0_TXDLY0_TX_ARDQ2_DLY_B0, 0, + SHU_R0_B0_TXDLY0_TX_ARDQ3_DLY_B0, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rk].shu_r0_b0_txdly1, + SHU_R0_B0_TXDLY1_TX_ARDQ4_DLY_B0, 0, + SHU_R0_B0_TXDLY1_TX_ARDQ5_DLY_B0, 0, + SHU_R0_B0_TXDLY1_TX_ARDQ6_DLY_B0, 0, + SHU_R0_B0_TXDLY1_TX_ARDQ7_DLY_B0, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rk].shu_r0_b0_txdly0, + SHU_R0_B1_TXDLY0_TX_ARDQ0_DLY_B1, 0, + SHU_R0_B1_TXDLY0_TX_ARDQ1_DLY_B1, 0, + SHU_R0_B1_TXDLY0_TX_ARDQ2_DLY_B1, 0, + SHU_R0_B1_TXDLY0_TX_ARDQ3_DLY_B1, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rk].shu_r0_b0_txdly1, + SHU_R0_B1_TXDLY1_TX_ARDQ4_DLY_B1, 0, + SHU_R0_B1_TXDLY1_TX_ARDQ5_DLY_B1, 0, + SHU_R0_B1_TXDLY1_TX_ARDQ6_DLY_B1, 0, + SHU_R0_B1_TXDLY1_TX_ARDQ7_DLY_B1, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].rk[rk].shu_r0_b0_txdly3, + SHU_R0_B0_TXDLY3_TX_ARDQM0_DLY_B0, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].rk[rk].shu_r0_b0_txdly3, + SHU_R0_B1_TXDLY3_TX_ARDQM0_DLY_B1, 0x0); + } + } + + dramc_set_broadcast(bc_bak); +} + +static void dramc_init(const struct ddr_cali *cali) +{ + dramc_reset_delay_chain_before_calibration(); +} + +static void dramc_before_calibration(const struct ddr_cali *cali) +{ + u8 ma_type = get_column_num(); + dram_freq_grp freq_group = cali->freq_group; + u8 dis_imp_hw = (freq_group > DDRFREQ_1200) ? 0: 1; + + dramc_hw_gating_onoff(false); + + cke_fix_onoff(cali, CHANNEL_A, RANK_MAX, CKE_FIXON); + cke_fix_onoff(cali, CHANNEL_B, RANK_MAX, CKE_FIXON); + + set_cke2rank_independent(); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.shu_tx_set0, SHU_TX_SET0_DBIWR, 0x0); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_shu_impedamce_upd_dis1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_ODTN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DRVP_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_ODTN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQ_DRVP_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_ODTN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVN_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_DQS_DRVP_UPD_DIS, dis_imp_hw, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVP_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_DRVN_UPD_DIS, 1, + MISC_SHU_IMPEDAMCE_UPD_DIS1_WCK_ODTN_UPD_DIS, 1); + + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_impcal1, + SHU_MISC_IMPCAL1_IMPCALCNT, (dis_imp_hw? 0x0:0x40)); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_drving1, + SHU_MISC_DRVING1_DIS_IMPCAL_HW, dis_imp_hw); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_drving1, + SHU_MISC_DRVING1_DIS_IMP_ODTN_TRACK, dis_imp_hw); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_misc_drving2, + SHU_MISC_DRVING2_DIS_IMPCAL_ODT_EN, dis_imp_hw); + SET32_BITFIELDS(&ch[chn].phy_ao.shu_ca_cmd12, + SHU_CA_CMD12_RG_RIMP_UNTERM_EN, dis_imp_hw); + SET32_BITFIELDS(&ch[chn].phy_ao.misc_clk_ctrl, + MISC_CLK_CTRL_DVFS_CLK_MEM_SEL, 0, + MISC_CLK_CTRL_DVFS_MEM_CK_MUX_UPDATE_EN, 0); + SET32_BITFIELDS(&ch[chn].ao.shu_zq_set0, + SHU_ZQ_SET0_ZQCSCNT, 0x1ff, + SHU_ZQ_SET0_TZQLAT, 0x1b); + SET32_BITFIELDS(&ch[chn].ao.zq_set0, + ZQ_SET0_ZQCSDUAL, 1, + ZQ_SET0_ZQCSMASK_OPT, 0, + ZQ_SET0_ZQMASK_CGAR, 0, + ZQ_SET0_ZQCS_MASK_SEL_CGAR, 0); + } + SET32_BITFIELDS(&ch[0].ao.zq_set0, ZQ_SET0_ZQCSMASK, 1); + SET32_BITFIELDS(&ch[1].ao.zq_set0, ZQ_SET0_ZQCSMASK, 0); + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.zq_set0, ZQ_SET0_ZQCS_MASK_SEL, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[0].shu_b0_dq2, + SHU_B0_DQ2_RG_ARPI_OFFSET_LAT_EN_B0, 0); + SET32_BITFIELDS(&ch[chn].phy_ao.byte[1].shu_b0_dq2, + SHU_B1_DQ2_RG_ARPI_OFFSET_LAT_EN_B1, 0); + SET32_BITFIELDS(&ch[chn].ao.dcm_sub_ctrl, + DCM_SUB_CTRL_SUBCLK_CTRL_TX_AUTOK, 0x0); + SET32_BITFIELDS(&ch[chn].ao.dcm_sub_ctrl, + DCM_SUB_CTRL_SUBCLK_CTRL_TX_TRACKING, 0); + SET32_BITFIELDS(&ch[chn].ao.dqsoscr, DQSOSCR_DQSOSCRDIS, 0x1); + SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, 0x1); + SET32_BITFIELDS(&ch[chn].ao.shu_matype, SHU_MATYPE_MATYPE, ma_type); + } + tx_path_algorithm(cali); +} + void dfs_init_for_calibration(const struct ddr_cali *cali) { + dramc_init(cali); + dramc_before_calibration(cali); } + diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c index eb110cc..b587993 100644 --- a/src/soc/mediatek/mt8192/emi.c +++ b/src/soc/mediatek/mt8192/emi.c @@ -309,6 +309,17 @@ write32(&ch[chn].emi_chn.cona, emi_con->chn_cona_val); } +u32 get_column_num(void) +{ + u32 ma_type = read32(&emi_reg->cona); + u32 ma_type_r0 = ((ma_type >> 20) & 0x3) + 1; + u32 ma_type_r1 = ((ma_type >> 22) & 0x3) + 1; + + ma_type = (ma_type_r0 > ma_type_r1) ? ma_type_r1 : ma_type_r0; + + return ma_type; +} + static void emi_sw_setting(void) { setbits32(&emi_mpu->mpu_ctrl_d[1], BIT(4)); -- To view, visit https://review.coreboot.org/c/coreboot/+/44706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I071eca037f89a916d6cfaf5b008d64f2b4a269a9 Gerrit-Change-Number: 44706 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

7 25

Change in coreboot[master]: crossgcc: Upgrade Expat to version 2.2.10
by HAOUAS Elyes (Code Review) 28 Dec '20

28 Dec '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46108 ) Change subject: crossgcc: Upgrade Expat to version 2.2.10 ...................................................................... crossgcc: Upgrade Expat to version 2.2.10 Change-Id: I3da314d2696acb990918a6fae9750896a16dec8d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc A util/crossgcc/sum/expat-2.2.10.tar.bz2.cksum D util/crossgcc/sum/expat-2.2.9.tar.bz2.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/46108/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 10aa04f..ca35b43 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -42,7 +42,7 @@ GDB_VERSION=9.2 IASL_VERSION=20200717 PYTHON_VERSION=3.9.0 -EXPAT_VERSION=2.2.9 +EXPAT_VERSION=2.2.10 # CLANG version number CLANG_VERSION=10.0.1 CMAKE_VERSION=3.18.1 diff --git a/util/crossgcc/sum/expat-2.2.10.tar.bz2.cksum b/util/crossgcc/sum/expat-2.2.10.tar.bz2.cksum new file mode 100644 index 0000000..2e175fe --- /dev/null +++ b/util/crossgcc/sum/expat-2.2.10.tar.bz2.cksum @@ -0,0 +1 @@ +0a9f06081d92ddea17b8b9f4086b3f68e337bf8f tarballs/expat-2.2.10.tar.bz2 diff --git a/util/crossgcc/sum/expat-2.2.9.tar.bz2.cksum b/util/crossgcc/sum/expat-2.2.9.tar.bz2.cksum deleted file mode 100644 index 924b412..0000000 --- a/util/crossgcc/sum/expat-2.2.9.tar.bz2.cksum +++ /dev/null @@ -1 +0,0 @@ -ef5c1c55913a6ab18496ee99166f86269c7cdc31 tarballs/expat-2.2.9.tar.bz2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3da314d2696acb990918a6fae9750896a16dec8d Gerrit-Change-Number: 46108 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: crossgcc: Upgrade Python to version 3.8.6
by HAOUAS Elyes (Code Review) 28 Dec '20

28 Dec '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45725 ) Change subject: crossgcc: Upgrade Python to version 3.8.6 ...................................................................... crossgcc: Upgrade Python to version 3.8.6 Change-Id: I07fa420921bdfcbacde48db486873f92e2630fc8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/Python-3.8.5.tar.xz.cksum A util/crossgcc/sum/Python-3.8.6.tar.xz.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/45725/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 0f9cac5..11cd2f5 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -41,7 +41,7 @@ BINUTILS_VERSION=2.35 GDB_VERSION=9.2 IASL_VERSION=20200717 -PYTHON_VERSION=3.8.5 +PYTHON_VERSION=3.8.6 EXPAT_VERSION=2.2.9 # CLANG version number CLANG_VERSION=10.0.1 diff --git a/util/crossgcc/sum/Python-3.8.5.tar.xz.cksum b/util/crossgcc/sum/Python-3.8.5.tar.xz.cksum deleted file mode 100644 index 2f4d4ad..0000000 --- a/util/crossgcc/sum/Python-3.8.5.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -68d6c7f948801cc755905162f5ee7589595edee4 tarballs/Python-3.8.5.tar.xz diff --git a/util/crossgcc/sum/Python-3.8.6.tar.xz.cksum b/util/crossgcc/sum/Python-3.8.6.tar.xz.cksum new file mode 100644 index 0000000..9d29116 --- /dev/null +++ b/util/crossgcc/sum/Python-3.8.6.tar.xz.cksum @@ -0,0 +1 @@ +6ee446eaacf901a3305565bd6569e2de135168e3 tarballs/Python-3.8.6.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/45725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07fa420921bdfcbacde48db486873f92e2630fc8 Gerrit-Change-Number: 45725 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: [RFC] vpd: Add vpd_get_int() function
by Nico Huber (Code Review) 27 Dec '20

27 Dec '20

Hello Martin Roth, Marc Jones, Johnny Lin, Angel Pons, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45773 to review the following change. Change subject: [RFC] vpd: Add vpd_get_int() function ...................................................................... [RFC] vpd: Add vpd_get_int() function Change-Id: I1c1b5710a5236fe4a3bdda1fc978393e636e9817 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/drivers/vpd/vpd.c M src/drivers/vpd/vpd.h 2 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/45773/1 diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index c332a6e..d3ff370 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -3,10 +3,12 @@ #include <assert.h> #include <console/console.h> #include <cbmem.h> +#include <ctype.h> #include <fmap.h> #include <program_loading.h> #include <string.h> #include <timestamp.h> +#include <types.h> #include "vpd.h" #include "vpd_decode.h" @@ -274,4 +276,25 @@ return false; } +/* + * Find value of integer type by vpd key. + * + * Expects to find a decimal string, trailing chars are ignored. + * Returns true if the key is found and the value is not too long and + * starts with a decimal digit. Leaves `val` untouched if unsuccessful. + */ +bool vpd_get_int(const char *const key, const enum vpd_region region, int *const val) +{ + char value[11]; + + if (!vpd_gets(key, value, sizeof(value), region)) + return false; + + if (!isdigit(*value)) + return false; + + *val = (int)atol(value); + return true; +} + ROMSTAGE_CBMEM_INIT_HOOK(cbmem_add_cros_vpd) diff --git a/src/drivers/vpd/vpd.h b/src/drivers/vpd/vpd.h index 25e0aed..817867a 100644 --- a/src/drivers/vpd/vpd.h +++ b/src/drivers/vpd/vpd.h @@ -50,4 +50,13 @@ bool vpd_get_bool(const char *key, enum vpd_region region, uint8_t *val); +/* + * Find value of integer type by vpd key. + * + * Expects to find a decimal string, trailing chars are ignored. + * Returns true if the key is found and the value is not too long and + * starts with a decimal digit. + */ +bool vpd_get_int(const char *key, enum vpd_region region, int *val); + #endif /* __VPD_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c1b5710a5236fe4a3bdda1fc978393e636e9817 Gerrit-Change-Number: 45773 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Marc Jones <marc.jones(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: src: Move DEFAULT_MCHBAR to Kconfig
by HAOUAS Elyes (Code Review) 27 Dec '20

27 Dec '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45610 ) Change subject: src: Move DEFAULT_MCHBAR to Kconfig ...................................................................... src: Move DEFAULT_MCHBAR to Kconfig Change-Id: Idca25b2e4bf65abcb3f8b150452ab2567baa60c3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asus/p8z77-m_pro/early_init.c M src/mainboard/dell/optiplex_9010/early_init.c M src/mainboard/google/butterfly/early_init.c M src/mainboard/google/link/early_init.c M src/mainboard/google/parrot/early_init.c M src/mainboard/google/stout/early_init.c M src/mainboard/intel/dcp847ske/romstage.c M src/mainboard/intel/emeraldlake2/early_init.c M src/mainboard/kontron/ktqm77/early_init.c M src/mainboard/lenovo/x220/early_init.c M src/mainboard/roda/rv11/variants/rv11/early_init.c M src/mainboard/roda/rv11/variants/rw11/early_init.c M src/mainboard/samsung/lumpy/early_init.c M src/mainboard/samsung/stumpy/early_init.c A src/northbridge/intel/Kconfig M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/gm45/acpi/gm45.asl M src/northbridge/intel/gm45/early_init.c M src/northbridge/intel/gm45/gm45.h M src/northbridge/intel/gm45/pcie.c M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/haswell/acpi/haswell.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/memmap.h M src/northbridge/intel/haswell/romstage.c M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/i945/acpi/i945.asl M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/i945.h M src/northbridge/intel/ironlake/Kconfig M src/northbridge/intel/ironlake/acpi/hostbridge.asl M src/northbridge/intel/ironlake/acpi/ironlake.asl M src/northbridge/intel/ironlake/early_init.c M src/northbridge/intel/ironlake/ironlake.h M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/pineview/acpi/pineview.asl M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/memmap.h M src/northbridge/intel/pineview/pineview.h M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/memmap.h M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/sandybridge.h M src/northbridge/intel/x4x/Kconfig M src/northbridge/intel/x4x/acpi/x4x.asl M src/northbridge/intel/x4x/early_init.c M src/northbridge/intel/x4x/iomap.h M src/northbridge/intel/x4x/x4x.h 51 files changed, 88 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/45610/1 diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index 81eb6f4..b5c23bc 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -85,7 +85,7 @@ struct pei_data pd = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/dell/optiplex_9010/early_init.c b/src/mainboard/dell/optiplex_9010/early_init.c index e96ee34..4947ff0 100644 --- a/src/mainboard/dell/optiplex_9010/early_init.c +++ b/src/mainboard/dell/optiplex_9010/early_init.c @@ -32,8 +32,8 @@ * FIXME: the board gets stuck in reset loop in * mainboard_romstage_entry. Avoid that by clearing SSKPD */ - pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + CONFIG_DEFAULT_MCHBAR) >> 32); MCHBAR16(SSKPD_HI) = 0; sch5545_early_init(0x2e); diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index 2ffa3aa..ecfdfab 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -79,7 +79,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index f3da77c..f8e8553 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -86,7 +86,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index f0ffc9f..68e7905 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -54,7 +54,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index f2f21bc..8fd923f 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -91,7 +91,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index 391d1f2..c83a110 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -14,7 +14,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index a2aaf33b..a44ee24 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -51,7 +51,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index d1aa9d5..85c87c1 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -56,7 +56,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index bb120bf..f08ea8c 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -12,7 +12,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c index 5b55873..fc0eaec 100644 --- a/src/mainboard/roda/rv11/variants/rv11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c @@ -10,7 +10,7 @@ { const struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c index 7076eb7..f43b21a 100644 --- a/src/mainboard/roda/rv11/variants/rw11/early_init.c +++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c @@ -40,7 +40,7 @@ { const struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index ad4ddb9..3c1887a 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -117,7 +117,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index 7d4a9a4..03ddf21 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -101,7 +101,7 @@ { struct pei_data pei_data_template = { .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, + .mchbar = CONFIG_DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig new file mode 100644 index 0000000..3c2bb66 --- /dev/null +++ b/src/northbridge/intel/Kconfig @@ -0,0 +1,4 @@ +#SPDX-License-Identifier: GPL-2.0-or-later + +config DEFAULT_MCHBAR + hex diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index f5d6712..788e15a 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -14,6 +14,10 @@ select INTEL_GMA_SSC_ALTERNATE_REF select PARALLEL_MP +config DEFAULT_MCHBAR + hex + default 0xfed14000 + config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl index af58e0e..2051afa 100644 --- a/src/northbridge/intel/gm45/acpi/gm45.asl +++ b/src/northbridge/intel/gm45/acpi/gm45.asl @@ -14,7 +14,7 @@ // now. Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c index 1be3518..25daf38 100644 --- a/src/northbridge/intel/gm45/early_init.c +++ b/src/northbridge/intel/gm45/early_init.c @@ -9,7 +9,7 @@ const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0); /* Setup MCHBAR. */ - pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)CONFIG_DEFAULT_MCHBAR | 1); /* Setup DMIBAR. */ pci_write_config32(d0f0, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1); diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index dc993cf..fe5a265 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -171,10 +171,8 @@ (could be reduced to 10 bytes) */ #ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed14000) #define DEFAULT_DMIBAR ((u8 *)0xfed18000) #else -#define DEFAULT_MCHBAR 0xfed14000 #define DEFAULT_DMIBAR 0xfed18000 #endif #define DEFAULT_EPBAR 0xfed19000 @@ -237,9 +235,9 @@ * MCHBAR */ -#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR8(x) *((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + x)) +#define MCHBAR16(x) *((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + x)) +#define MCHBAR32(x) *((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + x)) #define HPLLVCO_MCHBAR 0x0c0f diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c index 5a4999e..ffb52c8 100644 --- a/src/northbridge/intel/gm45/pcie.c +++ b/src/northbridge/intel/gm45/pcie.c @@ -268,7 +268,7 @@ /* Link2: component ID 1 (MCH), link valid */ DMIBAR32(DMILE2D) = (DMIBAR32(DMILE2D) & 0xff000000) | (1 << 16) | (1 << 0); - DMIBAR32(DMILE2A) = (uintptr_t)DEFAULT_MCHBAR; + DMIBAR32(DMILE2A) = (uintptr_t)CONFIG_DEFAULT_MCHBAR; } void gm45_late_init(const stepping_t stepping) diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 84be33d..5152645 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -9,6 +9,10 @@ if NORTHBRIDGE_INTEL_HASWELL +config DEFAULT_MCHBAR + hex + default 0xfed10000 + config HASWELL_VBOOT_IN_BOOTBLOCK depends on VBOOT bool "Start verstage in bootblock" diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl index 4a9debf..243cb25 100644 --- a/src/northbridge/intel/haswell/acpi/haswell.asl +++ b/src/northbridge/intel/haswell/acpi/haswell.asl @@ -13,7 +13,7 @@ Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) + Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 1d4eba6..e42c356 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -88,7 +88,7 @@ Name (CTCU, 2) /* CTDP Up Select */ Name (SPL1, 0) /* Saved PL1 value */ - OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR + 0x5000, 0x1000) + OperationRegion (MCHB, SystemMemory, CONFIG_DEFAULT_MCHBAR + 0x5000, 0x1000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x930), /* PACKAGE_POWER_SKU */ diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 9db6a9d..b9c2c03 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -16,8 +16,8 @@ /* Set up all hardcoded northbridge BARs */ pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + CONFIG_DEFAULT_MCHBAR) >> 32); pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 4bcaaa7..a1125ab 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -28,9 +28,9 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) diff --git a/src/northbridge/intel/haswell/memmap.h b/src/northbridge/intel/haswell/memmap.h index ac3b1db..2c1aa6a 100644 --- a/src/northbridge/intel/haswell/memmap.h +++ b/src/northbridge/intel/haswell/memmap.h @@ -7,7 +7,6 @@ #define IED_SIZE CONFIG_IED_REGION_SIZE /* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 5b025eb..f922e68 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -47,7 +47,7 @@ struct pei_data pei_data = { .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .mchbar = (uintptr_t)CONFIG_DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index d6498f1..0499a7c 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -15,6 +15,10 @@ select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select PARALLEL_MP +config DEFAULT_MCHBAR + hex + default 0xfed14000 + config VBOOT select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl index 789225c..76a50f0 100644 --- a/src/northbridge/intel/i945/acpi/i945.asl +++ b/src/northbridge/intel/i945/acpi/i945.asl @@ -39,7 +39,7 @@ Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index b04a2f594..0bdcd17 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -145,7 +145,7 @@ printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR, (uintptr_t)CONFIG_DEFAULT_MCHBAR | 1); pci_write_config32(HOST_BRIDGE, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); pci_write_config32(HOST_BRIDGE, X60BAR, DEFAULT_X60BAR | 1); diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 4b79b2b..96623be 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -6,10 +6,8 @@ /* Northbridge BARs */ #define DEFAULT_X60BAR 0xfed13000 #ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed14000) /* 16 KB */ #define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ #else -#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #endif #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ @@ -99,9 +97,9 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + (x)))) /* Chipset Control Registers */ #define FSBPMC3 0x40 /* 32bit */ diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig index fbad4be..4c77849 100644 --- a/src/northbridge/intel/ironlake/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -11,6 +11,10 @@ if NORTHBRIDGE_INTEL_IRONLAKE +config DEFAULT_MCHBAR + hex + default 0xfed10000 + config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK diff --git a/src/northbridge/intel/ironlake/acpi/hostbridge.asl b/src/northbridge/intel/ironlake/acpi/hostbridge.asl index d6a2cf8..bdfd281 100644 --- a/src/northbridge/intel/ironlake/acpi/hostbridge.asl +++ b/src/northbridge/intel/ironlake/acpi/hostbridge.asl @@ -48,7 +48,7 @@ Name (CTCD, 1) /* CTDP Down Select */ Name (CTCU, 2) /* CTDP Up Select */ - OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000) + OperationRegion (MCHB, SystemMemory, CONFIG_DEFAULT_MCHBAR, 0x8000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x5930), diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl index 3cf597d..4a09ee1 100644 --- a/src/northbridge/intel/ironlake/acpi/ironlake.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -12,7 +12,7 @@ Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) + Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR, 0x00008000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index fa89bd9..7b4c11f 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -19,7 +19,7 @@ /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, 0); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)CONFIG_DEFAULT_MCHBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, 0); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, 0); diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index 7ed6afd..20de8f5 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -26,10 +26,8 @@ /* Northbridge BARs */ #ifndef __ACPI__ -#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ #define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ #else -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #endif #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ @@ -100,9 +98,9 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index a1b0894..7d2f7b1 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -15,6 +15,10 @@ select INTEL_GMA_ACPI select PARALLEL_MP +config DEFAULT_MCHBAR + hex + default 0xfed14000 + config VGA_BIOS_ID string default "8086,a001" diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index 9515c31..1e6cf4d 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -14,7 +14,7 @@ Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x10000000) diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 42a68d8..7a7cc32 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -137,7 +137,7 @@ /* Set up all hardcoded northbridge BARs */ pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_DEFAULT_MCHBAR | 1); pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(HOST_BRIDGE, PMIOBAR, DEFAULT_PMIOBAR | 1); diff --git a/src/northbridge/intel/pineview/memmap.h b/src/northbridge/intel/pineview/memmap.h index 50ede0b..0075cd9 100644 --- a/src/northbridge/intel/pineview/memmap.h +++ b/src/northbridge/intel/pineview/memmap.h @@ -3,7 +3,6 @@ #ifndef PINEVIEW_MEMMAP_H #define PINEVIEW_MEMMAP_H -#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define DEFAULT_PMIOBAR 0x00000400 diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index 03fa318..0df17a5 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -38,9 +38,9 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) /* FIXME: causes changes */ +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + x))) /* FIXME: causes changes */ #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index ef6dc3d..8ab557d 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -9,6 +9,10 @@ if NORTHBRIDGE_INTEL_SANDYBRIDGE +config DEFAULT_MCHBAR + hex + default 0xfed10000 + config SANDYBRIDGE_VBOOT_IN_ROMSTAGE bool default n diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 45b5b8f..92165b0 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -52,8 +52,8 @@ /* Set up all hardcoded northbridge BARs */ pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + CONFIG_DEFAULT_MCHBAR) >> 32); pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); diff --git a/src/northbridge/intel/sandybridge/memmap.h b/src/northbridge/intel/sandybridge/memmap.h index 9825125..bd40252 100644 --- a/src/northbridge/intel/sandybridge/memmap.h +++ b/src/northbridge/intel/sandybridge/memmap.h @@ -4,7 +4,6 @@ #define __NORTHBRIDGE_INTEL_SANDYBRIDGE_MEMMAP_H__ /* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 697862f..b9defda 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -229,7 +229,7 @@ static void northbridge_fill_pei_data(struct pei_data *pei_data) { - pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; + pei_data->mchbar = (uintptr_t)CONFIG_DEFAULT_MCHBAR; pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; pei_data->epbar = DEFAULT_EPBAR; pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 8f9d118..fdb1795 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -49,9 +49,9 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 27754c8..b76c78c 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -13,6 +13,10 @@ select CACHE_MRC_SETTINGS select PARALLEL_MP +config DEFAULT_MCHBAR + hex + default 0xfed14000 + config CBFS_SIZE hex default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl index 51deea8..ee30098 100644 --- a/src/northbridge/intel/x4x/acpi/x4x.asl +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -12,7 +12,7 @@ Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000) - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) + Memory32Fixed(ReadWrite, CONFIG_DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index d3c3308..4921774 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -16,7 +16,7 @@ void x4x_early_init(void) { /* Setup MCHBAR. */ - pci_write_config32(HOST_BRIDGE, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); + pci_write_config32(HOST_BRIDGE, D0F0_MCHBAR_LO, (uintptr_t)CONFIG_DEFAULT_MCHBAR | 1); /* Setup DMIBAR. */ pci_write_config32(HOST_BRIDGE, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1); diff --git a/src/northbridge/intel/x4x/iomap.h b/src/northbridge/intel/x4x/iomap.h index 22a675f..03b1b18 100644 --- a/src/northbridge/intel/x4x/iomap.h +++ b/src/northbridge/intel/x4x/iomap.h @@ -3,7 +3,6 @@ #ifndef X4X_IOMAP_H #define X4X_IOMAP_H -#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define DEFAULT_HECIBAR 0xfed10000 diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 45785a0..95c79e2 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -40,9 +40,9 @@ * MCHBAR */ -#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8(x) (*((volatile u8 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(CONFIG_DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(CONFIG_DEFAULT_MCHBAR + (x)))) #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) #define MCHBAR8_AND_OR(x, and, or) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/45610 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idca25b2e4bf65abcb3f8b150452ab2567baa60c3 Gerrit-Change-Number: 45610 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

7 39

Change in ...coreboot[master]: superio/ite: Add and use it8528e
by Patrick Rudolph (Code Review) 26 Dec '20

26 Dec '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30957 Change subject: superio/ite: Add and use it8528e ...................................................................... superio/ite: Add and use it8528e * Add SuperIO ITE8528E * Use ITE8528E to configure serial on wedge100s TODO: Add support for accessing EC space. Tested on wedge100s. The serial works without CONFIG_CONSOLE_SERIAL. Change-Id: I72aa756e123d6f99d9ef4fe955c4b7f1be25d547 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/ocp/wedge100s/Kconfig M src/mainboard/ocp/wedge100s/devicetree.cb M src/superio/ite/Makefile.inc A src/superio/ite/it8528e/Kconfig A src/superio/ite/it8528e/Makefile.inc A src/superio/ite/it8528e/chip.h A src/superio/ite/it8528e/it8528e.h A src/superio/ite/it8528e/superio.c 8 files changed, 226 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/30957/1 diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig index ce9c097..6224340 100644 --- a/src/mainboard/ocp/wedge100s/Kconfig +++ b/src/mainboard/ocp/wedge100s/Kconfig @@ -16,6 +16,7 @@ select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 select DRIVERS_UART_8250IO + select SUPERIO_ITE_IT8528E config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/ocp/wedge100s/devicetree.cb b/src/mainboard/ocp/wedge100s/devicetree.cb index 3d66d0d..fc6dccc 100644 --- a/src/mainboard/ocp/wedge100s/devicetree.cb +++ b/src/mainboard/ocp/wedge100s/devicetree.cb @@ -11,6 +11,58 @@ chip drivers/pc80/tpm device pnp 0c31.0 on end end + chip superio/ite/it8528e + # COM1, routed to COM-e header + device pnp 6e.1 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + # COM2, routed to COM-e header + device pnp 6e.2 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 6e.4 off end + device pnp 6e.5 off end + device pnp 6e.6 off end + device pnp 6e.a off end + device pnp 6e.f off end + device pnp 6e.10 off + io 0x60 = 0x70 + io 0x62 = 0x72 + irq 0x70 = 8 + end + device pnp 6e.11 off + io 0x60 = 0x620 + io 0x62 = 0x660 + irq 0x70 = 1 + end + device pnp 6e.12 off + io 0x60 = 0x680 + io 0x62 = 0x6c0 + irq 0x70 = 1 + end + device pnp 6e.13 off + io 0x60 = 0x300 + irq 0x70 = 2 + end + device pnp 6e.14 off end + device pnp 6e.17 off + io 0x60 = 0x6a0 + io 0x62 = 0x6e0 + irq 0x70 = 1 + end + device pnp 6e.18 off + io 0x60 = 0x740 + io 0x62 = 0x780 + irq 0x70 = 1 + end + device pnp 6e.19 off + io 0x60 = 0x7a0 + io 0x62 = 0x7c0 + irq 0x70 = 1 + end + end #superio/ite/it8528e end # LPC Bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus Controller diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index e73fd71..551abe9 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -20,6 +20,7 @@ ## include generic ite environment controller driver ramstage-$(CONFIG_SUPERIO_ITE_ENV_CTRL) += common/env_ctrl.c +subdirs-y += it8528e subdirs-y += it8623e subdirs-y += it8671f subdirs-y += it8712f diff --git a/src/superio/ite/it8528e/Kconfig b/src/superio/ite/it8528e/Kconfig new file mode 100644 index 0000000..3815c28 --- /dev/null +++ b/src/superio/ite/it8528e/Kconfig @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ITE_IT8528E + bool + select SUPERIO_ITE_COMMON_PRE_RAM diff --git a/src/superio/ite/it8528e/Makefile.inc b/src/superio/ite/it8528e/Makefile.inc new file mode 100644 index 0000000..def04e5 --- /dev/null +++ b/src/superio/ite/it8528e/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8528E) += superio.c diff --git a/src/superio/ite/it8528e/chip.h b/src/superio/ite/it8528e/chip.h new file mode 100644 index 0000000..ef7e14f --- /dev/null +++ b/src/superio/ite/it8528e/chip.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8528E_CHIP_H +#define SUPERIO_ITE_IT8528E_CHIP_H + +#include <superio/ite/common/env_ctrl_chip.h> + +struct superio_ite_it8528e_config { + // FIXME: Add support for EC +}; + +#endif /* SUPERIO_ITE_IT8528E_CHIP_H */ diff --git a/src/superio/ite/it8528e/it8528e.h b/src/superio/ite/it8528e/it8528e.h new file mode 100644 index 0000000..7b19349 --- /dev/null +++ b/src/superio/ite/it8528e/it8528e.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Patrick Rudolph <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8528E_H +#define SUPERIO_ITE_IT8528E_H + +#define IT8528E_SP1 0x01 /* Com1 */ +#define IT8528E_SP2 0x02 /* Com2 */ +#define IT8528E_SWUC 0x04 /* System Wake-Up */ +#define IT8528E_KBCM 0x05 /* PS/2 mouse */ +#define IT8528E_KBCK 0x06 /* PS/2 keyboard */ +#define IT8528E_IR 0x0a /* Consumer IR */ +#define IT8528E_SMFI 0x0f /* Shared Memory/Flash Interface */ +#define IT8528E_RTCT 0x10 /* RTC-like Timer */ +#define IT8528E_PMC1 0x11 /* Power Management Channel 1 */ +#define IT8528E_PMC2 0x12 /* Power Management Channel 2 */ +#define IT8528E_SSPI 0x13 /* Serial Periphial Interface */ +#define IT8528E_PECI 0x14 /* Platform EC Interface */ +#define IT8528E_PMC3 0x17 /* Power Management Channel 3 */ +#define IT8528E_PMC4 0x18 /* Power Management Channel 4 */ +#define IT8528E_PMC5 0x19 /* Power Management Channel 5 */ + + +#endif /* SUPERIO_ITE_IT8528E_H */ diff --git a/src/superio/ite/it8528e/superio.c b/src/superio/ite/it8528e/superio.c new file mode 100644 index 0000000..ae2a8e9 --- /dev/null +++ b/src/superio/ite/it8528e/superio.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2007 Philipp Degler <pdegler(a)rumms.uni-mannheim.de> + * Copyright (C) 2017 Gergely Kiss <mail.gery(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <arch/io.h> +#include <stdlib.h> +#include <superio/conf_mode.h> + +#include "chip.h" +#include "it8528e.h" + +static void it8528e_init(struct device *dev) +{ + // FIXME: Init EC +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8528e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, IT8528E_SP1, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8528E_SP2, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, + { NULL, IT8528E_SWUC, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + { NULL, IT8528E_KBCM, PNP_IRQ0, }, + /* Documentation: Programm io0 = 0x60 and io1 = 0x64 */ + { NULL, IT8528E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, 0x07ff, 0x07ff, }, + { NULL, IT8528E_IR, PNP_IO0 | PNP_IRQ0, 0xfff8, }, + { NULL, IT8528E_SMFI, PNP_IO0 | PNP_IRQ0, 0xfff0, }, + /* Documentation: Programm io0 = 0x70 and io1 = 0x272 */ + { NULL, IT8528E_RTCT, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0, + 0xfffe, 0xfffe, 0xfffe, 0xfffe}, + /* Documentation: Programm io0 = 0x62 and io1 = 0x66 */ + { NULL, IT8528E_PMC1, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff }, + { NULL, IT8528E_PMC2, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0 , 0x07fc, + 0x07fc, 0xfff0 }, + /* Documentation is unclear if PMC3-5 have LPC I/O decoding support */ + { NULL, IT8528E_PMC3, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff }, + { NULL, IT8528E_PMC4, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff }, + { NULL, IT8528E_PMC5, PNP_IO0 | PNP_IO1 | PNP_IRQ0 , 0x07ff, 0x07ff }, + { NULL, IT8528E_SSPI, PNP_IO0 | PNP_IRQ0, 0xfff8 }, + { NULL, IT8528E_PECI, PNP_IO0 , 0xfff8 }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8528e_ops = { + CHIP_NAME("ITE IT8528E Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/30957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72aa756e123d6f99d9ef4fe955c4b7f1be25d547 Gerrit-Change-Number: 30957 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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