coreboot-gerrit June 2019

coreboot-gerrit@coreboot.org

1 participants
1454 discussions

Change in ...coreboot[master]: MAINTAINERS: Add myself as a maintainer for apple boards
by Evgeny Zinoviev (Code Review) 28 Jun '19

28 Jun '19

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33148 Change subject: MAINTAINERS: Add myself as a maintainer for apple boards ...................................................................... MAINTAINERS: Add myself as a maintainer for apple boards Change-Id: I33bf45c81cc4be157ea71806900a545ee68ecee8 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M MAINTAINERS 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/33148/1 diff --git a/MAINTAINERS b/MAINTAINERS index 04f784f..9905540 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -164,6 +164,11 @@ S: Maintained F: src/mainboard/lenovo/ +APPLE MAINBOARDS +M: Evgeny Zinoviev <me(a)ch1p.io> +S: Maintained +F: src/mainboard/apple/ + GETAC P470 MAINBOARD M: Patrick Georgi <patrick(a)georgi.software> S: Maintained -- To view, visit https://review.coreboot.org/c/coreboot/+/33148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33bf45c81cc4be157ea71806900a545ee68ecee8 Gerrit-Change-Number: 33148 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: {soc,northbridge}/Kconfig: Remove unused CACHE_MRC_SIZE_KB
by HAOUAS Elyes (Code Review) 28 Jun '19

28 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33743 Change subject: {soc,northbridge}/Kconfig: Remove unused CACHE_MRC_SIZE_KB ...................................................................... {soc,northbridge}/Kconfig: Remove unused CACHE_MRC_SIZE_KB Change-Id: Ie922832bc7641a44a53c0cda8d808579c66420b5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/sandybridge/Kconfig M src/soc/intel/broadwell/Kconfig 3 files changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/33743/1 diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index e1067c5..3678cb8 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -55,10 +55,6 @@ hex default 0xf0000000 -config CACHE_MRC_SIZE_KB - int - default 512 - config DCACHE_RAM_BASE hex default 0xff7c0000 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 59cf92c..53725ca 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -64,10 +64,6 @@ string default "8086,0106" -config CACHE_MRC_SIZE_KB - int - default 512 - config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/intel/sandybridge/bootblock.c" diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index d81ab8a..801800c 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -106,10 +106,6 @@ string default "8086,0406" -config CACHE_MRC_SIZE_KB - int - default 512 - config DCACHE_RAM_BASE hex default 0xff7c0000 -- To view, visit https://review.coreboot.org/c/coreboot/+/33743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie922832bc7641a44a53c0cda8d808579c66420b5 Gerrit-Change-Number: 33743 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: soc/intel/cannonlake: set use of legacy 8254 timer
by Matt DeVillier (Code Review) 28 Jun '19

28 Jun '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33512 Change subject: soc/intel/cannonlake: set use of legacy 8254 timer ...................................................................... soc/intel/cannonlake: set use of legacy 8254 timer The Enable8254ClockGating/Enable8254ClockGatingOnS3 UPDs default to enabled, but need to be disabled on Coffeelake/Whiskeylake when SeaBIOS is used as the payload. Add a Kconfig option to set it as such. Test: build/boot out-of-tree WHL board with both SeaBIOS and Tianocore, ensure 8254 timer usage set correctly for each. Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: I0e888bf754cb72093f14fc02f39bddcd6d288203 --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/33512/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dac3522..19b9679 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -315,4 +315,13 @@ Setting non-zero value will allow to use DBC or DCI to debug SOC. PlatformDebugConsent in FspmUpd.h has the details. +config USE_LEGACY_8254_TIMER + bool + default n if (SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE) && PAYLOAD_SEABIOS + default y + help + This sets the Enable8254ClockGating and Enable8254ClockGatingOnS3 UPDs. + On Coffeelake/Whiskeylake, these UPDs need to be disabled in order to + boot SeabIOS, but should otherwise be enabled. + endif diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index dd93882..a518541 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -244,6 +244,10 @@ /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + /* Legacy 8254 timer support */ + params->Enable8254ClockGating = CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGatingOnS3 = CONFIG_USE_LEGACY_8254_TIMER; + /* USB */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/33512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e888bf754cb72093f14fc02f39bddcd6d288203 Gerrit-Change-Number: 33512 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

6 30

Change in ...coreboot[master]: asus/am1i-a: Fix UART 0 port while preserving the UART 1 functionality
by Mike Banon (Code Review) 28 Jun '19

28 Jun '19

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33796 Change subject: asus/am1i-a: Fix UART 0 port while preserving the UART 1 functionality ...................................................................... asus/am1i-a: Fix UART 0 port while preserving the UART 1 functionality It has been observed by me and Elisenda Cuadros / Gergely Kiss [1] that the boot process of this board is super slow when UART 0 is being used - even if nothing is connected to it. Fix UART 0 by initializing it at romstage. [1] https://mail.coreboot.org/pipermail/coreboot/2018-February/086132.html Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I6579aa8fd092da84f8afdcc33496db45c582919f --- M src/mainboard/asus/am1i-a/romstage.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/33796/1 diff --git a/src/mainboard/asus/am1i-a/romstage.c b/src/mainboard/asus/am1i-a/romstage.c index 4b172ea..258ca03 100644 --- a/src/mainboard/asus/am1i-a/romstage.c +++ b/src/mainboard/asus/am1i-a/romstage.c @@ -25,7 +25,8 @@ #include <superio/ite/it8623e/it8623e.h> #define ITE_CONFIG_REG_CC 0x02 -#define SERIAL_DEV PNP_DEV(0x2e, IT8623E_SP2) +#define SERIAL_DEV1 PNP_DEV(0x2e, IT8623E_SP1) +#define SERIAL_DEV2 PNP_DEV(0x2e, IT8623E_SP2) #define GPIO_DEV PNP_DEV(0x2e, IT8623E_GPIO) #define CLKIN_DEV PNP_DEV(0x2e, IT8623E_GPIO) #define ENVC_DEV PNP_DEV(0x2e, IT8623E_EC) @@ -160,7 +161,8 @@ ite_evc_conf(ENVC_DEV); ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV2, CONFIG_TTYS0_BASE); ite_kill_watchdog(GPIO_DEV); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/33796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6579aa8fd092da84f8afdcc33496db45c582919f Gerrit-Change-Number: 33796 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

5 15

Change in ...coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock
by David Guckian (Code Review) 28 Jun '19

28 Jun '19

David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25442 ) Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock ...................................................................... Patch Set 14: Code-Review+1 I tend to agree that spi probably does not belong in the function name. -- To view, visit https://review.coreboot.org/c/coreboot/+/25442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd Gerrit-Change-Number: 25442 Gerrit-PatchSet: 14 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Steve Mooney Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Comment-Date: Fri, 28 Jun 2019 17:52:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/google/kohaku: Correct trackpad i2c address
by shkim (Code Review) 28 Jun '19

28 Jun '19

Hello Seunghwan Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/33798 to review the following change. Change subject: mb/google/kohaku: Correct trackpad i2c address ...................................................................... mb/google/kohaku: Correct trackpad i2c address Correct i2c address of trackpad. It should be 0x20. BUG=None BRANCH=None TEST=Verified trackpad works on pre-evt system Change-Id: I7ded21ce8ff9e907e436777a27edb4273512011d Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/33798/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 9546420..21475cb 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -70,7 +70,7 @@ register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" - device i2c 0x2c on end + device i2c 0x20 on end end end # I2C 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/33798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ded21ce8ff9e907e436777a27edb4273512011d Gerrit-Change-Number: 33798 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: soc/amd/stoneyridge: Change code to accommodate merlinfalcon SOC
by Richard Spiegel (Code Review) 28 Jun '19

28 Jun '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33856 Change subject: soc/amd/stoneyridge: Change code to accommodate merlinfalcon SOC ...................................................................... soc/amd/stoneyridge: Change code to accommodate merlinfalcon SOC Merlinfalcon is essentially a carrizo CPU in a SOC presentation. Just as stoneyridge, they are both family 15h CPU, thus most of the code is similar if not identical. Add changes base on config parameter SOC_AMD_MERLINFALCON to accommodate for merlinfalcon SOC. BUG=b:none. TEST=Tested later with padmelon board. Change-Id: I785bf706ceb28e8cb293f785d87613a2933ca3c3 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/acpi/cpu.asl M src/soc/amd/stoneyridge/chip.h M src/soc/amd/stoneyridge/cpu.c M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/northbridge.c 5 files changed, 82 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/33856/1 diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl index 414326e..aa59040 100644 --- a/src/soc/amd/stoneyridge/acpi/cpu.asl +++ b/src/soc/amd/stoneyridge/acpi/cpu.asl @@ -34,7 +34,27 @@ /* Return a package containing enabled processor entries */ Method (PPKG) { - If (LGreaterEqual (\PCNT, 2)) { + If (LGreaterEqual (\PCNT, 8)) { + Return (Package () + { + \_PR.P000, + \_PR.P001, + \_PR.P002, + \_PR.P003, + \_PR.P004, + \_PR.P005, + \_PR.P006, + \_PR.P007 + }) + } ElseIf (LGreaterEqual (\PCNT, 4)) { + Return (Package () + { + \_PR.P000, + \_PR.P001, + \_PR.P002, + \_PR.P003 + }) + } ElseIf (LGreaterEqual (\PCNT, 2)) { Return (Package () { \_PR.P000, diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index d1a7d30..34ad595 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -20,12 +20,18 @@ #include <stdint.h> #include <commonlib/helpers.h> #include <drivers/i2c/designware/dw_i2c.h> +#include <soc/cpu.h> #include <soc/i2c.h> #include <arch/acpi_device.h> #define MAX_NODES 1 +#if CONFIG(SOC_AMD_MERLINFALCON) +#define MAX_DRAM_CH 2 +#define MAX_DIMMS_PER_CH 4 +#else #define MAX_DRAM_CH 1 #define MAX_DIMMS_PER_CH 2 +#endif #define STONEY_I2C_DEV_MAX 4 diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 1d9804d..f751dc8 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -145,6 +145,7 @@ }; static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, 0x660f01 }, { X86_VENDOR_AMD, 0x670f00 }, { 0, 0 }, }; diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 02fed7a..01a0b7c 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -39,17 +39,24 @@ #define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC) #define SOC_IOMMU_DEV _SOC_DEV(IOMMU_DEV, IOMMU_FUNC) -/* Internal Graphics */ +/* + * Internal Graphics + * Device IDs subject to SKU/OPN variation + * GFX_DEVID for merlinfalcon PCI_DEVICE_ID_AMD_15H_MODEL_606F_GFX + * GFX_DEVID for stoneyridge PCI_DEVICE_ID_AMD_15H_MODEL_707F_GFX + */ #define GFX_DEV 0x1 #define GFX_FUNC 0 -#define GFX_DEVID 0x98e4 /* subject to SKU/OPN variation */ #define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) #define SOC_GFX_DEV _SOC_DEV(GFX_DEV, GFX_FUNC) -/* HD Audio 0 */ +/* HD Audio 0 + * Device IDs + * HDA0_DEVID PCI_DEVICE_ID_AMD_15H_MODEL_606F_HDA + * HDA0_DEVID PCI_DEVICE_ID_AMD_15H_MODEL_707F_HDA + */ #define HDA0_DEV 0x1 #define HDA0_FUNC 1 -#define HDA0_DEVID 0x15b3 #define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC) #define SOC_HDA0_DEV _SOC_DEV(HDA0_DEV, HDA0_FUNC) @@ -109,45 +116,63 @@ #define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC) #define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC) -/* HT Configuration */ +/* HT Configuration + * Device IDs + * HT_DEVID for merlinfalcon PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT + * HT_DEVID for stoneyridge PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT + */ #define HT_DEV 0x18 #define HT_FUNC 0 -#define HT_DEVID 0x15b0 #define HT_DEVFN PCI_DEVFN(HT_DEV, HT_FUNC) #define SOC_HT_DEV _SOC_DEV(HT_DEV, HT_FUNC) -/* Address Maps */ +/* Address Maps + * Device IDs + * ADDR_DEVID for merlinfalcon 0x1571 + * ADDR_DEVID for stoneyridge 0x15b1 + */ #define ADDR_DEV 0x18 #define ADDR_FUNC 1 -#define ADDR_DEVID 0x15b1 #define ADDR_DEVFN PCI_DEVFN(ADDR_DEV, ADDR_FUNC) #define SOC_ADDR_DEV _SOC_DEV(ADDR_DEV, ADDR_FUNC) -/* DRAM Configuration */ +/* DRAM Configuration + * Device IDs + * DCT_DEVID for merlinfalcon 0x1572 + * DCT_DEVID for stoneyridge 0x15b2 + */ #define DCT_DEV 0x18 #define DCT_FUNC 2 -#define DCT_DEVID 0x15b2 #define DCT_DEVFN PCI_DEVFN(DCT_DEV, DCT_FUNC) #define SOC_DCT_DEV _SOC_DEV(DCT_DEV, DCT_FUNC) -/* Misc. Configuration */ +/* Misc. Configuration + * Device IDs + * MISC_DEVID for merlinfalcon 0x1573 + * MISC_DEVID for stoneyridge 0x15b3 + */ #define MISC_DEV 0x18 #define MISC_FUNC 3 -#define MISC_DEVID 0x15b3 #define MISC_DEVFN PCI_DEVFN(MISC_DEV, MISC_FUNC) #define SOC_MISC_DEV _SOC_DEV(MISC_DEV, MISC_FUNC) -/* PM Configuration */ +/* PM Configuration + * Device IDs + * PM_DEVID for merlinfalcon 0x1574 + * PM_DEVID for stoneyridge 0x15b4 + */ #define PM_DEV 0x18 #define PM_FUNC 4 -#define PM_DEVID 0x15b4 #define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC) #define SOC_PM_DEV _SOC_DEV(PM_DEV, PM_FUNC) -/* Northbridge Configuration */ +/* Northbridge Configuration + * Device IDs + * NB_DEVID for merlinfalcon 0x1575 + * NB_DEVID for stoneyridge 0x15b5 + */ #define NB_DEV 0x18 #define NB_FUNC 5 -#define NB_DEVID 0x15b5 #define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC) #define SOC_NB_DEV _SOC_DEV(NB_DEV, NB_FUNC) diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 5985832..044a1b0 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -347,10 +347,15 @@ .ops_pci = 0, }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT, + PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT, + 0 }; + static const struct pci_driver family15_northbridge __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT, + .devices = pci_device_ids, }; /* @@ -464,9 +469,13 @@ u32 map_oprom_vendev(u32 vendev) { u32 new_vendev; - new_vendev = - ((vendev >= 0x100298e0) && (vendev <= 0x100298ef)) ? - 0x100298e0 : vendev; + + if ((vendev >= 0x100298e0) && (vendev <= 0x100298ef)) + new_vendev = 0x100298e0; + else if ((vendev >= 0x10029870) && (vendev <= 0x1002987f)) + new_vendev = 0x10029870; + else + new_vendev = vendev; if (vendev != new_vendev) printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/33856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I785bf706ceb28e8cb293f785d87613a2933ca3c3 Gerrit-Change-Number: 33856 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: drivers/intel/fsp1_1/raminit.c: Always check FSP HOBs
by Patrick Rudolph (Code Review) 28 Jun '19

28 Jun '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29371 ) Change subject: drivers/intel/fsp1_1/raminit.c: Always check FSP HOBs ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3776fa37866c7ef3aea090842387660c22bbdd4d Gerrit-Change-Number: 29371 Gerrit-PatchSet: 10 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 28 Jun 2019 14:34:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: payloads/external/LinuxBoot: Update x86_64 defconfig
by Patrick Rudolph (Code Review) 28 Jun '19

28 Jun '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33581 Change subject: payloads/external/LinuxBoot: Update x86_64 defconfig ...................................................................... payloads/external/LinuxBoot: Update x86_64 defconfig Add more UART drivers and increase console count to 32. Fixes non working console on APL Up2 board. Change-Id: Ib5bd33531741e588ac7d5ff6a02b0482f6655ddf Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M payloads/external/LinuxBoot/x86_64/defconfig 1 file changed, 13 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/33581/1 diff --git a/payloads/external/LinuxBoot/x86_64/defconfig b/payloads/external/LinuxBoot/x86_64/defconfig index 39ae162..08c8fc8 100644 --- a/payloads/external/LinuxBoot/x86_64/defconfig +++ b/payloads/external/LinuxBoot/x86_64/defconfig @@ -52,7 +52,7 @@ # CONFIG_ZONE_DMA is not set # CONFIG_X86_MPPARSE is not set # CONFIG_X86_EXTENDED_PLATFORM is not set -CONFIG_IOSF_MBI=y +CONFIG_X86_INTEL_LPSS=y # CONFIG_SCHED_OMIT_FRAME_POINTER is not set # CONFIG_DMI is not set CONFIG_PREEMPT=y @@ -99,13 +99,18 @@ CONFIG_MD=y CONFIG_BLK_DEV_DM=y CONFIG_DM_CRYPT=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set -# CONFIG_SERIAL_8250_EXAR is not set -# CONFIG_SERIAL_8250_LPSS is not set -# CONFIG_SERIAL_8250_MID is not set -# CONFIG_SERIAL_8250_PNP is not set CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_PNP is not set +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_EXAR is not set +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=32 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_DW=y +# CONFIG_SERIAL_8250_MID is not set +CONFIG_SERIAL_DEV_BUS=y CONFIG_HW_RANDOM_TIMERIOMEM=y # CONFIG_HW_RANDOM_AMD is not set # CONFIG_HW_RANDOM_VIA is not set @@ -115,6 +120,7 @@ CONFIG_I2C=y CONFIG_POWER_SUPPLY=y # CONFIG_HWMON is not set +CONFIG_MFD_INTEL_LPSS_PCI=y # CONFIG_VGA_ARB is not set CONFIG_FB=y CONFIG_FIRMWARE_EDID=y -- To view, visit https://review.coreboot.org/c/coreboot/+/33581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5bd33531741e588ac7d5ff6a02b0482f6655ddf Gerrit-Change-Number: 33581 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 10

Change in ...coreboot[master]: qcs405: Add RPM support
by Patrick Georgi (Code Review) 28 Jun '19

28 Jun '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29970 ) Change subject: qcs405: Add RPM support ...................................................................... Patch Set 32: (2 comments) https://review.coreboot.org/#/c/29970/32/src/soc/qualcomm/qcs405/include/so… File src/soc/qualcomm/qcs405/include/soc/symbols.h: https://review.coreboot.org/#/c/29970/32/src/soc/qualcomm/qcs405/include/so… PS32, Line 28: extern u8 _rpm[]; DECLARE_REGION(rpm)? https://review.coreboot.org/#/c/29970/32/src/soc/qualcomm/qcs405/include/so… PS32, Line 30: #define _rpm_size (_erpm - _rpm) replace with REGION_SIZE(rpm) at the use sites? -- To view, visit https://review.coreboot.org/c/coreboot/+/29970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945 Gerrit-Change-Number: 29970 Gerrit-PatchSet: 32 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Fri, 28 Jun 2019 12:44:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2019