Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29967 )
Change subject: qclib: Add qclib support with interface tables
......................................................................
Patch Set 32:
(1 comment)
Please document which blobs are used to boot the platform, their names, if they need to be loaded at a specific address, where to get them, why you don't compress them, ....
https://review.coreboot.org/#/c/29967/32/src/soc/qualcomm/common/qclib.c
File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/#/c/29967/32/src/soc/qualcomm/common/qclib.c@147
PS32, Line 147: _ddr_training, ssize, 0);
unrelated
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22415 )
Change subject: mainboard/google/coral: power off EN_PP3300_DX_LTE_SOC when entering S5
......................................................................
Patch Set 2:
> Patch Set 2:
>
> How do you verify if mainboard_smi_sleep() function is getting called in reboot cycle or not?
> we are seeing issue in hatch where modem is asking for PIN in reboot and mainboard_smi_sleep() function can't get call in reboot path. But if we drive required modem GPIO to low in reboot path (somehow) and its working fine, almost similar way how you have done in S5. But problem is that you have added this code inside Sleep handler which won't get called for reboot.
[Subrata] fixing typo
"where modem is not asking for PIN in reboot "
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Hello Patrick Georgi,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/33375
to review the following change.
Change subject: qualcomm: qclib: Ensure interface table entry name is terminated
......................................................................
qualcomm: qclib: Ensure interface table entry name is terminated
This string is printed in dump_te_table() so we should make sure it's
properly null-terminated.
This fixes Coverity issue 1401305.
Change-Id: I45827f552c2d8a4e01b50a699ac88ee457043282
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
---
M src/soc/qualcomm/common/qclib.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/33375/1
diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c
index 73c5250..25512a9 100644
--- a/src/soc/qualcomm/common/qclib.c
+++ b/src/soc/qualcomm/common/qclib.c
@@ -41,7 +41,7 @@
struct qclib_cb_if_table_entry *te =
&qclib_cb_if_table.te[qclib_cb_if_table.num_entries++];
assert(qclib_cb_if_table.num_entries <= qclib_cb_if_table.max_entries);
- strncpy(te->name, name, sizeof(te->name));
+ strncpy(te->name, name, sizeof(te->name) - 1);
te->blob_address = (uintptr_t)base;
te->size = size;
te->blob_attributes = attrs;
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22415 )
Change subject: mainboard/google/coral: power off EN_PP3300_DX_LTE_SOC when entering S5
......................................................................
Patch Set 2:
How do you verify if mainboard_smi_sleep() function is getting called in reboot cycle or not?
we are seeing issue in hatch where modem is asking for PIN in reboot and mainboard_smi_sleep() function can't get call in reboot path. But if we drive required modem GPIO to low in reboot path (somehow) and its working fine, almost similar way how you have done in S5. But problem is that you have added this code inside Sleep handler which won't get called for reboot.
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Steve Mooney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25440 )
Change subject: soc/intel/denverton_ns: Implement AES-NI Lock
......................................................................
Patch Set 13: Code-Review+1
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Steve Mooney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25442 )
Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
......................................................................
Patch Set 14:
> Patch Set 14: Code-Review+1
>
> My mistake on the previous comment. Looks good.
Curious if you meant keep SPI in the function name?
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Steve Mooney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25442 )
Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
......................................................................
Patch Set 14: Code-Review+1
My mistake on the previous comment. Looks good.
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Steve Mooney has removed a vote on this change.
Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
......................................................................
Removed Code-Review-1 by Steve Mooney (1002423)
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