coreboot-gerrit June 2019

coreboot-gerrit@coreboot.org

1 participants
1454 discussions

Change in ...coreboot[master]: src: Remove variable length arrays
by Julius Werner (Code Review) 27 Jun '19

27 Jun '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33821 ) Change subject: src: Remove variable length arrays ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/33821/8/src/drivers/spi/spi_flash.c File src/drivers/spi/spi_flash.c: https://review.coreboot.org/#/c/33821/8/src/drivers/spi/spi_flash.c@103 PS8, Line 103: #pragma GCC diagnostic ignored "-Wvla" > I really don't want to ignore this, especially considering the urgent TODO. […] This driver is used in all stages, so no malloc(). In theory this should be really easy to solve because our SPI API is a pure byte pushing API that controls CS independently, so xfer(cmd <concatenated with> data); should just be equivalent to { xfer(cmd); xfer(data); }. In practice, however, there are a lot of weird Intel and AMD controllers that are not really generic SPI controllers but rather specific SPI NOR flash controllers but were still implemented using the generic controller API. They expect that every xfer() they get sent is a whole SPI command (e.g. they inspect dout[0] and expect that it must be a SPI flash opcode). I think the only clean solution here would be to make all those drivers that aren't actually SPI controllers stop using the generic SPI API, and instead make them implement custom flash read/write ops by overriding .flash_probe() (like some more recent drivers for special controllers such as Intel fast_spi or the MT8173 flash controller already do). Then we rewrite this cleanly and mandate that from then on forward, drivers shouldn't implement the generic SPI API unless they can actually handle it. But there are a lot of old drivers like this (I think basically everything that implements xfer_vector, which we could remove if we fix them all), so this would be a lot of work (although most of these were copied from each other and are very similar... I think for the most part there's just 6 versions of the Intel controller and 4 versions of the AMD controller). A hackier but less complicated option might be to add a new SPI_CNTRLR flag for all these controllers and then make only them run the dangerous code, while other ones could run a safer version. +Aaron, what do you think? -- To view, visit https://review.coreboot.org/c/coreboot/+/33821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9 Gerrit-Change-Number: 33821 Gerrit-PatchSet: 8 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 27 Jun 2019 21:14:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: src: Remove variable length arrays
by Jacob Garber (Code Review) 27 Jun '19

27 Jun '19

Jacob Garber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33821 ) Change subject: src: Remove variable length arrays ...................................................................... Patch Set 8: (1 comment) I'm uncertain what to do about the VLA in spi_flash.c. Any feedback is appreciated :) https://review.coreboot.org/#/c/33821/8/src/drivers/spi/spi_flash.c File src/drivers/spi/spi_flash.c: https://review.coreboot.org/#/c/33821/8/src/drivers/spi/spi_flash.c@103 PS8, Line 103: #pragma GCC diagnostic ignored "-Wvla" I really don't want to ignore this, especially considering the urgent TODO. Could we just malloc() the buffer here instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/33821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9 Gerrit-Change-Number: 33821 Gerrit-PatchSet: 8 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 27 Jun 2019 20:38:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: qcs405: Combine BB with QC-Sec for ROM boot
by Patrick Georgi (Code Review) 27 Jun '19

27 Jun '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29958 ) Change subject: qcs405: Combine BB with QC-Sec for ROM boot ...................................................................... Patch Set 31: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2428fd067c0216d9cf6a63e218d1792788317db0 Gerrit-Change-Number: 29958 Gerrit-PatchSet: 31 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 27 Jun 2019 16:46:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: libpayload: remove re-initialization of uart in libpayload
by Nitheesh Sekar (Code Review) 27 Jun '19

27 Jun '19

Nitheesh Sekar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33424 Change subject: libpayload: remove re-initialization of uart in libpayload ...................................................................... libpayload: remove re-initialization of uart in libpayload Depend on the coreboot for initialization of UART instead of re-initialising in libpayload. Change-Id: I7820bd7afd2e5f81e21a43f330ed42d3a732d577 Signed-off-by: Prudhvi Yarlagadda <pyarlaga(a)codeaurora.org> --- M payloads/libpayload/drivers/serial/qcs405.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/33424/1 diff --git a/payloads/libpayload/drivers/serial/qcs405.c b/payloads/libpayload/drivers/serial/qcs405.c index 9f02e17..7a80aae 100644 --- a/payloads/libpayload/drivers/serial/qcs405.c +++ b/payloads/libpayload/drivers/serial/qcs405.c @@ -547,8 +547,10 @@ uart_board_param.uart_dm_base = (void *)(uintptr_t)sc_ptr->baseaddr; - /* TODO: We should rely on coreboot init. */ - msm_boot_uart_dm_init(uart_board_param.uart_dm_base); + /* We should re-initialise uart rx as it gets reset in coreboot. */ + write32(MSM_BOOT_UART_DM_IMR(uart_board_param.uart_dm_base), + MSM_BOOT_UART_DM_IMR_ENABLED); + msm_boot_uart_dm_init_rx_transfer(uart_board_param.uart_dm_base); console_add_output_driver(&consout); console_add_input_driver(&consin); -- To view, visit https://review.coreboot.org/c/coreboot/+/33424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7820bd7afd2e5f81e21a43f330ed42d3a732d577 Gerrit-Change-Number: 33424 Gerrit-PatchSet: 1 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-MessageType: newchange

2 4

Change in ...coreboot[master]: src/mainboards/asus: Add support for P8Z77-M PRO mainboard
by Vlado Cibic (Code Review) 27 Jun '19

27 Jun '19

Vlado Cibic has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33328 Change subject: src/mainboards/asus: Add support for P8Z77-M PRO mainboard ...................................................................... src/mainboards/asus: Add support for P8Z77-M PRO mainboard Add support for ASUS P8Z77-M PRO mainboard Signed-off-by: Vlado Ciric <vladocb(a)protonmail.com> Change-Id: I47d24ac8b236f929c3160f9a769b971d83710f9d --- A Documentation/mainboard/asus/p8z77-m_pro.jpg A Documentation/mainboard/asus/p8z77-m_pro.md A src/mainboard/asus/p8z77-m_pro/Kconfig A src/mainboard/asus/p8z77-m_pro/Kconfig.name A src/mainboard/asus/p8z77-m_pro/Makefile.inc A src/mainboard/asus/p8z77-m_pro/acpi/ec.asl A src/mainboard/asus/p8z77-m_pro/acpi/platform.asl A src/mainboard/asus/p8z77-m_pro/acpi/superio.asl A src/mainboard/asus/p8z77-m_pro/acpi_tables.c A src/mainboard/asus/p8z77-m_pro/board_info.txt A src/mainboard/asus/p8z77-m_pro/cmos.default A src/mainboard/asus/p8z77-m_pro/cmos.layout A src/mainboard/asus/p8z77-m_pro/data.vbt A src/mainboard/asus/p8z77-m_pro/devicetree.cb A src/mainboard/asus/p8z77-m_pro/dsdt.asl A src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads A src/mainboard/asus/p8z77-m_pro/gpio.c A src/mainboard/asus/p8z77-m_pro/hda_verb.c A src/mainboard/asus/p8z77-m_pro/mainboard.c A src/mainboard/asus/p8z77-m_pro/romstage.c 20 files changed, 1,551 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/33328/1 diff --git a/Documentation/mainboard/asus/p8z77-m_pro.jpg b/Documentation/mainboard/asus/p8z77-m_pro.jpg new file mode 100644 index 0000000..5c6411e --- /dev/null +++ b/Documentation/mainboard/asus/p8z77-m_pro.jpg Binary files differ diff --git a/Documentation/mainboard/asus/p8z77-m_pro.md b/Documentation/mainboard/asus/p8z77-m_pro.md new file mode 100644 index 0000000..b7c69ca --- /dev/null +++ b/Documentation/mainboard/asus/p8z77-m_pro.md @@ -0,0 +1,169 @@ +# ASUS P8Z77-M Pro + +This page describes how to run coreboot on the [ASUS P8Z77-M Pro] + +## Flashing coreboot + +```eval_rst ++---------------------+----------------+ +| Type | Value | ++=====================+================+ +| Socketed flash | yes | ++---------------------+----------------+ +| Model | W25Q64FVA1Q | ++---------------------+----------------+ +| Size | 8 MiB | ++---------------------+----------------+ +| Package | DIP-8 | ++---------------------+----------------+ +| Write protection | yes | ++---------------------+----------------+ +| Dual BIOS feature | no | ++---------------------+----------------+ +| Internal flashing | yes | ++---------------------+----------------+ +``` + +The flash IC is located right next to one of the SATA ports: +![](p8z77-m_pro.jpg) + +### Internal programming + +The main SPI flash cannot be written because Asus disables BIOSWE and +enables BLE/SMM_BWP flags in BIOS_CNTL for their latest bioses. +An external programmer is required. + +## Known issues + +- The rear's USB3s on bottom (closest to the PCB) have problems booting or + being used before the OS loads. For better compatibility, please use + the Z77's ones above the Ethernet connector or the Asmedia's top one. + +- After S3 suspend, some USB3 connectors on rear seem not to work. + +- At the moment, the power led does not blink when entering S3 state. + +- Although you can set gfx_uma_size NVRAM variable to 1024M, seems the + maximum real allocable memory in Mint 19.1 is 544Mb. Using MRC.bin, + seems the maximum allocable real size is 32Mb, independently of + the value of gfx_uma_size. The original Asus 2203 bios is 544Mb too. + +- Currently, we have not setup the SuperIO's Hardware Monitor (HWM), + so only the CPU sensors are reported. + +- Using TianoCore + a PCIe GPU, Windows crashes with a ACPI_BIOS_ERROR + fatal code, not sure why. Using just the IGP alone is ok and works + perfectly. + +- Under Windows 10, if you experiment problems with PS/2 devices, change + HKLM\SYSTEM\CurrentControlSet\Services\i8042prt->Start from '3' to '1' + Anyways, PS2 keyboard/mouse seems not to work! + +## Untested + +- EHCI & COM debugging +- S/PDIF audio +- Wake-on-LAN +- Serial port + +## Not working + +- PS/2 keyboard in Win10 using tianocore (please see [Known issues]) +- PS/2 mouse using tianocore +- PCIe graphics card on Windows & tianocore (throws critical ACPI_BIOS_ERROR) + +## Working + +- PS/2 keyboard with SEABios & tianocore (in Mint 18.3/19.1) + +- Rear/front headphones connector audio & mic + +- S3 Suspend to RAM (tested with OS installed in a HDD/SSD and also with a + Mint 19.1 LiveUSB pendrive on USB3 and USB2 connectors), but please see + [Known issues] + +- USB2 on rear + +- USB3 (Z77's and Asmedia's works, but please see [Known issues]) + +- Gigabit Ethernet (RTL8111F) + +- SATA3, SATA2 and eSATA on all ports ! + +- NVME SSD boot on PCIe-x16/x8/4x slot (tested with M.2-to-PCIe adapter and + a M.2 Samsung EVO 970 SSD). + +- CPU Temp sensors (tested PSensor on linux + HWINFO64 on Windows) + +- TPM on TPM-header (tested tpm-tools with Asus TPM 1.2 Infineon SLB9635TT12) + +- Native raminit and also MRC.bin(systemagent-r6.bin) memory initialization + ( please see [Native raminit compatibility] & [MRC memory compatibility] ) + +- Integrated graphics via libgfxinit and GENERIC_LINEAR_FRAMEBUFFER + (VGA/DVI-D/HDMI tested and working!) + +- Integrated graphics via extracted OpROM from Asus Bios 2203 + (VGA/DVI-D/HDMI tested and working!) + +- 1x PCIe GPU in PCIe-16x/8x/4x slots (tested using Zotac GeForce GTX + 750Ti and FirePro W5100) + + +## Native raminit compatibility + +- GSkill F3-2133C10D-16GAB(XMP,1.60v) 2x8Gb kit works at 1333Mhz instead of + XMP 2133Mhz ( tested with lshw, dmidecode & decode-dimms ) + +- Team Xtreem TXD38G2133HC9NDC01(XMP,1.50v) 2x4Gb kit works at 1600Mhz + instead of XMP 2133Mhz ( tested with lshw, dmidecode & decode-dimms ) + +- Kingston KVR1066D3N7K2/4G(JEDEC,1.50v) 2x4Gb kit works at 1066Mhz + ( tested with lshw, dmidecode & decode-dimms ), but the board only detects + half its RAM, because those DIMMs have Double Sided(DS) chips and seems only + Single Sided(SS) ones are fully detected. + +## MRC memory compatibility + +- Plug your memory DIMMs into blue slots only! (we hardcoded to disable the + black slots at file "src/mainboard/asus/p8z77-m_pro/romstage.c" in function + mainboard_fill_pei_data(), filling struct ".spd_addresses" ) + +- GSkill F3-2133C10D-16GAB(XMP,1.60v) 2x8Gb kit works at 1333Mhz instead of + XMP 2133Mhz ( tested with decode-dimms, lshw & dmidecode shows no + frequency info ) + +- Team Xtreem TXD38G2133HC9NDC01(XMP,1.50v) 2x4Gb kit works at 1600Mhz + instead of XMP 2133Mhz ( tested with decode-dimms, lshw & dmidecode + shows no frequency info ) + +- Kingston KVR1066D3N7K2/4G(JEDEC,1.50v) 2x4Gb kit works at 1066Mhz + ( tested with decode-dimms, lshw & dmidecode shows no freq info ) but the + board only detects half its RAM, as those DIMMs have Double Sided(DS) + chips and seems only Single Sided(SS) ones are fully detected. + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax / model_306ax | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT6779D | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +## Extra resources + +- [Flash chip datasheet][W25Q64FVA1Q] + +[ASUS P8Z88-M Pro]: https://www.asus.com/Motherboards/P8Z77M_PRO/ +[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf +[flashrom]: https://flashrom.org/Flashrom diff --git a/src/mainboard/asus/p8z77-m_pro/Kconfig b/src/mainboard/asus/p8z77-m_pro/Kconfig new file mode 100644 index 0000000..1e2a440 --- /dev/null +++ b/src/mainboard/asus/p8z77-m_pro/Kconfig @@ -0,0 +1,164 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ASUS_P8Z77_M_PRO + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select MAINBOARD_HAS_LIBGFXINIT + select INTEL_GMA_HAVE_VBT + select SUPERIO_NUVOTON_NCT6779D + select DRIVERS_ASMEDIA_ASPM_BLACKLIST # Board use a ASM1061(eSATA) +# select HAVE_IFD_BIN # uncomment if needed +# select HAVE_ME_BIN # uncomment if needed + +config MAINBOARD_DIR + string + default "asus/p8z77-m_pro" + +config MAINBOARD_PART_NUMBER + string + default "P8Z77-M PRO" + +config INTEL_GMA_ADD_VBT + def_bool y + +# This is used by libgfxinit. Comment it if you prefer to use VGA OpROMs +config INTEL_GMA_VBT_FILE + string + default "src/mainboard/$(MAINBOARDDIR)/data.vbt" + +# This is used OpROMs, not sure for libgfxinit +config VGA_BIOS_ID + string + default "8086,0152" # i5-3470T ( HD Graphics 2500 GT1 ) + +# This is used just in case you use OpROMs and not libgfxinit +#config VGA_BIOS_FILE +# string +# default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/pci8086,0152.rom" +# + +# Set this to use your IGP as primary display instead of the GPU +config ONBOARD_VGA_IS_PRIMARY + def_bool n + +config DRAM_RESET_GATE_GPIO + int + default 60 + +config MAX_CPUS + int + default 8 + +# This board works with both Native RAM Init + MRC blob. Use NRI as default. +config USE_NATIVE_RAMINIT + def_bool y + +# +# We dont use USB2.0 (EHCI) debugging. Uncomment it if you need. +# idx1 -> 00:1d.0 USB controller [0c03]: Intel Corporation 7 Series/C216 +# Chipset Family USB Enhanced Host Controller #1 [8086:1e26] (rev 04) +# idx2 -> 00:1a.0 USB controller [0c03]: Intel Corporation 7 Series/C216 +# Chipset Family USB Enhanced Host Controller #2 [8086:1e2d] (rev 04) +# +#config USBDEBUG_HCD_INDEX +# int +# default 2 + +config USE_OPTION_TABLE + def_bool y + +config IFD_BIN_PATH + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" + +config ME_BIN_PATH + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" + +# +# Uncomment if you need to partial-write parts of the bios image +# +#config IFD_SECTION +# string +# default "0x00000000:00000fff" +# +#config IFD_BIOS_SECTION +# string +# default "0x00180000:007fffff" +# +#config IFD_ME_SECTION +# string +# default "0x00001000:0017ffff" +# + +# Check Intel ME .bin file to be sure it's valid +config CHECK_ME + def_bool y + +config GENERATE_SMBIOS_TABLES + def_bool y + +config MAINBOARD_VERSION + string + default "1.01" # our board revision is v1.01 + +config MAINBOARD_SMBIOS_MANUFACTURER + string + default "ASUS" + +config MAINBOARD_SMBIOS_PRODUCT_NAME + string + default "P8Z77-M PRO" + +# This board has four memory DIMMS +config DIMM_MAX + int + default 4 + +# This board has a power button, it does not power-on via a +# jumper as other devboards. +config POWER_BUTTON_DEFAULT_ENABLE + def_bool y + +if USE_NATIVE_RAMINIT + config MMCONF_BASE_ADDRESS + hex + default 0xf8000000 + help + Set MMCONF_BASE_ADDRESS to 0xf8000000. It was already done for some + boards, but not all. The Sandy Bridge chipset code assumes 64 pci + buses behind MMCONF. See: + src/northbridge/sandybridge/bootblock.c:bootblock_northbridge_init() + Therefore, only 64MiB of physical address space is required. + Increasing the address allows to use additional 128MiB of MMIO space + to use the Intel IGP and a PEG at the same time. Previously it wasn't + possible to use both at the same time, as two 256MiB areas won't fit + into MMIO space. +endif # MRC requires fixed MMCONF address at 0xf0000000 + +endif # BOARD_ASUS_P8Z77_M_PRO diff --git a/src/mainboard/asus/p8z77-m_pro/Kconfig.name b/src/mainboard/asus/p8z77-m_pro/Kconfig.name new file mode 100644 index 0000000..c492094 --- /dev/null +++ b/src/mainboard/asus/p8z77-m_pro/Kconfig.name @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config BOARD_ASUS_P8Z77_M_PRO + bool "P8Z77-M PRO" diff --git a/src/mainboard/asus/p8z77-m_pro/Makefile.inc b/src/mainboard/asus/p8z77-m_pro/Makefile.inc new file mode 100644 index 0000000..4df65aa --- /dev/null +++ b/src/mainboard/asus/p8z77-m_pro/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += gpio.c + +# as we using libgfxinit, we need to include this +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + diff --git a/src/mainboard/asus/p8z77-m_pro/acpi/ec.asl b/src/mainboard/asus/p8z77-m_pro/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/p8z77-m_pro/acpi/ec.asl diff --git a/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl b/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl new file mode 100644 index 0000000..3a69621 --- /dev/null +++ b/src/mainboard/asus/p8z77-m_pro/acpi/platform.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl b/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl new file mode 100644 index 0000000..cfecdc6 --- /dev/null +++ b/src/mainboard/asus/p8z77-m_pro/acpi/superio.asl @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> + diff --git a/src/mainboard/asus/p8z77-m_pro/acpi_tables.c b/src/mainboard/asus/p8z77-m_pro/acpi_tables.c new file mode 100644 index 0000000..4dd59d9 --- /dev/null +++ b/src/mainboard/asus/p8z77-m_pro/acpi_tables.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> +#include <option.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* + * Keep USB ports powered in S3 by default, because the user may have + * booted using a LiveUSB and, in that way, won't get problems resuming + * from S3. Also, the user may want to charge a mobile phone while + * suspended... so keep the USB ports always powered on! + */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable/enable USB ports in S5 suspend */ + int usbPoweredS5 = 0; + get_option ( &usbPoweredS5, "usb_powered_on_s5" ); + usbPoweredS5 = usbPoweredS5 & 1; /* be sure is 0 or 1 only, not 3,4,5,etc... */ + gnvs->s5u0 = usbPoweredS5; + gnvs->s5u1 = usbPoweredS5; + + /* + * This is a desktop computer, so we have no "lid" really, so keep it as + * if where always open in a laptop. + */ + gnvs->lids = 1; + + gnvs->tcrt = 95; /* critical temp that will shutdown the pc == 95C degrees */ + gnvs->tpsv = 85; /* temp to start throttling the cpu == 85C */ +} + diff --git a/src/mainboard/asus/p8z77-m_pro/board_info.txt b/src/mainboard/asus/p8z77-m_pro/board_info.txt new file mode 100644 index 0000000..66e6f0d --- /dev/null +++ b/src/mainboard/asus/p8z77-m_pro/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/P8Z77M_PRO/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.default b/src/mainboard/asus/p8z77-m_pro/cmos.default new file mode 100644 index 0000000..0635955 --- /dev/null +++ b/src/mainboard/asus/p8z77-m_pro/cmos.default @@ -0,0 +1,27 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +boot_option=Fallback +debug_level=Emergency +gfx_uma_size=224M +nmi=Enable +power_on_after_fail=Disable +sata_mode=AHCI +hyper_threading=Enable +#usb3_XXXXX options only used by MRC, not by Native RAM Init +usb3_mode=Enable +usb3_preOS_drv=Enable +usb3_streams=Enable +usb_powered_on_s5=Disable diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.layout b/src/mainboard/asus/p8z77-m_pro/cmos.layout new file mode 100644 index 0000000..a14c05f --- /dev/null +++ b/src/mainboard/asus/p8z77-m_pro/cmos.layout @@ -0,0 +1,219 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 4 debug_level +#399 1 r 0 unused +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 5 power_on_after_fail +411 1 e 6 sata_mode + +# coreboot config options: northbridge +416 5 e 7 gfx_uma_size + +# coreboot config options: cpu +421 1 e 8 hyper_threading + +# usb3_xxxx are just used when using MRC blob to init ram/usb/pci. +# Not used when using Native RAM Init. +422 2 e 9 usb3_mode +424 1 e 10 usb3_preOS_drv +425 1 e 11 usb3_streams +426 1 e 12 usb_powered_on_s5 + +# Sandy/Ivy Bridge MRC Scrambler Seed values +# Used in src/northbridge/intel/sandybridge/raminit_mrc.c +# and MUST NOT be covered by checksum! +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + + +# coreboot config options: check sums +992 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations +#ID value text + +# nmi +# Non Maskable Interrupt(NMI) support, which is an interrupt that may +# occur on a RAM or unrecoverable error. +# See coreboot/src/southbridge/intel/bd82x6x/lpc.c:pch_power_options() +1 0 Disable +1 1 Enable + +# not sure that is enum 2 but just in case ... +2 0 Enable +2 1 Disable + +# boot_option +3 0 Fallback +3 1 Normal + +# debug_level +# Is the verbosity level for debugging purposes. +# See coreboot/src/console/init.c:init_log_level() +# I recommend to set it to "Emergency" for the BIOS release version. +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +# power_on_after_fail +# What happens when the power goes doen in your house and,then,recovers power? +# Should the BIOS kept the computer OFF or turn it on? ) +# why 2 bits? it should be a bool according to : +# https://www.coreboot.org/Nvramtool#Commonly_used_CMOS.2FNVRAM_options +# See coreboot/src/southbridge/intel/common/smihandler.c:southbridge_smi_sleep +# coreboot/src/southbridge/intel/bd82x6x/lpc.c:pch_power_options() +# +5 0 Disable +5 1 Enable +5 2 Keep + +# +# sata_mode +# Used in src/southbridge/intel/bd82x6x/sata.c:sata_init() +# Serial ATA Advanced Host Controller Interface(AHCI) for modern HDD/SDD +# or IDE-Compatible for Windows XP, etc... +# See https://en.wikipedia.org/wiki/Advanced_Host_Controller_Interface +# +6 0 AHCI +6 1 Compatible + +# gfx_uma_size ( == Unified Memory the Intel IGP can use for graphics & +# rendering, using the system's DDR3 ). +# Used in src/northbridge/intel/sandybridge/early_init.c +# at function sandybridge_setup_graphics() +# If you have enough RAM, I recommend not to keep it below 224M, as the IGP +# won't be able to render 3D things well due to not enough VRAM memory! +# +7 0 32M +7 1 64M +7 2 96M +7 3 128M +7 4 160M +7 5 192M +7 6 224M +7 7 256M +7 8 288M +7 9 320M +7 10 352M +7 11 384M +7 12 416M +7 13 448M +7 14 480M +7 15 512M +7 16 1024M + +# hyper_threading +# Used in src/cpu/intel/hyperthreading/intel_sibling.c:intel_sibling_init() +# Some Intel CPUs have the ability to execute more than a thread per core +# in an effective way. +# See this: https://en.wikipedia.org/wiki/Hyper-threading +# I recommend to keep it always Enable +# +8 0 Disable +8 1 Enable + +# usb3_mode +# Disable = Use the port always as USB 2.0 for compatibility +# Enable = Use the port always as USB 3.0 for speed +# Auto = Initialize the port as USB 2.0, until the OS loads +# xHCI USB 3.0 driver +# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver +# and the computer is reset, keep the USB 3.0 mode. +# +# I recommend to set this to Enable, as the ASUS P8Z77-M Pro Gen3 has +# four USB3.0 ports and the user can plug some device into any other +# of the USB2 port for compatibility. +# +9 0 Disable +9 1 Enable +9 2 Auto +9 3 SmartAuto + +# usb3_preOS_drv +# Load or not pre-OS xHCI bios driver +# I recommend to set it to Enable, so you could use full-speed on some +# devices prior to booting the operating system ( like an iPXE USB dongle ) +# +10 0 Disable +10 1 Enable + +# usb3_streams +# Enablong streams provide more speed (as they can use 64Kb packets), +# but they might cause incompatibilities with some devices. +# +11 0 Disable +11 1 Enable + +# usb_powered_on_s5 +# Option to let the user to decide if wants to keep the USB ports enabled on +# S5(power off computer) for instance to charge a mobile phone while the +# computer is shut down. +# +12 0 Disable +12 1 Enable + +# ----------------------------------------------------------------- +# <startBit[must be byte-aligned]> <endBit[must be byte aligned]> +# <bit where to start storing checksum[must be 16bits-aligned]> +checksums + +checksum 392 431 992 diff --git a/src/mainboard/asus/p8z77-m_pro/data.vbt b/src/mainboard/asus/p8z77-m_pro/data.vbt new file mode 100644 index 0000000..34679b3 --- /dev/null +++ b/src/mainboard/asus/p8z77-m_pro/data.vbt Binary files differ diff --git a/src/mainboard/asus/p8z77-m_pro/devicetree.cb b/src/mainboard/asus/p8z77-m_pro/devicetree.cb new file mode 100644 index 0000000..fd1f5ab --- /dev/null +++ b/src/mainboard/asus/p8z77-m_pro/devicetree.cb @@ -0,0 +1,125 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "4" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x00000000" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x0000ff29" + register "p_cnt_throttling_supported" = "0" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" # 0x3=SATAIII + register "sata_port_map" = "0x3f" # Enable the 6 SATA ports on board + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" # the four ports + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x1043 0x84ca + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1043 0x84ca + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # P8Z77-M Pro does not use "gbe.bin" + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1043 0x84ca + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x1043 0x8436 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1043 0x84ca + end + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 on # PCIe Port #6 + subsystemid 0x1043 0x84ca + end + device pci 1c.6 on # PCIe Port #7 + subsystemid 0x1043 0x84ca + end + device pci 1c.7 on # PCIe Port #8 + subsystemid 0x1043 0x84ca + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1043 0x84ca + end + device pci 1e.0 off end # PCI bridge(P8Z77-M Pro has no legacy PCI) + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x1043 0x84ca + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM module + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x1043 0x84ca + end + device pci 1f.3 on # SMBus + subsystemid 0x1043 0x84ca + end + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1043 0x84ca + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x1043 0x84ca + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x1043 0x84ca + end + end +end diff --git a/src/mainboard/asus/p8z77-m_pro/dsdt.asl b/src/mainboard/asus/p8z77-m_pro/dsdt.asl new file mode 100644 index 0000000..b0db386 --- /dev/null +++ b/src/mainboard/asus/p8z77-m_pro/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + /* Some macros */ + #include "acpi/platform.asl" + #include "acpi/superio.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads b/src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads new file mode 100644 index 0000000..622ccdd --- /dev/null +++ b/src/mainboard/asus/p8z77-m_pro/gma-mainboard.ads @@ -0,0 +1,33 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com> +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- Discovered the correct ports were HDMI 1&3 just using + -- "intelvbttool --inoprom vga.rom -d" and looking for "dvo_port" + ports : constant Port_List := + (HDMI1, -- DVI-D port on rear(managed through HDMI, it's not an error!) + HDMI3, -- real HDMI port on rear + Analog, -- VGA port on rear + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/p8z77-m_pro/gpio.c b/src/mainboard/asus/p8z77-m_pro/gpio.c new file mode 100644 index 0000000..458fff5 --- /dev/null +++ b/src/mainboard/asus/p8z77-m_pro/gpio.c @@ -0,0 +1,200 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +/* generated by autoport */ + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asus/p8z77-m_pro/hda_verb.c b/src/mainboard/asus/p8z77-m_pro/hda_verb.c new file mode 100644 index 0000000..d294474 --- /dev/null +++ b/src/mainboard/asus/p8z77-m_pro/hda_verb.c @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* generated by autoport */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x10438436, /* Subsystem ID */ + + 0x0000000f, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x10438436), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0x99430140), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x01014010), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x01011012), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x0, 0x16, 0x01016011), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x01012014), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x01a19850), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19c60), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x0181305f), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214c20), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x4005e601), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x01456130), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x58560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/p8z77-m_pro/mainboard.c b/src/mainboard/asus/p8z77-m_pro/mainboard.c new file mode 100644 index 0000000..fdd8529 --- /dev/null +++ b/src/mainboard/asus/p8z77-m_pro/mainboard.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <device/pci_type.h> +#include <device/pci_ops.h> + +static void mainboard_enable(struct device *dev) +{ + /* + * As the ASUS P8Z77-M Pro is a desktop motherboard, there is no + * internal LCD connection to eDP/LVDS, so we must use + * GMA_INT15_ACTIVE_LFP_NONE as first parameter. More info at: + * https://github.com/coreboot/coreboot/tree/master/util/autoport + */ + install_intel_vga_int15_handler ( GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0 ); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable +}; + diff --git a/src/mainboard/asus/p8z77-m_pro/romstage.c b/src/mainboard/asus/p8z77-m_pro/romstage.c new file mode 100644 index 0000000..8f3258c --- /dev/null +++ b/src/mainboard/asus/p8z77-m_pro/romstage.c @@ -0,0 +1,304 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Vlado Cibic <vladocb(a)protonmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6779d/nct6779d.h> + +#include <option.h> + +#if CONFIG(USE_NATIVE_RAMINIT) + #include <northbridge/intel/sandybridge/raminit_native.h> +#else + #include <northbridge/intel/sandybridge/raminit.h> + #include <northbridge/intel/sandybridge/pei_data.h> +#endif + +void pch_enable_lpc(void) +{ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF1_LPC_EN | CNF2_LPC_EN | MC_LPC_EN | + KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | + COMB_LPC_EN | COMA_LPC_EN); + + /* Generic Decode Ranges 1/2/3/4. Already in devicetree.cb */ + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x000c0291u); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x00000000u); + pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x00000000u); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0000ff29u); + + /* 10000b=0x10 to enable 2F8h – 2FFh (COMB->COM2) */ + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010u); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* {enable, current, oc_pin} */ + { 1, 2, 0 }, /* USB3 front internal header */ + { 1, 2, 0 }, /* USB3 front internal header */ + { 1, 2, 1 }, /* USB3 rear, ETH top */ + { 1, 2, 1 }, /* USB3 rear, ETH botton */ + { 1, 2, 2 }, /* USB2 rear, PS2 top */ + { 1, 2, 2 }, /* USB2 read, PS2 bottom */ + { 0, 2, 3 }, /* USB2 internal header 1 (USB1112 on board). Let's disable it */ + { 0, 2, 3 }, /* USB2 internal header 1 (USB1112 on board). Let's disable it */ + { 0, 2, 4 }, /* USB2 internal header 2 (USB910 on board). Let's disable it */ + { 0, 2, 4 }, /* USB2 internal header 2 (USB910 on board). Let's disable it */ + { 0, 2, 6 }, /* USB2 internal header 3 (USB78 on board). Let's disable it */ + { 0, 2, 5 }, /* USB2 internal header 3 (USB78 on board). Let's disable it */ + { 0, 2, 5 }, /* ??? . Let's disable it */ + { 0, 2, 6 } /* ??? . Let's disable it */ +}; /* NOTE: Asmedia ASM1042 USB3 aren't managed by this, but by PCIe driver! */ + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + static const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); + + /* Begin configuration */ + nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); + + /* + * Config PS/2 keyboard & mouse. + * See section "21.5 Configuration Register -> Logical Device 5 + * ( Keyboard Controller)", page 315-316 on Nuvoton 6779D datasheet. + * pnp_set_iobase() funcs write 16bits value ( writes 1st the high part ). + * pnp_set_irq() funcs write 8bits value. + * pnp_set_drq() funcs write (8bits value & 0xff). + * The "&0xff" is cuz some systems may define CHAR_SIZE=9, so need a mask. + * Values are set accoding to the Asus Bios 2203 defaults, extracted using + * "superiotool -d" and checking Nuvoton 6779D data sheet. + * It's needed to include "#include <drivers/pc80/pc/ps2_controller.asl>" + * in superio.asl / DSDT.asl, and also to specify DRIVERS_PS2_KEYBOARD=y + * in your config file. + */ + static const pnp_devfn_t KBC_DEV = PNP_DEV(0x2e, NCT6779D_KBC); + pnp_set_logical_device ( KBC_DEV ); + + pnp_set_enable(KBC_DEV, 1); /* enable logical device */ + pnp_set_iobase(KBC_DEV, 0x60u, 0x0060u); /* KBC1 IO base address (KBD) */ + pnp_set_iobase(KBC_DEV, 0x62u, 0x0064u); /* KBC2 IO base address (AUX) */ + pnp_set_drq(KBC_DEV, 0x70u, 0x01u); /* Keyboard IRQ=1 */ + pnp_set_drq(KBC_DEV, 0x72u, 0x0cu); /* Mouse IRQ=12 */ + pnp_set_drq(KBC_DEV, 0xf0u, 0x82u); + /* KB 12Mhz + Disable Port 92 + Gate A20 hw speedup + soft KBRST */ + /* Defval=0x83(KBRST by hw instead of sw). Asus Bios 2203 has 0x82 */ + + /* + * Config several SuperIO ACPI things. + * See section "21.10 Configuration Register -> Logical Device A (ACPI)", + * page 340-341 + */ + static const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6779D_ACPI); + pnp_set_logical_device ( ACPI_DEV ); + + uint8_t acp = (uint8_t)0U; + + /* + * We prefer the user to control "power on after fail" this via a NVRAM + * option instead of coreboot's make xconfig Maiboard-> + * POWER_STATE_OFF_AFTER_FAILURE / POWER_STATE_ON_AFTER_FAILURE / + * POWER_STATE_PREVIOUS_AFTER_FAILURE + */ + int powerOnAfterFail = 0; + get_option ( &powerOnAfterFail, "power_on_after_fail" ); + switch (powerOnAfterFail) { + case 2: + /* keep state before power off */ + acp = (uint8_t)0x40U; /* 01000000b=0x40 */ + break; + case 1: + /* enable: turn computer on after computer fail */ + acp = (uint8_t)0x20U; /* 00100000b=0x20 */ + break; + case 0: + default: + /* disable: turn off computer */ + acp = (uint8_t)0U; /* bits 6-5 to zero */ + break; + } + + /* + * Set "3VSBSW# enable bit" to keep RAM always powered on in S3 suspend, + * so do an OR mask 00010000b=0x10. + */ + acp |= (uint8_t)0x10u; + pnp_write_config ( ACPI_DEV, 0xe4u, acp ); + + /* + * Enable 0.5s keyboard delay after S3 suspend(EN_ONPSOUT-VBAT) to let + * devices to response better to power change. + */ + uint8_t acpiDelay = pnp_read_config ( ACPI_DEV, 0xe7u ); + acpiDelay |= (uint8_t)0x10u; /* Bit 4: Use 0.5s delay, OR mask 10000b=0x10 */ + pnp_write_config ( ACPI_DEV, 0xe7u, acpiDelay ); + + /* End configuration */ + nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); +} + +#if CONFIG(USE_NATIVE_RAMINIT) + void mainboard_get_spd(spd_raw_data *spd, bool id_only) + { + /* we got the index values(0x50-0x53) inspecting the SMBus */ + read_spd ( &spd[0], 0x50, id_only ); + read_spd ( &spd[1], 0x51, id_only ); + read_spd ( &spd[2], 0x52, id_only ); + read_spd ( &spd[3], 0x53, id_only ); + } +#else + int mainboard_should_reset_usb(int s3resume) + { + return !s3resume; + } + + void mainboard_fill_pei_data(struct pei_data *pei_data) + { + struct pei_data pd = + { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = (uintptr_t)DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 1, /* 0=Mobile, 1=Desktop/Server */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + /* SMBus ones mul by 2! + * Hardcoding 2x DIMMs at the BLUE slots only! + */ + .spd_addresses = { 0x00, 0xa2, 0x00, 0xa6 }, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + /* The P8Z77-M Pro apparently uses an EC. + * Asus Bios 2203 shows "XUECA-016" + */ + .ec_present = 1, + /* The P8Z77-M Pro has gbe.bin data config section + * in its original BIOS. + */ + .gbe_enable = 0, + /* 0=both DIMM enabled; 1=disable dimm#A(black); + * 2=disable DIMM#B(blue); 3=disable both DIMMS. + */ + .dimm_channel0_disabled = 1, + /* 0=both DIMM enabled; 1=disable dimm#A(black); + * 2=disable DIMM#B(blue); 3=disable both DIMMS. + */ + .dimm_channel1_disabled = 1, + .max_ddr3_freq = 1600, /* 1333=sandy; 1600=Ivy */ + .usb_port_config = { + /* copyed mainboard_usb_ports array above and added cable len: + * {enabled, oc_pin, cable len 0x0080=<8inches/20cm} + */ + { 1, 0, 0x0080 }, /* USB3 front internal header */ + { 1, 0, 0x0080 }, /* USB3 front internal header */ + { 1, 1, 0x0080 }, /* USB3 ETH top connector */ + { 1, 1, 0x0080 }, /* USB3 ETH botton connector */ + { 1, 2, 0x0080 }, /* USB2 PS2 top connector */ + { 1, 2, 0x0080 }, /* USB2 PS2 botton connector */ + { 0, 3, 0x0080 }, /* USB2 internal header (USB1112 on board) */ + { 0, 3, 0x0080 }, /* USB2 internal header (USB1112 on board) */ + { 0, 4, 0x0080 }, /* USB2 internal header (USB910 on board) */ + { 0, 4, 0x0080 }, /* USB2 internal header (USB910 on board) */ + { 0, 6, 0x0080 }, /* USB2 internal header (USB78 on board) */ + { 0, 5, 0x0080 }, /* USB2 internal header (USB78 on board) */ + { 0, 5, 0x0080 }, /* ??? Lets disable it */ + { 0, 6, 0x0080 } /* ??? Lets disable it */ + }, + .usb3 = { + /* 0=Disable; 1=Enable(start at USB3 speed) + * 2=Auto(start as USB2 until OS) + * 3=Smart Auto(like #2 but keep speed on reboot) + */ + 1, + /* 4 bit switch mask. 0=not switchable, 1=switchable; + * Means once it's loaded the OS, it can swap ports + * from/to EHCI/xHCI + */ + 0xf, + 1, /* 0=No xHCI preOS driver; 1=xHCI preOS driver */ + /* 0=Don't use xHCI streams (less speed,more compatibility) + * 1=use xHCI streams for better speed (and less compatibility) + */ + 1 + }, + /* ASUS P8Z77-M Pro supports 1.35v DIMMs according to the manual */ + .ddr3lv_support = 1, + /* PCIe 3.0 support. As we use Ivy Bridge, let's enable this... + * but might cause some system inestability! + */ + .pcie_init = 1, + /* Command Rate. 0=Auto; 1=1N; 2=2N. + * Better leave it always at Auto for compatibility & stability. + */ + .nmode = 0, + /* DDR refresh rate. 0=Auto based on DRAM's temperature; + * 1=Normal rate; 2=Double rate for better stability. + */ + .ddr_refresh_rate_config = 0 + }; + + /* + * USB3 mode: + * 0 = Disable: work always as USB 2.0(ehci) + * 1 = Enable: work always as USB 3.0(xhci) + * 2 = Auto: work as USB2.0(ehci) until OS loads USB3 xhci driver + * 3 = Smart Auto : same than Auto, but if OS loads USB3 driver and + * reboots, it will keep the USB3.0 speed. + */ + int usb3Mode = 1; + get_option ( &usb3Mode, "usb3_mode" ); + pd.usb3.mode = (uint16_t)usb3Mode; + + /* Load USB3 pre-OS xHCI driver */ + int usb3PreOSDrv = 1; + get_option ( &usb3PreOSDrv, "usb3_preOS_drv" ); + pd.usb3.preboot_support = (uint16_t)usb3PreOSDrv; + + /* Use USB3 xHCI streams */ + int usb3Streams = 1; + get_option ( &usb3Streams, "usb3_streams" ); + pd.usb3.xhci_streams = (uint16_t)usb3Streams; + + /* copy the data to output PEI */ + *pei_data = pd; + } +#endif /* CONFIG(USE_NATIVE_RAMINIT) */ + -- To view, visit https://review.coreboot.org/c/coreboot/+/33328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47d24ac8b236f929c3160f9a769b971d83710f9d Gerrit-Change-Number: 33328 Gerrit-PatchSet: 1 Gerrit-Owner: Vlado Cibic Gerrit-MessageType: newchange

7 73

Change in ...coreboot[master]: src/superio/nuvoton/common/early_serial.c: Add symbol to select COM p...
by Pavel Sayekat (Code Review) 27 Jun '19

27 Jun '19

Pavel Sayekat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33841 Change subject: src/superio/nuvoton/common/early_serial.c: Add symbol to select COM port for NCT5539D src/superio/nuvoton/Makefile.inc: Add definition for NCT5539D src/superio/nuvoton: Add support for NCT5539D ...................................................................... src/superio/nuvoton/common/early_serial.c: Add symbol to select COM port for NCT5539D src/superio/nuvoton/Makefile.inc: Add definition for NCT5539D src/superio/nuvoton: Add support for NCT5539D Signed-off-by: Pavel Sayekat <pavelsayekat(a)gmail.com> Change-Id: I3c07eb97f879033ff500c632f6cb42e5e7a61024 --- M src/superio/nuvoton/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/33841/1 diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index de4e99c..7306242 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -24,3 +24,4 @@ subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += nct6791d subdirs-$(CONFIG_SUPERIO_NUVOTON_NPCD378) += npcd378 +subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += nct5539d -- To view, visit https://review.coreboot.org/c/coreboot/+/33841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c07eb97f879033ff500c632f6cb42e5e7a61024 Gerrit-Change-Number: 33841 Gerrit-PatchSet: 1 Gerrit-Owner: Pavel Sayekat Gerrit-MessageType: newchange

5 8

Change in ...coreboot[master]: superio/nuvoton/nct6791d: Add symbol to select COM port:x
by Pavel Sayekat (Code Review) 27 Jun '19

27 Jun '19

Pavel Sayekat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33840 Change subject: superio/nuvoton/nct6791d: Add symbol to select COM port:x ...................................................................... superio/nuvoton/nct6791d: Add symbol to select COM port:x Signed-off-by: Pavel Sayekat <pavelsayekat(a)gmail.com> Change-Id: I84bd8312cb9d0a2545b4e9d0de458e048c009301 --- M src/superio/nuvoton/common/early_serial.c A src/superio/nuvoton/nct5539d/Kconfig A src/superio/nuvoton/nct5539d/Makefile.inc A src/superio/nuvoton/nct5539d/nct5539d.h A src/superio/nuvoton/nct5539d/superio.c 5 files changed, 196 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33840/1 diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index eaa3c5a..aaa0c63 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -73,6 +73,10 @@ /* Route COM A to GPIO8 pin group */ pnp_write_config(dev, 0x2a, 0x00); + if (CONFIG(SUPERIO_NUVOTON_NCT5539D_COM_A)) + /* Route COM A to GPIO8 pin group */ + pnp_write_config(dev, 0x2a, 0x40); + pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); diff --git a/src/superio/nuvoton/nct5539d/Kconfig b/src/superio/nuvoton/nct5539d/Kconfig new file mode 100644 index 0000000..0dd1402 --- /dev/null +++ b/src/superio/nuvoton/nct5539d/Kconfig @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_NUVOTON_NCT5539D + bool + select SUPERIO_NUVOTON_COMMON_PRE_RAM + +config SUPERIO_NUVOTON_NCT5539D_COM_A + bool + depends on SUPERIO_NUVOTON_NCT5539D + default n diff --git a/src/superio/nuvoton/nct5539d/Makefile.inc b/src/superio/nuvoton/nct5539d/Makefile.inc new file mode 100644 index 0000000..6e3fdf2 --- /dev/null +++ b/src/superio/nuvoton/nct5539d/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += superio.c diff --git a/src/superio/nuvoton/nct5539d/nct5539d.h b/src/superio/nuvoton/nct5539d/nct5539d.h new file mode 100644 index 0000000..f34660c --- /dev/null +++ b/src/superio/nuvoton/nct5539d/nct5539d.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_NUVOTON_NCT5539D_H +#define SUPERIO_NUVOTON_NCT5539D_H + +/* Logical Device Numbers (LDN). */ +#define NCT5539D_SP1 0x02 /* UART A */ +#define NCT5539D_KBC 0x05 /* Keyboard Controller */ +#define NCT5539D_CIR 0x06 /* Consumer IR */ +#define NCT5539D_GPIO78 0x07 /* GPIO 7 & 8 */ +#define NCT5539D_WDT1_WDT3_GPIO0 0x08 /* WDT1, WDT3, GPIO 0 & KBC P20 */ +#define NCT5539D_GPIO2345 0x09 /* GPIO 2, 3, 4 & 5 */ +#define NCT5539D_ACPI 0x0A /* ACPI */ +#define NCT5539D_HWM_FPLED 0x0B /* HW Monitor, Front Panel LED */ +#define NCT5539D_BCLK_WDT2 0x0D /* BCLK, WDT2 */ +#define NCT5539D_CIRWUP 0x0E /* CIR Wake-Up */ +#define NCT5539D_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open-Drain */ +#define NCT5539D_GPIO_PSO 0x11/*GPIO, RI PSOUT Wake-Up Status*/ +#define NCT5539D_SWEC 0x12/*SW Error Control*/ +#define NCT5539D_FLED 0x15 /* Fading LED */ +#define NCT5539D_DS 0x16 /* Deep Sleep */ + +/* Virtual LDNs */ +#define NCT5539D_WDT1 ((0 << 8) | NCT5539D_WDT1_WDT3_GPIO0) +#define NCT5539D_WDT3 ((4 << 8) | NCT5539D_WDT1_WDT3_GPIO0) +#define NCT5539D_GPIOBASE ((3 << 8) | NCT5539D_WDT1_WDT3_GPIO0) +#define NCT5539D_GPIO0 ((1 << 8) | NCT5539D_WDT1_WDT3_GPIO0) +#define NCT5539D_GPIO2 ((0 << 8) | NCT5539D_GPIO2345) +#define NCT5539D_GPIO3 ((1 << 8) | NCT5539D_GPIO2345) +#define NCT5539D_GPIO4 ((2 << 8) | NCT5539D_GPIO2345) +#define NCT5539D_GPIO5 ((3 << 8) | NCT5539D_GPIO2345) +#define NCT5539D_GPIO7 ((1 << 8) | NCT5539D_GPIO78) +#define NCT5539D_GPIO8 ((2 << 8) | NCT5539D_GPIO78) +#define NCT5539D_DS5 ((0 << 8) | NCT5539D_DS) +#define NCT5539D_DS3 ((1 << 8) | NCT5539D_DS) +#define NCT5539D_PCHDSW ((3 << 8) | NCT5539D_DS) +#define NCT5539D_DSWWOPT ((4 << 8) | NCT5539D_DS) +#define NCT5539D_DS3OPT ((5 << 8) | NCT5539D_DS) +#define NCT5539D_DSDSS ((6 << 8) | NCT5539D_DS) +#define NCT5539D_DSPU ((7 << 8) | NCT5539D_DS) + +#endif /* SUPERIO_NUVOTON_NCT5539D_H */ diff --git a/src/superio/nuvoton/nct5539d/superio.c b/src/superio/nuvoton/nct5539d/superio.c new file mode 100644 index 0000000..4cec976 --- /dev/null +++ b/src/superio/nuvoton/nct5539d/superio.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2015 Matt DeVillier <matt.devillier(a)gmail.com> + * Copyright (C) 2016 Omar Pakker <omarpakker+coreboot(a)gmail.com> +* Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <stdlib.h> +#include <superio/conf_mode.h> + +#include "nct5539d.h" + + +static void nct5539d_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case NCT5539D_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = nct5539d_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, NCT5539D_SP1, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT5539D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, + 0x0fff, 0x0fff, }, + { NULL, NCT5539D_CIR, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT5539D_ACPI}, + { NULL, NCT5539D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, + 0x0ffe, 0x0ffe, }, + { NULL, NCT5539D_BCLK_WDT2}, + { NULL, NCT5539D_CIRWUP, PNP_IO0 | PNP_IRQ0, + 0x0ff8, }, + { NULL, NCT5539D_GPIO_PP_OD}, + { NULL, NCT5539D_WDT1}, + { NULL, NCT5539D_WDT3}, + { NULL, NCT5539D_GPIOBASE, PNP_IO0, + 0x0ff8, }, + { NULL, NCT5539D_GPIO0}, + { NULL, NCT5539D_GPIO2}, + { NULL, NCT5539D_GPIO3}, + { NULL, NCT5539D_GPIO4}, + { NULL, NCT5539D_GPIO5}, + { NULL, NCT5539D_GPIO7}, + { NULL, NCT5539D_GPIO8}, + { NULL, NCT5539D_GPIO_PSO}, + { NULL, NCT5539D_SWEC}, + { NULL, NCT5539D_FLED}, + { NULL, NCT5539D_DS5}, + { NULL, NCT5539D_DS3}, + { NULL, NCT5539D_PCHDSW}, + { NULL, NCT5539D_DSWWOPT}, + { NULL, NCT5539D_DS3OPT}, + { NULL, NCT5539D_DSDSS}, + { NULL, NCT5539D_DSPU}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_nuvoton_nct5539d_ops = { + CHIP_NAME("NUVOTON NCT5539D Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/33840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bd8312cb9d0a2545b4e9d0de458e048c009301 Gerrit-Change-Number: 33840 Gerrit-PatchSet: 1 Gerrit-Owner: Pavel Sayekat Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: mb/upsquared: Align partitions to 4KiB
by Patrick Rudolph (Code Review) 27 Jun '19

27 Jun '19

Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33784 ) Change subject: mb/upsquared: Align partitions to 4KiB ...................................................................... mb/upsquared: Align partitions to 4KiB This fixes warnings while booting coreboot. Change-Id: If1e99b74ded5f743a3ad4fc829ae9747276c483a Signed-off-by: Felix Singer <felix.singer(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33784 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/up/squared/upsquared.fmd 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved Arthur Heymans: Looks good to me, but someone else must approve diff --git a/src/mainboard/up/squared/upsquared.fmd b/src/mainboard/up/squared/upsquared.fmd index 4ea1375..891138e 100644 --- a/src/mainboard/up/squared/upsquared.fmd +++ b/src/mainboard/up/squared/upsquared.fmd @@ -3,14 +3,14 @@ SI_BIOS@0x1000 0xefe000 { IFWI@0x0 0x2ff000 OBB@0x2ff000 0xbff000 { - FMAP@0x0 0x800 - UNIFIED_MRC_CACHE@0x800 0x21000 { + FMAP@0x0 0x1000 + UNIFIED_MRC_CACHE@0x1000 0x21000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 RW_VAR_MRC_CACHE@0x20000 0x1000 } - CONSOLE@0x21800 0x20000 - COREBOOT(CBFS)@0x41800 0xb7d800 + CONSOLE@0x22000 0x20000 + COREBOOT(CBFS)@0x42000 0xb7d000 BIOS_UNUSABLE@0xbbf000 0x40000 } } -- To view, visit https://review.coreboot.org/c/coreboot/+/33784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1e99b74ded5f743a3ad4fc829ae9747276c483a Gerrit-Change-Number: 33784 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: mb/upsquared: Align partitions to 4KiB
by Patrick Rudolph (Code Review) 27 Jun '19

27 Jun '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33784 ) Change subject: mb/upsquared: Align partitions to 4KiB ...................................................................... Patch Set 4: > Patch Set 4: Code-Review+1 > > Note that you can also try to drop the @xxxx offset and sometimes the size. That way you have to compute less things. See for instance https://review.coreboot.org/c/coreboot/+/33276/1 Sounds good. @Felix Let's update all FMDs in a separate commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/33784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1e99b74ded5f743a3ad4fc829ae9747276c483a Gerrit-Change-Number: 33784 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph Gerrit-Comment-Date: Thu, 27 Jun 2019 11:52:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/asrock/h110m: set serirq_mode to continuous mode
by Maxim Polyakov (Code Review) 27 Jun '19

27 Jun '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33801 Change subject: mb/asrock/h110m: set serirq_mode to continuous mode ...................................................................... mb/asrock/h110m: set serirq_mode to continuous mode This option sets the serial IRQ mode for LPC bus in the devicetree.cb Change-Id: I37e26b271fb61f6c0343d6bf65c029924df82caf Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/33801/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 158801f..3067ffe 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -62,6 +62,9 @@ register "pirqg_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11" + # Set LPC Serial IRQ mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s register "PmConfigSlpS3MinAssert" = "0x02" -- To view, visit https://review.coreboot.org/c/coreboot/+/33801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37e26b271fb61f6c0343d6bf65c029924df82caf Gerrit-Change-Number: 33801 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

2 6

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2019