coreboot-gerrit June 2019

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Change in ...coreboot[master]: security: Add memory subfolder
by Philipp Deppenwiese (Code Review) 26 Jun '19

26 Jun '19

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31548 ) Change subject: security: Add memory subfolder ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110 Gerrit-Change-Number: 31548 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alex Thiessen <alex.thiessen.de+coreboot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 26 Jun 2019 12:07:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/upsquared: Align partitions to 4KiB
by Arthur Heymans (Code Review) 26 Jun '19

26 Jun '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33784 ) Change subject: mb/upsquared: Align partitions to 4KiB ...................................................................... Patch Set 4: Code-Review+1 Note that you can also try to drop the @xxxx offset and sometimes the size. That way you have to compute less things. See for instance https://review.coreboot.org/c/coreboot/+/33276/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/33784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1e99b74ded5f743a3ad4fc829ae9747276c483a Gerrit-Change-Number: 33784 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 26 Jun 2019 10:17:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake/Kconfig: Don't have all variants select SOC_INTE...
by Arthur Heymans (Code Review) 26 Jun '19

26 Jun '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33559 Change subject: soc/intel/cannonlake/Kconfig: Don't have all variants select SOC_INTEL_CANNONLAKE ...................................................................... soc/intel/cannonlake/Kconfig: Don't have all variants select SOC_INTEL_CANNONLAKE Change-Id: Ica11c68377e3d0dc8a8f48198e01a74d7bebe642 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc 2 files changed, 9 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/33559/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dac3522..277635a 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -1,12 +1,6 @@ -config SOC_INTEL_CANNONLAKE - bool - help - Intel Cannonlake support - config SOC_INTEL_COMMON_CANNONLAKE_BASE bool default n - select SOC_INTEL_CANNONLAKE help Single Kconfig option to select common base Cannonlake support. This Kconfig will help to select majority of CNL SoC features. @@ -16,34 +10,37 @@ required SoC support FSP headers. Any future Intel SoC would like to make use of CNL support might just select this Kconfig. + +config SOC_INTEL_CANNONLAKE + bool + select SOC_INTEL_COMMON_CANNONLAKE_BASE + help + Intel Cannonlake support + config SOC_INTEL_COFFEELAKE bool - default n select SOC_INTEL_COMMON_CANNONLAKE_BASE help Intel Coffeelake support config SOC_INTEL_WHISKEYLAKE bool - default n select SOC_INTEL_COMMON_CANNONLAKE_BASE help Intel Whiskeylake support config SOC_INTEL_COMETLAKE bool - default n select SOC_INTEL_COMMON_CANNONLAKE_BASE help Intel Cometlake support config SOC_INTEL_CANNONLAKE_PCH_H bool - default n help Choose this option if you have a PCH-H chipset. -if SOC_INTEL_CANNONLAKE +if SOC_INTEL_COMMON_CANNONLAKE_BASE config CPU_SPECIFIC_OPTIONS def_bool y diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 1328944..77b48f8 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y) +ifeq ($(CONFIG_SOC_INTEL_COMMON_CANNONLAKE_BASE),y) subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode -- To view, visit https://review.coreboot.org/c/coreboot/+/33559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica11c68377e3d0dc8a8f48198e01a74d7bebe642 Gerrit-Change-Number: 33559 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cbfstool/fit: need inttypes.h for PRIx64
by Joel Kitching (Code Review) 26 Jun '19

26 Jun '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33780 Change subject: cbfstool/fit: need inttypes.h for PRIx64 ...................................................................... cbfstool/fit: need inttypes.h for PRIx64 This is causing coreboot build in Chromium OS to fail. BUG=None TEST=emerge-eve coreboot BRANCH=none Change-Id: I4faa140b3046651b4ed0a9aeefe437048c6ef0da Signed-off-by: Joel Kitching <kitching(a)google.com> --- M util/cbfstool/fit.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/33780/1 diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index 4cd84f2..ee12c96 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <inttypes.h> #include <stdint.h> #include <stdio.h> #include <stdlib.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4faa140b3046651b4ed0a9aeefe437048c6ef0da Gerrit-Change-Number: 33780 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/up/squared: Remove unnecessary code
by Philipp Deppenwiese (Code Review) 26 Jun '19

26 Jun '19

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33136 ) Change subject: mb/up/squared: Remove unnecessary code ...................................................................... mb/up/squared: Remove unnecessary code This patch removes unnecessary code which configures default FSP values. Change-Id: If7dae4f24a9fcb01d2d47063dd3a0f4ce6c120d2 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33136 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/up/squared/ramstage.c 1 file changed, 38 insertions(+), 376 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/up/squared/ramstage.c b/src/mainboard/up/squared/ramstage.c index e9fcfb2..be70ea9 100644 --- a/src/mainboard/up/squared/ramstage.c +++ b/src/mainboard/up/squared/ramstage.c @@ -29,7 +29,6 @@ silconfig->CStateUnDemotion = 0x3; // 0x0 silconfig->PkgCStateDemotion = 0x1; // 0x0 silconfig->PkgCStateUnDemotion = 0x1; // 0x0 - silconfig->IpuEn = 0x0; // 0x1 silconfig->Pme = 0x1; // 0x0 silconfig->HdAudioIoBufferOwnership = 0x3; // 0x0 silconfig->DspEndpointDmic = 0x0; // 0x1 @@ -43,390 +42,53 @@ silconfig->HpetDeviceNumber = 0xF; // 0x1f silconfig->IoApicBdfValid = 0x1; // 0x0 silconfig->IoApicDeviceNumber = 0x1F; // 0xf - silconfig->IshEnable = 0x0; // 0x1 - silconfig->SpiEiss = 0x0; // 0x1 silconfig->LPSS_S0ixEnable = 0x1; // 0x0 - silconfig->SdcardEnabled = 0x0; // 0x1 silconfig->eMMCHostMaxSpeed = 0x2; // 0x0 silconfig->Usb30Mode = 0x1; // 0x0 - silconfig->VtdEnable = 0x1; // 0x0 - silconfig->MonitorMwaitEnable = 0x0; // 0x1 - silconfig->HdAudioDspUaaCompliance = 0x1; // 0x0 - silconfig->InitS3Cpu = 0x1; // 0x0 + silconfig->HdAudioDspUaaCompliance = 0x1; // 0x0 + silconfig->InitS3Cpu = 0x1; // 0x0 - silconfig->PortUsb20PerPortTxPeHalf[0] = 0x0; - silconfig->PortUsb20PerPortPeTxiSet[0] = 0x7; - silconfig->PortUsb20PerPortTxiSet[0] = 0x0; - silconfig->PortUsb20HsSkewSel[0] = 0x0; - silconfig->PortUsb20IUsbTxEmphasisEn[0] = 0x3; - silconfig->PortUsb20PerPortRXISet[0] = 0x0; - silconfig->PortUsb20HsNpreDrvSel[0] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[0] = 0x1003; // 0x0 + silconfig->PcieRpLtrMaxSnoopLatency[0] = 0x1003; // 0x0 - silconfig->PortUsb20PerPortTxPeHalf[1] = 0x0; - silconfig->PortUsb20PerPortPeTxiSet[1] = 0x6; - silconfig->PortUsb20PerPortTxiSet[1] = 0x0; - silconfig->PortUsb20HsSkewSel[1] = 0x0; - silconfig->PortUsb20IUsbTxEmphasisEn[1] = 0x3; - silconfig->PortUsb20PerPortRXISet[1] = 0x0; - silconfig->PortUsb20HsNpreDrvSel[1] = 0x0; + silconfig->PcieRpHotPlug[1] = 0x0; // 0x1 + silconfig->PcieRpPmSci[1] = 0x1; // 0x0 + silconfig->PcieRpTransmitterHalfSwing[1] = 0x0; // 0x1 + silconfig->PcieRpClkReqNumber[1] = 0x3; // 0x5 + silconfig->PcieRpLtrMaxNonSnoopLatency[1] = 0x1003; // 0x0 + silconfig->PcieRpLtrMaxSnoopLatency[1] = 0x1003; // 0x0 - silconfig->PortUsb20PerPortTxPeHalf[2] = 0x0; - silconfig->PortUsb20PerPortPeTxiSet[2] = 0x6; - silconfig->PortUsb20PerPortTxiSet[2] = 0x0; - silconfig->PortUsb20HsSkewSel[2] = 0x0; - silconfig->PortUsb20IUsbTxEmphasisEn[2] = 0x3; - silconfig->PortUsb20PerPortRXISet[2] = 0x0; - silconfig->PortUsb20HsNpreDrvSel[2] = 0x0; + silconfig->PcieRpHotPlug[2] = 0x0; // 0x1 + silconfig->PcieRpPmSci[2] = 0x1; // 0x0 + silconfig->PcieRpTransmitterHalfSwing[2] = 0x0; // 0x1 + silconfig->PcieRpLtrMaxNonSnoopLatency[2] = 0x1003; // 0x0 + silconfig->PcieRpLtrMaxSnoopLatency[2] = 0x1003; // 0x0 - silconfig->PortUsb20PerPortTxPeHalf[3] = 0x0; - silconfig->PortUsb20PerPortPeTxiSet[3] = 0x6; - silconfig->PortUsb20PerPortTxiSet[3] = 0x0; - silconfig->PortUsb20HsSkewSel[3] = 0x0; - silconfig->PortUsb20IUsbTxEmphasisEn[3] = 0x3; - silconfig->PortUsb20PerPortRXISet[3] = 0x0; - silconfig->PortUsb20HsNpreDrvSel[3] = 0x0; + silconfig->PcieRpHotPlug[3] = 0x0; // 0x1 + silconfig->PcieRpPmSci[3] = 0x1; // 0x0 + silconfig->PcieRpTransmitterHalfSwing[3] = 0x0; // 0x1 + silconfig->PcieRpLtrMaxNonSnoopLatency[3] = 0x1003; // 0x0 + silconfig->PcieRpLtrMaxSnoopLatency[3] = 0x1003; // 0x0 - silconfig->PortUsb20PerPortTxPeHalf[4] = 0x0; - silconfig->PortUsb20PerPortPeTxiSet[4] = 0x7; - silconfig->PortUsb20PerPortTxiSet[4] = 0x0; - silconfig->PortUsb20HsSkewSel[4] = 0x0; - silconfig->PortUsb20IUsbTxEmphasisEn[4] = 0x3; - silconfig->PortUsb20PerPortRXISet[4] = 0x0; - silconfig->PortUsb20HsNpreDrvSel[4] = 0x0; + silconfig->PcieRpHotPlug[4] = 0x0; // 0x1 + silconfig->PcieRpPmSci[4] = 0x1; // 0x0 + silconfig->PcieRpTransmitterHalfSwing[4] = 0x0; // 0x1 + silconfig->PcieRpLtrMaxNonSnoopLatency[4] = 0x1003; // 0x0 + silconfig->PcieRpLtrMaxSnoopLatency[4] = 0x1003; // 0x0 - silconfig->PortUsb20PerPortTxPeHalf[5] = 0x0; - silconfig->PortUsb20PerPortPeTxiSet[5] = 0x7; - silconfig->PortUsb20PerPortTxiSet[5] = 0x0; - silconfig->PortUsb20HsSkewSel[5] = 0x0; - silconfig->PortUsb20IUsbTxEmphasisEn[5] = 0x3; - silconfig->PortUsb20PerPortRXISet[5] = 0x0; - silconfig->PortUsb20HsNpreDrvSel[5] = 0x0; + silconfig->PcieRpHotPlug[5] = 0x0; // 0x1 + silconfig->PcieRpPmSci[5] = 0x1; // 0x0 + silconfig->PcieRpTransmitterHalfSwing[5] = 0x0; // 0x1 + silconfig->PcieRpLtrMaxNonSnoopLatency[5] = 0x1003; // 0x0 + silconfig->PcieRpLtrMaxSnoopLatency[5] = 0x1003; // 0x0 - silconfig->PortUsb20PerPortTxPeHalf[6] = 0x0; - silconfig->PortUsb20PerPortPeTxiSet[6] = 0x7; - silconfig->PortUsb20PerPortTxiSet[6] = 0x0; - silconfig->PortUsb20HsSkewSel[6] = 0x0; - silconfig->PortUsb20IUsbTxEmphasisEn[6] = 0x3; - silconfig->PortUsb20PerPortRXISet[6] = 0x0; - silconfig->PortUsb20HsNpreDrvSel[6] = 0x0; + silconfig->PortUs30bOverCurrentPin[0] = 0x0; // 0x1 - silconfig->PortUsb20PerPortTxPeHalf[7] = 0x0; - silconfig->PortUsb20PerPortPeTxiSet[7] = 0x1; - silconfig->PortUsb20PerPortTxiSet[7] = 0x3; - silconfig->PortUsb20HsSkewSel[7] = 0x1; - silconfig->PortUsb20IUsbTxEmphasisEn[7] = 0x1; - silconfig->PortUsb20PerPortRXISet[7] = 0x0; - silconfig->PortUsb20HsNpreDrvSel[7] = 0x3; - - - silconfig->WriteProtectionEnable[0] = 0x1; - silconfig->ReadProtectionEnable[0] = 0x1; - silconfig->ProtectedRangeLimit[0] = 0xFFF; - silconfig->ProtectedRangeBase[0] = 0x0; - - silconfig->IPC[0] = 0xFFFFEEF8; - silconfig->IPC[1] = 0xFFFFFFFF; - silconfig->IPC[2] = 0xFFFFFFFF; - silconfig->IPC[3] = 0xFFFFFFFF; - - silconfig->SataPortsDisableDynamicPg[0] = 0x0; - silconfig->SataPortsEnable[0] = 0x1; - silconfig->SataPortsDevSlp[0] = 0x0; - silconfig->SataPortsHotPlug[0] = 0x0; - silconfig->SataPortsInterlockSw[0] = 0x1; - silconfig->SataPortsExternal[0] = 0x0; - silconfig->SataPortsSpinUp[0] = 0x0; - silconfig->SataPortsSolidStateDrive[0] = 0x0; - silconfig->SataPortsEnableDitoConfig[0] = 0x0; - silconfig->SataPortsDmVal[0] = 0xF; - silconfig->SataPortsDitoVal[0] = 0x271; - - silconfig->SataPortsDisableDynamicPg[1] = 0x0; - silconfig->SataPortsEnable[1] = 0x1; - silconfig->SataPortsDevSlp[1] = 0x0; - silconfig->SataPortsHotPlug[1] = 0x0; - silconfig->SataPortsInterlockSw[1] = 0x1; - silconfig->SataPortsExternal[1] = 0x0; - silconfig->SataPortsSpinUp[1] = 0x0; - silconfig->SataPortsSolidStateDrive[1] = 0x0; - silconfig->SataPortsEnableDitoConfig[1] = 0x0; - silconfig->SataPortsDmVal[1] = 0xF; - silconfig->SataPortsDitoVal[1] = 0x271; - - - silconfig->PcieRootPortEn[0] = 0x1; - silconfig->PcieRpHide[0] = 0x0; - silconfig->PcieRpSlotImplemented[0] = 0x1; - silconfig->PcieRpHotPlug[0] = 0x0; - silconfig->PcieRpPmSci[0] = 0x1; - silconfig->PcieRpExtSync[0] = 0x1; - silconfig->PcieRpTransmitterHalfSwing[0] = 0x0; - silconfig->PcieRpAcsEnabled[0] = 0x1; - silconfig->PcieRpClkReqSupported[0] = 0x1; - silconfig->PcieRpClkReqNumber[0] = 0x2; - silconfig->PcieRpClkReqDetect[0] = 0x0; - silconfig->AdvancedErrorReporting[0] = 0x0; - silconfig->PmeInterrupt[0] = 0x0; - silconfig->UnsupportedRequestReport[0] = 0x0; - silconfig->FatalErrorReport[0] = 0x0; - silconfig->NoFatalErrorReport[0] = 0x0; - silconfig->CorrectableErrorReport[0] = 0x0; - silconfig->SystemErrorOnFatalError[0] = 0x0; - silconfig->SystemErrorOnNonFatalError[0] = 0x0; - silconfig->SystemErrorOnCorrectableError[0] = 0x0; - silconfig->PcieRpSpeed[0] = 0x0; - silconfig->PhysicalSlotNumber[0] = 0x0; - silconfig->PcieRpCompletionTimeout[0] = 0x0; - silconfig->PtmEnable[0] = 0x0; - silconfig->PcieRpAspm[0] = 0x4; - silconfig->PcieRpL1Substates[0] = 0x3; - silconfig->PcieRpLtrEnable[0] = 0x1; - silconfig->PcieRpLtrConfigLock[0] = 0x0; - silconfig->PcieRpSelectableDeemphasis[0] = 0x1; - silconfig->PcieRpNonSnoopLatencyOverrideValue[0] = 0x3C; - silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[0] = 0x2; - silconfig->PcieRpSlotPowerLimitScale[0] = 0x0; - silconfig->PcieRpSlotPowerLimitValue[0] = 0x0; - silconfig->PcieRpLtrMaxNonSnoopLatency[0] = 0x1003; - silconfig->PcieRpNonSnoopLatencyOverrideMode[0] = 0x2; - silconfig->PcieRpLtrMaxSnoopLatency[0] = 0x1003; - silconfig->PcieRpSnoopLatencyOverrideMode[0] = 0x2; - silconfig->PcieRpSnoopLatencyOverrideValue[0] = 0x3C; - silconfig->PcieRpSnoopLatencyOverrideMultiplier[0] = 0x2; - - silconfig->PcieRootPortEn[1] = 0x1; - silconfig->PcieRpHide[1] = 0x0; - silconfig->PcieRpSlotImplemented[1] = 0x1; - silconfig->PcieRpHotPlug[1] = 0x0; - silconfig->PcieRpPmSci[1] = 0x1; - silconfig->PcieRpExtSync[1] = 0x1; - silconfig->PcieRpTransmitterHalfSwing[1] = 0x0; - silconfig->PcieRpAcsEnabled[1] = 0x1; - silconfig->PcieRpClkReqSupported[1] = 0x1; - silconfig->PcieRpClkReqNumber[1] = 0x3; - silconfig->PcieRpClkReqDetect[1] = 0x0; - silconfig->AdvancedErrorReporting[1] = 0x0; - silconfig->PmeInterrupt[1] = 0x0; - silconfig->UnsupportedRequestReport[1] = 0x0; - silconfig->FatalErrorReport[1] = 0x0; - silconfig->NoFatalErrorReport[1] = 0x0; - silconfig->CorrectableErrorReport[1] = 0x0; - silconfig->SystemErrorOnFatalError[1] = 0x0; - silconfig->SystemErrorOnNonFatalError[1] = 0x0; - silconfig->SystemErrorOnCorrectableError[1] = 0x0; - silconfig->PcieRpSpeed[1] = 0x0; - silconfig->PhysicalSlotNumber[1] = 0x1; - silconfig->PcieRpCompletionTimeout[1] = 0x0; - silconfig->PtmEnable[1] = 0x0; - silconfig->PcieRpAspm[1] = 0x4; - silconfig->PcieRpL1Substates[1] = 0x3; - silconfig->PcieRpLtrEnable[1] = 0x1; - silconfig->PcieRpLtrConfigLock[1] = 0x0; - silconfig->PcieRpSelectableDeemphasis[1] = 0x1; - silconfig->PcieRpNonSnoopLatencyOverrideValue[1] = 0x3C; - silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[1] = 0x2; - silconfig->PcieRpSlotPowerLimitScale[1] = 0x0; - silconfig->PcieRpSlotPowerLimitValue[1] = 0x0; - silconfig->PcieRpLtrMaxNonSnoopLatency[1] = 0x1003; - silconfig->PcieRpNonSnoopLatencyOverrideMode[1] = 0x2; - silconfig->PcieRpLtrMaxSnoopLatency[1] = 0x1003; - silconfig->PcieRpSnoopLatencyOverrideMode[1] = 0x2; - silconfig->PcieRpSnoopLatencyOverrideValue[1] = 0x3C; - silconfig->PcieRpSnoopLatencyOverrideMultiplier[1] = 0x2; - - silconfig->PcieRootPortEn[2] = 0x1; - silconfig->PcieRpHide[2] = 0x0; - silconfig->PcieRpSlotImplemented[2] = 0x1; - silconfig->PcieRpHotPlug[2] = 0x0; - silconfig->PcieRpPmSci[2] = 0x1; - silconfig->PcieRpExtSync[2] = 0x1; - silconfig->PcieRpTransmitterHalfSwing[2] = 0x0; - silconfig->PcieRpAcsEnabled[2] = 0x1; - silconfig->PcieRpClkReqSupported[2] = 0x1; - silconfig->PcieRpClkReqNumber[2] = 0x0; - silconfig->PcieRpClkReqDetect[2] = 0x0; - silconfig->AdvancedErrorReporting[2] = 0x0; - silconfig->PmeInterrupt[2] = 0x0; - silconfig->UnsupportedRequestReport[2] = 0x0; - silconfig->FatalErrorReport[2] = 0x0; - silconfig->NoFatalErrorReport[2] = 0x0; - silconfig->CorrectableErrorReport[2] = 0x0; - silconfig->SystemErrorOnFatalError[2] = 0x0; - silconfig->SystemErrorOnNonFatalError[2] = 0x0; - silconfig->SystemErrorOnCorrectableError[2] = 0x0; - silconfig->PcieRpSpeed[2] = 0x0; - silconfig->PhysicalSlotNumber[2] = 0x2; - silconfig->PcieRpCompletionTimeout[2] = 0x0; - silconfig->PtmEnable[2] = 0x0; - silconfig->PcieRpAspm[2] = 0x4; - silconfig->PcieRpL1Substates[2] = 0x3; - silconfig->PcieRpLtrEnable[2] = 0x1; - silconfig->PcieRpLtrConfigLock[2] = 0x0; - silconfig->PcieRpSelectableDeemphasis[2] = 0x1; - silconfig->PcieRpNonSnoopLatencyOverrideValue[2] = 0x3C; - silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[2] = 0x2; - silconfig->PcieRpSlotPowerLimitScale[2] = 0x0; - silconfig->PcieRpSlotPowerLimitValue[2] = 0x0; - silconfig->PcieRpLtrMaxNonSnoopLatency[2] = 0x1003; - silconfig->PcieRpNonSnoopLatencyOverrideMode[2] = 0x2; - silconfig->PcieRpLtrMaxSnoopLatency[2] = 0x1003; - silconfig->PcieRpSnoopLatencyOverrideMode[2] = 0x2; - silconfig->PcieRpSnoopLatencyOverrideValue[2] = 0x0; - silconfig->PcieRpSnoopLatencyOverrideMultiplier[2] = 0x2; - - silconfig->PcieRootPortEn[3] = 0x1; - silconfig->PcieRpHide[3] = 0x0; - silconfig->PcieRpSlotImplemented[3] = 0x1; - silconfig->PcieRpHotPlug[3] = 0x0; - silconfig->PcieRpPmSci[3] = 0x1; - silconfig->PcieRpExtSync[3] = 0x1; - silconfig->PcieRpTransmitterHalfSwing[3] = 0x0; - silconfig->PcieRpAcsEnabled[3] = 0x1; - silconfig->PcieRpClkReqSupported[3] = 0x1; - silconfig->PcieRpClkReqNumber[3] = 0x1; - silconfig->PcieRpClkReqDetect[3] = 0x0; - silconfig->AdvancedErrorReporting[3] = 0x0; - silconfig->PmeInterrupt[3] = 0x0; - silconfig->UnsupportedRequestReport[3] = 0x0; - silconfig->FatalErrorReport[3] = 0x0; - silconfig->NoFatalErrorReport[3] = 0x0; - silconfig->CorrectableErrorReport[3] = 0x0; - silconfig->SystemErrorOnFatalError[3] = 0x0; - silconfig->SystemErrorOnNonFatalError[3] = 0x0; - silconfig->SystemErrorOnCorrectableError[3] = 0x0; - silconfig->PcieRpSpeed[3] = 0x0; - silconfig->PhysicalSlotNumber[3] = 0x3; - silconfig->PcieRpCompletionTimeout[3] = 0x0; - silconfig->PtmEnable[3] = 0x0; - silconfig->PcieRpAspm[3] = 0x4; - silconfig->PcieRpL1Substates[3] = 0x3; - silconfig->PcieRpLtrEnable[3] = 0x1; - silconfig->PcieRpLtrConfigLock[3] = 0x0; - silconfig->PcieRpSelectableDeemphasis[3] = 0x1; - silconfig->PcieRpNonSnoopLatencyOverrideValue[3] = 0x3C; - silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[3] = 0x2; - silconfig->PcieRpSlotPowerLimitScale[3] = 0x0; - silconfig->PcieRpSlotPowerLimitValue[3] = 0x0; - silconfig->PcieRpLtrMaxNonSnoopLatency[3] = 0x1003; - silconfig->PcieRpNonSnoopLatencyOverrideMode[3] = 0x2; - silconfig->PcieRpLtrMaxSnoopLatency[3] = 0x1003; - silconfig->PcieRpSnoopLatencyOverrideMode[3] = 0x2; - silconfig->PcieRpSnoopLatencyOverrideValue[3] = 0x3C; - silconfig->PcieRpSnoopLatencyOverrideMultiplier[3] = 0x2; - - silconfig->PcieRootPortEn[4] = 0x1; - silconfig->PcieRpHide[4] = 0x0; - silconfig->PcieRpSlotImplemented[4] = 0x1; - silconfig->PcieRpHotPlug[4] = 0x0; - silconfig->PcieRpPmSci[4] = 0x1; - silconfig->PcieRpExtSync[4] = 0x1; - silconfig->PcieRpTransmitterHalfSwing[4] = 0x0; - silconfig->PcieRpAcsEnabled[4] = 0x1; - silconfig->PcieRpClkReqSupported[4] = 0x1; - silconfig->PcieRpClkReqNumber[4] = 0x2; - silconfig->PcieRpClkReqDetect[4] = 0x0; - silconfig->AdvancedErrorReporting[4] = 0x0; - silconfig->PmeInterrupt[4] = 0x0; - silconfig->UnsupportedRequestReport[4] = 0x0; - silconfig->FatalErrorReport[4] = 0x0; - silconfig->NoFatalErrorReport[4] = 0x0; - silconfig->CorrectableErrorReport[4] = 0x0; - silconfig->SystemErrorOnFatalError[4] = 0x0; - silconfig->SystemErrorOnNonFatalError[4] = 0x0; - silconfig->SystemErrorOnCorrectableError[4] = 0x0; - silconfig->PcieRpSpeed[4] = 0x0; - silconfig->PhysicalSlotNumber[4] = 0x4; - silconfig->PcieRpCompletionTimeout[4] = 0x0; - silconfig->PtmEnable[4] = 0x0; - silconfig->PcieRpAspm[4] = 0x4; - silconfig->PcieRpL1Substates[4] = 0x3; - silconfig->PcieRpLtrEnable[4] = 0x1; - silconfig->PcieRpLtrConfigLock[4] = 0x0; - silconfig->PcieRpSelectableDeemphasis[4] = 0x1; - silconfig->PcieRpNonSnoopLatencyOverrideValue[4] = 0x3C; - silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[4] = 0x2; - silconfig->PcieRpSlotPowerLimitScale[4] = 0x0; - silconfig->PcieRpSlotPowerLimitValue[4] = 0x0; - silconfig->PcieRpLtrMaxNonSnoopLatency[4] = 0x1003; - silconfig->PcieRpNonSnoopLatencyOverrideMode[4] = 0x2; - silconfig->PcieRpLtrMaxSnoopLatency[4] = 0x1003; - silconfig->PcieRpSnoopLatencyOverrideMode[4] = 0x2; - silconfig->PcieRpSnoopLatencyOverrideValue[4] = 0x3C; - silconfig->PcieRpSnoopLatencyOverrideMultiplier[4] = 0x2; - - silconfig->PcieRootPortEn[5] = 0x1; - silconfig->PcieRpHide[5] = 0x0; - silconfig->PcieRpSlotImplemented[5] = 0x1; - silconfig->PcieRpHotPlug[5] = 0x0; - silconfig->PcieRpPmSci[5] = 0x1; - silconfig->PcieRpExtSync[5] = 0x1; - silconfig->PcieRpTransmitterHalfSwing[5] = 0x0; - silconfig->PcieRpAcsEnabled[5] = 0x1; - silconfig->PcieRpClkReqSupported[5] = 0x1; - silconfig->PcieRpClkReqNumber[5] = 0x3; - silconfig->PcieRpClkReqDetect[5] = 0x0; - silconfig->AdvancedErrorReporting[5] = 0x0; - silconfig->PmeInterrupt[5] = 0x0; - silconfig->UnsupportedRequestReport[5] = 0x0; - silconfig->FatalErrorReport[5] = 0x0; - silconfig->NoFatalErrorReport[5] = 0x0; - silconfig->CorrectableErrorReport[5] = 0x0; - silconfig->SystemErrorOnFatalError[5] = 0x0; - silconfig->SystemErrorOnNonFatalError[5] = 0x0; - silconfig->SystemErrorOnCorrectableError[5] = 0x0; - silconfig->PcieRpSpeed[5] = 0x0; - silconfig->PhysicalSlotNumber[5] = 0x5; - silconfig->PcieRpCompletionTimeout[5] = 0x0; - silconfig->PtmEnable[5] = 0x0; - silconfig->PcieRpAspm[5] = 0x4; - silconfig->PcieRpL1Substates[5] = 0x3; - silconfig->PcieRpLtrEnable[5] = 0x1; - silconfig->PcieRpLtrConfigLock[5] = 0x0; - silconfig->PcieRpSelectableDeemphasis[5] = 0x1; - silconfig->PcieRpNonSnoopLatencyOverrideValue[5] = 0x3C; - silconfig->PcieRpNonSnoopLatencyOverrideMultiplier[5] = 0x2; - silconfig->PcieRpSlotPowerLimitScale[5] = 0x0; - silconfig->PcieRpSlotPowerLimitValue[5] = 0x0; - silconfig->PcieRpLtrMaxNonSnoopLatency[5] = 0x1003; - silconfig->PcieRpNonSnoopLatencyOverrideMode[5] = 0x2; - silconfig->PcieRpLtrMaxSnoopLatency[5] = 0x1003; - silconfig->PcieRpSnoopLatencyOverrideMode[5] = 0x2; - silconfig->PcieRpSnoopLatencyOverrideValue[5] = 0x3C; - silconfig->PcieRpSnoopLatencyOverrideMultiplier[5] = 0x2; - - - silconfig->SsicRate[0] = 0x1; - silconfig->SsicPortEnable[0] = 0x0; - silconfig->SsicRate[1] = 0x1; - silconfig->SsicPortEnable[1] = 0x0; - - silconfig->PortUsb30Enable[0] = 0x1; - silconfig->PortUs30bOverCurrentPin[0] = 0x0; - silconfig->PortUsb30Enable[1] = 0x1; - silconfig->PortUs30bOverCurrentPin[1] = 0x1; - silconfig->PortUsb30Enable[2] = 0x1; - silconfig->PortUs30bOverCurrentPin[2] = 0x1; - silconfig->PortUsb30Enable[3] = 0x1; - silconfig->PortUs30bOverCurrentPin[3] = 0x1; - silconfig->PortUsb30Enable[4] = 0x1; - silconfig->PortUs30bOverCurrentPin[4] = 0x1; - silconfig->PortUsb30Enable[5] = 0x1; - silconfig->PortUs30bOverCurrentPin[5] = 0x1; - - silconfig->PortUsb20Enable[0] = 0x1; - silconfig->PortUs20bOverCurrentPin[0] = 0x0; - silconfig->PortUsb20Enable[1] = 0x1; - silconfig->PortUs20bOverCurrentPin[1] = 0x1; - silconfig->PortUsb20Enable[2] = 0x1; - silconfig->PortUs20bOverCurrentPin[2] = 0x1; - silconfig->PortUsb20Enable[3] = 0x1; - silconfig->PortUs20bOverCurrentPin[3] = 0x1; - silconfig->PortUsb20Enable[4] = 0x1; - silconfig->PortUs20bOverCurrentPin[4] = 0x1; - silconfig->PortUsb20Enable[5] = 0x1; - silconfig->PortUs20bOverCurrentPin[5] = 0x1; - silconfig->PortUsb20Enable[6] = 0x1; - silconfig->PortUs20bOverCurrentPin[6] = 0x2; - silconfig->PortUsb20Enable[7] = 0x1; - silconfig->PortUs20bOverCurrentPin[7] = 0x2; + silconfig->PortUs20bOverCurrentPin[1] = 0x1; // 0x0 + silconfig->PortUs20bOverCurrentPin[2] = 0x1; // 0x0 + silconfig->PortUs20bOverCurrentPin[3] = 0x1; // 0x0 + silconfig->PortUs20bOverCurrentPin[4] = 0x1; // 0x0 + silconfig->PortUs20bOverCurrentPin[5] = 0x1; // 0x0 + silconfig->PortUs20bOverCurrentPin[6] = 0x2; // 0x0 + silconfig->PortUs20bOverCurrentPin[7] = 0x2; // 0x0 } -- To view, visit https://review.coreboot.org/c/coreboot/+/33136 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7dae4f24a9fcb01d2d47063dd3a0f4ce6c120d2 Gerrit-Change-Number: 33136 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/upsquared: Align partitions to 4KiB
by Philipp Deppenwiese (Code Review) 26 Jun '19

26 Jun '19

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33784 ) Change subject: mb/upsquared: Align partitions to 4KiB ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/33784 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1e99b74ded5f743a3ad4fc829ae9747276c483a Gerrit-Change-Number: 33784 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 26 Jun 2019 09:17:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: qclib: Add qclib support with interface tables
by Nitheesh Sekar (Code Review) 26 Jun '19

26 Jun '19

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29967 to look at the new patch set (#32). Change subject: qclib: Add qclib support with interface tables ...................................................................... qclib: Add qclib support with interface tables Add to load and execute qclib blob to configure pmic, clocks and ddr.This also loads the qcsdi, cdt blob. Added support for interface tables to read ddr info from qclib and do ddr one time training based on it. Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Raji Srinivasa Raghavan <c_rajira(a)quicinc.com> --- M src/mainboard/google/mistral/romstage.c M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/qcs405/mmu.c A src/soc/qualcomm/qcs405/soc_blob_load.c 7 files changed, 119 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29967/32 -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 32 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: qcs405: Add bl31 stage and elf
by Nitheesh Sekar (Code Review) 26 Jun '19

26 Jun '19

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29981 to look at the new patch set (#30). Change subject: qcs405: Add bl31 stage and elf ...................................................................... qcs405: Add bl31 stage and elf Change-Id: I967c0b78a3561574609bf8332a22838c85e43429 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Kconfig M src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/bl31_plat_params.c A src/soc/qualcomm/qcs405/include/soc/bl31_plat_params.h M src/soc/qualcomm/qcs405/soc.c 5 files changed, 87 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29981/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/29981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I967c0b78a3561574609bf8332a22838c85e43429 Gerrit-Change-Number: 29981 Gerrit-PatchSet: 30 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: qcs405: Combine BB with QC-Sec for ROM boot
by Nitheesh Sekar (Code Review) 26 Jun '19

26 Jun '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29958 to look at the new patch set (#30). Change subject: qcs405: Combine BB with QC-Sec for ROM boot ...................................................................... qcs405: Combine BB with QC-Sec for ROM boot TEST=build & run Change-Id: I2428fd067c0216d9cf6a63e218d1792788317db0 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/29958/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/29958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2428fd067c0216d9cf6a63e218d1792788317db0 Gerrit-Change-Number: 29958 Gerrit-PatchSet: 30 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: qcs405: Add RPM support
by Nitheesh Sekar (Code Review) 26 Jun '19

26 Jun '19

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29970 to look at the new patch set (#31). Change subject: qcs405: Add RPM support ...................................................................... qcs405: Add RPM support This patch adds support to read RPM image from 3rdparty/blobs and load it. It takes RPM out of reset. Note that, clock_reset_rpm function to touch the GCC registers actually should reside in clock.c, but for now keeping it here till clock patches are posted. Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/include/soc/memlayout.ld A src/soc/qualcomm/qcs405/include/soc/rpm.h M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/qcs405/mmu.c A src/soc/qualcomm/qcs405/rpm_load_reset.c M src/soc/qualcomm/qcs405/soc.c 7 files changed, 101 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29970/31 -- To view, visit https://review.coreboot.org/c/coreboot/+/29970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945 Gerrit-Change-Number: 29970 Gerrit-PatchSet: 31 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit June 2019