Patrick Havelange has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33573
Change subject: soc/intel/denverton_ns/include/soc/gpio_defs: Fix value of B_PCH_GPIO_RX_SCI_ROUTE
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soc/intel/denverton_ns/include/soc/gpio_defs: Fix value of B_PCH_GPIO_RX_SCI_ROUTE
The value for that macro should be 1<<19. This is confirmed by the intel doc
and also by N_PCH_GPIO_RX_SCI_ROUTE.
Signed-off-by: Patrick Havelange <patrick.havelange(a)essensium.com>
Change-Id: I808d9131032a9796d837e00ad6fb3369b792e597
---
M src/soc/intel/denverton_ns/include/soc/gpio_defs.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/33573/1
diff --git a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h
index 43e0647..ae61e6d 100644
--- a/src/soc/intel/denverton_ns/include/soc/gpio_defs.h
+++ b/src/soc/intel/denverton_ns/include/soc/gpio_defs.h
@@ -182,7 +182,7 @@
#define V_PCH_GPIO_RX_APIC_ROUTE_EN 0x01
// GPIO Input Route SCI
-#define B_PCH_GPIO_RX_SCI_ROUTE (1 << 10)
+#define B_PCH_GPIO_RX_SCI_ROUTE (1 << 19)
#define N_PCH_GPIO_RX_SCI_ROUTE 19
#define V_PCH_GPIO_RX_SCI_ROUTE_DIS 0x00
#define V_PCH_GPIO_RX_SCI_ROUTE_EN 0x01
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Karthik Ramasubramanian has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/33376 )
Change subject: device: Move pci_irq_info out of early devicetree
......................................................................
Abandoned
CB:31936 does more than this CL and does it better.
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Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33376 )
Change subject: device: Move pci_irq_info out of early devicetree
......................................................................
Patch Set 1:
> Patch Set 1:
>
> It's more effective to remove the node links from early tree; see CB:31936 (needs rebase).
>
> This does require that we resolve any nodes at compile-time already. Doing that would help us remove __SIMPLE_DEVICE__ too.
CB:31936 looks good to me and is much better than this one. I will abandon this CL and use the one you uploaded.
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Akash Asthana has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25372 )
Change subject: sdm845: Add QUPv3 FW load & config
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Patch Set 75:
(8 comments)
Thanks for reviewing.
https://review.coreboot.org/#/c/25372/75/src/mainboard/google/cheza/mainboa…
File src/mainboard/google/cheza/mainboard.c:
https://review.coreboot.org/#/c/25372/75/src/mainboard/google/cheza/mainboa…
PS75, Line 52: write32((void *)0x11874c, 0x21);
> Note that this can't stay here like this. […]
These are clock control registers(not QUP registers), we are writing them to enable DFS(dynamic frequency selection) mode for QUPs which is PORed with SPI & I2C use case(in kernel/HLOS). We are discussing this change internally, for the time being, we are moving it out into separate HACK patch to unblock this Gerrit.
https://review.coreboot.org/#/c/25372/6/src/mainboard/google/cheza/qupv3_co…
File src/mainboard/google/cheza/qupv3_config.c:
https://review.coreboot.org/#/c/25372/6/src/mainboard/google/cheza/qupv3_co…
PS6, Line 18: struct se_cfg se_mappings[QUPV3_SE_MAX] =
> Whoops, sorry for missing this. […]
This will violate HPG sequence requirement provided to us by the HW team which says that we have to do those common QUPV3 wrapper initialization every time before load firmware.
Suppose we moved common initialization to bootblock.c and loaded FW on demand for SPI use case and it started SPI transactions, now if we want to load FW for I2C usecase on same QUPV3 wrapper's QUP instance, we still need to do common QUPV3 wrapper initialization before loading FW to QUP. This can trouble running SPI.
https://review.coreboot.org/#/c/25372/75/src/soc/qualcomm/sdm845/include/so…
File src/soc/qualcomm/sdm845/include/soc/qupv3_config.h:
https://review.coreboot.org/#/c/25372/75/src/soc/qualcomm/sdm845/include/so…
PS75, Line 23: #endif // _SDM845_QUPV3_CONFIG_H_
> Please use /* C89 */ instead of // C99 comments (please fix globally).
Done
https://review.coreboot.org/#/c/25372/75/src/soc/qualcomm/sdm845/qupv3_fw_c…
File src/soc/qualcomm/sdm845/qupv3_fw_config.c:
https://review.coreboot.org/#/c/25372/75/src/soc/qualcomm/sdm845/qupv3_fw_c…
PS75, Line 166: static uintptr_t qupv3_se_base_addr[QUPV3_SE_MAX] = {
> You should be using the global 'qup' array we introduced for the SPI and I2C drivers instead of this […]
Done
https://review.coreboot.org/#/c/25372/75/src/soc/qualcomm/sdm845/qupv3_fw_c…
PS75, Line 200: reg_value = read32(se_base + GENI_OUTPUT_CTRL_REG) &
> All these register accesses should be using the struct qup_regs that we introduced for the SPI/I2C d […]
Done
https://review.coreboot.org/#/c/25372/75/src/soc/qualcomm/sdm845/qupv3_fw_c…
PS75, Line 396: reg_value = read32((void *)qupv3_common_base_list[i] +
> For all these register accesses you should make a new struct overlay for the common part of the QUPV […]
Done
https://review.coreboot.org/#/c/25372/75/src/soc/qualcomm/sdm845/qupv3_fw_c…
PS75, Line 425: write32((void *)0x0015200C + 0, 0x3FFFFFC0);
> All accesses to GCC registers should be made from clock.c.
Done
https://review.coreboot.org/#/c/25372/75/src/soc/qualcomm/sdm845/qupv3_fw_c…
PS75, Line 427: fw_init_qup_common();
> Can we change this to something like […]
Done
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33785 )
Change subject: mb/up/squared: Add kernel cmdline parameters
......................................................................
Patch Set 1:
This change is ready for review.
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33784 )
Change subject: mb/upsquared: Align partitions to 4KiB
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Patch Set 4:
(2 comments)
This change is ready for review.
https://review.coreboot.org/#/c/33784/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/33784/2//COMMIT_MSG@7
PS2, Line 7: with
> to
Done
https://review.coreboot.org/#/c/33784/2//COMMIT_MSG@7
PS2, Line 7: 4K
> 4K as display resolution? Or is it 4KiB?
Done
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33784 )
Change subject: mb/upsquared: Align partitions with 4K
......................................................................
Patch Set 3:
This change is ready for review.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33784 )
Change subject: mb/upsquared: Align partitions with 4K
......................................................................
Patch Set 2: Code-Review+1
(2 comments)
https://review.coreboot.org/#/c/33784/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/33784/2//COMMIT_MSG@7
PS2, Line 7: with
to
https://review.coreboot.org/#/c/33784/2//COMMIT_MSG@7
PS2, Line 7: 4K
4K as display resolution? Or is it 4KiB?
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