coreboot-gerrit June 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: sdm845: Add SPI QUP driver
by Julius Werner (Code Review) 25 Jun '19

25 Jun '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27483 ) Change subject: sdm845: Add SPI QUP driver ...................................................................... Patch Set 55: (1 comment) LGTM except for the thing that was added with the UART patch. Rebase to front? https://review.coreboot.org/#/c/27483/55/src/soc/qualcomm/sdm845/include/so… File src/soc/qualcomm/sdm845/include/soc/qcom_qup_se.h: https://review.coreboot.org/#/c/27483/55/src/soc/qualcomm/sdm845/include/so… PS55, Line 462: uintptr_t base_addr; Like mentioned in the UART patch, this shouldn't be here. -- To view, visit https://review.coreboot.org/c/coreboot/+/27483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35061727d5ccc550eaeb06caef4524bc4cf25b54 Gerrit-Change-Number: 27483 Gerrit-PatchSet: 55 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vin Kamath <vink(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 25 Jun 2019 00:37:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch: Add missing #include <commonlib/helpers.h>
by HAOUAS Elyes (Code Review) 25 Jun '19

25 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33657 Change subject: arch: Add missing #include <commonlib/helpers.h> ...................................................................... arch: Add missing #include <commonlib/helpers.h> ALIGN((a), b) and ALIGN_UP(a, b) needs 'helpers.h' Change-Id: I029c7c5cbb19c7e69997b3d84f929cb61e8e2b23 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/armv7/mmu.c M src/arch/arm/cpu.c M src/arch/arm64/fit_payload.c M src/arch/x86/acpi.c M src/arch/x86/acpi_s3.c M src/arch/x86/gdt.c M src/arch/x86/include/arch/early_variables.h M src/arch/x86/pirq_routing.c M src/arch/x86/smbios.c M src/arch/x86/tables.c 10 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/33657/1 diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index ce9d3fd..b3133a0 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -29,6 +29,7 @@ */ #include <assert.h> +#include <commonlib/helpers.h> #include <stdlib.h> #include <stdint.h> #include <symbols.h> diff --git a/src/arch/arm/cpu.c b/src/arch/arm/cpu.c index fae1a37..118cae4 100644 --- a/src/arch/arm/cpu.c +++ b/src/arch/arm/cpu.c @@ -29,6 +29,7 @@ */ #include <stdlib.h> #include <arch/cpu.h> +#include <commonlib/helpers.h> /* Return the CPU struct which is at the high memory address of the stack. */ diff --git a/src/arch/arm64/fit_payload.c b/src/arch/arm64/fit_payload.c index c4bbcee..410f7bb 100644 --- a/src/arch/arm64/fit_payload.c +++ b/src/arch/arm64/fit_payload.c @@ -20,6 +20,7 @@ #include <string.h> #include <commonlib/compression.h> #include <commonlib/cbfs_serialized.h> +#include <commonlib/helpers.h> #include <lib.h> #include <fit.h> #include <endian.h> diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 1d645bb..8327e30 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -44,6 +44,7 @@ #include <arch/acpigen.h> #include <device/pci.h> #include <cbmem.h> +#include <commonlib/helpers.h> #include <cpu/x86/lapic_def.h> #include <cpu/cpu.h> #include <cbfs.h> diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 4c57303..049fb12 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -18,6 +18,7 @@ #include <arch/acpi.h> #include <arch/cpu.h> #include <cbmem.h> +#include <commonlib/helpers.h> #include <fallback.h> #include <timestamp.h> #include <program_loading.h> diff --git a/src/arch/x86/gdt.c b/src/arch/x86/gdt.c index c9aec6d..e5444e8 100644 --- a/src/arch/x86/gdt.c +++ b/src/arch/x86/gdt.c @@ -16,6 +16,7 @@ #include <types.h> #include <string.h> #include <cbmem.h> +#include <commonlib/helpers.h> #include <console/console.h> #include <cpu/x86/gdt.h> diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 9ea1537..424b11a 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -17,6 +17,7 @@ #define ARCH_EARLY_VARIABLES_H #include <arch/symbols.h> +#include <commonlib/helpers.h> #include <stdlib.h> #if ENV_CACHE_AS_RAM && !CONFIG(NO_CAR_GLOBAL_MIGRATION) diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index 194efb4..2bed69e 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -16,6 +16,7 @@ */ #include <console/console.h> #include <arch/pirq_routing.h> +#include <commonlib/helpers.h> #include <string.h> #include <device/pci.h> diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 54c2b09..d285d55 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -30,6 +30,7 @@ #include <memory_info.h> #include <spd.h> #include <cbmem.h> +#include <commonlib/helpers.h> #include <device/pci_ids.h> #include <device/pci_def.h> #include <device/pci.h> diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index f17fb85..04da8c4 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -23,6 +23,7 @@ #include <arch/pirq_routing.h> #include <arch/smp/mpspec.h> #include <arch/acpi.h> +#include <commonlib/helpers.h> #include <string.h> #include <cbmem.h> #include <smbios.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I029c7c5cbb19c7e69997b3d84f929cb61e8e2b23 Gerrit-Change-Number: 33657 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/stoneyridge: Generate SPCR table
by Martin Roth (Code Review) 24 Jun '19

24 Jun '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25345 ) Change subject: soc/amd/stoneyridge: Generate SPCR table ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/#/c/25345/6/src/soc/amd/stoneyridge/uart.c File src/soc/amd/stoneyridge/uart.c: https://review.coreboot.org/#/c/25345/6/src/soc/amd/stoneyridge/uart.c@41 PS6, Line 41: AMDCZ > Why do we need to use the special IDs? […] Raul, I'm fine with configuring the baud rate in coreboot and passing a 0 here. Relevant line from the spec: The baud rate the BIOS used for redirection. 0 = as is, operating system relies on the current configuration of serial port until the full featured driver will be initialized. Dan, Does that work for you? -- To view, visit https://review.coreboot.org/c/coreboot/+/25345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc98bcf4f8c070b8002bcc795254b19f928c741b Gerrit-Change-Number: 25345 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Mon, 24 Jun 2019 21:57:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Daniel Kurtz <djkurtz(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/amd/stoneyridge: Generate SPCR table
by Raul Rangel (Code Review) 24 Jun '19

24 Jun '19

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25345 ) Change subject: soc/amd/stoneyridge: Generate SPCR table ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/#/c/25345/6/src/soc/amd/stoneyridge/uart.c File src/soc/amd/stoneyridge/uart.c: https://review.coreboot.org/#/c/25345/6/src/soc/amd/stoneyridge/uart.c@41 PS6, Line 41: AMDCZ > thanks Why do we need to use the special IDs? I was able to use a serial bios with the following command line to get earlycon working: earlycon=uart,mmio32,0xfedc6000 console= By not setting the baudrate in the command line, the kernel driver will assume the correct baud rate has been set. We could also set the Baud Rate to 0 in the SPCR table, and avoid having to use a custom kernel driver to set the uartclk. See https://docs.microsoft.com/en-us/windows-hardware/drivers/serports/serial-p… -- To view, visit https://review.coreboot.org/c/coreboot/+/25345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc98bcf4f8c070b8002bcc795254b19f928c741b Gerrit-Change-Number: 25345 Gerrit-PatchSet: 6 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Mon, 24 Jun 2019 21:38:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Daniel Kurtz <djkurtz(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: add ctype.h header
by Joel Kitching (Code Review) 24 Jun '19

24 Jun '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33525 Change subject: add ctype.h header ...................................................................... add ctype.h header Sometimes coreboot needs to compile external code (e.g. vboot_reference) using its own set of system header files. When these headers don't line up with C Standard Library, it causes problems. Create ctype.h header file. Relocate ctype.h functions from string.h into ctype.h. Update source files which call ctype.h functions accordingly. Note that ctype.h still lacks five functions which are not used in coreboot source: isalnum, isalpha, iscntrl, isgraph, ispunct BUG=b:124141368 TEST=make clean && make test-abuild BRANCH=none Change-Id: I31b5e8af49956ec024a392a73c3c9024b9a9c194 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/console/vtxprintf.c A src/include/ctype.h M src/include/string.h M src/lib/edid.c M src/lib/hexdump.c M src/lib/hexstrtobin.c M src/lib/string.c M src/vendorcode/google/chromeos/vpd_mac.c 8 files changed, 62 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/33525/1 diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index c429ac7..01091c8 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -16,6 +16,7 @@ */ #include <console/vtxprintf.h> +#include <ctype.h> #include <string.h> #define call_tx(x) tx_byte(x, data) diff --git a/src/include/ctype.h b/src/include/ctype.h new file mode 100644 index 0000000..b4684af --- /dev/null +++ b/src/include/ctype.h @@ -0,0 +1,56 @@ +#ifndef CTYPE_H +#define CTYPE_H + +static inline int isspace(int c) +{ + switch (c) { + case ' ': case '\f': case '\n': + case '\r': case '\t': case '\v': + return 1; + default: + return 0; + } +} + +static inline int isprint(int c) +{ + return c >= ' ' && c <= '~'; +} + +static inline int isdigit(int c) +{ + return (c >= '0' && c <= '9'); +} + +static inline int isxdigit(int c) +{ + return ((c >= '0' && c <= '9') || + (c >= 'a' && c <= 'f') || + (c >= 'A' && c <= 'F')); +} + +static inline int isupper(int c) +{ + return (c >= 'A' && c <= 'Z'); +} + +static inline int islower(int c) +{ + return (c >= 'a' && c <= 'z'); +} + +static inline int toupper(int c) +{ + if (islower(c)) + c -= 'a'-'A'; + return c; +} + +static inline int tolower(int c) +{ + if (isupper(c)) + c -= 'A'-'a'; + return c; +} + +#endif /* CTYPE_H */ diff --git a/src/include/string.h b/src/include/string.h index d164f32..3024130 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -50,56 +50,4 @@ */ unsigned int skip_atoi(char **s); -static inline int isspace(int c) -{ - switch (c) { - case ' ': case '\f': case '\n': - case '\r': case '\t': case '\v': - return 1; - default: - return 0; - } -} - -static inline int isprint(int c) -{ - return c >= ' ' && c <= '~'; -} - -static inline int isdigit(int c) -{ - return (c >= '0' && c <= '9'); -} - -static inline int isxdigit(int c) -{ - return ((c >= '0' && c <= '9') || - (c >= 'a' && c <= 'f') || - (c >= 'A' && c <= 'F')); -} - -static inline int isupper(int c) -{ - return (c >= 'A' && c <= 'Z'); -} - -static inline int islower(int c) -{ - return (c >= 'a' && c <= 'z'); -} - -static inline int toupper(int c) -{ - if (islower(c)) - c -= 'a'-'A'; - return c; -} - -static inline int tolower(int c) -{ - if (isupper(c)) - c -= 'A'-'a'; - return c; -} - #endif /* STRING_H */ diff --git a/src/lib/edid.c b/src/lib/edid.c index 3087172..e2f213c 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -31,6 +31,7 @@ #include <assert.h> #include <stddef.h> #include <console/console.h> +#include <ctype.h> #include <stdint.h> #include <string.h> #include <stdlib.h> diff --git a/src/lib/hexdump.c b/src/lib/hexdump.c index ca36dde..1e689e3 100644 --- a/src/lib/hexdump.c +++ b/src/lib/hexdump.c @@ -13,6 +13,7 @@ */ #include <console/console.h> +#include <ctype.h> #include <lib.h> #include <string.h> diff --git a/src/lib/hexstrtobin.c b/src/lib/hexstrtobin.c index ed2abc4..61290b8 100644 --- a/src/lib/hexstrtobin.c +++ b/src/lib/hexstrtobin.c @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include <ctype.h> #include <lib.h> #include <string.h> diff --git a/src/lib/string.c b/src/lib/string.c index a19f017..eb6adb6 100644 --- a/src/lib/string.c +++ b/src/lib/string.c @@ -1,4 +1,5 @@ #include <assert.h> +#include <ctype.h> #include <rules.h> #include <string.h> #include <stddef.h> diff --git a/src/vendorcode/google/chromeos/vpd_mac.c b/src/vendorcode/google/chromeos/vpd_mac.c index e3ef04b..fcd3efe 100644 --- a/src/vendorcode/google/chromeos/vpd_mac.c +++ b/src/vendorcode/google/chromeos/vpd_mac.c @@ -15,6 +15,7 @@ #include <boot/coreboot_tables.h> #include <console/console.h> +#include <ctype.h> #include <string.h> #include <drivers/vpd/vpd.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31b5e8af49956ec024a392a73c3c9024b9a9c194 Gerrit-Change-Number: 33525 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/x86: Support x86_64 exceptions
by build bot (Jenkins) (Code Review) 24 Jun '19

24 Jun '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30117 ) Change subject: arch/x86: Support x86_64 exceptions ...................................................................... Patch Set 16: (2 comments) https://review.coreboot.org/#/c/30117/16/src/arch/x86/include/arch/register… File src/arch/x86/include/arch/registers.h: https://review.coreboot.org/#/c/30117/16/src/arch/x86/include/arch/register… PS16, Line 46: #define QUAD_DOWNTO8(A) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/30117/16/src/arch/x86/include/arch/register… PS16, Line 52: #define QUAD_DOWNTO16(A) \ macros should not use a trailing semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/30117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48 Gerrit-Change-Number: 30117 Gerrit-PatchSet: 16 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 24 Jun 2019 16:48:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support
by Paul Menzel (Code Review) 24 Jun '19

24 Jun '19

Paul Menzel has uploaded a new patch set (#25) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/29667 ) Change subject: mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support ...................................................................... mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support * Enable optional x86_64 romstage, postcar and ramstage * Add Kconfig for x86_64 compilation * Add documentation for x86 qemu mainboards * Increase CAR stack as x86_64 uses more than 0x4000 bytes Working: * Boots to Linux * Boots to SeaBIOS * Drops to protected mode at end of ramstage * Enumerates PCI devices * Relocateable ramstage Broken: * Entering SMM due to missing long mode setup Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/arch/x86/index.md A Documentation/mainboard/emulation/qemu-i440fx.md A Documentation/mainboard/emulation/qemu-q35.md M Documentation/mainboard/index.md M src/arch/x86/Kconfig M src/cpu/qemu-x86/Kconfig M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig 8 files changed, 168 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29667/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/29667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 Gerrit-Change-Number: 29667 Gerrit-PatchSet: 25 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: arch/x86/boot: Call payload in protected mode
by Paul Menzel (Code Review) 24 Jun '19

24 Jun '19

Paul Menzel has uploaded a new patch set (#16) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/30118 ) Change subject: arch/x86/boot: Call payload in protected mode ...................................................................... arch/x86/boot: Call payload in protected mode * On ARCH_RAMSTAGE_X86_64 call the payload in protected mode. * Add a helper function to call arbitraty code in protected mode, similar to the real mode call handler. * Tested on qemu using SeaBios as payload. * Untested for anything else. * Doesn't affect existing x86_32 code. Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/arch/x86/index.md M src/arch/x86/boot.c M src/arch/x86/c_start.S M src/include/program_loading.h 4 files changed, 188 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/30118/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/30118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14 Gerrit-Change-Number: 30118 Gerrit-PatchSet: 16 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: arch/x86/assembly_entry: Enable long mode on x86_64
by Paul Menzel (Code Review) 24 Jun '19

24 Jun '19

Paul Menzel has uploaded a new patch set (#14) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/30114 ) Change subject: arch/x86/assembly_entry: Enable long mode on x86_64 ...................................................................... arch/x86/assembly_entry: Enable long mode on x86_64 * Install simple page tables for long mode * Activate long mode * Add new Kconfig for CPUs that have 1 GiB hugepage support * Use a minimum of two pagetables if possible * Autodetect 1 GiB hugepage support if not known at compile time The same approach was done on AMD based platforms. The main reason to have a 64bit romstage, is to support rmodules. The existing code assumes that both stages (the loader and the one that is being relocated) have the same architecture. Tested on qemu using KVM. Doesn't affect existing x86_32 code. Change-Id: I57974a55f3b778c90b3587f39e86e4eb8692ad48 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/arch/x86/index.md M src/arch/x86/Kconfig M src/arch/x86/Makefile.inc M src/arch/x86/assembly_entry.S M src/arch/x86/c_start.S M src/arch/x86/exit_car_x86_64.S A src/arch/x86/long_mode.S M src/cpu/Kconfig M src/cpu/intel/fsp_model_406dx/Kconfig M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig 21 files changed, 316 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/30114/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/30114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57974a55f3b778c90b3587f39e86e4eb8692ad48 Gerrit-Change-Number: 30114 Gerrit-PatchSet: 14 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: arch/x86: Support x86_64 exceptions
by Paul Menzel (Code Review) 24 Jun '19

24 Jun '19

Paul Menzel has uploaded a new patch set (#16) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/30117 ) Change subject: arch/x86: Support x86_64 exceptions ...................................................................... arch/x86: Support x86_64 exceptions * Tested on qemu using division by zero. • Doesn't affect existing x86_32 code. Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/arch/x86/index.md M src/arch/x86/exception.c M src/arch/x86/idt.S M src/arch/x86/include/arch/registers.h 4 files changed, 141 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/30117/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/30117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48 Gerrit-Change-Number: 30117 Gerrit-PatchSet: 16 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit June 2019