coreboot-gerrit June 2019

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Change in ...coreboot[master]: [WIP]arch/x86/postcar: Add x86_64 support
by Paul Menzel (Code Review) 24 Jun '19

24 Jun '19

Paul Menzel has uploaded a new patch set (#12) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/30500 ) Change subject: [WIP]arch/x86/postcar: Add x86_64 support ...................................................................... [WIP]arch/x86/postcar: Add x86_64 support * Add support for loading GDT on x86_64. * Add x86_64 assembly code to do the same as the x86_32 code. * Separate x86_32 and x86_64 code. Tested on qemu x86_32 and x86_64 using additional MTRRs. Needs test on real hardware. Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/arch/x86/Makefile.inc R src/arch/x86/exit_car_x86_32.S A src/arch/x86/exit_car_x86_64.S M src/arch/x86/gdt_init.S M src/arch/x86/postcar_loader.c 5 files changed, 163 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/30500/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/30500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Gerrit-Change-Number: 30500 Gerrit-PatchSet: 12 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: sdm845: Add UART support
by Akash Asthana (Code Review) 24 Jun '19

24 Jun '19

Akash Asthana has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25373 ) Change subject: sdm845: Add UART support ...................................................................... Patch Set 75: (11 comments) https://review.coreboot.org/#/c/25373/74/src/soc/qualcomm/sdm845/Kconfig File src/soc/qualcomm/sdm845/Kconfig: https://review.coreboot.org/#/c/25373/74/src/soc/qualcomm/sdm845/Kconfig@40 PS74, Line 40: default 9 > Not sure if this should have a default here, it's really completely dependent on each board... […] Selection of QUP instance depends on PORed defined in file@ https://review.coreboot.org/c/coreboot/+/25372/74/src/mainboard/google/chez… Because we load FW to QUPs based on above PORed use cases. Yes, 9 is the fixed QUP instance for console UART on SDM845 products. https://review.coreboot.org/#/c/25373/74/src/soc/qualcomm/sdm845/Kconfig@42 PS74, Line 42: QUP SE instance is 9. > This should explain what the config does, not why you're choosing this default. […] Done https://review.coreboot.org/#/c/25373/74/src/soc/qualcomm/sdm845/include/so… File src/soc/qualcomm/sdm845/include/soc/qcom_qup_se.h: https://review.coreboot.org/#/c/25373/74/src/soc/qualcomm/sdm845/include/so… PS74, Line 462: uintptr_t base_addr; > No, don't store the same thing twice. […] Done https://review.coreboot.org/#/c/25373/74/src/soc/qualcomm/sdm845/uart.c File src/soc/qualcomm/sdm845/uart.c: https://review.coreboot.org/#/c/25373/74/src/soc/qualcomm/sdm845/uart.c@81 PS74, Line 81: div = (unsigned int)(19.2 * MHz) / uart_freq; > This looks like it should use QUP_WRAP_CORE_2X_19_2_MHZ […] Done https://review.coreboot.org/#/c/25373/74/src/soc/qualcomm/sdm845/uart.c@120 PS74, Line 120: 0x8000000 > This should probably be a named constant? Done https://review.coreboot.org/#/c/25373/74/src/soc/qualcomm/sdm845/uart.c@126 PS74, Line 126: unsigned char data = 0x0; > nit: Don't really need this variable. You can just do […] Done https://review.coreboot.org/#/c/25373/74/src/soc/qualcomm/sdm845/uart.c@141 PS74, Line 141: while (read32(&regs->geni_status) & GENI_STATUS_M_GENI_CMD_ACTIVE_MASK) > nit: Just call uart_tx_flush(idx) Done https://review.coreboot.org/#/c/25373/74/src/soc/qualcomm/sdm845/uart.c@146 PS74, Line 146: write32(&regs->geni_m_cmd0, 0x08000000); > Same named constant? In UART protocol, we write 0x8000000 to the main engine to start TX transfers and the same to secondary engine to start RX transfer. I think it will be better to define 2 different constant START_UART_RX, START_UART_TX for better readability. https://review.coreboot.org/#/c/25373/74/src/soc/qualcomm/sdm845/uart.c@161 PS74, Line 161: 0 > This needs to be CONFIG_UART_FOR_CONSOLE Done https://review.coreboot.org/#/c/25373/74/src/soc/qualcomm/sdm845/uart.c@162 PS74, Line 162: 115200 > Shouldn't this be get_uart_baudrate()? Done https://review.coreboot.org/#/c/25373/74/src/soc/qualcomm/sdm845/uart.c@166 PS74, Line 166: lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); > Not sure if you should be setting this tbh. This is not an 8250 console. […] Done, Removed. -- To view, visit https://review.coreboot.org/c/coreboot/+/25373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I827906e820bc15b7f60fdd7876a54c9ed36a48a1 Gerrit-Change-Number: 25373 Gerrit-PatchSet: 75 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Mon, 24 Jun 2019 16:28:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: security/vboot: Add VBNV flags to save the Cr50 recovery switch state
by Keith Short (Code Review) 24 Jun '19

24 Jun '19

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31800 Change subject: security/vboot: Add VBNV flags to save the Cr50 recovery switch state ...................................................................... security/vboot: Add VBNV flags to save the Cr50 recovery switch state Add flags to save the Cr50 recovery switch state. This ensures that the Cr50 recovery switch state is only read during verstage. BUG=b:123360379 BRANCH=none TEST=build coreboot on sarien and arcada. Test normal boot and recovery boot on arcada - confirm that that tpm transaction errors are gone. Change-Id: Id30a7b203e5aac8631971eb102986427b8362a71 Signed-off-by: Keith Short <keithshort(a)chromium.org> --- M src/mainboard/google/sarien/chromeos.c M src/security/vboot/vbnv.c M src/security/vboot/vbnv.h M src/security/vboot/vbnv_layout.h 4 files changed, 71 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/31800/1 diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 1e363fd..308b682 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -20,18 +20,12 @@ #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include <security/tpm/tss.h> +#include <security/vboot/vbnv.h> #include <device/device.h> #include <intelblocks/pmclib.h> #include <soc/pmc.h> #include <soc/pci_devs.h> -enum rec_mode_state { - REC_MODE_UNINITIALIZED, - REC_MODE_NOT_REQUESTED, - REC_MODE_REQUESTED, -}; -static enum rec_mode_state saved_rec_mode; - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -84,30 +78,33 @@ int get_recovery_mode_switch(void) { - enum rec_mode_state state = saved_rec_mode; + int rec_switch; uint8_t recovery_button_state = 0; - /* Check the global variable first. */ - if (state == REC_MODE_NOT_REQUESTED) - return 0; - else if (state == REC_MODE_REQUESTED) - return 1; + /* + * Only verstage performs a real check of the Cr50 recovery switch. + * The recovery switch state is cleared on the first access by the AP + * so there's no point in querying the Cr50 at later stages. All other + * stages use the state saved in VBNV. + */ + if (!ENV_VERSTAGE && + !get_recovery_switch_from_vbnv(&rec_switch)) + return rec_switch; - state = REC_MODE_NOT_REQUESTED; + rec_switch = 0; /* Read state from the GPIO controlled by servo. */ if (cros_get_gpio_value(CROS_GPIO_REC)) - state = REC_MODE_REQUESTED; + rec_switch = 1; /* Read one-time recovery request from cr50. */ else if (tlcl_cr50_get_recovery_button(&recovery_button_state) == TPM_SUCCESS) - state = recovery_button_state ? - REC_MODE_REQUESTED : REC_MODE_NOT_REQUESTED; + rec_switch = !!recovery_button_state; /* Store the state in case this is called again in verstage. */ - saved_rec_mode = state; + set_recovery_switch_into_vbnv(rec_switch); - return state == REC_MODE_REQUESTED; + return rec_switch; } int get_lid_switch(void) diff --git a/src/security/vboot/vbnv.c b/src/security/vboot/vbnv.c index 636e5e3..8156fc5 100644 --- a/src/security/vboot/vbnv.c +++ b/src/security/vboot/vbnv.c @@ -140,6 +140,42 @@ return vbnv_data(RECOVERY_OFFSET); } +/* Save the recovery switch state into VBNV. */ +void set_recovery_switch_into_vbnv(int recovery_switch) +{ + uint8_t vbnv_copy[VBOOT_VBNV_BLOCK_SIZE]; + + read_vbnv(vbnv_copy); + + vbnv_copy[MISC_FLAGS_OFFSET] |= MISC_FLAGS_RECOVERY_SWITCH_VALID_MASK; + if (recovery_switch) + vbnv_copy[MISC_FLAGS_OFFSET] |= + MISC_FLAGS_RECOVERY_SWITCH_STATE_MASK; + else + vbnv_copy[MISC_FLAGS_OFFSET] &= + ~MISC_FLAGS_RECOVERY_SWITCH_STATE_MASK; + + vbnv_copy[CRC_OFFSET] = crc8_vbnv(vbnv_copy, CRC_OFFSET); + + save_vbnv(vbnv_copy); +} + +/* Read the recovery switch state from VBNV. */ +int get_recovery_switch_from_vbnv(int *recovery_switch) +{ + uint8_t misc_flags; + vbnv_setup(); + misc_flags = vbnv_data(MISC_FLAGS_OFFSET); + + if (!(misc_flags & MISC_FLAGS_RECOVERY_SWITCH_VALID_MASK)) + return -1; + + *recovery_switch = + !!(misc_flags & MISC_FLAGS_RECOVERY_SWITCH_STATE_MASK); + + return 0; +} + /* Read the BOOT_OPROM_NEEDED flag from VBNV. */ int vboot_wants_oprom(void) { diff --git a/src/security/vboot/vbnv.h b/src/security/vboot/vbnv.h index c8e689f..367a376 100644 --- a/src/security/vboot/vbnv.h +++ b/src/security/vboot/vbnv.h @@ -25,6 +25,22 @@ void regen_vbnv_crc(uint8_t *vbnv_copy); int get_recovery_mode_from_vbnv(void); void set_recovery_mode_into_vbnv(int recovery_reason); + +/** + * Save the recovery switch state into VBNV + * + * @param recovery_switch Current state of the recovery switch. + */ +void set_recovery_switch_into_vbnv(int recovery_switch); +/** + * Get the recovery switch date from VBNV + * + * @param recovery_switch On success, set to the saved recovery switch state. + * + * @return 0 on success, !=0 if recovery switch state not saved. + */ +int get_recovery_switch_from_vbnv(int *recovery_switch); + int vboot_wants_oprom(void); /* Read the USB Device Controller(UDC) enable flag from VBNV. */ diff --git a/src/security/vboot/vbnv_layout.h b/src/security/vboot/vbnv_layout.h index a9326e4..322fcf7 100644 --- a/src/security/vboot/vbnv_layout.h +++ b/src/security/vboot/vbnv_layout.h @@ -43,7 +43,9 @@ #define DEV_ENABLE_UDC 0x40 #define MISC_FLAGS_OFFSET 8 -#define MISC_FLAGS_BATTERY_CUTOFF_MASK 0x08 +#define MISC_FLAGS_BATTERY_CUTOFF_MASK 0x08 +#define MISC_FLAGS_RECOVERY_SWITCH_VALID_MASK 0x10 +#define MISC_FLAGS_RECOVERY_SWITCH_STATE_MASK 0x20 #define KERNEL_FIELD_OFFSET 11 #define CRC_OFFSET 15 -- To view, visit https://review.coreboot.org/c/coreboot/+/31800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id30a7b203e5aac8631971eb102986427b8362a71 Gerrit-Change-Number: 31800 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/sarien: Save the Cr50 recovery switch state in VBNV
by Keith Short (Code Review) 24 Jun '19

24 Jun '19

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31801 Change subject: mainboard/sarien: Save the Cr50 recovery switch state in VBNV ...................................................................... mainboard/sarien: Save the Cr50 recovery switch state in VBNV Update sarien so the Cr50 recovery switch is only read during verstage and save the recovery switch state to VBNV. BUG=b:123360379 BRANCH=none TEST=build coreboot on sarien and arcada. Test normal boot and recovery boot on arcada - confirm that that tpm transaction errors are gone. Change-Id: Iadf0cec651b3a26ceebadfeb637e189805c328bf Signed-off-by: Keith Short <keithshort(a)chromium.org> --- M src/mainboard/google/sarien/chromeos.c 1 file changed, 16 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/31801/1 diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 1e363fd..308b682 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -20,18 +20,12 @@ #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include <security/tpm/tss.h> +#include <security/vboot/vbnv.h> #include <device/device.h> #include <intelblocks/pmclib.h> #include <soc/pmc.h> #include <soc/pci_devs.h> -enum rec_mode_state { - REC_MODE_UNINITIALIZED, - REC_MODE_NOT_REQUESTED, - REC_MODE_REQUESTED, -}; -static enum rec_mode_state saved_rec_mode; - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -84,30 +78,33 @@ int get_recovery_mode_switch(void) { - enum rec_mode_state state = saved_rec_mode; + int rec_switch; uint8_t recovery_button_state = 0; - /* Check the global variable first. */ - if (state == REC_MODE_NOT_REQUESTED) - return 0; - else if (state == REC_MODE_REQUESTED) - return 1; + /* + * Only verstage performs a real check of the Cr50 recovery switch. + * The recovery switch state is cleared on the first access by the AP + * so there's no point in querying the Cr50 at later stages. All other + * stages use the state saved in VBNV. + */ + if (!ENV_VERSTAGE && + !get_recovery_switch_from_vbnv(&rec_switch)) + return rec_switch; - state = REC_MODE_NOT_REQUESTED; + rec_switch = 0; /* Read state from the GPIO controlled by servo. */ if (cros_get_gpio_value(CROS_GPIO_REC)) - state = REC_MODE_REQUESTED; + rec_switch = 1; /* Read one-time recovery request from cr50. */ else if (tlcl_cr50_get_recovery_button(&recovery_button_state) == TPM_SUCCESS) - state = recovery_button_state ? - REC_MODE_REQUESTED : REC_MODE_NOT_REQUESTED; + rec_switch = !!recovery_button_state; /* Store the state in case this is called again in verstage. */ - saved_rec_mode = state; + set_recovery_switch_into_vbnv(rec_switch); - return state == REC_MODE_REQUESTED; + return rec_switch; } int get_lid_switch(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/31801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadf0cec651b3a26ceebadfeb637e189805c328bf Gerrit-Change-Number: 31801 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Documentation: How to run coreboot on PC Engines APU2
by Piotr Kleinschmidt (Code Review) 24 Jun '19

24 Jun '19

Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33146 Change subject: Documentation: How to run coreboot on PC Engines APU2 ...................................................................... Documentation: How to run coreboot on PC Engines APU2 There is no documentation about running coreboot on apu2 platform, so now it describes how to do this. Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581 Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> --- A Documentation/mainboard/pcengines/apu2.jpg A Documentation/mainboard/pcengines/apu2.md A Documentation/mainboard/pcengines/apu2_spi.jpg 3 files changed, 110 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/33146/1 diff --git a/Documentation/mainboard/pcengines/apu2.jpg b/Documentation/mainboard/pcengines/apu2.jpg new file mode 100644 index 0000000..d221857 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu2.jpg Binary files differ diff --git a/Documentation/mainboard/pcengines/apu2.md b/Documentation/mainboard/pcengines/apu2.md new file mode 100644 index 0000000..a8aa3d2 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu2.md @@ -0,0 +1,110 @@ +# PC Engines APU2 + +This page describes how to run coreboot on PC Engines APU2 platform. + +## Technology + +```eval_rst ++------------+---------------------------------------------------------------+ +| CPU | AMD G series GX-412TC | ++------------+---------------------------------------------------------------+ +| CPU core | 1 GHz quad Jaguar core with 64 bit support | +| | 32K data + 32K instruction cache per core, shared 2MB L2 cache| ++------------+---------------------------------------------------------------+ +| DRAM | 2 or 4 GB DDR3-1333 DRAM | ++------------+---------------------------------------------------------------+ +| Boot | From SD card, USB, mSATA SSD, SATA | ++------------+---------------------------------------------------------------+ +| Power | 6 to 12W of 12V power | ++------------+---------------------------------------------------------------+ +| Firmware | coreboot with support for iPXE and USB boot | ++------------+---------------------------------------------------------------+ +``` + +## Required proprietary blobs + +To build working coreboot image some blobs are needed. + +```eval_rst ++-----------------+---------------------------------+---------------------+ +| Binary file | Apply | Required / Optional | ++=====================+=============================+=====================+ +| AmdPubKey.bin | AMD Platform Security Processor | Required | ++-----------------+---------------------------------+---------------------+ +| AGESA.bin | AGESA Platform Initialization | Required | ++-----------------+---------------------------------+---------------------+ +| xhci.bin | AMD XHCI controller | Optional | ++-----------------+---------------------------------+---------------------+ +``` + +## Flashing coreboot + +```eval_rst ++---------------------+--------------------------+ +| Type | Value | ++=====================+==========================+ +| Socketed flash | no | ++---------------------+--------------------------+ +| Model | MX25L1606E | ++---------------------+--------------------------+ +| Size | 2 MiB | ++---------------------+--------------------------+ +| Package | SOP-8 | ++---------------------+--------------------------+ +| Write protection | jumper on WP# pin | ++---------------------+--------------------------+ +| Dual BIOS feature | no | ++---------------------+--------------------------+ +| Internal flashing | Super IO Nuvoton NCT5104D| ++---------------------+--------------------------+ +``` + +### Internal programming + +The SPI flash can be accessed using [flashrom]. It is important to execute +command with a `-c <chipname>` argument: + + flashrom -p internal -c "MX25L1606E" -w coreboot.rom + +### External programming + +**IMPORTANT**: When programming SPI flash, first you need to enter apu2 in S5 +(Soft-off) power state. S5 state can be forced by shorting power button pin on +J2 header. + +The external access to flash chip is available through standard SOP-8 clip or +SOP-8 header next to the flash chip on the board. Notice that not all boards +have a header soldered down originally. Hence, there could be an empty slot with +8 eyelets, so you can solder down a header on your own. The SPI flash chip and +SPI header are marked in the picture below. Also there is SPI header and SPI +flash pin layout included. + +There is no restrictions as to the programmer device. It is only recommended to +flash firmware without supplying power. External programming can be performed, +for example using OrangePi and Armbian. You can exploit linux_spi driver which +provide communication with SPI devices. Example command to program SPI flash +with OrangePi using linux_spi: + + flashrom -f -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 + + +**apu2 platform with marked in SPI header and SPI flash chip** + +![][apu2_flash] + +**SPI header pin layout** + +![][spi_header] + + +## Schematics + +PC Engines APU2 platform schematics are available for free on PC Engines +official site. Depending on the configuration: +- [apu2b](https://www.pcengines.ch/schema/apu2b.pdf) +- [apu2c](https://www.pcengines.ch/schema/apu2c.pdf) +- [apu2d](https://www.pcengines.ch/schema/apu2d.pdf) + +[apu2_flash]: apu2.jpg +[spi_header]: apu2_spi.jpg +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/pcengines/apu2_spi.jpg b/Documentation/mainboard/pcengines/apu2_spi.jpg new file mode 100644 index 0000000..f8a5b58 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu2_spi.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/33146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581 Gerrit-Change-Number: 33146 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] Documentation: How to run coreboot on PC Engines apu1
by Piotr Kleinschmidt (Code Review) 24 Jun '19

24 Jun '19

Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32907 Change subject: [WIP] Documentation: How to run coreboot on PC Engines apu1 ...................................................................... [WIP] Documentation: How to run coreboot on PC Engines apu1 There were no documentation about running coreboot on apu1 platform, so now it describes how to do this. Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Change-Id: If79693e893c4afe52bf1c9aa8017ac6f650a96e4 --- A Documentation/mainboard/pcengines/apu1.md A Documentation/mainboard/pcengines/apu1c1_flash.jpg 2 files changed, 63 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32907/1 diff --git a/Documentation/mainboard/pcengines/apu1.md b/Documentation/mainboard/pcengines/apu1.md new file mode 100644 index 0000000..20259a6 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu1.md @@ -0,0 +1,63 @@ +# PC Engines apu1 + +This page describes how to run coreboot on PC Engines apu1 platform. + +## Technology + +| | | +| -----------|:-------------------------------------------------------| +| CPU | AMD G series T40E APU | +| CPU core | 1 GHz dual core (Bobcat core) with 64 bit support | +| | 32K data + 32K instruction + 512KB L2 cache per core | +| DRAM | 2 or 4 GB DDR3-1066 DRAM | +| Boot | From SD card, USB, m-SATA | +| Power | 6 to 12W of 12V power | +| Firmware | coreboot with support for iPXE and USB boot | + +## Flashing coreboot + +| Type | Value | +|---------------------|:-----------| +| Socketed flash | no | +| Model | MX25L1606E | +| Size | 2 MiB | +| Package | SOP-8 | +| Write protection | no | +| Dual BIOS feature | no | +| Internal flashing | yes | + +### Internal programming + +The SPI flash can be accessed using [flashrom]. It is important to execute +command with a `-c <chipname>` argument: + +`flashrom -p internal -c MX25L1606E -w coreboot.rom ` + +### External programming + +**IMPORTANT**: When programming SPI flash, first you need to enter apu1 in S5 +(Soft-off) power state. More details about that state is available in ACPI +Specification documentation. + +The external access to flash chip is available through standard SOP-8 clip or +SOP-8 header which is next to the flash chip on the board. Notice that not all +boards have a header soldered down originally. Hence, there could be an empty +slot with 8 eyelets, so you can solder down a header on your own. The SPI flash +chip and SPI header are marked in the picture below. + +There is no restrictions as to programmer device. However, [flashrom] is +strongly recommended. The example command to program SPI flash with a linux_spi +is: + +`flashrom -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 -c +"MX25L1606E"` + + +**apu1 platform with marked in SPI header and SPI flash chip** +![][apu1c1_flash] + +[apu1c1_flash]: apu1c1_flash.jpg + + +[flashrom]: https://flashrom.org/Flashrom +[here]: https://www.coreboot.org/Binary_situation diff --git a/Documentation/mainboard/pcengines/apu1c1_flash.jpg b/Documentation/mainboard/pcengines/apu1c1_flash.jpg new file mode 100644 index 0000000..069e976 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu1c1_flash.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/32907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If79693e893c4afe52bf1c9aa8017ac6f650a96e4 Gerrit-Change-Number: 32907 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant
by Kyösti Mälkki (Code Review) 24 Jun '19

24 Jun '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31832 ) Change subject: mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant ...................................................................... Patch Set 9: Code-Review+2 (2 comments) https://review.coreboot.org/#/c/31832/9/src/mainboard/gigabyte/ga-h61m-s2pv… File src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c: https://review.coreboot.org/#/c/31832/9/src/mainboard/gigabyte/ga-h61m-s2pv… PS9, Line 31: pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); I guess routing CNF2 (for 0x4e) is not really needed here. And without COMB_LPC_EN set programming LPC_IO_DEC is not really needed either. https://review.coreboot.org/#/c/31832/9/src/mainboard/gigabyte/ga-h61m-s2pv… File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb: https://review.coreboot.org/#/c/31832/9/src/mainboard/gigabyte/ga-h61m-s2pv… PS9, Line 85: io 0x64 = 0x0000 I am not sure how resource allocator treats these IO base 0x0 entries. From what I remember, we generally don't have a range/size associated for these anyways, so probably they just get ignored. -- To view, visit https://review.coreboot.org/c/coreboot/+/31832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26 Gerrit-Change-Number: 31832 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 24 Jun 2019 12:27:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant
by Felix Held (Code Review) 24 Jun '19

24 Jun '19

Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31832 ) Change subject: mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant ...................................................................... mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant Tested with SeaBIOS as a payload, booting Arch Linux with a Linux kernel. The new code is based on autoport and the existing GA-H61M-S2PV code. The GA-H61M-S2PV has been boot-tested too, it still boots. Working: - S3 suspend/resume - USB ports and headers (Intel USB2 and EtronTech USB3) - Gigabit Ethernet - Integrated DVI/VGA graphics (libgfxinit) - PCIe x16 graphics - PCIe x1 ports - PS/2 port with a keyboard - SATA controllers (Intel SATA2 and Marvell SATA3) - User-space fan control (fancontrol on Linux) - Native raminit (4+4GB DDR3-1333) - flashrom, using the internal programmer. Tested with coreboot, as well as with the vendor firmware. Backup chip is untested. Untested: - VGA BIOS for integrated graphics init - Audio: Only front/read outputs has been tested. - Non-Linux OSes - ACPI thermal zone and OS-independent fan control Not working: - Default IFD defines the BIOS region as the entire flash chip. Using 'flashrom --ifd -i bios' is asking for a failed flash! Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31832 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name M src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc M src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c M src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c R src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb R src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c 11 files changed, 425 insertions(+), 80 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig index 5e46365..62d7f40 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -if BOARD_GIGABYTE_GA_H61M_S2PV +if BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61MA_D3V config BOARD_SPECIFIC_OPTIONS def_bool y @@ -31,21 +31,36 @@ select INTEL_GMA_HAVE_VBT select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT + select NO_UART_ON_SUPERIO if BOARD_GIGABYTE_GA_H61MA_D3V config MAINBOARD_DIR string default "gigabyte/ga-h61m-s2pv" +config VARIANT_DIR + string + default "ga-h61m-s2pv" if BOARD_GIGABYTE_GA_H61M_S2PV + default "ga-h61ma-d3v" if BOARD_GIGABYTE_GA_H61MA_D3V + config MAINBOARD_PART_NUMBER string - default "GA-H61M-S2PV" + default "GA-H61M-S2PV" if BOARD_GIGABYTE_GA_H61M_S2PV + default "GA-H61MA-D3V" if BOARD_GIGABYTE_GA_H61MA_D3V + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" config MAX_CPUS int default 8 +# Override the default variant behavior, since the data.vbt is the same +config INTEL_GMA_VBT_FILE + default "src/mainboard/$(MAINBOARDDIR)/data.vbt" + config USBDEBUG_HCD_INDEX # Bottom left port seen from rear int default 2 -endif # BOARD_GIGABYTE_GA_H61M_S2PV +endif # BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61MA_D3V diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name index 04da3f0..83b5803 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_GIGABYTE_GA_H61M_S2PV bool "GA-H61M-S2PV" + +config BOARD_GIGABYTE_GA_H61MA_D3V + bool "GA-H61MA-D3V" diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc b/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc index ea035d3..fe7cc81 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc @@ -1,3 +1,4 @@ -romstage-y += gpio.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c index 15a2b01..e69de29 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ - 0x1458a002, /* Subsystem ID */ - - 0x0000000f, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ - AZALIA_SUBVENDOR(0x2, 0x1458a002), - - /* NID 0x11. */ - AZALIA_PIN_CFG(0x2, 0x11, 0x411111f0), - - /* NID 0x12. */ - AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), - - /* NID 0x14. */ - AZALIA_PIN_CFG(0x2, 0x14, 0x01014410), - - /* NID 0x15. */ - AZALIA_PIN_CFG(0x2, 0x15, 0x411111f0), - - /* NID 0x16. */ - AZALIA_PIN_CFG(0x2, 0x16, 0x411111f0), - - /* NID 0x17. */ - AZALIA_PIN_CFG(0x2, 0x17, 0x411111f0), - - /* NID 0x18. */ - AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50), - - /* NID 0x19. */ - AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60), - - /* NID 0x1a. */ - AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f), - - /* NID 0x1b. */ - AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20), - - /* NID 0x1c. */ - AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0), - - /* NID 0x1d. */ - AZALIA_PIN_CFG(0x2, 0x1d, 0x4004c601), - - /* NID 0x1e. */ - AZALIA_PIN_CFG(0x2, 0x1e, 0x411111f0), - - /* NID 0x1f. */ - AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0), -}; - -const u32 pc_beep_verbs[0] = {}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c index 7154cc9..27fbb2c 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c @@ -25,10 +25,15 @@ void pch_enable_lpc(void) { - pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | - CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); + if (CONFIG(BOARD_GIGABYTE_GA_H61M_S2PV)) { + pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | + CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + } else if (CONFIG(BOARD_GIGABYTE_GA_H61MA_D3V)) { + pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | + CNF1_LPC_EN); + } } void mainboard_rcba_config(void) @@ -58,8 +63,10 @@ void mainboard_config_superio(void) { - /* Enable serial port */ - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + if (!CONFIG(NO_UART_ON_SUPERIO)) { + /* Enable serial port */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + } /* Disable SIO WDT which kicks in DualBIOS */ ite_reg_write(SUPERIO_GPIO, 0xEF, 0x7E); diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb rename to src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/gpio.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c similarity index 100% rename from src/mainboard/gigabyte/ga-h61m-s2pv/gpio.c rename to src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c new file mode 100644 index 0000000..93c7e11 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Realtek ALC887 */ + 0x1458a002, /* Subsystem ID */ + 0x0000000f, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x2, 0x1458a002), + AZALIA_PIN_CFG(0x2, 0x11, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x14, 0x01014410), + AZALIA_PIN_CFG(0x2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0x2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb new file mode 100644 index 0000000..22d483e --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb @@ -0,0 +1,101 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.ndid" = "3" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + register "pci_mmio_size" = "2048" + device domain 0x0 on + subsystemid 0x1458 0x5001 inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x003c0a01" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # COM1 + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + io 0x62 = 0x0a20 + irq 0x70 = 9 + irq 0xf2 = 0x40 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0xf0 = 0x08 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + irq 0x25 = 0x40 + irq 0x26 = 0xf7 + irq 0x27 = 0x10 + irq 0x2c = 0x80 + io 0x60 = 0x0000 + io 0x62 = 0x0a00 + io 0x64 = 0x0000 + irq 0x73 = 0x00 + irq 0xcb = 0x00 + irq 0xf0 = 0x10 + irq 0xf1 = 0x40 + irq 0xf6 = 0x1c + end + device pnp 2e.a off end # CIR + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 on end # Thermal + end + end +end diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c new file mode 100644 index 0000000..b717374 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c @@ -0,0 +1,205 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c new file mode 100644 index 0000000..e160538 --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Realtek ALC887 */ + 0x1458a002, /* Subsystem ID */ + 0x0000000f, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x2, 0x1458a002), + AZALIA_PIN_CFG(0x2, 0x11, 0x411110f0), + AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x14, 0x01014410), + AZALIA_PIN_CFG(0x2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0x2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x1f, 0x41c46060), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; -- To view, visit https://review.coreboot.org/c/coreboot/+/31832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26 Gerrit-Change-Number: 31832 Gerrit-PatchSet: 9 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant
by Felix Held (Code Review) 24 Jun '19

24 Jun '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31832 ) Change subject: mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26 Gerrit-Change-Number: 31832 Gerrit-PatchSet: 8 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 24 Jun 2019 12:13:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: util/cbfstool/flashmap: Correct local includes
by HAOUAS Elyes (Code Review) 24 Jun '19

24 Jun '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33733 Change subject: util/cbfstool/flashmap: Correct local includes ...................................................................... util/cbfstool/flashmap: Correct local includes Change-Id: I78ba7afd2085c7e9c93e892470111bfee154bb04 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/cbfstool/flashmap/fmap.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/33733/1 diff --git a/util/cbfstool/flashmap/fmap.c b/util/cbfstool/flashmap/fmap.c index f1d2fb9..06f179f 100644 --- a/util/cbfstool/flashmap/fmap.c +++ b/util/cbfstool/flashmap/fmap.c @@ -48,10 +48,9 @@ #include <limits.h> #include <assert.h> -#include <fmap.h> -#include <valstr.h> - +#include "fmap.h" #include "kv_pair.h" +#include "valstr.h" #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) -- To view, visit https://review.coreboot.org/c/coreboot/+/33733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78ba7afd2085c7e9c93e892470111bfee154bb04 Gerrit-Change-Number: 33733 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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