Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29970 )
Change subject: qcs405: Add RPM support
......................................................................
Patch Set 32:
(2 comments)
https://review.coreboot.org/#/c/29970/29/src/soc/qualcomm/qcs405/include/so…
File src/soc/qualcomm/qcs405/include/soc/memlayout.ld:
https://review.coreboot.org/#/c/29970/29/src/soc/qualcomm/qcs405/include/so…
PS29, Line 35: 76K
> This considerably reduces the size of the region compared to the previous patch set (from 0x2c000, w […]
Done
https://review.coreboot.org/#/c/29970/29/src/soc/qualcomm/qcs405/rpm_load_r…
File src/soc/qualcomm/qcs405/rpm_load_reset.c:
https://review.coreboot.org/#/c/29970/29/src/soc/qualcomm/qcs405/rpm_load_r…
PS29, Line 42: BIOS_DEBUG
> BIOS_SPEW? (or remove completely)
Done
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Hello Patrick Rudolph, Piotr Król, Huang Jin, Arthur Heymans, York Yang, Lee Leahy, build bot (Jenkins), Michał Żygowski, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29371
to look at the new patch set (#10).
Change subject: drivers/intel/fsp1_1/raminit.c: Always check FSP HOBs
......................................................................
drivers/intel/fsp1_1/raminit.c: Always check FSP HOBs
Check for FSP HOBs is depending on CONFIG_DISPLAY_HOBS.
Use the CONFIG_DISPLAY_HOBS for display HOB info only and always check HOBs.
Use BIOS_ERR of printk() for FSP errors.
BUG=N/A
TEST=Check console output on Facebook FBG1701.
Change-Id: I3776fa37866c7ef3aea090842387660c22bbdd4d
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp1_1/ramstage.c
2 files changed, 24 insertions(+), 60 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/29371/10
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29371 )
Change subject: drivers/intel/fsp1_1/raminit.c: Always check FSP HOBs
......................................................................
Patch Set 9:
(4 comments)
Will update with new patchset
https://review.coreboot.org/#/c/29371/9/src/drivers/intel/fsp1_1/raminit.c
File src/drivers/intel/fsp1_1/raminit.c:
https://review.coreboot.org/#/c/29371/9/src/drivers/intel/fsp1_1/raminit.c@…
PS9, Line 209:
> Done
Done
https://review.coreboot.org/#/c/29371/9/src/drivers/intel/fsp1_1/raminit.c@…
PS9, Line 205: if (hob_ptr.Raw == NULL)
> merge with next if
Will merge the 2 if lines
https://review.coreboot.org/#/c/29371/9/src/drivers/intel/fsp1_1/raminit.c@…
PS9, Line 217: if (hob_list_ptr != NULL) {
> merge with next if
This check is already performed. Will remove it.
https://review.coreboot.org/#/c/29371/9/src/drivers/intel/fsp1_1/raminit.c@…
PS9, Line 220: } else {
> unreachable as you die above
Done
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David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25440 )
Change subject: soc/intel/denverton_ns: Implement AES-NI Lock
......................................................................
Patch Set 13: Code-Review+1
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Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33434
Change subject: soc/intel/skylake/romstage: Increase size of postcar stack
......................................................................
soc/intel/skylake/romstage: Increase size of postcar stack
I increase the size oof the postcar stack to prevent a stack overflow
during the measured boot feature. After common string functions have
been moved from inline into .c file
(https://review.coreboot.org/c/coreboot/+/32901), I experienced a stack
overflow in the postcar stage while verifiying the romstage during
measured boot. To prevent this, the stack size should be increased. To
play it safe, it should be increased to 8 KiB - though this is open for
discussion.
Change-Id: I6f1a4631bcadfb8c7d1de5bf0919e40990a65606
Signed-off-by: Christian Walter <christian.walter(a)9elements.com>
---
M src/soc/intel/skylake/romstage/romstage_fsp20.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/33434/1
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 2819c6f..0eff793 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -156,7 +156,7 @@
pmc_set_disb();
if (!s3wake)
save_dimm_info();
- if (postcar_frame_init(&pcf, 1*KiB))
+ if (postcar_frame_init(&pcf, 8*KiB))
die("Unable to initialize postcar frame.\n");
/*
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29371 )
Change subject: drivers/intel/fsp1_1/raminit.c: Always check FSP HOBs
......................................................................
Patch Set 9: Code-Review+1
(3 comments)
https://review.coreboot.org/#/c/29371/9/src/drivers/intel/fsp1_1/raminit.c
File src/drivers/intel/fsp1_1/raminit.c:
https://review.coreboot.org/#/c/29371/9/src/drivers/intel/fsp1_1/raminit.c@…
PS9, Line 205: if (hob_ptr.Raw == NULL)
merge with next if
https://review.coreboot.org/#/c/29371/9/src/drivers/intel/fsp1_1/raminit.c@…
PS9, Line 217: if (hob_list_ptr != NULL) {
merge with next if
https://review.coreboot.org/#/c/29371/9/src/drivers/intel/fsp1_1/raminit.c@…
PS9, Line 220: } else {
unreachable as you die above
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