coreboot-gerrit May 2019

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Change in ...libgfxinit[master]: gma config: Group mutable state into a record
by Nico Huber (Code Review) 08 May '19

08 May '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/libgfxinit/+/27065 ) Change subject: gma config: Group mutable state into a record ...................................................................... gma config: Group mutable state into a record Put all state into a record, `Config.Variable`, so it can be referenced at once from other packages. This is required to add stateful variables to `Config` without changing the rest of the codebase. Change-Id: Iffc7984b61e57cda7bdaf3b915a4fc51b396423a Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/27065 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-dp_aux_request.adb M common/hw-gfx-gma.adb 3 files changed, 23 insertions(+), 14 deletions(-) Approvals: Nico Huber: Verified Arthur Heymans: Looks good to me, approved diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 6033dc0..ea42443 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -14,7 +14,7 @@ private package HW.GFX.GMA.Config with - Initializes => (Valid_Port, Raw_Clock) + Initializes => Variable is Gen : constant Generation := <<GEN>>; @@ -58,6 +58,23 @@ ---------------------------------------------------------------------------- + type Valid_Port_Array is array (Port_Type) of Boolean; + type Variable_Config is record + Valid_Port : Valid_Port_Array; + Raw_Clock : Frequency_Type; + end record; + + Variable : Variable_Config := + (Valid_Port => (others => False), + Raw_Clock => Frequency_Type'First) + with + Part_Of => GMA.Config_State; + + Valid_Port : Valid_Port_Array renames Variable.Valid_Port; + Raw_Clock : Frequency_Type renames Variable.Raw_Clock; + + ---------------------------------------------------------------------------- + Gen_G45 : constant Boolean := Gen = G45; Gen_Ironlake : constant Boolean := Gen = Ironlake; Gen_Haswell : constant Boolean := Gen = Haswell; @@ -187,10 +204,6 @@ Max_Pipe : constant Pipe_Index := (if Has_Tertiary_Pipe then Tertiary else Secondary); - Valid_Port : array (Port_Type) of Boolean := (others => False) - with - Part_Of => GMA.Config_State; - Last_Digital_Port : constant Digital_Port := (if Has_DDI_E then DIGI_E else DIGI_C); @@ -239,9 +252,6 @@ elsif Gen_Skylake then 24_000_000 else Frequency_Type'First); - Raw_Clock : Frequency_Type := Default_RawClk_Freq - with Part_Of => GMA.Config_State; - ---------------------------------------------------------------------------- -- Maximum source width with enabled scaler. This only accounts diff --git a/common/hw-gfx-gma-dp_aux_request.adb b/common/hw-gfx-gma-dp_aux_request.adb index 75a2cca..c057059 100644 --- a/common/hw-gfx-gma-dp_aux_request.adb +++ b/common/hw-gfx-gma-dp_aux_request.adb @@ -163,7 +163,7 @@ Success : out Boolean) with Global => (In_Out => Registers.Register_State, - Input => (Time.State, Config.Raw_Clock)), + Input => (Time.State, Config.Variable)), Depends => ((Registers.Register_State, Response, @@ -171,7 +171,7 @@ Success) => (Registers.Register_State, - Config.Raw_Clock, + Config.Variable, Time.State, Port, Request, diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index dfe986f..b62ebce 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -44,7 +44,7 @@ HPD_Delay, Wait_For_HPD, Linear_FB_Base), Init_State => Initialized, - Config_State => (Config.Valid_Port, Config.Raw_Clock), + Config_State => (Config.Variable), Device_State => (Dev.PCI_State, Registers.Register_State, Registers.GTT_State)) is @@ -371,9 +371,8 @@ with Refined_Global => (In_Out => - (Config.Valid_Port, Dev.PCI_State, - Registers.Register_State, Port_IO.State, - Config.Raw_Clock), + (Config.Variable, Dev.PCI_State, + Registers.Register_State, Port_IO.State), Input => (Time.State), Output => -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Iffc7984b61e57cda7bdaf3b915a4fc51b396423a Gerrit-Change-Number: 27065 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...libgfxinit[master]: gma pipe setup: Drop explicit Global and Depends contracts
by Nico Huber (Code Review) 08 May '19

08 May '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/libgfxinit/+/27064 ) Change subject: gma pipe setup: Drop explicit Global and Depends contracts ...................................................................... gma pipe setup: Drop explicit Global and Depends contracts These were originally only added to prevent proof inlining and are not needed any more. Change-Id: Ia75c78a7030960a56e9cb469601b24c677732875 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/27064 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/hw-gfx-gma-pipe_setup.adb 1 file changed, 0 insertions(+), 12 deletions(-) Approvals: Nico Huber: Verified Arthur Heymans: Looks good to me, approved diff --git a/common/hw-gfx-gma-pipe_setup.adb b/common/hw-gfx-gma-pipe_setup.adb index a237de7..76051dd 100644 --- a/common/hw-gfx-gma-pipe_setup.adb +++ b/common/hw-gfx-gma-pipe_setup.adb @@ -283,18 +283,6 @@ Dither_BPC : BPC_Type; Dither : Boolean) with - Global => (In_Out => (Registers.Register_State, Port_IO.State)), - Depends => - (Registers.Register_State - =>+ - (Registers.Register_State, - Controller, - Framebuffer, - Dither_BPC, - Dither), - Port_IO.State - =>+ - (Framebuffer)), Pre => Framebuffer.Offset = VGA_PLANE_FRAMEBUFFER_OFFSET or Framebuffer.Height + Framebuffer.Start_Y <= Framebuffer.V_Stride -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ia75c78a7030960a56e9cb469601b24c677732875 Gerrit-Change-Number: 27064 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...libgfxinit[master]: gma: Give constants depending on Config.CPU* a type
by Nico Huber (Code Review) 08 May '19

08 May '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/libgfxinit/+/27063 ) Change subject: gma: Give constants depending on Config.CPU* a type ...................................................................... gma: Give constants depending on Config.CPU* a type To reduce elaboration time dependencies, turn number constants into variable constants by giving them a type. This will allow us to use the same code for configurations with constant and non-constant `GMA.Config.CPU*`. Change-Id: I0b671cb18701d0ecae118e023e0fd21be5095da0 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/27063 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/hw-gfx-gma.adb M common/ironlake/hw-gfx-gma-connectors-fdi.adb 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: Nico Huber: Verified Arthur Heymans: Looks good to me, approved diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 0a80d6b..dfe986f 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -695,7 +695,7 @@ with Pre => Is_Initialized is - GGC_Reg : constant := + GGC_Reg : constant PCI.Index := (if Config.Gen_G45 or Config.CPU_Ironlake then 16#52# else 16#50#); GGC : Word16; begin diff --git a/common/ironlake/hw-gfx-gma-connectors-fdi.adb b/common/ironlake/hw-gfx-gma-connectors-fdi.adb index 5b7f105..9821f8e 100644 --- a/common/ironlake/hw-gfx-gma-connectors-fdi.adb +++ b/common/ironlake/hw-gfx-gma-connectors-fdi.adb @@ -270,7 +270,7 @@ procedure Pre_On (Port_Cfg : Port_Config) is - Composite_Sel : constant := + Composite_Sel : constant Word32 := (if Config.Has_FDI_Composite_Sel then FDI_TX_CTL_COMPOSITE_SYNC_SELECT else 0); begin -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27063 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I0b671cb18701d0ecae118e023e0fd21be5095da0 Gerrit-Change-Number: 27063 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...libgfxinit[master]: gma: Turn constants depending on Config.CPU* into functions
by Nico Huber (Code Review) 08 May '19

08 May '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/libgfxinit/+/27062 ) Change subject: gma: Turn constants depending on Config.CPU* into functions ...................................................................... gma: Turn constants depending on Config.CPU* into functions To reduce elaboration time dependencies, turn constants at package level into functions. This will allow us to use the same code for configurations with constant and non-constant `GMA.Config.CPU*`. Change-Id: I0522f5c63c63080bf9633f3d1b6019f35e52d226 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/27062 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/hw-gfx-gma-pch-fdi.adb M common/hw-gfx-gma-pch-vga.adb M common/hw-gfx-gma-pch.ads M common/ironlake/hw-gfx-gma-connectors-fdi.adb M common/ironlake/hw-gfx-gma-pch-hdmi.adb 5 files changed, 57 insertions(+), 45 deletions(-) Approvals: Nico Huber: Verified Arthur Heymans: Looks good to me, approved diff --git a/common/hw-gfx-gma-pch-fdi.adb b/common/hw-gfx-gma-pch-fdi.adb index 53756e2..c8b1ec6 100644 --- a/common/hw-gfx-gma-pch-fdi.adb +++ b/common/hw-gfx-gma-pch-fdi.adb @@ -30,15 +30,18 @@ FDI_RX_CTL_RAWCLK_TO_PCDCLK_SEL_RAWCLK : constant := 0 * 2 ** 4; FDI_RX_CTL_RAWCLK_TO_PCDCLK_SEL_PCDCLK : constant := 1 * 2 ** 4; - TP_SHIFT : constant := (if Config.Has_New_FDI_Sink then 8 else 28); - FDI_RX_CTL_TRAINING_PATTERN_MASK : constant := 3 * 2 ** TP_SHIFT; + function TP_SHIFT return Natural is + (if Config.Has_New_FDI_Sink then 8 else 28); - type TP_Array is array (Training_Pattern) of Word32; - FDI_RX_CTL_TRAINING_PATTERN : constant TP_Array := - (TP_1 => 0 * 2 ** TP_SHIFT, - TP_2 => 1 * 2 ** TP_SHIFT, - TP_Idle => 2 * 2 ** TP_SHIFT, - TP_None => 3 * 2 ** TP_SHIFT); + function FDI_RX_CTL_TRAINING_PATTERN_MASK + return Word32 is (Shift_Left (3, TP_SHIFT)); + + function FDI_RX_CTL_TRAINING_PATTERN (TP : Training_Pattern) return Word32 is + (case TP is + when TP_1 => Shift_Left (0, TP_SHIFT), + when TP_2 => Shift_Left (1, TP_SHIFT), + when TP_Idle => Shift_Left (2, TP_SHIFT), + when TP_None => Shift_Left (3, TP_SHIFT)); function FDI_RX_CTL_PORT_WIDTH_SEL (Lane_Count : DP_Lane_Count) return Word32 is diff --git a/common/hw-gfx-gma-pch-vga.adb b/common/hw-gfx-gma-pch-vga.adb index f090246..fd82740 100644 --- a/common/hw-gfx-gma-pch-vga.adb +++ b/common/hw-gfx-gma-pch-vga.adb @@ -29,13 +29,13 @@ PCH_ADPA_VSYNC_ACTIVE_HIGH : constant := 1 * 2 ** 4; PCH_ADPA_HSYNC_ACTIVE_HIGH : constant := 1 * 2 ** 3; - PCH_ADPA_MASK : constant Word32 := - PCH_TRANSCODER_SELECT_MASK or + function PCH_ADPA_MASK return Word32 is + (PCH_TRANSCODER_SELECT_MASK or PCH_ADPA_DAC_ENABLE or PCH_ADPA_VSYNC_DISABLE or PCH_ADPA_HSYNC_DISABLE or PCH_ADPA_VSYNC_ACTIVE_HIGH or - PCH_ADPA_HSYNC_ACTIVE_HIGH; + PCH_ADPA_HSYNC_ACTIVE_HIGH); ---------------------------------------------------------------------------- diff --git a/common/hw-gfx-gma-pch.ads b/common/hw-gfx-gma-pch.ads index 0acc852..6979b1f 100644 --- a/common/hw-gfx-gma-pch.ads +++ b/common/hw-gfx-gma-pch.ads @@ -22,16 +22,16 @@ -- common to all PCH outputs - PCH_TRANSCODER_SELECT_SHIFT : constant := + function PCH_TRANSCODER_SELECT_SHIFT return Natural is (if Config.Has_New_FDI_Sink then 29 else 30); - PCH_TRANSCODER_SELECT_MASK : constant := + function PCH_TRANSCODER_SELECT_MASK return Word32 is (if Config.Has_New_FDI_Sink then 3 * 2 ** 29 else 1 * 2 ** 30); - type PCH_TRANSCODER_SELECT_Array is array (FDI_Port_Type) of Word32; - PCH_TRANSCODER_SELECT : constant PCH_TRANSCODER_SELECT_Array := - (FDI_A => 0 * 2 ** PCH_TRANSCODER_SELECT_SHIFT, - FDI_B => 1 * 2 ** PCH_TRANSCODER_SELECT_SHIFT, - FDI_C => 2 * 2 ** PCH_TRANSCODER_SELECT_SHIFT); + function PCH_TRANSCODER_SELECT (Port : FDI_Port_Type) return Word32 is + (case Port is + when FDI_A => Shift_Left (0, PCH_TRANSCODER_SELECT_SHIFT), + when FDI_B => Shift_Left (1, PCH_TRANSCODER_SELECT_SHIFT), + when FDI_C => Shift_Left (2, PCH_TRANSCODER_SELECT_SHIFT)); end HW.GFX.GMA.PCH; diff --git a/common/ironlake/hw-gfx-gma-connectors-fdi.adb b/common/ironlake/hw-gfx-gma-connectors-fdi.adb index 4eec9c9..5b7f105 100644 --- a/common/ironlake/hw-gfx-gma-connectors-fdi.adb +++ b/common/ironlake/hw-gfx-gma-connectors-fdi.adb @@ -23,6 +23,8 @@ package body HW.GFX.GMA.Connectors.FDI is + use all type PCH.FDI.Training_Pattern; + PCH_FDI_CHICKEN_B_AND_C : constant := 1 * 2 ** 12; type TX_CTL_Regs is array (GPU_FDI_Port) of Registers.Registers_Index; @@ -40,12 +42,19 @@ FDI_TX_CTL_AUTO_TRAIN_ENABLE : constant := 1 * 2 ** 10; FDI_TX_CTL_AUTO_TRAIN_DONE : constant := 1 * 2 ** 1; - TP_SHIFT : constant := (if Config.Has_New_FDI_Source then 8 else 28); - FDI_TX_CTL_TRAINING_PATTERN_MASK : constant := 3 * 2 ** TP_SHIFT; - FDI_TX_CTL_TRAINING_PATTERN_1 : constant := 0 * 2 ** TP_SHIFT; - FDI_TX_CTL_TRAINING_PATTERN_2 : constant := 1 * 2 ** TP_SHIFT; - FDI_TX_CTL_TRAINING_PATTERN_IDLE : constant := 2 * 2 ** TP_SHIFT; - FDI_TX_CTL_TRAINING_PATTERN_NORMAL : constant := 3 * 2 ** TP_SHIFT; + function TP_SHIFT return Natural is + (if Config.Has_New_FDI_Source then 8 else 28); + + function FDI_TX_CTL_TRAINING_PATTERN_MASK + return Word32 is (Shift_Left (3, TP_SHIFT)); + + function FDI_TX_CTL_TRAINING_PATTERN (TP : PCH.FDI.Training_Pattern) + return Word32 is + (case TP is + when TP_1 => Shift_Left (0, TP_SHIFT), + when TP_2 => Shift_Left (1, TP_SHIFT), + when TP_Idle => Shift_Left (2, TP_SHIFT), + when TP_None => Shift_Left (3, TP_SHIFT)); subtype FDI_TX_CTL_VP_T is Natural range 0 .. 3; type Vswing_Preemph_Values is array (FDI_TX_CTL_VP_T) of Word32; @@ -88,7 +97,7 @@ Mask_Set => FDI_TX_CTL_FDI_TX_ENABLE or FDI_TX_CTL_VSWING_PREEMPH (VP2 / 2) or FDI_TX_CTL_AUTO_TRAIN_ENABLE or - FDI_TX_CTL_TRAINING_PATTERN_1); + FDI_TX_CTL_TRAINING_PATTERN (TP_1)); Registers.Posting_Read (TX_CTL (Port_Cfg.Port)); PCH.FDI.Auto_Train (PCH_FDI_Port); @@ -109,7 +118,7 @@ Mask_Unset => FDI_TX_CTL_FDI_TX_ENABLE or FDI_TX_CTL_AUTO_TRAIN_ENABLE or FDI_TX_CTL_TRAINING_PATTERN_MASK, - Mask_Set => FDI_TX_CTL_TRAINING_PATTERN_1); + Mask_Set => FDI_TX_CTL_TRAINING_PATTERN (TP_1)); PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Rx_Off); end loop; @@ -149,19 +158,19 @@ FDI_TX_CTL_TRAINING_PATTERN_MASK, Mask_Set => FDI_TX_CTL_FDI_TX_ENABLE or FDI_TX_CTL_VSWING_PREEMPH (VP2 / 2) or - FDI_TX_CTL_TRAINING_PATTERN_1); + FDI_TX_CTL_TRAINING_PATTERN (TP_1)); Registers.Posting_Read (TX_CTL (Port_Cfg.Port)); - PCH.FDI.Train (PCH_FDI_Port, PCH.FDI.TP_1, Success); + PCH.FDI.Train (PCH_FDI_Port, TP_1, Success); if Success then Registers.Unset_And_Set_Mask (Register => TX_CTL (Port_Cfg.Port), Mask_Unset => FDI_TX_CTL_TRAINING_PATTERN_MASK, - Mask_Set => FDI_TX_CTL_TRAINING_PATTERN_2); + Mask_Set => FDI_TX_CTL_TRAINING_PATTERN (TP_2)); Registers.Posting_Read (TX_CTL (Port_Cfg.Port)); - PCH.FDI.Train (PCH_FDI_Port, PCH.FDI.TP_2, Success); + PCH.FDI.Train (PCH_FDI_Port, TP_2, Success); end if; exit when Success; @@ -169,7 +178,7 @@ (Register => TX_CTL (Port_Cfg.Port), Mask_Unset => FDI_TX_CTL_FDI_TX_ENABLE or FDI_TX_CTL_TRAINING_PATTERN_MASK, - Mask_Set => FDI_TX_CTL_TRAINING_PATTERN_1); + Mask_Set => FDI_TX_CTL_TRAINING_PATTERN (TP_1)); PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Rx_Off); end loop; @@ -178,10 +187,10 @@ Registers.Unset_And_Set_Mask (Register => TX_CTL (Port_Cfg.Port), Mask_Unset => FDI_TX_CTL_TRAINING_PATTERN_MASK, - Mask_Set => FDI_TX_CTL_TRAINING_PATTERN_NORMAL); + Mask_Set => FDI_TX_CTL_TRAINING_PATTERN (TP_None)); Registers.Posting_Read (TX_CTL (Port_Cfg.Port)); - PCH.FDI.Train (PCH_FDI_Port, PCH.FDI.TP_None, Success); + PCH.FDI.Train (PCH_FDI_Port, TP_None, Success); else Registers.Unset_Mask (Register => TX_CTL (Port_Cfg.Port), @@ -219,35 +228,35 @@ (Register => TX_CTL (Port_Cfg.Port), Mask_Unset => FDI_TX_CTL_TRAINING_PATTERN_MASK, Mask_Set => FDI_TX_CTL_FDI_TX_ENABLE or - FDI_TX_CTL_TRAINING_PATTERN_1); + FDI_TX_CTL_TRAINING_PATTERN (TP_1)); Registers.Posting_Read (TX_CTL (Port_Cfg.Port)); - PCH.FDI.Train (PCH_FDI_Port, PCH.FDI.TP_1, Success); + PCH.FDI.Train (PCH_FDI_Port, TP_1, Success); if Success then Registers.Unset_And_Set_Mask (Register => TX_CTL (Port_Cfg.Port), Mask_Unset => FDI_TX_CTL_TRAINING_PATTERN_MASK, - Mask_Set => FDI_TX_CTL_TRAINING_PATTERN_2); + Mask_Set => FDI_TX_CTL_TRAINING_PATTERN (TP_2)); Registers.Posting_Read (TX_CTL (Port_Cfg.Port)); - PCH.FDI.Train (PCH_FDI_Port, PCH.FDI.TP_2, Success); + PCH.FDI.Train (PCH_FDI_Port, TP_2, Success); end if; if Success then Registers.Unset_And_Set_Mask (Register => TX_CTL (Port_Cfg.Port), Mask_Unset => FDI_TX_CTL_TRAINING_PATTERN_MASK, - Mask_Set => FDI_TX_CTL_TRAINING_PATTERN_NORMAL); + Mask_Set => FDI_TX_CTL_TRAINING_PATTERN (TP_None)); Registers.Posting_Read (TX_CTL (Port_Cfg.Port)); - PCH.FDI.Train (PCH_FDI_Port, PCH.FDI.TP_None, Success); + PCH.FDI.Train (PCH_FDI_Port, TP_None, Success); else Registers.Unset_And_Set_Mask (Register => TX_CTL (Port_Cfg.Port), Mask_Unset => FDI_TX_CTL_FDI_TX_ENABLE or FDI_TX_CTL_TRAINING_PATTERN_MASK, - Mask_Set => FDI_TX_CTL_TRAINING_PATTERN_1); + Mask_Set => FDI_TX_CTL_TRAINING_PATTERN (TP_1)); PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Rx_Off); Registers.Unset_Mask @@ -293,7 +302,7 @@ FDI_TX_CTL_ENHANCED_FRAMING_ENABLE or FDI_TX_CTL_FDI_PLL_ENABLE or Composite_Sel or - FDI_TX_CTL_TRAINING_PATTERN_1); + FDI_TX_CTL_TRAINING_PATTERN (TP_1)); Registers.Posting_Read (TX_CTL (Port_Cfg.Port)); Time.U_Delay (100); end Pre_On; @@ -327,7 +336,7 @@ Mask_Unset => FDI_TX_CTL_FDI_TX_ENABLE or FDI_TX_CTL_AUTO_TRAIN_ENABLE or FDI_TX_CTL_TRAINING_PATTERN_MASK, - Mask_Set => FDI_TX_CTL_TRAINING_PATTERN_1); + Mask_Set => FDI_TX_CTL_TRAINING_PATTERN (TP_1)); PCH.FDI.Off (PCH_FDI_Port, PCH.FDI.Rx_Off); diff --git a/common/ironlake/hw-gfx-gma-pch-hdmi.adb b/common/ironlake/hw-gfx-gma-pch-hdmi.adb index e53d85a..aaf7951 100644 --- a/common/ironlake/hw-gfx-gma-pch-hdmi.adb +++ b/common/ironlake/hw-gfx-gma-pch-hdmi.adb @@ -31,13 +31,13 @@ PCH_HDMI_HSYNC_ACTIVE_HIGH : constant := 1 * 2 ** 3; PCH_HDMI_PORT_DETECT : constant := 1 * 2 ** 2; - PCH_HDMI_MASK : constant Word32 := - PCH_TRANSCODER_SELECT_MASK or + function PCH_HDMI_MASK return Word32 is + (PCH_TRANSCODER_SELECT_MASK or PCH_HDMI_ENABLE or PCH_HDMI_COLOR_FORMAT_MASK or PCH_HDMI_SDVO_ENCODING_MASK or PCH_HDMI_HSYNC_ACTIVE_HIGH or - PCH_HDMI_VSYNC_ACTIVE_HIGH; + PCH_HDMI_VSYNC_ACTIVE_HIGH); type PCH_HDMI_Array is array (PCH_HDMI_Port) of Registers.Registers_Index; PCH_HDMI : constant PCH_HDMI_Array := PCH_HDMI_Array' -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I0522f5c63c63080bf9633f3d1b6019f35e52d226 Gerrit-Change-Number: 27062 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...libgfxinit[master]: gma config: Limit types of CPU and CPU_Var
by Nico Huber (Code Review) 08 May '19

08 May '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/libgfxinit/+/27061 ) Change subject: gma config: Limit types of CPU and CPU_Var ...................................................................... gma config: Limit types of CPU and CPU_Var Limit the range of values for `CPU` and `CPU_Var` based on the generation. Change-Id: Ibeca7d0fb5cbc617a0819448e78d406793c6f866 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/27061 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/hw-gfx-gma-config.ads.template 1 file changed, 23 insertions(+), 2 deletions(-) Approvals: Nico Huber: Verified Arthur Heymans: Looks good to me, approved diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 8f231e0..6033dc0 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -19,9 +19,30 @@ Gen : constant Generation := <<GEN>>; - CPU : constant CPU_Type := <<CPU>>; + CPU_First : constant CPU_Type := + (case Gen is + when G45 => G45, + when Ironlake => Ironlake, + when Haswell => Haswell, + when Broxton => Broxton, + when Skylake => Skylake); + CPU_Last : constant CPU_Type := + (case Gen is + when G45 => G45, + when Ironlake => Ivybridge, + when Haswell => Broadwell, + when Broxton => Broxton, + when Skylake => Skylake); + CPU_Var_Last : constant CPU_Variant := + (case Gen is + when Haswell | Skylake => ULT, + when others => Normal); + subtype Gen_CPU_Type is CPU_Type range CPU_First .. CPU_Last; + subtype Gen_CPU_Variant is CPU_Variant range Normal .. CPU_Var_Last; - CPU_Var : constant CPU_Variant := <<CPU_VARIANT>>; + CPU : constant Gen_CPU_Type := <<CPU>>; + + CPU_Var : constant Gen_CPU_Variant := <<CPU_VARIANT>>; Internal_Display : constant Internal_Type := <<INTERNAL_PORT>>; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27061 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ibeca7d0fb5cbc617a0819448e78d406793c6f866 Gerrit-Change-Number: 27061 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...libgfxinit[master]: gma config: Introduce per CPU booleans
by Nico Huber (Code Review) 08 May '19

08 May '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/libgfxinit/+/27060 ) Change subject: gma config: Introduce per CPU booleans ...................................................................... gma config: Introduce per CPU booleans The per CPU booleans are additionally guarded by the respective generation so that the compiler may decide purely on the generation. Also use the new booleans to get rid of all direct references to `Config.CPU` and `Config.CPU_Var`. Change-Id: I307d1dd56f480fdb4fbc6e2e25fc5f413c4158f8 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/27060 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/haswell/hw-gfx-gma-connectors-ddi-buffers.adb M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma.adb 3 files changed, 121 insertions(+), 127 deletions(-) Approvals: Nico Huber: Verified Arthur Heymans: Looks good to me, approved diff --git a/common/haswell/hw-gfx-gma-connectors-ddi-buffers.adb b/common/haswell/hw-gfx-gma-connectors-ddi-buffers.adb index baceb10..df5c55b 100644 --- a/common/haswell/hw-gfx-gma-connectors-ddi-buffers.adb +++ b/common/haswell/hw-gfx-gma-connectors-ddi-buffers.adb @@ -125,27 +125,25 @@ else Config.Default_DDI_HDMI_Buffer_Translation); begin Trans := - (case Config.CPU is - when Broadwell => - (case Port is - when DIGI_A => - (if Config.EDP_Low_Voltage_Swing - then Broadwell_Trans_EDP - else Broadwell_Trans_DP), - when DIGI_B .. DIGI_D => Broadwell_Trans_DP, - when DIGI_E => Broadwell_Trans_FDI), - when others => - (case Port is - when DIGI_A .. DIGI_D => Haswell_Trans_DP, - when DIGI_E => Haswell_Trans_FDI)); - case Config.CPU is - when Broadwell => - Trans (18) := Broadwell_Trans_HDMI (HDMI_Trans).Trans1; - Trans (19) := Broadwell_Trans_HDMI (HDMI_Trans).Trans2; - when others => - Trans (18) := Haswell_Trans_HDMI (HDMI_Trans).Trans1; - Trans (19) := Haswell_Trans_HDMI (HDMI_Trans).Trans2; - end case; + (if Config.CPU_Haswell then + (case Port is + when DIGI_A .. DIGI_D => Haswell_Trans_DP, + when DIGI_E => Haswell_Trans_FDI) + else + (case Port is + when DIGI_A => + (if Config.EDP_Low_Voltage_Swing + then Broadwell_Trans_EDP + else Broadwell_Trans_DP), + when DIGI_B .. DIGI_D => Broadwell_Trans_DP, + when DIGI_E => Broadwell_Trans_FDI)); + if Config.CPU_Haswell then + Trans (18) := Haswell_Trans_HDMI (HDMI_Trans).Trans1; + Trans (19) := Haswell_Trans_HDMI (HDMI_Trans).Trans2; + else + Trans (18) := Broadwell_Trans_HDMI (HDMI_Trans).Trans1; + Trans (19) := Broadwell_Trans_HDMI (HDMI_Trans).Trans2; + end if; end Translations; end HW.GFX.GMA.Connectors.DDI.Buffers; diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 5703926..8f231e0 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -49,6 +49,19 @@ Broxton_On : constant Boolean := Gen >= Broxton; Skylake_On : constant Boolean := Gen >= Skylake; + CPU_Ironlake : constant Boolean := Gen_Ironlake and then CPU = Ironlake; + CPU_Sandybridge : constant Boolean := Gen_Ironlake and then CPU = Sandybridge; + CPU_Ivybridge : constant Boolean := Gen_Ironlake and then CPU = Ivybridge; + CPU_Haswell : constant Boolean := Gen_Haswell and then CPU = Haswell; + CPU_Broadwell : constant Boolean := Gen_Haswell and then CPU = Broadwell; + + Sandybridge_On : constant Boolean := + ((Gen_Ironlake and then CPU >= Sandybridge) or Haswell_On); + Ivybridge_On : constant Boolean := + ((Gen_Ironlake and then CPU >= Ivybridge) or Haswell_On); + Broadwell_On : constant Boolean := + ((Gen_Haswell and then CPU >= Broadwell) or Broxton_On); + ---------------------------------------------------------------------------- Have_HDMI_Buf_Override : constant Boolean := DDI_HDMI_Buffer_Translation >= 0; @@ -59,24 +72,25 @@ Internal_Is_EDP : constant Boolean := Internal_Display = DP; Have_DVI_I : constant Boolean := Analog_I2C_Port /= PCH_DAC; Has_Presence_Straps : constant Boolean := not Gen_Broxton; - Is_ULT : constant Boolean := CPU_Var = ULT; + Is_ULT : constant Boolean := + ((Gen_Haswell or Gen_Skylake) and then CPU_Var = ULT); ----- CPU pipe: -------- - Has_Tertiary_Pipe : constant Boolean := CPU >= Ivybridge; + Has_Tertiary_Pipe : constant Boolean := Ivybridge_On; Disable_Trickle_Feed : constant Boolean := not Gen_Haswell; - Pipe_Enabled_Workaround : constant Boolean := CPU = Broadwell; + Pipe_Enabled_Workaround : constant Boolean := CPU_Broadwell; Has_EDP_Transcoder : constant Boolean := Haswell_On; - Use_PDW_For_EDP_Scaling : constant Boolean := CPU = Haswell; + Use_PDW_For_EDP_Scaling : constant Boolean := CPU_Haswell; Has_Pipe_DDI_Func : constant Boolean := Haswell_On; Has_Trans_Clk_Sel : constant Boolean := Haswell_On; Has_Pipe_MSA_Misc : constant Boolean := Haswell_On; - Has_Pipeconf_Misc : constant Boolean := CPU >= Broadwell; - Has_Pipeconf_BPC : constant Boolean := CPU /= Haswell; + Has_Pipeconf_Misc : constant Boolean := Broadwell_On; + Has_Pipeconf_BPC : constant Boolean := not CPU_Haswell; Has_Plane_Control : constant Boolean := Broxton_On; Has_DSP_Linoff : constant Boolean := Up_To_Ironlake; - Has_PF_Pipe_Select : constant Boolean := CPU in Ivybridge .. Haswell; - Has_Cursor_FBC_Control : constant Boolean := CPU >= Ivybridge; - VGA_Plane_Workaround : constant Boolean := CPU = Ivybridge; + Has_PF_Pipe_Select : constant Boolean := CPU_Ivybridge or CPU_Haswell; + Has_Cursor_FBC_Control : constant Boolean := Ivybridge_On; + VGA_Plane_Workaround : constant Boolean := CPU_Ivybridge; Has_GMCH_DP_Transcoder : constant Boolean := Gen_G45; Has_GMCH_VGACNTRL : constant Boolean := Gen_G45; Has_GMCH_PFIT_CONTROL : constant Boolean := Gen_G45; @@ -89,24 +103,22 @@ ----- PCH/FDI: --------- Has_PCH : constant Boolean := not Gen_Broxton and not Gen_G45; - Has_PCH_DAC : constant Boolean := CPU in Ironlake .. Ivybridge or - (CPU in Haswell .. Broadwell - and not Is_ULT); + Has_PCH_DAC : constant Boolean := + (Gen_Ironlake or (Gen_Haswell and then not Is_ULT)); Has_PCH_Aux_Channels : constant Boolean := Gen_Ironlake or Gen_Haswell; VGA_Has_Sync_Disable : constant Boolean := Up_To_Ironlake; - Has_Trans_Timing_Ovrrde : constant Boolean := CPU >= Sandybridge; + Has_Trans_Timing_Ovrrde : constant Boolean := Sandybridge_On; Has_DPLL_SEL : constant Boolean := Gen_Ironlake; Has_FDI_BPC : constant Boolean := Gen_Ironlake; - Has_FDI_Composite_Sel : constant Boolean := CPU = Ivybridge; - Has_New_FDI_Sink : constant Boolean := CPU >= Sandybridge; - Has_New_FDI_Source : constant Boolean := CPU >= Ivybridge; - Has_Trans_DP_Ctl : constant Boolean := CPU in - Sandybridge .. Ivybridge; - Has_FDI_C : constant Boolean := CPU = Ivybridge; + Has_FDI_Composite_Sel : constant Boolean := CPU_Ivybridge; + Has_New_FDI_Sink : constant Boolean := Sandybridge_On; + Has_New_FDI_Source : constant Boolean := Ivybridge_On; + Has_Trans_DP_Ctl : constant Boolean := CPU_Sandybridge or CPU_Ivybridge; + Has_FDI_C : constant Boolean := CPU_Ivybridge; Has_FDI_RX_Power_Down : constant Boolean := Gen_Haswell; @@ -116,15 +128,13 @@ End_EDP_Training_Late : constant Boolean := Gen_Haswell; Has_Per_DDI_Clock_Sel : constant Boolean := Gen_Haswell; Has_HOTPLUG_CTL : constant Boolean := Gen_Haswell; - Has_SHOTPLUG_CTL_A : constant Boolean := (CPU in Haswell .. Broadwell - and Is_ULT) or - CPU >= Skylake; + Has_SHOTPLUG_CTL_A : constant Boolean := + ((Gen_Haswell and then Is_ULT) or Skylake_On); Has_DDI_PHYs : constant Boolean := Gen_Broxton; - Has_DDI_D : constant Boolean := CPU >= Haswell and - not Is_ULT and - not Has_DDI_PHYs; + Has_DDI_D : constant Boolean := + ((Gen_Haswell or Gen_Skylake) and then not Is_ULT); Has_DDI_E : constant Boolean := -- might be disabled by x4 eDP Has_DDI_D; @@ -141,14 +151,15 @@ Has_PCH_GMBUS : constant Boolean := Ironlake_On; ----- Power: ----------- - Has_IPS : constant Boolean := (CPU = Haswell and Is_ULT) or - CPU = Broadwell; - Has_IPS_CTL_Mailbox : constant Boolean := CPU = Broadwell; + Has_IPS : constant Boolean := + (Gen_Haswell and then + ((CPU_Haswell and Is_ULT) or CPU_Broadwell)); + Has_IPS_CTL_Mailbox : constant Boolean := CPU_Broadwell; - Has_Per_Pipe_SRD : constant Boolean := CPU >= Broadwell; + Has_Per_Pipe_SRD : constant Boolean := Broadwell_On; ----- GTT: ------------- - Has_64bit_GTT : constant Boolean := CPU >= Broadwell; + Has_64bit_GTT : constant Boolean := Broadwell_On; ---------------------------------------------------------------------------- @@ -177,44 +188,35 @@ others => (if Gen_Ironlake then DP_Lane_Count_4 else DP_Lane_Count_2)); FDI_Training : constant FDI_Training_Type := - (case CPU is - when Ironlake => Simple_Training, - when Sandybridge => Full_Training, - when others => Auto_Training); + (if CPU_Ironlake then Simple_Training + elsif CPU_Sandybridge then Full_Training + else Auto_Training); ---------------------------------------------------------------------------- Default_DDI_HDMI_Buffer_Translation : constant DDI_HDMI_Buf_Trans_Range := - (case CPU is - when Haswell => 6, - when Broadwell => 7, - when Broxton => 8, - when Skylake => 8, - when others => 0); + (if CPU_Haswell then 6 + elsif CPU_Broadwell then 7 + elsif Broxton_On then 8 + else 0); ---------------------------------------------------------------------------- Default_CDClk_Freq : constant Frequency_Type := - (case CPU is - when G45 => 320_000_000, -- unused - when Ironlake | - Haswell | - Broadwell => 450_000_000, - when Sandybridge | - Ivybridge => 400_000_000, - when Broxton => 288_000_000, - when Skylake => 337_500_000); + (if Gen_G45 then 320_000_000 -- unused + elsif CPU_Ironlake or Gen_Haswell then 450_000_000 + elsif CPU_Sandybridge or CPU_Ivybridge then 400_000_000 + elsif Gen_Broxton then 288_000_000 + elsif Gen_Skylake then 337_500_000 + else Frequency_Type'First); Default_RawClk_Freq : constant Frequency_Type := - (case CPU is - when G45 => 100_000_000, -- unused, depends on FSB - when Ironlake | - Sandybridge | - Ivybridge => 125_000_000, - when Haswell | - Broadwell => (if Is_ULT then 24_000_000 else 125_000_000), - when Broxton => Frequency_Type'First, -- none needed - when Skylake => 24_000_000); + (if Gen_G45 then 100_000_000 -- unused, depends on FSB + elsif Gen_Ironlake then 125_000_000 + elsif Gen_Haswell then (if Is_ULT then 24_000_000 else 125_000_000) + elsif Gen_Broxton then Frequency_Type'First -- none needed + elsif Gen_Skylake then 24_000_000 + else Frequency_Type'First); Raw_Clock : Frequency_Type := Default_RawClk_Freq with Part_Of => GMA.Config_State; @@ -227,19 +229,18 @@ type Width_Per_Pipe is array (Pipe_Index) of Width_Type; Maximum_Scalable_Width : constant Width_Per_Pipe := - (case CPU is - when G45 => -- TODO: Is this true? - (Primary => 4096, - Secondary => 2048, - Tertiary => Pos32'First), - when Ironlake..Haswell => - (Primary => 4096, - Secondary => 2048, - Tertiary => 2048), - when Broadwell..Skylake => - (Primary => 4096, - Secondary => 4096, - Tertiary => 4096)); + (if Gen_G45 then -- TODO: Is this true? + (Primary => 4096, + Secondary => 2048, + Tertiary => Pos32'First) + elsif Gen_Ironlake or CPU_Haswell then + (Primary => 4096, + Secondary => 2048, + Tertiary => 2048) + else + (Primary => 4096, + Secondary => 4096, + Tertiary => 4096)); -- Maximum X position of hardware cursors Maximum_Cursor_X : constant := (case Gen is @@ -258,13 +259,11 @@ GTT_PTE_Size : constant := (if Has_64bit_GTT then 8 else 4); - Fence_Base : constant := (case CPU is - when G45 .. Ironlake => 16#0000_3000#, - when Sandybridge .. Skylake => 16#0010_0000#); + Fence_Base : constant := + (if not Sandybridge_On then 16#0000_3000# else 16#0010_0000#); - Fence_Count : constant := (case CPU is - when G45 .. Sandybridge => 16, - when Ivybridge .. Skylake => 32); + Fence_Count : constant := + (if not Ivybridge_On then 16 else 32); ---------------------------------------------------------------------------- diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index abb9ffc..0a80d6b 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -407,18 +407,17 @@ Registers.Read (Registers.AUD_VID_DID, Audio_VID_DID); end case; Success := - (case Config.CPU is - when Broxton => Audio_VID_DID = 16#8086_280a#, - when Skylake => Audio_VID_DID = 16#8086_2809#, - when Broadwell => Audio_VID_DID = 16#8086_2808#, - when Haswell => Audio_VID_DID = 16#8086_2807#, - when Ivybridge | - Sandybridge => Audio_VID_DID = 16#8086_2806# or - Audio_VID_DID = 16#8086_2805#, - when Ironlake => Audio_VID_DID = 16#0000_0000#, - when G45 => Audio_VID_DID = 16#8086_2801# or - Audio_VID_DID = 16#8086_2802# or - Audio_VID_DID = 16#8086_2803#); + ((Config.Gen_Broxton and Audio_VID_DID = 16#8086_280a#) or + (Config.Gen_Skylake and Audio_VID_DID = 16#8086_2809#) or + (Config.CPU_Broadwell and Audio_VID_DID = 16#8086_2808#) or + (Config.CPU_Haswell and Audio_VID_DID = 16#8086_2807#) or + ((Config.CPU_Ivybridge or + Config.CPU_Sandybridge) and (Audio_VID_DID = 16#8086_2806# or + Audio_VID_DID = 16#8086_2805#)) or + (Config.CPU_Ironlake and Audio_VID_DID = 16#0000_0000#) or + (Config.Gen_G45 and (Audio_VID_DID = 16#8086_2801# or + Audio_VID_DID = 16#8086_2802# or + Audio_VID_DID = 16#8086_2803#))); end Check_Platform; procedure Check_Platform_PCI (Success : out Boolean) @@ -697,26 +696,24 @@ Pre => Is_Initialized is GGC_Reg : constant := - (case Config.CPU is - when G45 | Ironlake => 16#52#, - when Sandybridge .. Skylake => 16#50#); + (if Config.Gen_G45 or Config.CPU_Ironlake then 16#52# else 16#50#); GGC : Word16; begin Dev.Read16 (GGC, GGC_Reg); - case Config.CPU is - when G45 | Ironlake => - GTT_Size := GTT_Size_Gen4 (GGC); - Stolen_Size := Stolen_Size_Gen4 (GGC); - when Sandybridge .. Haswell => - GTT_Size := GTT_Size_Gen6 (GGC); - Stolen_Size := Stolen_Size_Gen6 (GGC); - when Broadwell => - GTT_Size := GTT_Size_Gen8 (GGC); - Stolen_Size := Stolen_Size_Gen8 (GGC); - when Broxton .. Skylake => - GTT_Size := GTT_Size_Gen8 (GGC); - Stolen_Size := Stolen_Size_Gen9 (GGC); - end case; + if Config.Gen_G45 or Config.CPU_Ironlake then + GTT_Size := GTT_Size_Gen4 (GGC); + Stolen_Size := Stolen_Size_Gen4 (GGC); + elsif Config.CPU_Sandybridge or Config.CPU_Ivybridge or Config.CPU_Haswell + then + GTT_Size := GTT_Size_Gen6 (GGC); + Stolen_Size := Stolen_Size_Gen6 (GGC); + elsif Config.CPU_Broadwell then + GTT_Size := GTT_Size_Gen8 (GGC); + Stolen_Size := Stolen_Size_Gen8 (GGC); + else + GTT_Size := GTT_Size_Gen8 (GGC); + Stolen_Size := Stolen_Size_Gen9 (GGC); + end if; end Decode_Stolen; -- Additional runtime validation that FB fits stolen memory and aperture. -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I307d1dd56f480fdb4fbc6e2e25fc5f413c4158f8 Gerrit-Change-Number: 27060 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...libgfxinit[master]: gma: Introduce Generation type
by Nico Huber (Code Review) 08 May '19

08 May '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/libgfxinit/+/27059 ) Change subject: gma: Introduce Generation type ...................................................................... gma: Introduce Generation type It's the subset of `CPU_Type` that we have different compilation units for. Also use it in the `Config` wherever we can decide something purely on the `Generation` (i.e. don't mix `Gen` and `CPU` in expressions). Change-Id: I5061021a80cd75ee3d7996ca343e6388b22bf341 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/27059 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/Makefile.inc M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-config_helpers.adb M common/hw-gfx-gma.adb M common/hw-gfx-gma.ads M configs/broadwell M configs/broadwell_ult M configs/broxton M configs/g45 M configs/haswell M configs/haswell_ult M configs/ironlake M configs/ivybridge_edp M configs/ivybridge_lvds M configs/sandybridge M configs/skylake M configs/skylake_ult 17 files changed, 82 insertions(+), 61 deletions(-) Approvals: Nico Huber: Verified Arthur Heymans: Looks good to me, approved diff --git a/common/Makefile.inc b/common/Makefile.inc index 8d6634e..410eeba 100644 --- a/common/Makefile.inc +++ b/common/Makefile.inc @@ -45,6 +45,7 @@ gfxinit-y += hw-gfx-framebuffer_filler.adb gfxinit-y += hw-gfx-framebuffer_filler.ads +CONFIG_GFX_GMA_GENERATION := $(call strip_quotes,$(CONFIG_GFX_GMA_GENERATION)) CONFIG_GFX_GMA_CPU := $(call strip_quotes,$(CONFIG_GFX_GMA_CPU)) CONFIG_GFX_GMA_CPU_VARIANT := $(call strip_quotes,$(CONFIG_GFX_GMA_CPU_VARIANT)) CONFIG_GFX_GMA_INTERNAL_PORT := $(call strip_quotes,$(CONFIG_GFX_GMA_INTERNAL_PORT)) @@ -54,7 +55,8 @@ $(hw-gfx-gma-config-ads): $(dir)/hw-gfx-gma-config.ads.template $(cnf) printf " GENERATE $(patsubst /%,%,$(subst $(obj)/,,$@))\n" - sed -e's/<<CPU>>/$(CONFIG_GFX_GMA_CPU)/' \ + sed -e's/<<GEN>>/$(CONFIG_GFX_GMA_GENERATION)/' \ + -e's/<<CPU>>/$(CONFIG_GFX_GMA_CPU)/' \ -e's/<<CPU_VARIANT>>/$(CONFIG_GFX_GMA_CPU_VARIANT)/' \ -e's/<<INTERNAL_PORT>>/$(CONFIG_GFX_GMA_INTERNAL_PORT)/' \ -e's/<<ANALOG_I2C_PORT>>/$(CONFIG_GFX_GMA_ANALOG_I2C_PORT)/' \ diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index e34e89d..5703926 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -17,6 +17,8 @@ Initializes => (Valid_Port, Raw_Clock) is + Gen : constant Generation := <<GEN>>; + CPU : constant CPU_Type := <<CPU>>; CPU_Var : constant CPU_Variant := <<CPU_VARIANT>>; @@ -35,6 +37,20 @@ ---------------------------------------------------------------------------- + Gen_G45 : constant Boolean := Gen = G45; + Gen_Ironlake : constant Boolean := Gen = Ironlake; + Gen_Haswell : constant Boolean := Gen = Haswell; + Gen_Broxton : constant Boolean := Gen = Broxton; + Gen_Skylake : constant Boolean := Gen = Skylake; + + Up_To_Ironlake : constant Boolean := Gen <= Ironlake; + Ironlake_On : constant Boolean := Gen >= Ironlake; + Haswell_On : constant Boolean := Gen >= Haswell; + Broxton_On : constant Boolean := Gen >= Broxton; + Skylake_On : constant Boolean := Gen >= Skylake; + + ---------------------------------------------------------------------------- + Have_HDMI_Buf_Override : constant Boolean := DDI_HDMI_Buffer_Translation >= 0; Default_MMIO_Base_Set : constant Boolean := Default_MMIO_Base /= 0; @@ -42,50 +58,49 @@ Internal_Is_LVDS : constant Boolean := Internal_Display = LVDS; Internal_Is_EDP : constant Boolean := Internal_Display = DP; Have_DVI_I : constant Boolean := Analog_I2C_Port /= PCH_DAC; - Has_Presence_Straps : constant Boolean := CPU /= Broxton; + Has_Presence_Straps : constant Boolean := not Gen_Broxton; Is_ULT : constant Boolean := CPU_Var = ULT; ----- CPU pipe: -------- Has_Tertiary_Pipe : constant Boolean := CPU >= Ivybridge; - Disable_Trickle_Feed : constant Boolean := not - (CPU in Haswell .. Broadwell); + Disable_Trickle_Feed : constant Boolean := not Gen_Haswell; Pipe_Enabled_Workaround : constant Boolean := CPU = Broadwell; - Has_EDP_Transcoder : constant Boolean := CPU >= Haswell; + Has_EDP_Transcoder : constant Boolean := Haswell_On; Use_PDW_For_EDP_Scaling : constant Boolean := CPU = Haswell; - Has_Pipe_DDI_Func : constant Boolean := CPU >= Haswell; - Has_Trans_Clk_Sel : constant Boolean := CPU >= Haswell; - Has_Pipe_MSA_Misc : constant Boolean := CPU >= Haswell; + Has_Pipe_DDI_Func : constant Boolean := Haswell_On; + Has_Trans_Clk_Sel : constant Boolean := Haswell_On; + Has_Pipe_MSA_Misc : constant Boolean := Haswell_On; Has_Pipeconf_Misc : constant Boolean := CPU >= Broadwell; Has_Pipeconf_BPC : constant Boolean := CPU /= Haswell; - Has_Plane_Control : constant Boolean := CPU >= Broxton; - Has_DSP_Linoff : constant Boolean := CPU <= Ivybridge; + Has_Plane_Control : constant Boolean := Broxton_On; + Has_DSP_Linoff : constant Boolean := Up_To_Ironlake; Has_PF_Pipe_Select : constant Boolean := CPU in Ivybridge .. Haswell; Has_Cursor_FBC_Control : constant Boolean := CPU >= Ivybridge; VGA_Plane_Workaround : constant Boolean := CPU = Ivybridge; - Has_GMCH_DP_Transcoder : constant Boolean := CPU = G45; - Has_GMCH_VGACNTRL : constant Boolean := CPU = G45; - Has_GMCH_PFIT_CONTROL : constant Boolean := CPU = G45; + Has_GMCH_DP_Transcoder : constant Boolean := Gen_G45; + Has_GMCH_VGACNTRL : constant Boolean := Gen_G45; + Has_GMCH_PFIT_CONTROL : constant Boolean := Gen_G45; ----- Panel power: ----- - Has_PP_Write_Protection : constant Boolean := CPU <= Ivybridge; - Has_PP_Port_Select : constant Boolean := CPU <= Ivybridge; - Use_PP_VDD_Override : constant Boolean := CPU <= Ivybridge; - Has_PCH_Panel_Power : constant Boolean := CPU >= Ironlake; + Has_PP_Write_Protection : constant Boolean := Up_To_Ironlake; + Has_PP_Port_Select : constant Boolean := Up_To_Ironlake; + Use_PP_VDD_Override : constant Boolean := Up_To_Ironlake; + Has_PCH_Panel_Power : constant Boolean := Ironlake_On; ----- PCH/FDI: --------- - Has_PCH : constant Boolean := CPU /= Broxton and CPU /= G45; + Has_PCH : constant Boolean := not Gen_Broxton and not Gen_G45; Has_PCH_DAC : constant Boolean := CPU in Ironlake .. Ivybridge or (CPU in Haswell .. Broadwell and not Is_ULT); - Has_PCH_Aux_Channels : constant Boolean := CPU in Ironlake .. Broadwell; + Has_PCH_Aux_Channels : constant Boolean := Gen_Ironlake or Gen_Haswell; - VGA_Has_Sync_Disable : constant Boolean := CPU <= Ivybridge; + VGA_Has_Sync_Disable : constant Boolean := Up_To_Ironlake; Has_Trans_Timing_Ovrrde : constant Boolean := CPU >= Sandybridge; - Has_DPLL_SEL : constant Boolean := CPU in Ironlake .. Ivybridge; - Has_FDI_BPC : constant Boolean := CPU in Ironlake .. Ivybridge; + Has_DPLL_SEL : constant Boolean := Gen_Ironlake; + Has_FDI_BPC : constant Boolean := Gen_Ironlake; Has_FDI_Composite_Sel : constant Boolean := CPU = Ivybridge; Has_New_FDI_Sink : constant Boolean := CPU >= Sandybridge; Has_New_FDI_Source : constant Boolean := CPU >= Ivybridge; @@ -93,19 +108,19 @@ Sandybridge .. Ivybridge; Has_FDI_C : constant Boolean := CPU = Ivybridge; - Has_FDI_RX_Power_Down : constant Boolean := CPU in Haswell .. Broadwell; + Has_FDI_RX_Power_Down : constant Boolean := Gen_Haswell; - Has_GMCH_RawClk : constant Boolean := CPU = G45; + Has_GMCH_RawClk : constant Boolean := Gen_G45; ----- DDI: ------------- - End_EDP_Training_Late : constant Boolean := CPU in Haswell .. Broadwell; - Has_Per_DDI_Clock_Sel : constant Boolean := CPU in Haswell .. Broadwell; - Has_HOTPLUG_CTL : constant Boolean := CPU in Haswell .. Broadwell; + End_EDP_Training_Late : constant Boolean := Gen_Haswell; + Has_Per_DDI_Clock_Sel : constant Boolean := Gen_Haswell; + Has_HOTPLUG_CTL : constant Boolean := Gen_Haswell; Has_SHOTPLUG_CTL_A : constant Boolean := (CPU in Haswell .. Broadwell and Is_ULT) or CPU >= Skylake; - Has_DDI_PHYs : constant Boolean := CPU = Broxton; + Has_DDI_PHYs : constant Boolean := Gen_Broxton; Has_DDI_D : constant Boolean := CPU >= Haswell and not Is_ULT and @@ -113,17 +128,17 @@ Has_DDI_E : constant Boolean := -- might be disabled by x4 eDP Has_DDI_D; - Has_DDI_Buffer_Trans : constant Boolean := CPU >= Haswell and - CPU /= Broxton; - Has_Low_Voltage_Swing : constant Boolean := CPU >= Broxton; - Has_Iboost_Config : constant Boolean := CPU >= Skylake; + Has_DDI_Buffer_Trans : constant Boolean := Haswell_On and + not Gen_Broxton; + Has_Low_Voltage_Swing : constant Boolean := Broxton_On; + Has_Iboost_Config : constant Boolean := Skylake_On; Need_DP_Aux_Mutex : constant Boolean := False; -- Skylake & (PSR | GTC) ----- GMBUS: ----------- - Ungate_GMBUS_Unit_Level : constant Boolean := CPU >= Skylake; - GMBUS_Alternative_Pins : constant Boolean := CPU = Broxton; - Has_PCH_GMBUS : constant Boolean := CPU >= Ironlake; + Ungate_GMBUS_Unit_Level : constant Boolean := Skylake_On; + GMBUS_Alternative_Pins : constant Boolean := Gen_Broxton; + Has_PCH_GMBUS : constant Boolean := Ironlake_On; ----- Power: ----------- Has_IPS : constant Boolean := (CPU = Haswell and Is_ULT) or @@ -151,24 +166,15 @@ type FDI_Per_Port is array (Port_Type) of Boolean; Is_FDI_Port : constant FDI_Per_Port := - (case CPU is - when Ironlake .. Ivybridge => FDI_Per_Port' - (Internal => Internal_Is_LVDS, - others => True), - when Haswell .. Broadwell => FDI_Per_Port' - (Analog => Has_PCH_DAC, - others => False), - when others => FDI_Per_Port' - (others => False)); + (Disabled => False, + Internal => Gen_Ironlake and Internal_Is_LVDS, + DP1 .. HDMI3 => Gen_Ironlake, + Analog => Has_PCH_DAC); type FDI_Lanes_Per_Port is array (GPU_Port) of DP_Lane_Count; FDI_Lane_Count : constant FDI_Lanes_Per_Port := (DIGI_D => DP_Lane_Count_2, - others => - (if CPU in Ironlake .. Ivybridge then - DP_Lane_Count_4 - else - DP_Lane_Count_2)); + others => (if Gen_Ironlake then DP_Lane_Count_4 else DP_Lane_Count_2)); FDI_Training : constant FDI_Training_Type := (case CPU is @@ -236,8 +242,8 @@ Tertiary => 4096)); -- Maximum X position of hardware cursors - Maximum_Cursor_X : constant := (case CPU is - when G45 .. Ivybridge => 4095, + Maximum_Cursor_X : constant := (case Gen is + when G45 .. Ironlake => 4095, when Haswell .. Skylake => 8191); Maximum_Cursor_Y : constant := 4095; @@ -246,7 +252,7 @@ -- FIXME: Unknown for Broxton, Linux' i915 contains a fixme too :-D HDMI_Max_Clock_24bpp : constant Frequency_Type := - (if CPU >= Haswell then 300_000_000 else 225_000_000); + (if Haswell_On then 300_000_000 else 225_000_000); ---------------------------------------------------------------------------- diff --git a/common/hw-gfx-gma-config_helpers.adb b/common/hw-gfx-gma-config_helpers.adb index 57163a6..c95bebc 100644 --- a/common/hw-gfx-gma-config_helpers.adb +++ b/common/hw-gfx-gma-config_helpers.adb @@ -29,24 +29,23 @@ is begin return - (case Config.CPU is - when G45 => + (case Config.Gen is + when G45 => -- everything on GMCH (case Port is when Internal => LVDS, when HDMI1 | DP1 => DIGI_B, when HDMI2 | DP2 => DIGI_C, when HDMI3 | DP3 => DIGI_D, when Analog => VGA), - when Ironlake .. Ivybridge => -- everything but eDP through FDI/PCH + when Ironlake => -- everything but eDP through FDI/PCH (if Config.Internal_Is_EDP and then Port = Internal then DIGI_A else - (case Pipe is - -- FDIs are fixed to the CPU pipe + (case Pipe is -- FDIs are fixed to the CPU pipe when Primary => DIGI_B, when Secondary => DIGI_C, when Tertiary => DIGI_D)), - when Haswell .. Skylake => -- everything but VGA directly on CPU + when others => -- everything but VGA directly on CPU (case Port is when Internal => DIGI_A, -- LVDS not available when HDMI1 | DP1 => DIGI_B, diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index abd19b1..abb9ffc 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -398,13 +398,13 @@ is Audio_VID_DID : Word32; begin - case Config.CPU is + case Config.Gen is when G45 => Registers.Read (Registers.G4X_AUD_VID_DID, Audio_VID_DID); + when Ironlake => + Registers.Read (Registers.PCH_AUD_VID_DID, Audio_VID_DID); when Haswell .. Skylake => Registers.Read (Registers.AUD_VID_DID, Audio_VID_DID); - when Ironlake .. Ivybridge => - Registers.Read (Registers.PCH_AUD_VID_DID, Audio_VID_DID); end case; Success := (case Config.CPU is diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index dcb3975..db7f2bf 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -35,6 +35,8 @@ subtype GTT_Range is Natural range 0 .. 16#8_0000# - 1; GTT_Rotation_Offset : constant GTT_Range := GTT_Range'Last / 2 + 1; + type Generation is (G45, Ironlake, Haswell, Broxton, Skylake); + type CPU_Type is (G45, Ironlake, diff --git a/configs/broadwell b/configs/broadwell index a8aa58a..06a6c2a 100644 --- a/configs/broadwell +++ b/configs/broadwell @@ -1,3 +1,4 @@ +CONFIG_GFX_GMA_GENERATION = Haswell CONFIG_GFX_GMA_CPU = Broadwell CONFIG_GFX_GMA_CPU_VARIANT = Normal CONFIG_GFX_GMA_INTERNAL_PORT = DP diff --git a/configs/broadwell_ult b/configs/broadwell_ult index 3507a41..105992a 100644 --- a/configs/broadwell_ult +++ b/configs/broadwell_ult @@ -1,3 +1,4 @@ +CONFIG_GFX_GMA_GENERATION = Haswell CONFIG_GFX_GMA_CPU = Broadwell CONFIG_GFX_GMA_CPU_VARIANT = ULT CONFIG_GFX_GMA_INTERNAL_PORT = DP diff --git a/configs/broxton b/configs/broxton index b5f1f9a..35db833 100644 --- a/configs/broxton +++ b/configs/broxton @@ -1,3 +1,4 @@ +CONFIG_GFX_GMA_GENERATION = Broxton CONFIG_GFX_GMA_CPU = Broxton CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = DP diff --git a/configs/g45 b/configs/g45 index 6b54563..ef97850 100644 --- a/configs/g45 +++ b/configs/g45 @@ -1,3 +1,4 @@ +CONFIG_GFX_GMA_GENERATION = G45 CONFIG_GFX_GMA_CPU = G45 CONFIG_GFX_GMA_CPU_VARIANT = Normal CONFIG_GFX_GMA_INTERNAL_PORT = LVDS diff --git a/configs/haswell b/configs/haswell index d28168c..8c025da 100644 --- a/configs/haswell +++ b/configs/haswell @@ -1,3 +1,4 @@ +CONFIG_GFX_GMA_GENERATION = Haswell CONFIG_GFX_GMA_CPU = Haswell CONFIG_GFX_GMA_CPU_VARIANT = Normal CONFIG_GFX_GMA_INTERNAL_PORT = DP diff --git a/configs/haswell_ult b/configs/haswell_ult index 3ba633a..9559042 100644 --- a/configs/haswell_ult +++ b/configs/haswell_ult @@ -1,3 +1,4 @@ +CONFIG_GFX_GMA_GENERATION = Haswell CONFIG_GFX_GMA_CPU = Haswell CONFIG_GFX_GMA_CPU_VARIANT = ULT CONFIG_GFX_GMA_INTERNAL_PORT = DP diff --git a/configs/ironlake b/configs/ironlake index d29d71c..2c26a79 100644 --- a/configs/ironlake +++ b/configs/ironlake @@ -1,3 +1,4 @@ +CONFIG_GFX_GMA_GENERATION = Ironlake CONFIG_GFX_GMA_CPU = Ironlake CONFIG_GFX_GMA_CPU_VARIANT = Normal CONFIG_GFX_GMA_INTERNAL_PORT = LVDS diff --git a/configs/ivybridge_edp b/configs/ivybridge_edp index 257b59c..6ce8543 100644 --- a/configs/ivybridge_edp +++ b/configs/ivybridge_edp @@ -1,3 +1,4 @@ +CONFIG_GFX_GMA_GENERATION = Ironlake CONFIG_GFX_GMA_CPU = Ivybridge CONFIG_GFX_GMA_CPU_VARIANT = Normal CONFIG_GFX_GMA_INTERNAL_PORT = DP diff --git a/configs/ivybridge_lvds b/configs/ivybridge_lvds index 4327652..31813f9 100644 --- a/configs/ivybridge_lvds +++ b/configs/ivybridge_lvds @@ -1,3 +1,4 @@ +CONFIG_GFX_GMA_GENERATION = Ironlake CONFIG_GFX_GMA_CPU = Ivybridge CONFIG_GFX_GMA_CPU_VARIANT = Normal CONFIG_GFX_GMA_INTERNAL_PORT = LVDS diff --git a/configs/sandybridge b/configs/sandybridge index 2bdce64..5cc15cd 100644 --- a/configs/sandybridge +++ b/configs/sandybridge @@ -1,3 +1,4 @@ +CONFIG_GFX_GMA_GENERATION = Ironlake CONFIG_GFX_GMA_CPU = Sandybridge CONFIG_GFX_GMA_CPU_VARIANT = Normal CONFIG_GFX_GMA_INTERNAL_PORT = LVDS diff --git a/configs/skylake b/configs/skylake index 12ca514..26c9896 100644 --- a/configs/skylake +++ b/configs/skylake @@ -1,3 +1,4 @@ +CONFIG_GFX_GMA_GENERATION = Skylake CONFIG_GFX_GMA_CPU = Skylake CONFIG_GFX_GMA_CPU_VARIANT = Normal CONFIG_GFX_GMA_INTERNAL_PORT = DP diff --git a/configs/skylake_ult b/configs/skylake_ult index 94d1161..c683251 100644 --- a/configs/skylake_ult +++ b/configs/skylake_ult @@ -1,3 +1,4 @@ +CONFIG_GFX_GMA_GENERATION = Skylake CONFIG_GFX_GMA_CPU = Skylake CONFIG_GFX_GMA_CPU_VARIANT = ULT CONFIG_GFX_GMA_INTERNAL_PORT = DP -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27059 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I5061021a80cd75ee3d7996ca343e6388b22bf341 Gerrit-Change-Number: 27059 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: Documentation: Convert vboot to markdown
by Patrick Rudolph (Code Review) 08 May '19

08 May '19

Hello Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32610 to review the following change. Change subject: Documentation: Convert vboot to markdown ...................................................................... Documentation: Convert vboot to markdown Convert the HTML document to markdown and place it under security section. Change-Id: I212c6d0c977fd6772371ff6676478d48cc215d6e Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/Intel/index.html D Documentation/Intel/vboot.html M Documentation/security/index.md A Documentation/security/vboot/index.md 4 files changed, 325 insertions(+), 403 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/32610/1 diff --git a/Documentation/Intel/index.html b/Documentation/Intel/index.html index b4daa96..9d8aad0 100644 --- a/Documentation/Intel/index.html +++ b/Documentation/Intel/index.html @@ -29,7 +29,6 @@ </li> <li><a target="_blank" href="SoC/soc.html">SoC</a> support</li> <li><a target="_blank" href="Board/board.html">Board</a> support</li> - <li><a target="_blank" href="vboot.html">Verified Boot (vboot)</a> support</li> </ul> diff --git a/Documentation/Intel/vboot.html b/Documentation/Intel/vboot.html deleted file mode 100644 index ca49ac2..0000000 --- a/Documentation/Intel/vboot.html +++ /dev/null @@ -1,402 +0,0 @@ -<!DOCTYPE html> -<html> - <head> - <title>vboot - Verified Boot Support</title> - </head> - <body> - -<h1>vboot - Verified Boot Support</h1> - -<p> -Google's verified boot support consists of: -</p> -<ul> - <li>A root of trust</li> - <li>Special firmware layout</li> - <li>Firmware verification</li> - <li>Firmware measurements</li> - <li>A firmware update mechanism</li> - <li>Specific build flags</li> - <li>Signing the coreboot image</li> -</ul> - -Google's vboot verifies the firmware and places measurements -within the TPM. - -<hr> -<h2>Root of Trust</h2> -<p> -When using vboot, the root-of-trust is basically the read-only portion of the -SPI flash. The following items factor into the trust equation: -</p> -<ul> - <li>The GCC compiler must reliably translate the code into machine code - without inserting any additional code (virus, backdoor, etc.) - </li> - <li>The CPU must reliably execute the reset sequence and instructions as - documented by the CPU manufacturer. - </li> - <li>The SPI flash must provide only the code programmed into it to the CPU - without providing any alternative reset vector or code sequence. - </li> - <li>The SPI flash must honor the write-protect input and protect the - specified portion of the SPI flash from all erase and write accesses. - </li> -</ul> - -<p> -The firmware is typically protected using the write-protect pin on the SPI -flash part and setting some of the write-protect bits in the status register -during manufacturing. The protected area is platform specific and for x86 -platforms is typically 1/4th of the SPI flash -part size. Because this portion of the SPI flash is hardware write protected, -it is not possible to update this portion of the SPI flash in the field, -without altering the system to eliminate the ground connection to the SPI flash -write-protect pin. Without hardware modifications, this portion of the SPI -flash maintains the manufactured state during the system's lifetime. -</p> - -<hr> -<h2>Firmware Layout</h2> -<p> -Several sections are added to the firmware layout to support vboot: -</p> -<ul> - <li>Read-only section</li> - <li>Google Binary Blob (GBB) area</li> - <li>Read/write section A</li> - <li>Read/write section B</li> -</ul> -<p> -The following sections describe the various portions of the flash layout. -</p> - -<h3>Read-Only Section</h3> -<p> -The read-only section contains a coreboot file system (CBFS) that contains all -of the boot firmware necessary to perform recovery for the system. This -firmware is typically protected using the write-protect pin on the SPI flash -part and setting some of the write-protect bits in the status register during -manufacturing. The protected area is typically 1/4th of the SPI flash part -size and must cover the entire read-only section which consists of: -</p> -<ul> - <li>Vital Product Data (VPD) area</li> - <li>Firmware ID area</li> - <li>Google Binary Blob (GBB) area</li> - <li>coreboot file system containing read-only recovery firmware</li> -</ul> - -<h3>Google Binary Blob (GBB) Area</h3> -<p> -The GBB area is part of the read-only section. This area contains a 4096 or -8192 bit public root RSA key that is used to verify the VBLOCK area to obtain -the firmware signing key. -</p> - -<h3>Recovery Firmware</h3> -<p> -The recovery firmware is contained within a coreboot file system and consists -of: -</p> -<ul> - <li>reset vector</li> - <li>bootblock</li> - <li>verstage</li> - <li>romstage</li> - <li>postcar</li> - <li>ramstage</li> - <li>payload</li> - <li>flash map file</li> - <li>config file</li> - <li>processor specific files: - <ul> - <li>Microcode</li> - <li>fspm.bin</li> - <li>fsps.bin</li> - </ul> - </li> -</ul> - -<p> -The recovery firmware is written during manufacturing and typically contains -code to write the storage device (eMMC device or hard disk). The recovery -image is usually contained on a socketed device such as a USB flash drive or -an SD card. Depending upon the payload firmware doing the recovery, it may -be possible for the user to interact with the system to specify the recovery -image path. Part of the recovery is also to write the A and B areas of the -SPI flash device to boot the system. -</p> - - -<h3>Read/Write Section</h3> - -<p> -The read/write sections contain an area which contains the firmware signing -key and signature and an area containing a coreboot file system with a subset -of the firmware. The firmware files in FW_MAIN_A and FW_MAIN_B are: -</p> -<ul> - <li>romstage</li> - <li>postcar</li> - <li>ramstage</li> - <li>payload</li> - <li>config file</li> - <li>processor specific files: - <ul> - <li>Microcode</li> - <li>fspm.bin</li> - <li>fsps.bin</li> - </ul> - </li> -</ul> - -<p> -The firmware subset enables most issues to be fixed in the field with firmware -updates. The firmware files handle memory and most of silicon initialization. -These files also produce the tables which get passed to the operating system. -</p> - -<hr> -<h2>Firmware Updates</h2> -<p> -The read/write sections exist in one of three states: -</p> -<ul> - <li>Invalid</li> - <li>Ready to boot</li> - <li>Successfully booted</li> -</ul> - -<table border="1"> -<tr bgcolor="#ffc0c0"> -<td> -Where is this state information written? -<br/>CMOS? -<br/>RW_NVRAM? -<br/>RW_FWID_* -</td> -</tr> -</table> - -<p> -Firmware updates are handled by the operating system by writing any read/write -section that is not in the "successfully booted" state. Upon the next reboot, -vboot determines the section to boot. If it finds one in the "ready to boot" -state then it attempts to boot using that section. If the boot fails then -vboot marks the section as invalid and attempts to fall back to a read/write -section in the "successfully booted" state. If vboot is not able to find a -section in the "successfully booted" state then vboot enters recovery mode. -</p> - -<p> -Only the operating system is able to transition a section from the "ready to -boot" state to the "successfully booted" state. The transition is typically -done after the operating system has been running for a while indicating -that successful boot was possible and the operating system is stable. -</p> - -<p> -Note that as long as the SPI write protection is in place then the system is -always recoverable. If the flash update fails then the system will continue -to boot using the previous read/write area. The same is true if coreboot -passes control to the payload or the operating system and then the boot fails. -In the worst case, the SPI flash gets totally corrupted in which case vboot -fails the signature checks and enters recovery mode. There are no times where -the SPI flash is exposed and the reset vector or part of the recovery firmware -gets corrupted. -</p> - -<hr> -<h2>Build Flags</h2> -<p> -The following Kconfig values need to be selected to enable vboot: -</p> -<ul> - <li>COLLECT_TIMESTAMPS</li> - <li>VBOOT</li> -</ul> - -<p> -The starting stage needs to be specified by selecting either -VBOOT_STARTS_IN_BOOTBLOCK or VBOOT_STARTS_IN_ROMSTAGE. -</p> - -<p> -If vboot starts in bootblock then vboot may be built as a separate stage by -selecting VBOOT_SEPARATE_VERSTAGE. Additionally, if static RAM is too small -to fit both verstage and romstage then selecting VBOOT_RETURN_FROM_VERSTAGE -enables bootblock to reuse the RAM occupied by verstage for romstage. -</p> - -<p> -Non-volatile flash is needed for vboot operation. This flash area may be in -CMOS, the EC, or in a read/write area of the SPI flash device. Select one of -the following: -</p> -<ul> - <li>VBOOT_VBNV_CMOS</li> - <li>VBOOT_VBNV_EC</li> - <li>VBOOT_VBNV_FLASH</li> -</ul> -<p> -More non-volatile storage features may be found in src/vboot/Kconfig. -</p> - -<p> -A TPM is also required for vboot operation. TPMs are available in -drivers/i2c/tpm and drivers/pc80/tpm. -</p> - -<p> -In addition to adding the coreboot files into the read-only region, enabling -vboot causes the build script to add the read/write files into coreboot file -systems in FW_MAIN_A and FW_MAIN_B. -</p> - -<hr> -<h2>Signing the coreboot Image</h2> -<p> -The following command script is an example of how to sign the coreboot image file. -This script is used on the Intel Galileo board and creates the GBB area and -inserts it into the coreboot image. It also updates the VBLOCK areas with the -firmware signing key and the signature for the FW_MAIN firmware. More details -are available in 3rdparty/vboot/README. -</p> - -<pre><code>#!/bin/sh -# -# The necessary tools were built and installed using the following commands: -# -# pushd 3rdparty/vboot -# make -# sudo make install -# popd -# -# The keys were made using the following command -# -# 3rdparty/vboot/scripts/keygeneration/create_new_keys.sh \ -# --4k --4k-root --output $PWD/keys -# -# -# The "magic" numbers below are derived from the GBB section in -# src/mainboard/intel/galileo/vboot.fmd. -# -# GBB Header Size: 0x80 -# GBB Offset: 0x611000, 4KiB block number: 1553 (0x611) -# GBB Length: 0x7f000, 4KiB blocks: 127 (0x7f) -# COREBOOT Offset: 0x690000, 4KiB block number: 1680 (0x690) -# COREBOOT Length: 0x170000, 4KiB blocks: 368 (0x170) -# -# 0x7f000 (GBB Length) = 0x80 + 0x100 + 0x1000 + 0x7ce80 + 0x1000 -# -# Create the GBB area blob -# Parameters: hwid_size,rootkey_size,bmpfv_size,recoverykey_size -# -gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob - -# -# Copy from the start of the flash to the GBB region into the signed flash -# image. -# -# 1553 * 4096 = 0x611 * 0x1000 = 0x611000, size of area before GBB -# -dd conv=fdatasync ibs=4096 obs=4096 count=1553 \ - if=build/coreboot.rom of=build/coreboot.signed.rom - -# -# Append the empty GBB area to the coreboot.rom image. -# -# 1553 * 4096 = 0x611 * 0x1000 = 0x611000, offset to GBB -# -dd conv=fdatasync obs=4096 obs=4096 seek=1553 if=gbb.blob \ - of=build/coreboot.signed.rom - -# -# Append the rest of the read-only region into the signed flash image. -# -# 1680 * 4096 = 0x690 * 0x1000 = 0x690000, offset to COREBOOT area -# 368 * 4096 = 0x170 * 0x1000 = 0x170000, length of COREBOOT area -# -dd conv=fdatasync ibs=4096 obs=4096 skip=1680 seek=1680 count=368 \ - if=build/coreboot.rom of=build/coreboot.signed.rom - -# -# Insert the HWID and public root and recovery RSA keys into the GBB area. -# -gbb_utility \ - --set --hwid='Galileo' \ - -r $PWD/keys/recovery_key.vbpubk \ - -k $PWD/keys/root_key.vbpubk \ - build/coreboot.signed.rom - -# -# Sign the read/write firmware areas with the private signing key and update -# the VBLOCK_A and VBLOCK_B regions. -# -3rdparty/vboot/scripts/image_signing/sign_firmware.sh \ - build/coreboot.signed.rom \ - $PWD/keys \ - build/coreboot.signed.rom -</code></pre> - -<hr> -<h2>Boot Flow</h2> -<p> -The reset vector exist in the read-only area and points to the bootblock entry -point. The only copy of the bootblock exists in the read-only area of the SPI -flash. Verstage may be part of the bootblock or a separate stage. If separate -then the bootblock loads verstage from the read-only area and transfers control -to it. -</p> - -<p> -Upon first boot, verstage attempts to verify the read/write section A. It gets -the public root key from the GBB area and uses that to verify the VBLOCK area -in read-write section A. If the VBLOCK area is valid then it extracts the -firmware signing key (1024-8192 bits) and uses that to verify the FW_MAIN_A -area of read/write section A. If the verification is successful then verstage -instructs coreboot to use the coreboot file system in read/write section A for -the contents of the remaining boot firmware (romstage, postcar, ramstage and -the payload). -</p> - -<p> -If verification fails for the read/write area and the other read/write area is -not valid vboot falls back to the read-only area to boot into system recovery. -</p> - -<hr> -<h2>Chromebook Special Features</h2> -<p> -Google's Chromebooks have some special features: -</p> -<ul> - <li>Developer mode</li> - <li>Write-protect screw</li> -</ul> - -<h3>Developer Mode</h3> -<p> -Developer mode allows the user to use coreboot to boot another operating system. -This may be a another (beta) version of Chrome OS, or another flavor of -GNU/Linux. Use of developer mode does not void the system warranty. Upon -entry into developer mode, all locally saved data on the system is lost. -This prevents someone from entering developer mode to subvert the system -security to access files on the local system or cloud. -</p> - -<h3>Write Protect Screw</h3> -<p> -Chromebooks have a write-protect screw which provides the ground to the -write-protect pin of the SPI flash. Google specifically did this to allow -the manufacturing line and advanced developers to re-write the entire SPI flash -part. Once the screw is removed, any firmware may be placed on the device. -However, accessing this screw requires opening the case and voids the system -warranty! -</p> - -<hr> -<p>Modified: 2 May 2017</p> - </body> -</html> diff --git a/Documentation/security/index.md b/Documentation/security/index.md index 89db42e..9ad5486 100644 --- a/Documentation/security/index.md +++ b/Documentation/security/index.md @@ -4,4 +4,5 @@ ## Vendor +- [Verified Boot](vboot/index.md) - [Measured Boot](vboot/measured_boot.md) diff --git a/Documentation/security/vboot/index.md b/Documentation/security/vboot/index.md new file mode 100644 index 0000000..9742089 --- /dev/null +++ b/Documentation/security/vboot/index.md @@ -0,0 +1,324 @@ +# vboot - Verified Boot Support + +Google's verified boot support consists of: + +* A root of trust +* Special firmware layout +* Firmware verification +* Firmware measurements +* A firmware update mechanism +* Specific build flags +* Signing the coreboot image + +Google's vboot verifies the firmware and places measurements within the TPM. + +*** + +## Root of Trust + +When using vboot, the root-of-trust is basically the read-only portion of the +SPI flash. The following items factor into the trust equation: + +* The GCC compiler must reliably translate the code into machine code + without inserting any additional code (virus, backdoor, etc.) +* The CPU must reliably execute the reset sequence and instructions as + documented by the CPU manufacturer. +* The SPI flash must provide only the code programmed into it to the CPU + without providing any alternative reset vector or code sequence. +* The SPI flash must honor the write-protect input and protect the specified + portion of the SPI flash from all erase and write accesses. + +The firmware is typically protected using the write-protect pin on the SPI +flash part and setting some of the write-protect bits in the status register +during manufacturing. The protected area is platform specific and for x86 +platforms is typically 1/4th of the SPI flash part size. +Because this portion of the SPI flash is hardware write protected, it is not +possible to update this portion of the SPI flash in the field, without altering +the system to eliminate the ground connection to the SPI flash write-protect pin. +Without hardware modifications, this portion of the SPI flash maintains the +manufactured state during the system's lifetime. + +*** + +## Firmware Layout + +Several sections are added to the firmware layout to support vboot: + +* Read-only section +* Google Binary Blob (GBB) area +* Read/write section A +* Read/write section B + +The following sections describe the various portions of the flash layout. + +### Read-Only Section + +The read-only section contains a coreboot file system (CBFS) that contains all +of the boot firmware necessary to perform recovery for the system. This firmware +is typically protected using the write-protect pin on the SPI flash part and +setting some of the write-protect bits in the status register during +manufacturing. +The protected area is typically 1/4th of the SPI flash part size and must cover +the entire read-only section which consists of: + +* Vital Product Data (VPD) area +* Firmware ID area +* Google Binary Blob (GBB) area +* coreboot file system containing read-only recovery firmware + +### Google Binary Blob (GBB) Area + +The GBB area is part of the read-only section. This area contains a 4096 or 8192 +bit public root RSA key that is used to verify the *VBLOCK* area to obtain the +firmware signing key. + +### Recovery Firmware + +The recovery firmware is contained within a coreboot file system and consists of: + +* reset vector +* bootblock +* verstage +* romstage +* postcar +* ramstage +* payload +* flash map file +* config file +* processor specific files: + * Microcode + * fspm.bin + * fsps.bin + +The recovery firmware is written during manufacturing and typically contains +code to write the storage device (eMMC device or hard disk). The recovery image +is usually contained on a socketed device such as a USB flash drive or an +SD card. Depending upon the payload firmware doing the recovery, it may be +possible for the user to interact with the system to specify the recovery +image path. Part of the recovery is also to write the A and B areas of the SPI +flash device to boot the system. + +### Read/Write Section + +The read/write sections contain an area which contains the firmware signing +key and signature and an area containing a coreboot file system with a subset +of the firmware. The firmware files in *FW_MAIN_A* and *FW_MAIN_B* are: + +* romstage +* postcar +* ramstage +* payload +* config file +* processor specific files: + * Microcode + * fspm.bin + * fsps.bin + +The firmware subset enables most issues to be fixed in the field with firmware +updates. The firmware files handle memory and most of silicon initialization. +These files also produce the tables which get passed to the operating system. + +*** + +## Firmware Updates + +The read/write sections exist in one of three states: + +* Invalid +* Ready to boot +* Successfully booted + + +Firmware updates are handled by the operating system by writing any read/write +section that is not in the "successfully booted" state. Upon the next reboot, +vboot determines the section to boot. If it finds one in the "ready to boot" +state then it attempts to boot using that section. If the boot fails then +vboot marks the section as invalid and attempts to fall back to a read/write +section in the "successfully booted" state. If vboot is not able to find a +section in the "successfully booted" state then vboot enters recovery mode. + +Only the operating system is able to transition a section from the +"ready to boot" state to the "successfully booted" state. +The transition is typically done after the operating system has been running +for a while indicating that successful boot was possible and the operating +system is stable. + +Note that as long as the SPI write protection is in place then the system +is always recoverable. If the flash update fails then the system will continue +to boot using the previous read/write area. The same is true if coreboot passes +control to the payload or the operating system and then the boot fails. In the +worst case, the SPI flash gets totally corrupted in which case vboot fails the +signature checks and enters recovery mode. There are no times where the SPI +flash is exposed and the reset vector or part of the recovery firmware gets +corrupted. + +*** + +## Build Flags + +The following *Kconfig* values need to be selected to enable vboot: + +* COLLECT_TIMESTAMPS +* VBOOT + +The starting stage needs to be specified by selecting either +VBOOT_STARTS_IN_BOOTBLOCK or VBOOT_STARTS_IN_ROMSTAGE. + +If vboot starts in bootblock then vboot may be built as a separate stage by +selecting `VBOOT_SEPARATE_VERSTAGE`. Additionally, if static RAM is too small +to fit both verstage and romstage then selecting `VBOOT_RETURN_FROM_VERSTAGE` +enables bootblock to reuse the RAM occupied by verstage for romstage. + +Non-volatile flash is needed for vboot operation. This flash area may be in +CMOS, the EC, or in a read/write area of the SPI flash device. +Select one of the following: + +* `VBOOT_VBNV_CMOS` +* `VBOOT_VBNV_EC` +* `VBOOT_VBNV_FLASH` + +More non-volatile storage features may be found in `security/vboot/Kconfig`. + +A TPM is also required for vboot operation. +TPMs are available in `drivers/i2c/tpm` and `drivers/pc80/tpm`. + +In addition to adding the coreboot files into the read-only region, +enabling vboot causes the build script to add the read/write files into +coreboot file systems in *FW_MAIN_A* and *FW_MAIN_B*. + +*** + +## Signing the coreboot Image + +The following command script is an example of how to sign the coreboot image +file. This script is used on the Intel Galileo board and creates the *GBB* area +and inserts it into the coreboot image. It also updates the *VBLOCK* areas with +the firmware signing key and the signature for the *FW_MAIN* firmware. +More details are available in `3rdparty/vboot/README`. + +```bash +#!/bin/sh +# +# The necessary tools were built and installed using the following commands: +# +# pushd 3rdparty/vboot +# make +# sudo make install +# popd +# +# The keys were made using the following command +# +# 3rdparty/vboot/scripts/keygeneration/create_new_keys.sh \ +# --4k --4k-root --output $PWD/keys +# +# +# The "magic" numbers below are derived from the GBB section in +# src/mainboard/intel/galileo/vboot.fmd. +# +# GBB Header Size: 0x80 +# GBB Offset: 0x611000, 4KiB block number: 1553 (0x611) +# GBB Length: 0x7f000, 4KiB blocks: 127 (0x7f) +# COREBOOT Offset: 0x690000, 4KiB block number: 1680 (0x690) +# COREBOOT Length: 0x170000, 4KiB blocks: 368 (0x170) +# +# 0x7f000 (GBB Length) = 0x80 + 0x100 + 0x1000 + 0x7ce80 + 0x1000 +# +# Create the GBB area blob +# Parameters: hwid_size,rootkey_size,bmpfv_size,recoverykey_size +# +gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob + +# +# Copy from the start of the flash to the GBB region into the signed flash +# image. +# +# 1553 * 4096 = 0x611 * 0x1000 = 0x611000, size of area before GBB +# +dd conv=fdatasync ibs=4096 obs=4096 count=1553 \ +if=build/coreboot.rom of=build/coreboot.signed.rom + +# +# Append the empty GBB area to the coreboot.rom image. +# +# 1553 * 4096 = 0x611 * 0x1000 = 0x611000, offset to GBB +# +dd conv=fdatasync obs=4096 obs=4096 seek=1553 if=gbb.blob \ +of=build/coreboot.signed.rom + +# +# Append the rest of the read-only region into the signed flash image. +# +# 1680 * 4096 = 0x690 * 0x1000 = 0x690000, offset to COREBOOT area +# 368 * 4096 = 0x170 * 0x1000 = 0x170000, length of COREBOOT area +# +dd conv=fdatasync ibs=4096 obs=4096 skip=1680 seek=1680 count=368 \ +if=build/coreboot.rom of=build/coreboot.signed.rom + +# +# Insert the HWID and public root and recovery RSA keys into the GBB area. +# +gbb_utility \ +--set --hwid='Galileo' \ +-r $PWD/keys/recovery_key.vbpubk \ +-k $PWD/keys/root_key.vbpubk \ +build/coreboot.signed.rom + +# +# Sign the read/write firmware areas with the private signing key and update +# the VBLOCK_A and VBLOCK_B regions. +# +3rdparty/vboot/scripts/image_signing/sign_firmware.sh \ +build/coreboot.signed.rom \ +$PWD/keys \ + build/coreboot.signed.rom +``` + +*** + +## Boot Flow + +The reset vector exist in the read-only area and points to the bootblock +entry point. The only copy of the bootblock exists in the read-only area +of the SPI flash. Verstage may be part of the bootblock or a separate stage. +If separate then the bootblock loads verstage from the read-only area and +transfers control to it. + +Upon first boot, verstage attempts to verify the read/write section A. +It gets the public root key from the GBB area and uses that to verify the +*VBLOCK* area in read-write section A. If the *VBLOCK* area is valid then it +extracts the firmware signing key (1024-8192 bits) and uses that to verify +the *FW_MAIN_A* area of read/write section A. If the verification is successful +then verstage instructs coreboot to use the coreboot file system in read/write +section A for the contents of the remaining boot firmware (romstage, postcar, +ramstage and the payload). + +If verification fails for the read/write area and the other read/write area is +not valid vboot falls back to the read-only area to boot into system recovery. + +*** + +## Chromebook Special Features + +Google's Chromebooks have some special features: + +* Developer mode +* Write-protect screw + +### Developer Mode + +Developer mode allows the user to use coreboot to boot another operating system. +This may be a another (beta) version of Chrome OS, or another flavor of +GNU/Linux. Use of developer mode does not void the system warranty. Upon entry +into developer mode, all locally saved data on the system is lost. +This prevents someone from entering developer mode to subvert the system +security to access files on the local system or cloud. + +### Write Protect Screw + +Chromebooks have a write-protect screw which provides the ground to the +write-protect pin of the SPI flash. +Google specifically did this to allow the manufacturing line and advanced +developers to re-write the entire SPI flash part. Once the screw is removed, +any firmware may be placed on the device. +However, accessing this screw requires opening the case and voids the +system warranty! -- To view, visit https://review.coreboot.org/c/coreboot/+/32610 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I212c6d0c977fd6772371ff6676478d48cc215d6e Gerrit-Change-Number: 32610 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: ec/lenovo/h8: Add VBOOT board support
by Patrick Rudolph (Code Review) 08 May '19

08 May '19

Hello Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32607 to review the following change. Change subject: ec/lenovo/h8: Add VBOOT board support ...................................................................... ec/lenovo/h8: Add VBOOT board support Use Fn-Key as recovery mode switch. Tested using Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6. Change-Id: I2c682431b3f09839db265259205104bd9ef4abfc Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/ec/lenovo/h8/Kconfig M src/ec/lenovo/h8/Makefile.inc A src/ec/lenovo/h8/vboot.c 3 files changed, 66 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32607/1 diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig index b109831..d874975 100644 --- a/src/ec/lenovo/h8/Kconfig +++ b/src/ec/lenovo/h8/Kconfig @@ -32,6 +32,14 @@ bool default n +config H8_FN_KEY_AS_VBOOT_RECOVERY_SW + bool "Enable Fn-Key as VBOOT recovery switch" + depends on VBOOT + default n + help + If VBOOT is enabled, press Fn-Key at power on to force a recovery mode + boot instead of regular FW_MAIN_x boot. + endif config H8_DOCK_EARLY_INIT diff --git a/src/ec/lenovo/h8/Makefile.inc b/src/ec/lenovo/h8/Makefile.inc index bccdd91..fbe2171 100644 --- a/src/ec/lenovo/h8/Makefile.inc +++ b/src/ec/lenovo/h8/Makefile.inc @@ -7,6 +7,12 @@ postcar-y += sense.c smm-y += sense.c +ramstage-$(CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW) += vboot.c +verstage-$(CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW) += vboot.c +romstage-$(CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW) += vboot.c +bootblock-$(CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW) += vboot.c +postcar-$(CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW) += vboot.c + ifneq ($(filter y,$(CONFIG_H8_BEEP_ON_DEATH) $(CONFIG_H8_FLASH_LEDS_ON_DEATH)),) romstage-y += panic.c ramstage-y += panic.c diff --git a/src/ec/lenovo/h8/vboot.c b/src/ec/lenovo/h8/vboot.c new file mode 100644 index 0000000..d7723e9 --- /dev/null +++ b/src/ec/lenovo/h8/vboot.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/acpi/ec.h> +#include <bootmode.h> +#include <timer.h> +#include <delay.h> + +#include "h8.h" + +/** + * HACK: Use Fn-Key as recovery mode switch. + * Wait for sense register ready and read Fn-Key state. + */ +int get_recovery_mode_switch(void) +{ + struct stopwatch sw; + + /* Tested on Lenovo T500: + * - 700msec from AC power on + * - less than 150msec on Lenovo T520 from AC power on + */ + stopwatch_init_msecs_expire(&sw, 1000); + while (!stopwatch_expired(&sw) && !h8_get_sense_ready()) + mdelay(1); + + if (!h8_get_sense_ready()) + return 0; + + return h8_get_fn_key(); +} + +/** + * Only used if CONFIG_CHROMEOS is set. + * Always zero as there's no HW write protection. + */ +int get_write_protect_state(void) +{ + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32607 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c682431b3f09839db265259205104bd9ef4abfc Gerrit-Change-Number: 32607 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: ec/lenovo/h8: Add function to query sense state
by Patrick Georgi (Code Review) 08 May '19

08 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29204 ) Change subject: ec/lenovo/h8: Add function to query sense state ...................................................................... ec/lenovo/h8: Add function to query sense state * Add function to wait for sense registers to become valid. * Add function to retrieve Fn-Key state. Tested on Lenovo T500: * It takes about 700msec for the registers to become valid. Tested on Lenovo T520: * It takes less than 150msec for the registers to become valid. Change-Id: Ie27e2881a256c4efb3def11f05070c446db6e5fc Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29204 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/ec/lenovo/h8/Makefile.inc M src/ec/lenovo/h8/h8.h A src/ec/lenovo/h8/sense.c 3 files changed, 66 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Philipp Deppenwiese: Looks good to me, but someone else must approve diff --git a/src/ec/lenovo/h8/Makefile.inc b/src/ec/lenovo/h8/Makefile.inc index ebf6d7d..bccdd91 100644 --- a/src/ec/lenovo/h8/Makefile.inc +++ b/src/ec/lenovo/h8/Makefile.inc @@ -1,5 +1,12 @@ ifeq ($(CONFIG_EC_LENOVO_H8),y) +ramstage-y += sense.c +verstage-y += sense.c +romstage-y += sense.c +bootblock-y += sense.c +postcar-y += sense.c +smm-y += sense.c + ifneq ($(filter y,$(CONFIG_H8_BEEP_ON_DEATH) $(CONFIG_H8_FLASH_LEDS_ON_DEATH)),) romstage-y += panic.c ramstage-y += panic.c diff --git a/src/ec/lenovo/h8/h8.h b/src/ec/lenovo/h8/h8.h index a46ba1f..14948c5 100644 --- a/src/ec/lenovo/h8/h8.h +++ b/src/ec/lenovo/h8/h8.h @@ -38,6 +38,9 @@ void h8_mainboard_init_dock (void); +int h8_get_fn_key(void); +int h8_get_sense_ready(void); + void h8_bluetooth_enable(int on); bool h8_bluetooth_nv_enable(void); bool h8_has_bdc(struct device *dev); @@ -135,8 +138,10 @@ #define H8_EVENT_FN_PRESS 0x39 #define H8_STATUS0 0x46 +#define H8_STATUS0_FN_KEY_DOWN 0x01 #define H8_STATUS1 0x47 #define H8_STATUS2 0x48 +#define H8_STATUS3 0x49 #define H8_EVENT_BAT0 0x4a #define H8_EVENT_BAT0_STATE 0x4b diff --git a/src/ec/lenovo/h8/sense.c b/src/ec/lenovo/h8/sense.c new file mode 100644 index 0000000..b929d7e --- /dev/null +++ b/src/ec/lenovo/h8/sense.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/acpi/ec.h> + +#include "h8.h" + +/** + * Return the EC sense status register state. + * + * Observations showed the sense registers are all zero until the EC populates + * them after some time. Likely the EC sets all bits to it's valid state at + * once, but there's no prove as the firmware isn't available. + * + * Wait for any register having at least one bit set. + * Unlikely that all register will be zero after booting has finished. + * + * @return 1 if the EC provides valid data in sense status registers + */ +int h8_get_sense_ready(void) +{ + static const u8 regs[] = { H8_STATUS0, H8_STATUS1, H8_STATUS2, + H8_STATUS3}; + + for (size_t i = 0; i < ARRAY_SIZE(regs); i++) { + if (ec_read(regs[i])) + return 1; + } + + return 0; +} + +/** + * Return the state of Fn key. + * Only valid if h8_get_sense_ready (see above) returns true. + * + * @return 1 if the key is pressed. + */ +int h8_get_fn_key(void) +{ + return ec_read(H8_STATUS0) & H8_STATUS0_FN_KEY_DOWN; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/29204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie27e2881a256c4efb3def11f05070c446db6e5fc Gerrit-Change-Number: 29204 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit May 2019