coreboot-gerrit May 2019

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Change in ...coreboot[master]: google/kukui: Add panel config data for display
by jitao shi (Code Review) 08 May '19

08 May '19

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31590 Change subject: google/kukui: Add panel config data for display ...................................................................... google/kukui: Add panel config data for display BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Ife4a724ff1ddc36b29f37690a22c1b344e0629f7 Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- M src/mainboard/google/kukui/mainboard.c 1 file changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/31590/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 950dca4..bf9bd02 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -15,9 +15,12 @@ #include <bootmode.h> #include <console/console.h> +#include <delay.h> #include <device/device.h> #include <edid.h> +#include <gpio.h> #include <soc/ddp.h> +#include <soc/dsi.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> #include <soc/mtcmos.h> @@ -42,13 +45,66 @@ setup_usb_host(); } +/* Setup backlight control pins as output pin and power-off by default */ +static void configure_backlight(void) +{ + /* Configure PANEL_LCD_POWER_EN */ + gpio_output(GPIO(PERIPHERAL_EN13), 1); + gpio_output(GPIO(DISP_PWM), 1); /* DISP_PWM0 */ +} + +static void configure_display(void) +{ + /* board from p0 */ + gpio_output(GPIO(LCM_RST), 0); + udelay(100); + gpio_output(GPIO(LCM_RST), 1); + mdelay(20); +} + +static const struct edid kukui_innolux_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "768x1024@60Hz", + .pixel_clock = 56900, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 768, .hbl = 120, .hso = 40, .hspw = 40, .hborder = 0, + .va = 1024, .vbl = 44, .vso = 20, .vspw = 4, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 120, .y_mm = 160, + }, +}; + +struct lcm_init_table lcm_init_cmd[] = { + {INIT_CMD, 1, {MIPI_DCS_EXIT_SLEEP_MODE}}, + {DELAY_CMD, 120, {}}, + {INIT_CMD, 1, {MIPI_DCS_SET_DISPLAY_ON}}, + {DELAY_CMD, 120, {}}, +}; + + static void display_startup(void) { + int ret = 0; + u32 mipi_dsi_flags; struct edid edid; + edid = kukui_innolux_edid; + mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM; + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); mtk_ddp_init(); + ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, + false, &edid, lcm_init_cmd, sizeof(lcm_init_cmd) / sizeof(struct lcm_init_table)); + if (ret < 0) { + printk(BIOS_ERR, "dsi init fail\n"); + return; + } mtk_ddp_mode_set(&edid); @@ -62,6 +118,8 @@ mtcmos_display_power_on(); mtcmos_protect_display_bus(); + configure_backlight(); + configure_display(); display_startup(); } else { printk(BIOS_INFO, "Skipping display init.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/31590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife4a724ff1ddc36b29f37690a22c1b344e0629f7 Gerrit-Change-Number: 31590 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sdm845: Port I2C driver
by Akash Asthana (Code Review) 08 May '19

08 May '19

Akash Asthana has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29104 ) Change subject: sdm845: Port I2C driver ...................................................................... Patch Set 32: (1 comment) https://review.coreboot.org/#/c/29104/24/src/mainboard/google/cheza/mainboa… File src/mainboard/google/cheza/mainboard.c: https://review.coreboot.org/#/c/29104/24/src/mainboard/google/cheza/mainboa… PS24, Line 42: i2c_init(12, 400 * KHz, 1); > Sure!, in discussion with clock team for this comment. According to our discussion, qup enum should be defined in clock driver and qup drivers should include clock header in order to access those enums because: 1)As clock driver is the provider and the serial engine clocks are laid out by clock HW for the consumers. It is up to the consumers to use the corresponding serial engine instances as per their requirement 2) In case of the new board as well we will not be having the qup header file in the initial phase of code so it will be problematic to generate and add support in clock code. -- To view, visit https://review.coreboot.org/c/coreboot/+/29104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb76564d8a11427423dd14d8ba7c8c7d500ef346 Gerrit-Change-Number: 29104 Gerrit-PatchSet: 32 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 08 May 2019 09:45:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: WIP: mediaek/mt8183: add panel driver for kukui p2
by jitao shi (Code Review) 08 May '19

08 May '19

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32097 Change subject: WIP: mediaek/mt8183: add panel driver for kukui p2 ...................................................................... WIP: mediaek/mt8183: add panel driver for kukui p2 BUG=b:80501386,b:117254947 BRANCH=none TEST=build pass Change-Id: I878c9e0454acdbc0cd2cd310b8519efb845bb6ee Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> --- M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/dsi.c 2 files changed, 222 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/32097/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index bf9bd02..541485a 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <boardid.h> #include <bootmode.h> #include <console/console.h> #include <delay.h> @@ -55,11 +56,72 @@ static void configure_display(void) { - /* board from p0 */ - gpio_output(GPIO(LCM_RST), 0); - udelay(100); - gpio_output(GPIO(LCM_RST), 1); - mdelay(20); + + printk(BIOS_ERR, "board_id() = %d\n", board_id()); + + if (board_id() < 2) { + /* board from p1 */ + gpio_output(GPIO(LCM_RST), 0); + udelay(100); + gpio_output(GPIO(LCM_RST), 1); + mdelay(20); + } else { + /* board from p2 */ + printk(BIOS_ERR, "board from p2\n"); + + gpio_output(GPIO(LCM_RST), 0); + gpio_output(GPIO(BPI_BUS3), 0); + gpio_output(GPIO(MISC_BSI_CK_3), 0); + gpio_output(GPIO(PERIPHERAL_EN9), 0); + gpio_output(GPIO(SIM2_SRST), 0); + gpio_output(GPIO(SIM2_SIO), 0); + gpio_output(GPIO(BPI_OLAT1), 0); + gpio_output(GPIO(SIM2_SCLK), 0); + gpio_set_pull(GPIO(LCM_RST), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(BPI_BUS3), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(MISC_BSI_CK_3), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(PERIPHERAL_EN9), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(SIM2_SRST), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(SIM2_SIO), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(BPI_OLAT1), GPIO_PULL_ENABLE, GPIO_PULL_UP); + gpio_set_pull(GPIO(SIM2_SCLK), GPIO_PULL_ENABLE, GPIO_PULL_UP); + + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + + gpio_output(GPIO(MISC_BSI_CK_3), 1); + gpio_output(GPIO(PERIPHERAL_EN9), 1); + gpio_output(GPIO(SIM2_SRST), 1); + gpio_output(GPIO(SIM2_SIO), 1); + gpio_output(GPIO(BPI_OLAT1), 1); + gpio_output(GPIO(SIM2_SCLK), 1); + + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + gpio_output(GPIO(LCM_RST), 1); + mdelay(20); + gpio_output(GPIO(BPI_BUS3), 1); + mdelay(20); + mdelay(20); + + printk(BIOS_ERR, "aaadump_gpio_reg : reg[ox350] = 0x%x\n", read32((void *)GPIO_BASE + 0x350)); + printk(BIOS_ERR, "aaadump_gpio_reg : reg[ox10] = 0x%x\n", read32((void *)GPIO_BASE + 0x10)); + printk(BIOS_ERR, "aaadump_gpio_reg : reg[ox110] = 0x%x\n", read32((void *)GPIO_BASE + 0x110)); + + printk(BIOS_ERR, "aaadump_gpio_reg : reg[ox390] = 0x%x\n", read32((void *)GPIO_BASE + 0x390)); + printk(BIOS_ERR, "aaadump_gpio_reg : reg[ox20] = 0x%x\n", read32((void *)GPIO_BASE + 0x20)); + printk(BIOS_ERR, "aaadump_gpio_reg : reg[ox120] = 0x%x\n", read32((void *)GPIO_BASE + 0x120)); + } } static const struct edid kukui_innolux_edid = { @@ -84,6 +146,76 @@ {DELAY_CMD, 120, {}}, }; +static const struct edid kukui_p097pfg_ssd2858_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1536x2048@60Hz", + .pixel_clock = 229000, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1536, .hbl = 160, .hso = 80, .hspw = 26, .hborder = 0, + .va = 2048, .vbl = 32, .vso = 20, .vspw = 2, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 147, .y_mm = 196, + }, +}; + +struct lcm_init_table lcm_p097pfg_ssd2858_init_cmd[] = { + /* SSD2858 config */ + {INIT_CMD, 2, {0xff, 0x00}}, + /* LOCKCNT=0x1f4, MRX=0, POSTDIV=1 (/2}}, MULT=0x49 + * 27 Mhz => 985.5 Mhz */ + {INIT_CMD, 6, {0x00, 0x08, 0x01, 0xf4, 0x01, 0x49}}, + /* MTXDIV=1, SYSDIV=3 (=> 4) */ + {INIT_CMD, 6, {0x00, 0x0c, 0x00, 0x00, 0x00, 0x03}}, + /* MTXVPF=24bpp, MRXLS=4 lanes, MRXVB=bypass, MRXECC=1, MRXEOT=1 + * MRXEE=1 */ + {INIT_CMD, 6, {0x00, 0x14, 0x0c, 0x3d, 0x80, 0x0f}}, + {INIT_CMD, 6, {0x00, 0x20, 0x15, 0x92, 0x56, 0x7d}}, + {INIT_CMD, 6, {0x00, 0x24, 0x00, 0x00, 0x30, 0x00}}, + +// {INIT_CMD, 1, {0x11}}, +// {DELAY_CMD, 120, {}}, + + {INIT_CMD, 6, {0x10, 0x08, 0x01, 0x20, 0x04, 0x45}}, + {INIT_CMD, 6, {0x10, 0x1c, 0x00, 0x00, 0x00, 0x00}}, + {INIT_CMD, 6, {0x20, 0x0c, 0x00, 0x00, 0x00, 0x04}}, + /* Pixel clock 985.5 Mhz * 0x49/0x4b = 959 Mhz */ + {INIT_CMD, 6, {0x20, 0x10, 0x00, 0x4b, 0x00, 0x49}}, + {INIT_CMD, 6, {0x20, 0xa0, 0x00, 0x00, 0x00, 0x00}}, + /* EOT=1, LPE = 0, LSOUT=4 lanes, LPD=25 */ + {INIT_CMD, 6, {0x60, 0x08, 0x00, 0xd9, 0x00, 0x08}}, + {INIT_CMD, 6, {0x60, 0x14, 0x01, 0x00, 0x01, 0x06}}, + /* DSI0 enable (default: probably not needed) */ + {INIT_CMD, 6, {0x60, 0x80, 0x00, 0x00, 0x00, 0x0f}}, + /* DSI1 enable */ + {INIT_CMD, 6, {0x60, 0xa0, 0x00, 0x00, 0x00, 0x0f}}, + + /* HSA=0x18, VSA=0x02, HBP=0x50, VBP=0x0c */ + {INIT_CMD, 6, {0x60, 0x0c, 0x0c, 0x50, 0x02, 0x18}}, + /* VACT= 0x800 (2048}}, VFP= 0x14, HFP=0x50 */ + {INIT_CMD, 6, {0x60, 0x10, 0x08, 0x00, 0x14, 0x50}}, + /* HACT=0x300 (768) */ + {INIT_CMD, 6, {0x60, 0x84, 0x00, 0x00, 0x03, 0x00}}, + {INIT_CMD, 6, {0x60, 0xa4, 0x00, 0x00, 0x03, 0x00}}, + + /* Take panel out of sleep. */ + {INIT_CMD, 2, {0xff, 0x01}}, + {INIT_CMD, 1, {0x11}}, + {DELAY_CMD, 120, {}}, + {INIT_CMD, 1, {0x29}}, + {DELAY_CMD, 20, {}}, + {INIT_CMD, 2, {0xff, 0x00}}, + + //{INIT_CMD, 6, {0x60, 0x14, 0x41, 0x00, 0x81, 0x02}}, + //{INIT_CMD, 6, {0x60, 0x14, 0xc1, 0x00, 0x81, 0x0A}}, + {DELAY_CMD, 120, {}}, + {INIT_CMD, 1, {0x11}}, + {DELAY_CMD, 120, {}}, + {INIT_CMD, 1, {0x29}}, + {DELAY_CMD, 20, {}}, +}; static void display_startup(void) { @@ -91,16 +223,30 @@ u32 mipi_dsi_flags; struct edid edid; - edid = kukui_innolux_edid; - mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | - MIPI_DSI_MODE_VIDEO_SYNC_PULSE | - MIPI_DSI_MODE_LPM; + if (board_id() < 2) { + edid = kukui_innolux_edid; + mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM; + } else { + edid = kukui_p097pfg_ssd2858_edid; + mipi_dsi_flags = MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM; + } edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); mtk_ddp_init(); - ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, - false, &edid, lcm_init_cmd, sizeof(lcm_init_cmd) / sizeof(struct lcm_init_table)); + if (board_id() < 2) + ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, + false, &edid, lcm_init_cmd, sizeof(lcm_init_cmd) / sizeof(struct lcm_init_table)); + else { + ret = mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, + false, &edid, lcm_p097pfg_ssd2858_init_cmd, sizeof(lcm_p097pfg_ssd2858_init_cmd) / sizeof(struct lcm_init_table)); + printk(BIOS_ERR, "mtk_dsi_init from p2\n"); + } + if (ret < 0) { printk(BIOS_ERR, "dsi init fail\n"); return; diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c index f96d847..316d92d 100644 --- a/src/soc/mediatek/mt8183/dsi.c +++ b/src/soc/mediatek/mt8183/dsi.c @@ -14,6 +14,7 @@ */ #include <arch/io.h> +#include <boardid.h> #include <console/console.h> #include <delay.h> #include <soc/addressmap.h> @@ -97,6 +98,11 @@ printk(BIOS_ERR, "data_rate: %u bps\n", data_rate); + if (board_id() == 2) + data_rate = 1420000000; + + printk(BIOS_ERR, "board_id() == 2 data_rate: %u bps\n", data_rate); + if (data_rate >= 2000000000) { txdiv = 1; txdiv0 = 0; @@ -169,26 +175,28 @@ timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 | phy_timing->clk_hs_exit << 16; - dsi_write32(&dsi->dsi_phy_timecon0, timcon0); - dsi_write32(&dsi->dsi_phy_timecon1, timcon1); - dsi_write32(&dsi->dsi_phy_timecon2, timcon2); - dsi_write32(&dsi->dsi_phy_timecon3, timcon3); + if (board_id() < 2) { + dsi_write32(&dsi->dsi_phy_timecon0, timcon0); + dsi_write32(&dsi->dsi_phy_timecon1, timcon1); + dsi_write32(&dsi->dsi_phy_timecon2, timcon2); + dsi_write32(&dsi->dsi_phy_timecon3, timcon3); + } else { + dsi_write32(&dsi->dsi_phy_timecon0, 0x0e1c070d); + dsi_write32(&dsi->dsi_phy_timecon1, 0x1a411334); + dsi_write32(&dsi->dsi_phy_timecon2, 0x11420100); + dsi_write32(&dsi->dsi_phy_timecon3, 0x001a180a); + } } static void mtk_dsi_reset(void) { - dsi_setbits_le32(&dsi->dsi_con_ctrl, 3); - dsi_clrbits_le32(&dsi->dsi_con_ctrl, 1); + dsi_write32(&dsi->dsi_con_ctrl, 1); + dsi_write32(&dsi->dsi_con_ctrl, 0); } static void mtk_dsi_clk_hs_mode_enable(void) { - dsi_setbits_le32(&dsi->dsi_phy_lccon, LC_HS_TX_EN); -} - -static void mtk_dsi_clk_hs_mode_disable(void) -{ - dsi_clrbits_le32(&dsi->dsi_phy_lccon, LC_HS_TX_EN); + dsi_setbits_le32(&dsi->dsi_phy_lccon, 1); } static void mtk_dsi_set_mode(u32 mode_flags) @@ -312,7 +320,7 @@ edid->mode.hborder) * bpp - 10; else hbp_byte = (edid->mode.hbl - edid->mode.hso - - edid->mode.hborder) * bpp - 10; + edid->mode.hborder) * bpp - 8; hsync_active_byte = edid->mode.hspw * bpp - 10; hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp - 12; @@ -348,8 +356,8 @@ static void mtk_dsi_start(void) { - dsi_write32(&dsi->dsi_start, 0); - dsi_write32(&dsi->dsi_start, 1); + dsi_clrbits_le32(&dsi->dsi_start, 1); + dsi_setbits_le32(&dsi->dsi_start, 1); } static void mtk_dsi_cmdq(u8 *data, u8 len) @@ -359,6 +367,15 @@ u8 cmdq_size; u32 reg_val, cmdq_mask, i, config, cmdq_off, type, intsta_0; + + while(read32(&dsi->dsi_intsta) & (1 << 31)) { + printk(BIOS_ERR, "mtk_dsi_cmdq wait dsi no busy\n"); + mdelay(20); + } + + printk(BIOS_ERR, "mtk_dsi_cmdq dsi no busy\n"); + dsi_write32(&dsi->dsi_intsta, 0); + switch (len) { case 0: return; @@ -393,14 +410,17 @@ reg_val = (type << 8) | config; } - for (i = 0; i < len; i++) - dsi_clrsetbits_le32(&dsi->dsi_cmdq0 + ((cmdq_off + i) & (~0x3)), + for (i = 0; i < 0x20; i = i + 4) + dsi_write32((void *)DSI_BASE + 0x200 + i, 0); + + for (i = 0; i < len; i++) { + dsi_clrsetbits_le32((void *)DSI_BASE + 0x200 + ((cmdq_off + i) & (0xfffffffc)), (0xff << (((i + cmdq_off) & 3) * 8)), tx_buf[i] << (((i + cmdq_off) & 3) * 8)); + } dsi_clrsetbits_le32(&dsi->dsi_cmdq0, cmdq_mask, reg_val); dsi_clrsetbits_le32(&dsi->dsi_cmdq_size, CMDQ_SIZE, cmdq_size); - dsi_write32(&dsi->dsi_intsta, 0); mtk_dsi_start(); stopwatch_init_usecs_expire(&sw, 400); @@ -414,7 +434,12 @@ if (!(intsta_0 & CMD_DONE_INT_FLAG)) printk(BIOS_ERR, "dsi DONE INT Timeout\n"); - dsi_write32(&dsi->dsi_start, 0); + for (i = 0x200; i < 0x210; i = i + 4) + printk(BIOS_ERR, "dump_dsi_reg : reg[0x%x] = 0x%x\n", i, read32((void *)DSI_BASE + i)); + + printk(BIOS_ERR, "xxxdump_dsi_reg : reg[0x60] = 0x%x\n", read32((void *)DSI_BASE + 0x60)); + printk(BIOS_ERR, "xxxdump_dsi_reg : reg[0x00] = 0x%x\n", read32((void *)DSI_BASE)); + printk(BIOS_ERR, "xxxdump_dsi_reg : reg[0x14] = 0x%x\n", read32((void *)DSI_BASE + 0x14)); } static void push_table(struct lcm_init_table *init_cmd, u32 count) @@ -426,7 +451,17 @@ switch (cmd) { case DELAY_CMD: - mdelay(init_cmd[i].cmd); + if (init_cmd[i].cmd > 20) { + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + mdelay(20); + } else { + mdelay(20); + } + printk(BIOS_ERR, "delay : init_cmd[%d].len = 0x%x\n", i, init_cmd[i].len); break; case END_OF_TABLE: @@ -434,6 +469,7 @@ case INIT_CMD: default: + printk(BIOS_ERR, "init_cmd : init_cmd[%d].data[0] = 0x%x\n", i, init_cmd[i].data[0]); mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len); break; } @@ -443,7 +479,7 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual, const struct edid *edid, struct lcm_init_table *init_cmd, u32 count) { - int data_rate; + int data_rate, i; struct mtk_phy_timing phy_timing; mtk_dsi_phy_timing_calc(format, lanes, edid, &phy_timing); @@ -453,18 +489,23 @@ if (data_rate < 0) return -1; - mtk_dsi_reset(); dsi_write32(&dsi->dsi_force_commit, 3); + mtk_dsi_reset(); mtk_dsi_phy_timconfig(data_rate, &phy_timing); mtk_dsi_rxtx_control(mode_flags, lanes); - mtk_dsi_clk_hs_mode_disable(); mtk_dsi_config_vdo_timing(mode_flags, format, edid); mtk_dsi_clk_hs_mode_enable(); - mtk_dsi_set_mode(0); push_table(init_cmd, count); mtk_dsi_set_mode(mode_flags); mtk_dsi_start(); + dsi_write32((void *)DSI_BASE + 0x178, 0x00ff0000); + dsi_write32((void *)DSI_BASE + 0x17c, 0x00200040); + + for (i = 0; i < 0x208; i = i + 4) { + printk(BIOS_ERR, "dump_dsi_reg : reg[ox%x] = 0x%x\n", i, read32((void *)DSI_BASE + i)); + } + return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I878c9e0454acdbc0cd2cd310b8519efb845bb6ee Gerrit-Change-Number: 32097 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/poppy/variants/rammus: Support new onboard Hynix memory
by YanRu Chen (Code Review) 08 May '19

08 May '19

YanRu Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32674 ) Change subject: mb/google/poppy/variants/rammus: Support new onboard Hynix memory ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd02953d0c6ac62fa4d7751fd8b103b74433aa73 Gerrit-Change-Number: 32674 Gerrit-PatchSet: 1 Gerrit-Owner: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Wed, 08 May 2019 06:10:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/arch/x86: Use core apic id to get cpu_index()
by Subrata Banik (Code Review) 08 May '19

08 May '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26346 ) Change subject: src/arch/x86: Use core apic id to get cpu_index() ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/#/c/26346/12/src/arch/x86/cpu.c File src/arch/x86/cpu.c: https://review.coreboot.org/#/c/26346/12/src/arch/x86/cpu.c@314 PS12, Line 314: #if CONFIG(PARALLEL_MP) > why is this #if needed? Looks like few mainboard doesn't select this config hence mp_get_apic_id() function is undefined while calling cpu_index() Error log below https://qa.coreboot.org/job/coreboot-gerrit/93546/testReport/junit/(root)/b… -- To view, visit https://review.coreboot.org/c/coreboot/+/26346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Gerrit-Change-Number: 26346 Gerrit-PatchSet: 12 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Wed, 08 May 2019 02:11:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: ec/lenovo/h8: Add function to query sense state
by Nico Huber (Code Review) 07 May '19

07 May '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29204 ) Change subject: ec/lenovo/h8: Add function to query sense state ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie27e2881a256c4efb3def11f05070c446db6e5fc Gerrit-Change-Number: 29204 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 May 2019 21:07:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: src/arch/x86: Use core apic id to get cpu_index()
by Aaron Durbin (Code Review) 07 May '19

07 May '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26346 ) Change subject: src/arch/x86: Use core apic id to get cpu_index() ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/#/c/26346/12/src/arch/x86/cpu.c File src/arch/x86/cpu.c: https://review.coreboot.org/#/c/26346/12/src/arch/x86/cpu.c@314 PS12, Line 314: #if CONFIG(PARALLEL_MP) why is this #if needed? -- To view, visit https://review.coreboot.org/c/coreboot/+/26346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Gerrit-Change-Number: 26346 Gerrit-PatchSet: 12 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 07 May 2019 18:35:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: libpayload: Add UART for qcs405
by Patrick Georgi (Code Review) 07 May '19

07 May '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29957 ) Change subject: libpayload: Add UART for qcs405 ...................................................................... Patch Set 22: ping? when is that updated patch with the comments handled to land? -- To view, visit https://review.coreboot.org/c/coreboot/+/29957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202 Gerrit-Change-Number: 29957 Gerrit-PatchSet: 22 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Prudhvi Yarlagadda <pyarlaga(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Tue, 07 May 2019 17:37:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: southbridge/intel/bd82x6x: Enable vboot support
by Philipp Deppenwiese (Code Review) 07 May '19

07 May '19

Philipp Deppenwiese has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29815 ) Change subject: southbridge/intel/bd82x6x: Enable vboot support ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe86ffe7bfc6f71090d106b1e1a6228435e127ed Gerrit-Change-Number: 29815 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

Change in ...coreboot[master]: soc/amd/stoneyridge: Add iomux read/write functions
by Martin Roth (Code Review) 07 May '19

07 May '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32647 ) Change subject: soc/amd/stoneyridge: Add iomux read/write functions ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a0f44b6ec7261648cf0357b44a6c18dd40d1504 Gerrit-Change-Number: 32647 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 07 May 2019 16:16:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2019