coreboot-gerrit May 2019

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Change in ...coreboot[master]: soc/amd/stoneyridge: Add aoac_ read/write functions
by Marshall Dawson (Code Review) 08 May '19

08 May '19

Hello Richard Spiegel, Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32645 to review the following change. Change subject: soc/amd/stoneyridge: Add aoac_ read/write functions ...................................................................... soc/amd/stoneyridge: Add aoac_ read/write functions Add 8-bit functions to access the AOAC registers and use them in southbridge.c. At this time, there is no reason to pursue WORD or DWORD access and it's not known if those transaction sizes are supported. Change-Id: I3a8f493625f941fb855c0b8a0eff511a9a5ddfe8 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/sb_util.c M src/soc/amd/stoneyridge/southbridge.c 3 files changed, 16 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/32645/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index aed3288..098d24e 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -533,6 +533,8 @@ uint16_t smbus_read16(uint8_t offset); void smbus_write8(uint8_t offset, uint8_t value); void smbus_write16(uint8_t offset, uint16_t value); +uint8_t aoac_read8(uint8_t reg); +void aoac_write8(uint8_t reg, uint8_t value); void bootblock_fch_early_init(void); void bootblock_fch_init(void); /** diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index 4bffdbc..530e9cd 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -271,6 +271,16 @@ /* aoac read/write - access registers at 0xfed81e00 - not currently used */ +u8 aoac_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_AOAC_BASE + reg)); +} + +void aoac_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); +} + uint16_t pm_acpi_pm_cnt_blk(void) { return pm_read16(PM1_CNT_BLK); diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 66894a2..7dc27c8 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -279,20 +279,18 @@ static void power_on_aoac_device(int aoac_device_control_register) { uint8_t byte; - uint8_t *register_pointer = (uint8_t *)(uintptr_t)ACPIMMIO_AOAC_BASE - + aoac_device_control_register; /* Power on the UART and AMBA devices */ - byte = read8(register_pointer); + byte = aoac_read8(aoac_device_control_register); byte |= FCH_AOAC_PWR_ON_DEV; - write8(register_pointer, byte); + aoac_write8(aoac_device_control_register, byte); } static bool is_aoac_device_enabled(int aoac_device_status_register) { uint8_t byte; - byte = read8((uint8_t *)(uintptr_t)ACPIMMIO_AOAC_BASE - + aoac_device_status_register); + + byte = aoac_read8(aoac_device_status_register); byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) return true; -- To view, visit https://review.coreboot.org/c/coreboot/+/32645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a8f493625f941fb855c0b8a0eff511a9a5ddfe8 Gerrit-Change-Number: 32645 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/stoneyridge: Rewrite smbus_read/write, add asf
by Marshall Dawson (Code Review) 08 May '19

08 May '19

Hello Richard Spiegel, Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32644 to review the following change. Change subject: soc/amd/stoneyridge: Rewrite smbus_read/write, add asf ...................................................................... soc/amd/stoneyridge: Rewrite smbus_read/write, add asf Convert smbus_read8() and smbus_write8() functions to use the same arguments as the other AcpiMmio blocks, and add 16 and 32 bit versions. Add matching functions for the ASF controller. Change-Id: I3b0ecf21f20472245da98ab5e711a54e99dca93a Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/sb_util.c M src/soc/amd/stoneyridge/smbus.c M src/soc/amd/stoneyridge/southbridge.c 4 files changed, 102 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/32644/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 9fa93c8..aed3288 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -525,8 +525,14 @@ uint16_t xhci_pm_read16(uint8_t reg); void xhci_pm_write32(uint8_t reg, uint32_t value); uint32_t xhci_pm_read32(uint8_t reg); -void smbus_write8(uint32_t mmio, uint8_t reg, uint8_t value); -uint8_t smbus_read8(uint32_t mmio, uint8_t reg); +uint8_t asf_read8(uint8_t offset); +uint16_t asf_read16(uint8_t offset); +void asf_write8(uint8_t offset, uint8_t value); +void asf_write16(uint8_t offset, uint16_t value); +uint8_t smbus_read8(uint8_t offset); +uint16_t smbus_read16(uint8_t offset); +void smbus_write8(uint8_t offset, uint8_t value); +void smbus_write16(uint8_t offset, uint16_t value); void bootblock_fch_early_init(void); void bootblock_fch_init(void); /** diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index b777b1a..4bffdbc 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -167,16 +167,48 @@ write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); } -/* smbus read/write - access registers at 0xfed80a00 and ASF at 0xfed80900 */ +/* asf read/write - access registers at 0xfed80900 - not currently used */ -void smbus_write8(uint32_t mmio, uint8_t reg, uint8_t value) +u8 asf_read8(u8 reg) { - write8((void *)(mmio + reg), value); + return read8((void *)(ACPIMMIO_ASF_BASE + reg)); } -uint8_t smbus_read8(uint32_t mmio, uint8_t reg) +u16 asf_read16(u8 reg) { - return read8((void *)(mmio + reg)); + return read16((void *)(ACPIMMIO_ASF_BASE + reg)); +} + +void asf_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_ASF_BASE + reg), value); +} + +void asf_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_ASF_BASE + reg), value); +} + +/* smbus read/write - access registers at 0xfed80a00 and ASF at 0xfed80900 */ + +u8 smbus_read8(u8 reg) +{ + return read8((void *)(ACPIMMIO_SMBUS_BASE + reg)); +} + +u16 smbus_read16(u8 reg) +{ + return read16((void *)(ACPIMMIO_SMBUS_BASE + reg)); +} + +void smbus_write8(u8 reg, u8 value) +{ + write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value); +} + +void smbus_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); } /* wdt read/write - access registers at 0xfed80b00 - not currently used */ diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c index c4a022a..6285d79 100644 --- a/src/soc/amd/stoneyridge/smbus.c +++ b/src/soc/amd/stoneyridge/smbus.c @@ -15,21 +15,51 @@ #include <arch/io.h> #include <stdint.h> +#include <console/console.h> #include <soc/smbus.h> #include <soc/southbridge.h> +static u8 controller_read8(u32 base, u8 reg) +{ + switch (base) { + case ACPIMMIO_SMBUS_BASE: + return smbus_read8(reg); + case ACPIMMIO_ASF_BASE: + return asf_read8(reg); + default: + printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%x\n", + base); + } + return 0xff; +} + +static void controller_write8(u32 base, u8 reg, u8 val) +{ + switch (base) { + case ACPIMMIO_SMBUS_BASE: + smbus_write8(reg, val); + break; + case ACPIMMIO_ASF_BASE: + asf_write8(reg, val); + break; + default: + printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%x\n", + base); + } +} + static int smbus_wait_until_ready(u32 mmio) { u32 loops; loops = SMBUS_TIMEOUT; do { u8 val; - val = smbus_read8(mmio, SMBHSTSTAT); + val = controller_read8(mmio, SMBHSTSTAT); val &= SMBHST_STAT_VAL_BITS; if (val == 0) { /* ready now */ return 0; } - smbus_write8(mmio, SMBHSTSTAT, val); + controller_write8(mmio, SMBHSTSTAT, val); } while (--loops); return -2; /* time out */ } @@ -41,12 +71,12 @@ do { u8 val; - val = smbus_read8(mmio, SMBHSTSTAT); + val = controller_read8(mmio, SMBHSTSTAT); val &= SMBHST_STAT_VAL_BITS; /* mask off reserved bits */ if (val & SMBHST_STAT_ERROR_BITS) return -5; /* error */ if (val == SMBHST_STAT_NOERROR) { - smbus_write8(mmio, SMBHSTSTAT, val); /* clear sts */ + controller_write8(mmio, SMBHSTSTAT, val); /* clr sts */ return 0; } } while (--loops); @@ -61,19 +91,19 @@ return -2; /* not ready */ /* set the device I'm talking to */ - smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); - byte = smbus_read8(mmio, SMBHSTCTRL); + byte = controller_read8(mmio, SMBHSTCTRL); byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */ - smbus_write8(mmio, SMBHSTCTRL, byte); + controller_write8(mmio, SMBHSTCTRL, byte); /* poll for transaction completion */ if (smbus_wait_until_done(mmio) < 0) return -3; /* timeout or error */ /* read results of transaction */ - byte = smbus_read8(mmio, SMBHSTDAT0); + byte = controller_read8(mmio, SMBHSTDAT0); return byte; } @@ -86,15 +116,15 @@ return -2; /* not ready */ /* set the command... */ - smbus_write8(mmio, SMBHSTDAT0, val); + controller_write8(mmio, SMBHSTDAT0, val); /* set the device I'm talking to */ - smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); - byte = smbus_read8(mmio, SMBHSTCTRL); + byte = controller_read8(mmio, SMBHSTCTRL); byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */ - smbus_write8(mmio, SMBHSTCTRL, byte); + controller_write8(mmio, SMBHSTCTRL, byte); /* poll for transaction completion */ if (smbus_wait_until_done(mmio) < 0) @@ -111,22 +141,22 @@ return -2; /* not ready */ /* set the command/address... */ - smbus_write8(mmio, SMBHSTCMD, address & 0xff); + controller_write8(mmio, SMBHSTCMD, address & 0xff); /* set the device I'm talking to */ - smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); - byte = smbus_read8(mmio, SMBHSTCTRL); + byte = controller_read8(mmio, SMBHSTCTRL); byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */ - smbus_write8(mmio, SMBHSTCTRL, byte); + controller_write8(mmio, SMBHSTCTRL, byte); /* poll for transaction completion */ if (smbus_wait_until_done(mmio) < 0) return -3; /* timeout or error */ /* read results of transaction */ - byte = smbus_read8(mmio, SMBHSTDAT0); + byte = controller_read8(mmio, SMBHSTDAT0); return byte; } @@ -139,18 +169,18 @@ return -2; /* not ready */ /* set the command/address... */ - smbus_write8(mmio, SMBHSTCMD, address & 0xff); + controller_write8(mmio, SMBHSTCMD, address & 0xff); /* set the device I'm talking to */ - smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); /* output value */ - smbus_write8(mmio, SMBHSTDAT0, val); + controller_write8(mmio, SMBHSTDAT0, val); - byte = smbus_read8(mmio, SMBHSTCTRL); + byte = controller_read8(mmio, SMBHSTCTRL); byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */ - smbus_write8(mmio, SMBHSTCTRL, byte); + controller_write8(mmio, SMBHSTCTRL, byte); /* poll for transaction completion */ if (smbus_wait_until_done(mmio) < 0) diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 4f9e8ef..66894a2 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -632,12 +632,12 @@ static void fch_smbus_init(void) { pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8); - smbus_write8(ACPIMMIO_SMBUS_BASE, SMBTIMING, SMB_SPEED_400KHZ); + smbus_write8(SMBTIMING, SMB_SPEED_400KHZ); /* Clear all SMBUS status bits */ - smbus_write8(ACPIMMIO_SMBUS_BASE, SMBHSTSTAT, SMBHST_STAT_CLEAR); - smbus_write8(ACPIMMIO_SMBUS_BASE, SMBSLVSTAT, SMBSLV_STAT_CLEAR); - smbus_write8(ACPIMMIO_ASF_BASE, SMBHSTSTAT, SMBHST_STAT_CLEAR); - smbus_write8(ACPIMMIO_ASF_BASE, SMBSLVSTAT, SMBSLV_STAT_CLEAR); + smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); + smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); + asf_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); + asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); } /* Before console init */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b0ecf21f20472245da98ab5e711a54e99dca93a Gerrit-Change-Number: 32644 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/stoneyridge: Rearrange sb_util.c
by Marshall Dawson (Code Review) 08 May '19

08 May '19

Hello Richard Spiegel, Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32643 to review the following change. Change subject: soc/amd/stoneyridge: Rearrange sb_util.c ...................................................................... soc/amd/stoneyridge: Rearrange sb_util.c In preparation to move code to a common directory, rearrange some of the functions in sb_util.c. Add various comments. This change should have no functional differences. Change-Id: I1ad55a4a14a27e45459dcaf2fcc7449e29da6d4b Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/sb_util.c 1 file changed, 163 insertions(+), 126 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32643/1 diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index 3005f41..b777b1a 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -18,34 +18,65 @@ #include <arch/acpi.h> #include <soc/southbridge.h> -void pm_write8(u8 reg, u8 value) +/* smbus pci read/write - access registers at 0xfed80000 - currently unused */ + +/* smi read/write - access registers at 0xfed80200 */ + +uint8_t smi_read8(uint8_t offset) { - write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); + return read8((void *)(ACPIMMIO_SMI_BASE + offset)); } +uint16_t smi_read16(uint8_t offset) +{ + return read16((void *)(ACPIMMIO_SMI_BASE + offset)); +} + +uint32_t smi_read32(uint8_t offset) +{ + return read32((void *)(ACPIMMIO_SMI_BASE + offset)); +} + +void smi_write8(uint8_t offset, uint8_t value) +{ + write8((void *)(ACPIMMIO_SMI_BASE + offset), value); +} + +void smi_write16(uint8_t offset, uint16_t value) +{ + write16((void *)(ACPIMMIO_SMI_BASE + offset), value); +} + +void smi_write32(uint8_t offset, uint32_t value) +{ + write32((void *)(ACPIMMIO_SMI_BASE + offset), value); +} + +/* pm read/write - access registers at 0xfed80300 */ + u8 pm_read8(u8 reg) { return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); } -void pm_write16(u8 reg, u16 value) -{ - write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); -} - u16 pm_read16(u8 reg) { return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); } -void misc_write32(u8 reg, u32 value) +u32 pm_read32(u8 reg) { - write32((void *)(ACPIMMIO_MISC_BASE + reg), value); + return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); } -u32 misc_read32(u8 reg) +void pm_write8(u8 reg, u8 value) { - return read32((void *)(ACPIMMIO_MISC_BASE + reg)); + write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); +} + +void pm_write16(u8 reg, u16 value) +{ + write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); } void pm_write32(u8 reg, u32 value) @@ -53,11 +84,59 @@ write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); } -u32 pm_read32(u8 reg) +/* pm2 read/write - access registers at 0xfed80400 - currently unused */ + +/* biosram read/write - access registers at 0xfed80500 */ + +uint8_t biosram_read8(uint8_t offset) { - return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); + return read8((void *)(ACPIMMIO_BIOSRAM_BASE + offset)); } +uint16_t biosram_read16(uint8_t offset) /* Must be 1 byte at a time */ +{ + int i; + uint16_t value = 0; + for (i = sizeof(value) - 1 ; i >= 0 ; i--) + value = (value << 8) | biosram_read8(offset + i); + return value; +} + +uint32_t biosram_read32(uint8_t offset) +{ + uint32_t value = biosram_read16(offset + sizeof(uint16_t)) << 16; + return value | biosram_read16(offset); +} + +void biosram_write8(uint8_t offset, uint8_t value) +{ + write8((void *)(ACPIMMIO_BIOSRAM_BASE + offset), value); +} + +void biosram_write16(uint8_t offset, uint16_t value) +{ + int i; + for (i = 0 ; i < sizeof(value) ; i++) { + biosram_write8(offset + i, value & 0xff); + value >>= 8; + } +} + +void biosram_write32(uint8_t offset, uint32_t value) +{ + int i; + for (i = 0 ; i < sizeof(value) ; i++) { + biosram_write8(offset + i, value & 0xff); + value >>= 8; + } +} + +/* cmosram read/write - access registers at 0xfed80600 - currently unused */ + +/* cmos read/write - access registers at 0xfed80700 - currently unused */ + +/* acpi read/write - access registers at 0xfed80800 */ + u8 acpi_read8(u8 reg) { return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); @@ -88,119 +167,7 @@ write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); } -void smi_write32(uint8_t offset, uint32_t value) -{ - write32((void *)(ACPIMMIO_SMI_BASE + offset), value); -} - -uint32_t smi_read32(uint8_t offset) -{ - return read32((void *)(ACPIMMIO_SMI_BASE + offset)); -} - -uint16_t smi_read16(uint8_t offset) -{ - return read16((void *)(ACPIMMIO_SMI_BASE + offset)); -} - -void smi_write16(uint8_t offset, uint16_t value) -{ - write16((void *)(ACPIMMIO_SMI_BASE + offset), value); -} - -uint8_t smi_read8(uint8_t offset) -{ - return read8((void *)(ACPIMMIO_SMI_BASE + offset)); -} - -void smi_write8(uint8_t offset, uint8_t value) -{ - write8((void *)(ACPIMMIO_SMI_BASE + offset), value); -} - -uint8_t biosram_read8(uint8_t offset) -{ - return read8((void *)(ACPIMMIO_BIOSRAM_BASE + offset)); -} - -void biosram_write8(uint8_t offset, uint8_t value) -{ - write8((void *)(ACPIMMIO_BIOSRAM_BASE + offset), value); -} - -/* BiosRam may only be accessed a byte at a time */ -uint16_t biosram_read16(uint8_t offset) -{ - int i; - uint16_t value = 0; - for (i = sizeof(value) - 1 ; i >= 0 ; i--) - value = (value << 8) | biosram_read8(offset + i); - return value; -} - -uint32_t biosram_read32(uint8_t offset) -{ - uint32_t value = biosram_read16(offset + sizeof(uint16_t)) << 16; - return value | biosram_read16(offset); -} - -void biosram_write16(uint8_t offset, uint16_t value) -{ - int i; - for (i = 0 ; i < sizeof(value) ; i++) { - biosram_write8(offset + i, value & 0xff); - value >>= 8; - } -} - -void biosram_write32(uint8_t offset, uint32_t value) -{ - int i; - for (i = 0 ; i < sizeof(value) ; i++) { - biosram_write8(offset + i, value & 0xff); - value >>= 8; - } -} - -uint16_t pm_acpi_pm_cnt_blk(void) -{ - return pm_read16(PM1_CNT_BLK); -} - -uint16_t pm_acpi_pm_evt_blk(void) -{ - return pm_read16(PM_EVT_BLK); -} - -void xhci_pm_write8(uint8_t reg, uint8_t value) -{ - write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); -} - -uint8_t xhci_pm_read8(uint8_t reg) -{ - return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); -} - -void xhci_pm_write16(uint8_t reg, uint16_t value) -{ - write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); -} - -uint16_t xhci_pm_read16(uint8_t reg) -{ - return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); -} - -void xhci_pm_write32(uint8_t reg, uint32_t value) -{ - write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); -} - -uint32_t xhci_pm_read32(uint8_t reg) -{ - return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); -} +/* smbus read/write - access registers at 0xfed80a00 and ASF at 0xfed80900 */ void smbus_write8(uint32_t mmio, uint8_t reg, uint8_t value) { @@ -212,6 +179,76 @@ return read8((void *)(mmio + reg)); } +/* wdt read/write - access registers at 0xfed80b00 - not currently used */ + +/* hpet read/write - access registers at 0xfed80c00 - not currently used */ + +/* iomux read/write - access registers at 0xfed80d00 - not currently used */ + +/* misc read/write - access registers at 0xfed80e00 */ + +u32 misc_read32(u8 reg) +{ + return read32((void *)(ACPIMMIO_MISC_BASE + reg)); +} + +void misc_write32(u8 reg, u32 value) +{ + write32((void *)(ACPIMMIO_MISC_BASE + reg), value); +} + +/* dpvga read/write - access registers at 0xfed81400 - not currently used */ + +/* gpio bk 0 read/write - access registers at 0xfed81500 - not currently used */ +/* gpio bk 1 read/write - access registers at 0xfed81600 - not currently used */ +/* gpio bk 2 read/write - access registers at 0xfed81700 - not currently used */ + +/* xhci_pm read/write - access registers at 0xfed81c00 */ + +uint8_t xhci_pm_read8(uint8_t reg) +{ + return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +uint16_t xhci_pm_read16(uint8_t reg) +{ + return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +uint32_t xhci_pm_read32(uint8_t reg) +{ + return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); +} + +void xhci_pm_write8(uint8_t reg, uint8_t value) +{ + write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +void xhci_pm_write16(uint8_t reg, uint16_t value) +{ + write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +void xhci_pm_write32(uint8_t reg, uint32_t value) +{ + write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); +} + +/* acdc_tmr read/write - access registers at 0xfed81d00 */ + +/* aoac read/write - access registers at 0xfed81e00 - not currently used */ + +uint16_t pm_acpi_pm_cnt_blk(void) +{ + return pm_read16(PM1_CNT_BLK); +} + +uint16_t pm_acpi_pm_evt_blk(void) +{ + return pm_read16(PM_EVT_BLK); +} + int acpi_get_sleep_type(void) { return acpi_sleep_from_pm1(inw(pm_acpi_pm_cnt_blk())); -- To view, visit https://review.coreboot.org/c/coreboot/+/32643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ad55a4a14a27e45459dcaf2fcc7449e29da6d4b Gerrit-Change-Number: 32643 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: soc/amd/stoneyridge: Rename AcpiMmio blocks
by Marshall Dawson (Code Review) 08 May '19

08 May '19

Hello Richard Spiegel, Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32642 to review the following change. Change subject: soc/amd/stoneyridge: Rename AcpiMmio blocks ...................................................................... soc/amd/stoneyridge: Rename AcpiMmio blocks A subsequent patch will move the AcpiMmio support into amd/common. Take this opportunity to rename the blocks in the 0xfed8xxxx region with more consistency. Change-Id: I9a69a6ecfc10f78b4860df05a77a061d2fc8be7d Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl M src/soc/amd/stoneyridge/acpi/gpio_lib.asl M src/soc/amd/stoneyridge/acpi/sb_fch.asl M src/soc/amd/stoneyridge/gpio.c M src/soc/amd/stoneyridge/include/soc/iomap.h M src/soc/amd/stoneyridge/sb_util.c M src/soc/amd/stoneyridge/sm.c M src/soc/amd/stoneyridge/smbus_spd.c M src/soc/amd/stoneyridge/southbridge.c 10 files changed, 75 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32642/1 diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 1bf6c07..ad979a5 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -145,13 +145,13 @@ pm_write8(PM_PCIB_CFG, pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE); /* Set low-power mode for BayHub eMMC bridge's PCIe clock. */ - clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL), + clrsetbits_le32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL), GPP_CLK2_REQ_MAP_MASK, GPP_CLK2_REQ_MAP_CLK_REQ2 << GPP_CLK2_REQ_MAP_SHIFT); /* Same for the WiFi */ - clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL), + clrsetbits_le32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL), GPP_CLK0_REQ_MAP_MASK, GPP_CLK0_REQ_MAP_CLK_REQ0 << GPP_CLK0_REQ_MAP_SHIFT); diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl index 6bb41ae..87890da 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl @@ -35,7 +35,7 @@ Name (RBUF, ResourceTemplate () { // Memory resource is for MISC FCH register set. // It is needed for enabling the clock. - Memory32Fixed(ReadWrite, MISC_MMIO_BASE, 0x100) + Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) }) Return (RBUF) diff --git a/src/soc/amd/stoneyridge/acpi/gpio_lib.asl b/src/soc/amd/stoneyridge/acpi/gpio_lib.asl index d18b147..8185c35 100644 --- a/src/soc/amd/stoneyridge/acpi/gpio_lib.asl +++ b/src/soc/amd/stoneyridge/acpi/gpio_lib.asl @@ -19,7 +19,7 @@ Method (GPAD, 0x1) { /* Arg0 - GPIO pin number */ - Return (Add(Multiply(Arg0, 4), GPIO_CONTROL_MMIO_BASE)) + Return (Add(Multiply(Arg0, 4), ACPIMMIO_GPIO0_BASE)) } /* Read pin control dword */ diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl index 114401e..4c1196d 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl @@ -144,7 +144,7 @@ Name (_HID, "AMD0040") Name (_UID, 0x3) Name (_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, MISC_MMIO_BASE, 0x100) + Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) }) Method (_STA, 0x0, NotSerialized) { diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index da1ba0b..b747538 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -228,7 +228,7 @@ uint8_t mux, index, gpio; int gevent_num; - inter_master = (uint32_t *)(uintptr_t)(GPIO_CONTROL_MMIO_BASE + inter_master = (uint32_t *)(uintptr_t)(ACPIMMIO_GPIO0_BASE + GPIO_MASTER_SWITCH); direction = 0; edge_level = 0; @@ -252,7 +252,7 @@ control = gpio_list_ptr[index].control; control_flags = gpio_list_ptr[index].flags; - mux_ptr = (uint8_t *)(uintptr_t)(gpio + GPIO_IOMUX_MMIO_BASE); + mux_ptr = (uint8_t *)(uintptr_t)(gpio + ACPIMMIO_IOMUX_BASE); write8(mux_ptr, mux & AMD_GPIO_MUX_MASK); read8(mux_ptr); /* Flush posted write */ /* special case if pin 2 is assigned to wake */ @@ -316,11 +316,13 @@ mem_read_write32(inter_master, GPIO_INTERRUPT_EN, GPIO_INTERRUPT_EN); /* Set all SCI trigger direction (high/low) */ - mem_read_write32((uint32_t *)(uintptr_t)(APU_SMI_BASE + SMI_SCI_TRIG), + mem_read_write32((uint32_t *) + (uintptr_t)(ACPIMMIO_SMI_BASE + SMI_SCI_TRIG), direction, mask); /* Set all SCI trigger level (edge/level) */ - mem_read_write32((uint32_t *)(uintptr_t)(APU_SMI_BASE + SMI_SCI_LEVEL), + mem_read_write32((uint32_t *) + (uintptr_t)(ACPIMMIO_SMI_BASE + SMI_SCI_LEVEL), edge_level, mask); } @@ -348,7 +350,7 @@ uint32_t *gpio_ptr; uint8_t *mux_ptr; - mux_ptr = (uint8_t *)(uintptr_t)(gpio + GPIO_IOMUX_MMIO_BASE); + mux_ptr = (uint8_t *)(uintptr_t)(gpio + ACPIMMIO_IOMUX_BASE); gpio_ptr = (uint32_t *)gpio_get_address(gpio); save_table->mux_value = read8(mux_ptr); save_table->control_value = read32(gpio_ptr); @@ -360,7 +362,7 @@ uint32_t *gpio_ptr; uint8_t *mux_ptr; - mux_ptr = (uint8_t *)(uintptr_t)(gpio + GPIO_IOMUX_MMIO_BASE); + mux_ptr = (uint8_t *)(uintptr_t)(gpio + ACPIMMIO_IOMUX_BASE); gpio_ptr = (uint32_t *)gpio_get_address(gpio); write8(mux_ptr, save_table->mux_value); read8(mux_ptr); diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 613dd04..e6327dc 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -32,19 +32,29 @@ #endif #define HPET_BASE_ADDRESS 0xfed00000 -/* Register blocks at fixed offsets from FED8_0000h and enabled in PMx04[1] */ +/* AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1] */ #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 -#define APU_SMI_BASE 0xfed80200 -#define PM_MMIO_BASE 0xfed80300 -#define BIOSRAM_MMIO_BASE 0xfed80500 -#define ACPI_REG_MMIO_BASE 0xfed80800 -#define ASF_MMIO_BASE 0xfed80900 -#define SMBUS_MMIO_BASE 0xfed80a00 -#define GPIO_IOMUX_MMIO_BASE 0xfed80d00 -#define MISC_MMIO_BASE 0xfed80e00 -#define XHCI_ACPI_PM_MMIO_BASE 0xfed81c00 -#define GPIO_CONTROL_MMIO_BASE 0xfed81500 -#define AOAC_MMIO_BASE 0xfed81e00 +#define ACPIMMIO_SM_PCI_BASE 0xfed80000 +#define ACPIMMIO_SMI_BASE 0xfed80200 +#define ACPIMMIO_PMIO_BASE 0xfed80300 +#define ACPIMMIO_PMIO2_BASE 0xfed80400 +#define ACPIMMIO_BIOSRAM_BASE 0xfed80500 +#define ACPIMMIO_CMOSRAM_BASE 0xfed80600 +#define ACPIMMIO_CMOS_BASE 0xfed80700 +#define ACPIMMIO_ACPI_BASE 0xfed80800 +#define ACPIMMIO_ASF_BASE 0xfed80900 +#define ACPIMMIO_SMBUS_BASE 0xfed80a00 +#define ACPIMMIO_WDT_BASE 0xfed80b00 +#define ACPIMMIO_HPET_BASE 0xfed80c00 +#define ACPIMMIO_IOMUX_BASE 0xfed80d00 +#define ACPIMMIO_MISC_BASE 0xfed80e00 +#define ACPIMMIO_DPVGA_BASE 0xfed81400 +#define ACPIMMIO_GPIO0_BASE 0xfed81500 +#define ACPIMMIO_GPIO1_BASE 0xfed81600 +#define ACPIMMIO_GPIO2_BASE 0xfed81700 +#define ACPIMMIO_XHCIPM_BASE 0xfed81c00 +#define ACPIMMIO_ACDCTMR_BASE 0xfed81d00 +#define ACPIMMIO_AOAC_BASE 0xfed81e00 #define APU_UART0_BASE 0xfedc6000 #define APU_UART1_BASE 0xfedc8000 diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index b60f186..3005f41 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -20,112 +20,112 @@ void pm_write8(u8 reg, u8 value) { - write8((void *)(PM_MMIO_BASE + reg), value); + write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); } u8 pm_read8(u8 reg) { - return read8((void *)(PM_MMIO_BASE + reg)); + return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); } void pm_write16(u8 reg, u16 value) { - write16((void *)(PM_MMIO_BASE + reg), value); + write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); } u16 pm_read16(u8 reg) { - return read16((void *)(PM_MMIO_BASE + reg)); + return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); } void misc_write32(u8 reg, u32 value) { - write32((void *)(MISC_MMIO_BASE + reg), value); + write32((void *)(ACPIMMIO_MISC_BASE + reg), value); } u32 misc_read32(u8 reg) { - return read32((void *)(MISC_MMIO_BASE + reg)); + return read32((void *)(ACPIMMIO_MISC_BASE + reg)); } void pm_write32(u8 reg, u32 value) { - write32((void *)(PM_MMIO_BASE + reg), value); + write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); } u32 pm_read32(u8 reg) { - return read32((void *)(PM_MMIO_BASE + reg)); + return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); } u8 acpi_read8(u8 reg) { - return read8((void *)(ACPI_REG_MMIO_BASE + reg)); + return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); } u16 acpi_read16(u8 reg) { - return read16((void *)(ACPI_REG_MMIO_BASE + reg)); + return read16((void *)(ACPIMMIO_ACPI_BASE + reg)); } u32 acpi_read32(u8 reg) { - return read32((void *)(ACPI_REG_MMIO_BASE + reg)); + return read32((void *)(ACPIMMIO_ACPI_BASE + reg)); } void acpi_write8(u8 reg, u8 value) { - write8((void *)(ACPI_REG_MMIO_BASE + reg), value); + write8((void *)(ACPIMMIO_ACPI_BASE + reg), value); } void acpi_write16(u8 reg, u16 value) { - write16((void *)(ACPI_REG_MMIO_BASE + reg), value); + write16((void *)(ACPIMMIO_ACPI_BASE + reg), value); } void acpi_write32(u8 reg, u32 value) { - write32((void *)(ACPI_REG_MMIO_BASE + reg), value); + write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); } void smi_write32(uint8_t offset, uint32_t value) { - write32((void *)(APU_SMI_BASE + offset), value); + write32((void *)(ACPIMMIO_SMI_BASE + offset), value); } uint32_t smi_read32(uint8_t offset) { - return read32((void *)(APU_SMI_BASE + offset)); + return read32((void *)(ACPIMMIO_SMI_BASE + offset)); } uint16_t smi_read16(uint8_t offset) { - return read16((void *)(APU_SMI_BASE + offset)); + return read16((void *)(ACPIMMIO_SMI_BASE + offset)); } void smi_write16(uint8_t offset, uint16_t value) { - write16((void *)(APU_SMI_BASE + offset), value); + write16((void *)(ACPIMMIO_SMI_BASE + offset), value); } uint8_t smi_read8(uint8_t offset) { - return read8((void *)(APU_SMI_BASE + offset)); + return read8((void *)(ACPIMMIO_SMI_BASE + offset)); } void smi_write8(uint8_t offset, uint8_t value) { - write8((void *)(APU_SMI_BASE + offset), value); + write8((void *)(ACPIMMIO_SMI_BASE + offset), value); } uint8_t biosram_read8(uint8_t offset) { - return read8((void *)(BIOSRAM_MMIO_BASE + offset)); + return read8((void *)(ACPIMMIO_BIOSRAM_BASE + offset)); } void biosram_write8(uint8_t offset, uint8_t value) { - write8((void *)(BIOSRAM_MMIO_BASE + offset), value); + write8((void *)(ACPIMMIO_BIOSRAM_BASE + offset), value); } /* BiosRam may only be accessed a byte at a time */ @@ -174,32 +174,32 @@ void xhci_pm_write8(uint8_t reg, uint8_t value) { - write8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value); + write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); } uint8_t xhci_pm_read8(uint8_t reg) { - return read8((void *)(XHCI_ACPI_PM_MMIO_BASE + reg)); + return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); } void xhci_pm_write16(uint8_t reg, uint16_t value) { - write16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value); + write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); } uint16_t xhci_pm_read16(uint8_t reg) { - return read16((void *)(XHCI_ACPI_PM_MMIO_BASE + reg)); + return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); } void xhci_pm_write32(uint8_t reg, uint32_t value) { - write32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg), value); + write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); } uint32_t xhci_pm_read32(uint8_t reg) { - return read32((void *)(XHCI_ACPI_PM_MMIO_BASE + reg)); + return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); } void smbus_write8(uint32_t mmio, uint8_t reg, uint8_t value) diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c index 9344b2f..803e628 100644 --- a/src/soc/amd/stoneyridge/sm.c +++ b/src/soc/amd/stoneyridge/sm.c @@ -42,9 +42,9 @@ pbus = get_pbus_smbus(dev); res = find_resource(pbus->dev, 0x90); if (res->base == SMB_BASE_ADDR) - return SMBUS_MMIO_BASE; + return ACPIMMIO_SMBUS_BASE; - return ASF_MMIO_BASE; + return ACPIMMIO_ASF_BASE; } static int lsmbus_recv_byte(struct device *dev) diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c index ed73a6e..e57ecde 100644 --- a/src/soc/amd/stoneyridge/smbus_spd.c +++ b/src/soc/amd/stoneyridge/smbus_spd.c @@ -46,7 +46,7 @@ dev_addr = (SmbusSlaveAddress >> 1); /* Read the first SPD byte */ - error = do_smbus_read_byte(SMBUS_MMIO_BASE, dev_addr, 0); + error = do_smbus_read_byte(ACPIMMIO_SMBUS_BASE, dev_addr, 0); if (error < 0) { printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); return error; @@ -56,7 +56,7 @@ /* Read the remaining SPD bytes using do_smbus_recv_byte for speed */ for (index = 1 ; index < count ; index++) { - error = do_smbus_recv_byte(SMBUS_MMIO_BASE, dev_addr); + error = do_smbus_recv_byte(ACPIMMIO_SMBUS_BASE, dev_addr); if (error < 0) { printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); return error; diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 9c54694..4f9e8ef 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -279,7 +279,7 @@ static void power_on_aoac_device(int aoac_device_control_register) { uint8_t byte; - uint8_t *register_pointer = (uint8_t *)(uintptr_t)AOAC_MMIO_BASE + uint8_t *register_pointer = (uint8_t *)(uintptr_t)ACPIMMIO_AOAC_BASE + aoac_device_control_register; /* Power on the UART and AMBA devices */ @@ -291,7 +291,7 @@ static bool is_aoac_device_enabled(int aoac_device_status_register) { uint8_t byte; - byte = read8((uint8_t *)(uintptr_t)AOAC_MMIO_BASE + byte = read8((uint8_t *)(uintptr_t)ACPIMMIO_AOAC_BASE + aoac_device_status_register); byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) @@ -393,7 +393,7 @@ void sb_clk_output_48Mhz(u32 osc) { u32 ctrl; - u32 *misc_clk_cntl_1_ptr = (u32 *)(uintptr_t)(MISC_MMIO_BASE + u32 *misc_clk_cntl_1_ptr = (u32 *)(uintptr_t)(ACPIMMIO_MISC_BASE + MISC_CLK_CNTL1); /* @@ -632,12 +632,12 @@ static void fch_smbus_init(void) { pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8); - smbus_write8(SMBUS_MMIO_BASE, SMBTIMING, SMB_SPEED_400KHZ); + smbus_write8(ACPIMMIO_SMBUS_BASE, SMBTIMING, SMB_SPEED_400KHZ); /* Clear all SMBUS status bits */ - smbus_write8(SMBUS_MMIO_BASE, SMBHSTSTAT, SMBHST_STAT_CLEAR); - smbus_write8(SMBUS_MMIO_BASE, SMBSLVSTAT, SMBSLV_STAT_CLEAR); - smbus_write8(ASF_MMIO_BASE, SMBHSTSTAT, SMBHST_STAT_CLEAR); - smbus_write8(ASF_MMIO_BASE, SMBSLVSTAT, SMBSLV_STAT_CLEAR); + smbus_write8(ACPIMMIO_SMBUS_BASE, SMBHSTSTAT, SMBHST_STAT_CLEAR); + smbus_write8(ACPIMMIO_SMBUS_BASE, SMBSLVSTAT, SMBSLV_STAT_CLEAR); + smbus_write8(ACPIMMIO_ASF_BASE, SMBHSTSTAT, SMBHST_STAT_CLEAR); + smbus_write8(ACPIMMIO_ASF_BASE, SMBSLVSTAT, SMBSLV_STAT_CLEAR); } /* Before console init */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a69a6ecfc10f78b4860df05a77a061d2fc8be7d Gerrit-Change-Number: 32642 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

3 4

Change in ...libgfxinit[master]: gma: Fix Ironlake panel fitting, revisited
by Nico Huber (Code Review) 08 May '19

08 May '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/libgfxinit/+/27153 ) Change subject: gma: Fix Ironlake panel fitting, revisited ...................................................................... gma: Fix Ironlake panel fitting, revisited This time avoid scaling to odd heights, too. At least Sandy Bridge has trouble with this. Change-Id: Ib7dfe1fd289661ecd6949eca4b39860dbecc4463 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/27153 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/hw-gfx-gma-pipe_setup.adb 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Nico Huber: Verified Arthur Heymans: Looks good to me, approved diff --git a/common/hw-gfx-gma-pipe_setup.adb b/common/hw-gfx-gma-pipe_setup.adb index 76051dd..0a2cbcf 100644 --- a/common/hw-gfx-gma-pipe_setup.adb +++ b/common/hw-gfx-gma-pipe_setup.adb @@ -508,6 +508,10 @@ if Width < Mode.H_Visible and Width mod 2 = 1 then Width := Width + 1; end if; + -- Do not scale to odd height (at least Sandy Bridge makes trouble). + if Height < Mode.V_Visible and Height mod 2 = 1 then + Height := Height + 1; + end if; X := (Mode.H_Visible - Width) / 2; Y := (Mode.V_Visible - Height) / 2; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ib7dfe1fd289661ecd6949eca4b39860dbecc4463 Gerrit-Change-Number: 27153 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in ...libgfxinit[master]: gma config: Enable Restrictions (No_Elaboration_Code)
by Nico Huber (Code Review) 08 May '19

08 May '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/libgfxinit/+/27143 ) Change subject: gma config: Enable Restrictions (No_Elaboration_Code) ...................................................................... gma config: Enable Restrictions (No_Elaboration_Code) Forcing compile-time evaluation seems to be the right thing and works well now. It also helps to compare binaries after refactorizations. Change-Id: I4eea973836a05eefcc2c98de75e6721ef3cd278b Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/27143 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/hw-gfx-gma-config.ads.template 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: Nico Huber: Verified Arthur Heymans: Looks good to me, approved diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 721252b..bf69dc8 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -12,6 +12,8 @@ -- GNU General Public License for more details. -- +pragma Restrictions (No_Elaboration_Code); + private package HW.GFX.GMA.Config is Gen : constant Generation := <<GEN>>; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I4eea973836a05eefcc2c98de75e6721ef3cd278b Gerrit-Change-Number: 27143 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in ...libgfxinit[master]: gma: Implement automatic CPU detection
by Nico Huber (Code Review) 08 May '19

08 May '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/libgfxinit/+/27138 ) Change subject: gma: Implement automatic CPU detection ...................................................................... gma: Implement automatic CPU detection In dynamic CPU configurations, Config.Detect_CPU() sets the CPU variables according to the given PCI device id. In static confi- gurations it does nothing. We update the default configs to make use of this feature where applicable. This should still give us full build-test coverage while cutting the amount of tests in half. Change-Id: I8ce31c867f97c8d6ef99ca096cb45f7719e78a19 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/27138 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/Makefile.inc A common/dyncpu/hw-gfx-gma-config.adb M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma.adb D configs/broadwell D configs/broadwell_ult M configs/broxton M configs/g45 M configs/haswell D configs/haswell_ult M configs/ironlake R configs/ironlake_edp D configs/ivybridge_lvds D configs/sandybridge M configs/skylake D configs/skylake_ult 16 files changed, 62 insertions(+), 63 deletions(-) Approvals: Nico Huber: Verified Arthur Heymans: Looks good to me, approved diff --git a/common/Makefile.inc b/common/Makefile.inc index ba48f85..7c5403b 100644 --- a/common/Makefile.inc +++ b/common/Makefile.inc @@ -79,6 +79,7 @@ -e's/<$ilk\|hsw\|skl$$...$\?var>/$(_GEN_CONST_TARGET)/' \ -e's/$.*: *<cpufunc>.*:=$ *$.*$;/\1\n (\2);/' \ -e's/$[^ ]\+$ *: *<cpufunc> \+$[^ ]*$ *:=/function \1 return \2 is/' \ + -e's/<cpunull>//' \ $< >$@ else $(hw-gfx-gma-config-ads): $(dir)/hw-gfx-gma-config.ads.template $(cnf) @@ -93,18 +94,20 @@ -e'/Dyn_CPU$_Var$\?/d' \ -e's/<$gen\|\(ilk\|hsw\|skl$$...$\?\)bool>/constant Boolean/' \ -e's/<$\(ilk\|hsw\|skl$$...$\?\)var>/constant/' \ + -e's/<cpunull>/ is null/' \ $< >$@ endif gfxinit-gen-y += $(hw-gfx-gma-config-ads) +gfxinit-$(CONFIG_GFX_GMA_DYN_CPU) += dyncpu/hw-gfx-gma-config.adb -ifneq ($(filter G45,$(CONFIG_GFX_GMA_CPU)),) +ifneq ($(filter G45,$(CONFIG_GFX_GMA_GENERATION)),) subdirs-y += g45 -else ifneq ($(filter Ironlake Sandybridge Ivybridge,$(CONFIG_GFX_GMA_CPU)),) +else ifneq ($(filter Ironlake,$(CONFIG_GFX_GMA_GENERATION)),) subdirs-y += ironlake -else ifneq ($(filter Haswell Broadwell,$(CONFIG_GFX_GMA_CPU)),) +else ifneq ($(filter Haswell,$(CONFIG_GFX_GMA_GENERATION)),) subdirs-y += haswell_shared haswell -else ifneq ($(filter Broxton,$(CONFIG_GFX_GMA_CPU)),) +else ifneq ($(filter Broxton,$(CONFIG_GFX_GMA_GENERATION)),) subdirs-y += haswell_shared broxton -else ifneq ($(filter Skylake,$(CONFIG_GFX_GMA_CPU)),) +else ifneq ($(filter Skylake,$(CONFIG_GFX_GMA_GENERATION)),) subdirs-y += haswell_shared skylake endif diff --git a/common/dyncpu/hw-gfx-gma-config.adb b/common/dyncpu/hw-gfx-gma-config.adb new file mode 100644 index 0000000..762ff6f --- /dev/null +++ b/common/dyncpu/hw-gfx-gma-config.adb @@ -0,0 +1,31 @@ +-- +-- Copyright (C) 2018 Nico Huber <nico.h(a)gmx.de> +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +package body HW.GFX.GMA.Config +is + + procedure Detect_CPU (Device : Word16) is + begin + for CPU in Gen_CPU_Type loop + for CPU_Var in Gen_CPU_Variant loop + if Is_GPU (Device, CPU, CPU_Var) then + Config.CPU := CPU; + Config.CPU_Var := CPU_Var; + exit; + end if; + end loop; + end loop; + end Detect_CPU; + +end HW.GFX.GMA.Config; diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 044036e..721252b 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -361,4 +361,8 @@ function Compatible_GPU (Device_Id : Word16) return Boolean is (Is_GPU (Device_Id, CPU, CPU_Var)); + pragma Warnings (GNATprove, Off, "subprogram ""Detect_CPU"" has no effect", + Reason => "only effective in dynamic cpu config"); + procedure Detect_CPU (Device : Word16)<cpunull>; + end HW.GFX.GMA.Config; diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 885072c..171d224 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -425,6 +425,7 @@ Dev.Read16 (Vendor, PCI.Vendor_Id); Dev.Read16 (Device, PCI.Device_Id); + Config.Detect_CPU (Device); Success := Vendor = 16#8086# and Config.Compatible_GPU (Device); end Check_Platform_PCI; begin @@ -443,29 +444,27 @@ Cursor => Default_Cursor, Mode => HW.GFX.Invalid_Mode)); Config.Variable := Config.Initial_Settings; + Registers.Set_Register_Base (Config.Default_MMIO_Base); PLLs.Initialize; Dev.Initialize (Success); if Success then - Dev.Map (PCI_MMIO_Base, PCI.Res0, Length => MMIO_GTT_Offset); - Dev.Map (PCI_GTT_Base, PCI.Res0, Offset => MMIO_GTT_Offset); - if PCI_MMIO_Base /= 0 and PCI_GTT_Base /= 0 then - Registers.Set_Register_Base (PCI_MMIO_Base, PCI_GTT_Base); - else - pragma Debug (Debug.Put_Line - ("ERROR: Couldn't map resoure0.")); - Registers.Set_Register_Base (Config.Default_MMIO_Base); - Success := Config.Default_MMIO_Base_Set; - end if; - + Check_Platform_PCI (Success); if Success then - Check_Platform_PCI (Success); + Dev.Map (PCI_MMIO_Base, PCI.Res0, Length => MMIO_GTT_Offset); + Dev.Map (PCI_GTT_Base, PCI.Res0, Offset => MMIO_GTT_Offset); + if PCI_MMIO_Base /= 0 and PCI_GTT_Base /= 0 then + Registers.Set_Register_Base (PCI_MMIO_Base, PCI_GTT_Base); + else + pragma Debug (Debug.Put_Line + ("ERROR: Couldn't map resoure0.")); + Success := Config.Default_MMIO_Base_Set; + end if; end if; else pragma Debug (Debug.Put_Line ("WARNING: Couldn't initialize PCI dev.")); - Registers.Set_Register_Base (Config.Default_MMIO_Base); Success := Config.Default_MMIO_Base_Set; if Success then diff --git a/configs/broadwell b/configs/broadwell deleted file mode 100644 index 06a6c2a..0000000 --- a/configs/broadwell +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_GFX_GMA_GENERATION = Haswell -CONFIG_GFX_GMA_CPU = Broadwell -CONFIG_GFX_GMA_CPU_VARIANT = Normal -CONFIG_GFX_GMA_INTERNAL_PORT = DP -CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC -CONFIG_GFX_GMA_DEFAULT_MMIO = 16\#e000_0000\# diff --git a/configs/broadwell_ult b/configs/broadwell_ult deleted file mode 100644 index 105992a..0000000 --- a/configs/broadwell_ult +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_GFX_GMA_GENERATION = Haswell -CONFIG_GFX_GMA_CPU = Broadwell -CONFIG_GFX_GMA_CPU_VARIANT = ULT -CONFIG_GFX_GMA_INTERNAL_PORT = DP -CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC -CONFIG_GFX_GMA_DEFAULT_MMIO = 16\#e000_0000\# diff --git a/configs/broxton b/configs/broxton index 35db833..5006125 100644 --- a/configs/broxton +++ b/configs/broxton @@ -1,3 +1,4 @@ +CONFIG_GFX_GMA_DYN_CPU = CONFIG_GFX_GMA_GENERATION = Broxton CONFIG_GFX_GMA_CPU = Broxton CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A diff --git a/configs/g45 b/configs/g45 index ef97850..9d2da64 100644 --- a/configs/g45 +++ b/configs/g45 @@ -1,6 +1,7 @@ +CONFIG_GFX_GMA_DYN_CPU = CONFIG_GFX_GMA_GENERATION = G45 CONFIG_GFX_GMA_CPU = G45 -CONFIG_GFX_GMA_CPU_VARIANT = Normal +CONFIG_GFX_GMA_CPU_VARIANT = Normal # N/A CONFIG_GFX_GMA_INTERNAL_PORT = LVDS CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC CONFIG_GFX_GMA_DEFAULT_MMIO = 16\#e000_0000\# diff --git a/configs/haswell b/configs/haswell index 8c025da..8adaafc 100644 --- a/configs/haswell +++ b/configs/haswell @@ -1,6 +1,5 @@ +CONFIG_GFX_GMA_DYN_CPU = y CONFIG_GFX_GMA_GENERATION = Haswell -CONFIG_GFX_GMA_CPU = Haswell -CONFIG_GFX_GMA_CPU_VARIANT = Normal CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC CONFIG_GFX_GMA_DEFAULT_MMIO = 16\#e000_0000\# diff --git a/configs/haswell_ult b/configs/haswell_ult deleted file mode 100644 index 9559042..0000000 --- a/configs/haswell_ult +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_GFX_GMA_GENERATION = Haswell -CONFIG_GFX_GMA_CPU = Haswell -CONFIG_GFX_GMA_CPU_VARIANT = ULT -CONFIG_GFX_GMA_INTERNAL_PORT = DP -CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC -CONFIG_GFX_GMA_DEFAULT_MMIO = 16\#e000_0000\# diff --git a/configs/ironlake b/configs/ironlake index 2c26a79..20b33a7 100644 --- a/configs/ironlake +++ b/configs/ironlake @@ -1,6 +1,5 @@ +CONFIG_GFX_GMA_DYN_CPU = y CONFIG_GFX_GMA_GENERATION = Ironlake -CONFIG_GFX_GMA_CPU = Ironlake -CONFIG_GFX_GMA_CPU_VARIANT = Normal CONFIG_GFX_GMA_INTERNAL_PORT = LVDS CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC CONFIG_GFX_GMA_DEFAULT_MMIO = 16\#e000_0000\# diff --git a/configs/ivybridge_edp b/configs/ironlake_edp similarity index 69% rename from configs/ivybridge_edp rename to configs/ironlake_edp index 6ce8543..9bc56c3 100644 --- a/configs/ivybridge_edp +++ b/configs/ironlake_edp @@ -1,6 +1,5 @@ +CONFIG_GFX_GMA_DYN_CPU = y CONFIG_GFX_GMA_GENERATION = Ironlake -CONFIG_GFX_GMA_CPU = Ivybridge -CONFIG_GFX_GMA_CPU_VARIANT = Normal CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC CONFIG_GFX_GMA_DEFAULT_MMIO = 16\#e000_0000\# diff --git a/configs/ivybridge_lvds b/configs/ivybridge_lvds deleted file mode 100644 index 31813f9..0000000 --- a/configs/ivybridge_lvds +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_GFX_GMA_GENERATION = Ironlake -CONFIG_GFX_GMA_CPU = Ivybridge -CONFIG_GFX_GMA_CPU_VARIANT = Normal -CONFIG_GFX_GMA_INTERNAL_PORT = LVDS -CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC -CONFIG_GFX_GMA_DEFAULT_MMIO = 16\#e000_0000\# diff --git a/configs/sandybridge b/configs/sandybridge deleted file mode 100644 index 5cc15cd..0000000 --- a/configs/sandybridge +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_GFX_GMA_GENERATION = Ironlake -CONFIG_GFX_GMA_CPU = Sandybridge -CONFIG_GFX_GMA_CPU_VARIANT = Normal -CONFIG_GFX_GMA_INTERNAL_PORT = LVDS -CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC -CONFIG_GFX_GMA_DEFAULT_MMIO = 16\#e000_0000\# diff --git a/configs/skylake b/configs/skylake index 26c9896..7ae760a 100644 --- a/configs/skylake +++ b/configs/skylake @@ -1,6 +1,5 @@ +CONFIG_GFX_GMA_DYN_CPU = y CONFIG_GFX_GMA_GENERATION = Skylake -CONFIG_GFX_GMA_CPU = Skylake -CONFIG_GFX_GMA_CPU_VARIANT = Normal CONFIG_GFX_GMA_INTERNAL_PORT = DP CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC CONFIG_GFX_GMA_DEFAULT_MMIO = 16\#e000_0000\# diff --git a/configs/skylake_ult b/configs/skylake_ult deleted file mode 100644 index c683251..0000000 --- a/configs/skylake_ult +++ /dev/null @@ -1,6 +0,0 @@ -CONFIG_GFX_GMA_GENERATION = Skylake -CONFIG_GFX_GMA_CPU = Skylake -CONFIG_GFX_GMA_CPU_VARIANT = ULT -CONFIG_GFX_GMA_INTERNAL_PORT = DP -CONFIG_GFX_GMA_ANALOG_I2C_PORT = PCH_DAC -CONFIG_GFX_GMA_DEFAULT_MMIO = 16\#e000_0000\# -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I8ce31c867f97c8d6ef99ca096cb45f7719e78a19 Gerrit-Change-Number: 27138 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in ...libgfxinit[master]: gma config: Make Config.CPU and Config.CPU_Var variable
by Nico Huber (Code Review) 08 May '19

08 May '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/libgfxinit/+/27068 ) Change subject: gma config: Make Config.CPU and Config.CPU_Var variable ...................................................................... gma config: Make Config.CPU and Config.CPU_Var variable Introduce CONFIG_GFX_GMA_DYN_CPU that, if set to `y`, makes `Config.CPU` and `Config.CPU_Var` variables. All other config values derived from these are turned into expression functions. Change-Id: If409b5afbd975f3a42e28ff191a092f89ece5ae2 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/27068 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M common/Makefile.inc M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-registers.adb M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.adb M common/hw-gfx-gma.ads 6 files changed, 86 insertions(+), 19 deletions(-) Approvals: Nico Huber: Verified Patrick Georgi: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/common/Makefile.inc b/common/Makefile.inc index 11ca2c3..ba48f85 100644 --- a/common/Makefile.inc +++ b/common/Makefile.inc @@ -51,8 +51,36 @@ CONFIG_GFX_GMA_INTERNAL_PORT := $(call strip_quotes,$(CONFIG_GFX_GMA_INTERNAL_PORT)) CONFIG_GFX_GMA_ANALOG_I2C_PORT := $(call strip_quotes,$(CONFIG_GFX_GMA_ANALOG_I2C_PORT)) +_GEN_NONCONST := $(strip \ + $(if $(filter Ironlake,$(CONFIG_GFX_GMA_GENERATION)),ilk, \ + $(if $(filter Haswell,$(CONFIG_GFX_GMA_GENERATION)),hsw, \ + $(if $(filter Skylake,$(CONFIG_GFX_GMA_GENERATION)),skl)))) +# GNATprove (GPL 2017) doesn't realize when a boolean expression +# that depends both on static values and variables can be evalu- +# ated at compile time (e.g. `False and then Variable` is always +# `False` and GNAT acts appropriately). So for now, we generate +# functions instead of constant expressions for these mixed ex- +# pressions. +_GEN_CONST_TARGET := <cpufunc> # set to `constant` to generate constants. + hw-gfx-gma-config-ads := $(subst //,/,$(call src-to-obj,,$(dir)/hw-gfx-gma-config).ads) +ifeq ($(CONFIG_GFX_GMA_DYN_CPU),y) +$(hw-gfx-gma-config-ads): $(dir)/hw-gfx-gma-config.ads.template $(cnf) + printf " GENERATE $(patsubst /%,%,$(subst $(obj)/,,$@))\n" + sed -e's/<<GEN>>/$(CONFIG_GFX_GMA_GENERATION)/' \ + -e's/<<INTERNAL_PORT>>/$(CONFIG_GFX_GMA_INTERNAL_PORT)/' \ + -e's/<<ANALOG_I2C_PORT>>/$(CONFIG_GFX_GMA_ANALOG_I2C_PORT)/' \ + -e's/<<DEFAULT_MMIO_BASE>>/$(CONFIG_GFX_GMA_DEFAULT_MMIO)/' \ + -e'/constant Gen_CPU$_Var$\?/d' \ + -e's/<genbool>/constant Boolean/' \ + -e's/<$\(ilk\|hsw\|skl$$...$\?\)bool>/<\1var> Boolean/' \ + $(if $(_GEN_NONCONST),-e's/<$...$\?$(_GEN_NONCONST)$...$\?var>/<cpufunc>/') \ + -e's/<$ilk\|hsw\|skl$$...$\?var>/$(_GEN_CONST_TARGET)/' \ + -e's/$.*: *<cpufunc>.*:=$ *$.*$;/\1\n (\2);/' \ + -e's/$[^ ]\+$ *: *<cpufunc> \+$[^ ]*$ *:=/function \1 return \2 is/' \ + $< >$@ +else $(hw-gfx-gma-config-ads): $(dir)/hw-gfx-gma-config.ads.template $(cnf) printf " GENERATE $(patsubst /%,%,$(subst $(obj)/,,$@))\n" sed -e's/<<GEN>>/$(CONFIG_GFX_GMA_GENERATION)/' \ @@ -61,9 +89,12 @@ -e's/<<INTERNAL_PORT>>/$(CONFIG_GFX_GMA_INTERNAL_PORT)/' \ -e's/<<ANALOG_I2C_PORT>>/$(CONFIG_GFX_GMA_ANALOG_I2C_PORT)/' \ -e's/<<DEFAULT_MMIO_BASE>>/$(CONFIG_GFX_GMA_DEFAULT_MMIO)/' \ + -e":s$$(printf '\n ')/,$$/{N;s/,\n.*Dyn_CPU$_Var$\?[^,)]*//;ts$$(printf '\n ')P;D;}" \ + -e'/Dyn_CPU$_Var$\?/d' \ -e's/<$gen\|\(ilk\|hsw\|skl$$...$\?\)bool>/constant Boolean/' \ -e's/<$\(ilk\|hsw\|skl$$...$\?\)var>/constant/' \ $< >$@ +endif gfxinit-gen-y += $(hw-gfx-gma-config-ads) ifneq ($(filter G45,$(CONFIG_GFX_GMA_CPU)),) diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 87126d5..044036e 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -59,16 +59,22 @@ type Variable_Config is record Valid_Port : Valid_Port_Array; Raw_Clock : Frequency_Type; + Dyn_CPU : Gen_CPU_Type; + Dyn_CPU_Var : Gen_CPU_Variant; end record; Initial_Settings : constant Variable_Config := (Valid_Port => (others => False), - Raw_Clock => Frequency_Type'First); + Raw_Clock => Frequency_Type'First, + Dyn_CPU => Gen_CPU_Type'First, + Dyn_CPU_Var => Gen_CPU_Variant'First); Variable : Variable_Config with Part_Of => GMA.Config_State; Valid_Port : Valid_Port_Array renames Variable.Valid_Port; Raw_Clock : Frequency_Type renames Variable.Raw_Clock; + CPU : Gen_CPU_Type renames Variable.Dyn_CPU; + CPU_Var : Gen_CPU_Variant renames Variable.Dyn_CPU_Var; ---------------------------------------------------------------------------- @@ -303,12 +309,12 @@ ---------------------------------------------------------------------------- - GTT_PTE_Size : <hswvar> := (if Has_64bit_GTT then 8 else 4); + GTT_PTE_Size : <hswvar> Natural := (if Has_64bit_GTT then 8 else 4); - Fence_Base : <ilkvar> := + Fence_Base : <ilkvar> Natural := (if not Sandybridge_On then 16#0000_3000# else 16#0010_0000#); - Fence_Count : <ilkvar> := + Fence_Count : <ilkvar> Natural := (if not Ivybridge_On then 16 else 32); ---------------------------------------------------------------------------- diff --git a/common/hw-gfx-gma-registers.adb b/common/hw-gfx-gma-registers.adb index 838afed..380bced 100644 --- a/common/hw-gfx-gma-registers.adb +++ b/common/hw-gfx-gma-registers.adb @@ -16,8 +16,6 @@ with HW.MMIO_Range; pragma Elaborate_All (HW.MMIO_Range); -with HW.GFX.GMA.Config; - with HW.Debug; with GNAT.Source_Info; diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index 3be2ec7..ac0f023 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -14,6 +14,7 @@ with System; with HW.GFX.GMA; +with HW.GFX.GMA.Config; private package HW.GFX.GMA.Registers with @@ -1720,21 +1721,39 @@ procedure Remove_Fence (First_Page, Last_Page : GTT_Range); + pragma Warnings (GNATprove, Off, "no check message justified by this", + Reason => "see Annotate aspects."); procedure Write_GTT (GTT_Page : GTT_Range; Device_Address : GTT_Address_Type; Valid : Boolean) with - Global => (In_Out => GTT_State), - Depends => (GTT_State =>+ (GTT_Page, Device_Address, Valid)); + Global => + (Input => Config.Variable, + In_Out => GTT_State), + Depends => + (GTT_State =>+ (Config.Variable, GTT_Page, Device_Address, Valid)), + Annotate => + (GNATprove, Intentional, + """GMA.Config_State"" of ""Write_GTT"" not read", + "Reading of Config_State depends on the platform configuration."); procedure Read_GTT (Device_Address : out GTT_Address_Type; Valid : out Boolean; GTT_Page : in GTT_Range) with - Global => (In_Out => GTT_State), - Depends => ((Device_Address, Valid, GTT_State) => (GTT_State, GTT_Page)); + Global => + (Input => Config.Variable, + In_Out => GTT_State), + Depends => + ((Device_Address, Valid, GTT_State) => + (Config.Variable, GTT_State, GTT_Page)), + Annotate => + (GNATprove, Intentional, + """GMA.Config_State"" of ""Read_GTT"" not read", + "Reading of Config_State depends on the platform configuration."); + pragma Warnings (GNATprove, On, "no check message justified by this"); procedure Set_Register_Base (Base : Word64; GTT_Base : Word64 := 0) with diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 1d97adb..885072c 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -528,11 +528,11 @@ pragma Warnings (GNATprove, Off, """Registers.Register_State"" * is not modified*", - Reason => "Power_Up_VGA is only effective on certain generations."); + Reason => "Power_Up_VGA is only effective in certain configurations."); procedure Power_Up_VGA with Refined_Global => - (Input => (Cur_Configs, Time.State), + (Input => (Cur_Configs, Config.Variable, Time.State), In_Out => (Registers.Register_State), Proof_In => (Initialized)) is @@ -554,7 +554,7 @@ (GNATprove, Off, "no check message justified*", Reason => "see below"); pragma Annotate (GNATprove, Intentional, "unused global", - "Power_Up_VGA is only effective on certain generations."); + "Power_Up_VGA is only effective in certain configurations."); pragma Warnings (GNATprove, On, "no check message justified*"); pragma Warnings (GNATprove, On, """Registers.Register_State"" * is not modified*"); diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 7c40dd9..3804cd4 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -111,7 +111,7 @@ procedure Power_Up_VGA with Global => - (Input => (State, Time.State), + (Input => (State, Config_State, Time.State), In_Out => (Device_State), Proof_In => (Init_State)), Pre => Is_Initialized; @@ -160,7 +160,9 @@ Device_Address : GTT_Address_Type; Valid : Boolean) with - Global => (In_Out => Device_State, Proof_In => Init_State), + Global => + (Input => Config_State, + In_Out => Device_State, Proof_In => Init_State), Pre => Is_Initialized; procedure Read_GTT @@ -168,7 +170,9 @@ Valid : out Boolean; GTT_Page : in GTT_Range) with - Global => (In_Out => Device_State, Proof_In => Init_State), + Global => + (Input => Config_State, + In_Out => Device_State, Proof_In => Init_State), Pre => Is_Initialized; procedure Setup_Default_FB @@ -177,18 +181,27 @@ Success : out Boolean) with Global => - (In_Out => + (Input => Config_State, + In_Out => (State, Device_State, Framebuffer_Filler.State, Framebuffer_Filler.Base_Address), Proof_In => (Init_State)), Pre => Is_Initialized and HW.Config.Dynamic_MMIO; + pragma Warnings (GNATprove, Off, "no check message justified by this", + Reason => "see Annotate aspects."); procedure Map_Linear_FB (Linear_FB : out Word64; FB : in Framebuffer_Type) with Global => - (In_Out => (State, Device_State), + (Input => Config_State, + In_Out => (State, Device_State), Proof_In => (Init_State)), - Pre => Is_Initialized and HW.Config.Dynamic_MMIO; + Pre => Is_Initialized and HW.Config.Dynamic_MMIO, + Annotate => + (GNATprove, Intentional, + "global input ""GMA.Config_State"" of ""Map_Linear_FB"" not read", + "Reading of Config_State depends on the platform configuration."); + pragma Warnings (GNATprove, On, "no check message justified by this"); ---------------------------------------------------------------------------- -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: If409b5afbd975f3a42e28ff191a092f89ece5ae2 Gerrit-Change-Number: 27068 Gerrit-PatchSet: 8 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Reto Buerki <reet(a)codelabs.ch> Gerrit-MessageType: merged

1 0

Change in ...libgfxinit[master]: gma config: Tag constants depending on generation or CPU
by Nico Huber (Code Review) 08 May '19

08 May '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/libgfxinit/+/27067 ) Change subject: gma config: Tag constants depending on generation or CPU ...................................................................... gma config: Tag constants depending on generation or CPU Tag all derived config booleans that depend on the generation <genbool> and those that may depend on the CPU with the generations where that is the case. For instance `CPU_Ivybridge` can be decided purely based on the generation unless the generation is Ironlake, thus, it is tagged <ilkbool>. For non-boolean constants, per generation tags <...var> are introduced (e.g. <ilkvar>) with similar meaning. This will allow us to make them variables later, based on the generation. To ease later parsing, also move all multiline expressions after a line break. Change-Id: Iaa50987c51dc62ab2eb8b31e8f223b8a94e8ac12 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/27067 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/Makefile.inc M common/hw-gfx-gma-config.ads.template 2 files changed, 117 insertions(+), 97 deletions(-) Approvals: Nico Huber: Verified Arthur Heymans: Looks good to me, approved diff --git a/common/Makefile.inc b/common/Makefile.inc index 410eeba..11ca2c3 100644 --- a/common/Makefile.inc +++ b/common/Makefile.inc @@ -61,6 +61,8 @@ -e's/<<INTERNAL_PORT>>/$(CONFIG_GFX_GMA_INTERNAL_PORT)/' \ -e's/<<ANALOG_I2C_PORT>>/$(CONFIG_GFX_GMA_ANALOG_I2C_PORT)/' \ -e's/<<DEFAULT_MMIO_BASE>>/$(CONFIG_GFX_GMA_DEFAULT_MMIO)/' \ + -e's/<$gen\|\(ilk\|hsw\|skl$$...$\?\)bool>/constant Boolean/' \ + -e's/<$\(ilk\|hsw\|skl$$...$\?\)var>/constant/' \ $< >$@ gfxinit-gen-y += $(hw-gfx-gma-config-ads) diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index d12a9f1..87126d5 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -72,29 +72,46 @@ ---------------------------------------------------------------------------- - Gen_G45 : constant Boolean := Gen = G45; - Gen_Ironlake : constant Boolean := Gen = Ironlake; - Gen_Haswell : constant Boolean := Gen = Haswell; - Gen_Broxton : constant Boolean := Gen = Broxton; - Gen_Skylake : constant Boolean := Gen = Skylake; + -- To support both static configurations, that are compiled for a + -- fixed CPU, and dynamic configurations, where the CPU and its + -- variant are detected at runtime, all derived config values are + -- tagged based on their dependencies. + -- + -- Booleans that only depend on the generation should be tagged + -- <genbool>. Those that may depend on the CPU are tagged with the + -- generations where that is the case. For instance `CPU_Ivybridge` + -- can be decided purely based on the generation unless the gene- + -- ration is Ironlake, thus, it is tagged <ilkbool>. + -- + -- For non-boolean constants, per generation tags <...var> are + -- used (e.g. <ilkvar>). + -- + -- To ease parsing, all multiline expressions of tagged config + -- values start after a line break. - Up_To_Ironlake : constant Boolean := Gen <= Ironlake; - Ironlake_On : constant Boolean := Gen >= Ironlake; - Haswell_On : constant Boolean := Gen >= Haswell; - Broxton_On : constant Boolean := Gen >= Broxton; - Skylake_On : constant Boolean := Gen >= Skylake; + Gen_G45 : <genbool> := Gen = G45; + Gen_Ironlake : <genbool> := Gen = Ironlake; + Gen_Haswell : <genbool> := Gen = Haswell; + Gen_Broxton : <genbool> := Gen = Broxton; + Gen_Skylake : <genbool> := Gen = Skylake; - CPU_Ironlake : constant Boolean := Gen_Ironlake and then CPU = Ironlake; - CPU_Sandybridge : constant Boolean := Gen_Ironlake and then CPU = Sandybridge; - CPU_Ivybridge : constant Boolean := Gen_Ironlake and then CPU = Ivybridge; - CPU_Haswell : constant Boolean := Gen_Haswell and then CPU = Haswell; - CPU_Broadwell : constant Boolean := Gen_Haswell and then CPU = Broadwell; + Up_To_Ironlake : <genbool> := Gen <= Ironlake; + Ironlake_On : <genbool> := Gen >= Ironlake; + Haswell_On : <genbool> := Gen >= Haswell; + Broxton_On : <genbool> := Gen >= Broxton; + Skylake_On : <genbool> := Gen >= Skylake; - Sandybridge_On : constant Boolean := + CPU_Ironlake : <ilkbool> := Gen_Ironlake and then CPU = Ironlake; + CPU_Sandybridge : <ilkbool> := Gen_Ironlake and then CPU = Sandybridge; + CPU_Ivybridge : <ilkbool> := Gen_Ironlake and then CPU = Ivybridge; + CPU_Haswell : <hswbool> := Gen_Haswell and then CPU = Haswell; + CPU_Broadwell : <hswbool> := Gen_Haswell and then CPU = Broadwell; + + Sandybridge_On : <ilkbool> := ((Gen_Ironlake and then CPU >= Sandybridge) or Haswell_On); - Ivybridge_On : constant Boolean := + Ivybridge_On : <ilkbool> := ((Gen_Ironlake and then CPU >= Ivybridge) or Haswell_On); - Broadwell_On : constant Boolean := + Broadwell_On : <hswbool> := ((Gen_Haswell and then CPU >= Broadwell) or Broxton_On); ---------------------------------------------------------------------------- @@ -106,108 +123,108 @@ Internal_Is_LVDS : constant Boolean := Internal_Display = LVDS; Internal_Is_EDP : constant Boolean := Internal_Display = DP; Have_DVI_I : constant Boolean := Analog_I2C_Port /= PCH_DAC; - Has_Presence_Straps : constant Boolean := not Gen_Broxton; - Is_ULT : constant Boolean := + + Has_Presence_Straps : <genbool> := not Gen_Broxton; + Is_ULT : <hswsklbool> := ((Gen_Haswell or Gen_Skylake) and then CPU_Var = ULT); - ----- CPU pipe: -------- - Has_Tertiary_Pipe : constant Boolean := Ivybridge_On; - Disable_Trickle_Feed : constant Boolean := not Gen_Haswell; - Pipe_Enabled_Workaround : constant Boolean := CPU_Broadwell; - Has_EDP_Transcoder : constant Boolean := Haswell_On; - Use_PDW_For_EDP_Scaling : constant Boolean := CPU_Haswell; - Has_Pipe_DDI_Func : constant Boolean := Haswell_On; - Has_Trans_Clk_Sel : constant Boolean := Haswell_On; - Has_Pipe_MSA_Misc : constant Boolean := Haswell_On; - Has_Pipeconf_Misc : constant Boolean := Broadwell_On; - Has_Pipeconf_BPC : constant Boolean := not CPU_Haswell; - Has_Plane_Control : constant Boolean := Broxton_On; - Has_DSP_Linoff : constant Boolean := Up_To_Ironlake; - Has_PF_Pipe_Select : constant Boolean := CPU_Ivybridge or CPU_Haswell; - Has_Cursor_FBC_Control : constant Boolean := Ivybridge_On; - VGA_Plane_Workaround : constant Boolean := CPU_Ivybridge; - Has_GMCH_DP_Transcoder : constant Boolean := Gen_G45; - Has_GMCH_VGACNTRL : constant Boolean := Gen_G45; - Has_GMCH_PFIT_CONTROL : constant Boolean := Gen_G45; + ---------- CPU pipe: --------- + Has_Tertiary_Pipe : <ilkbool> := Ivybridge_On; + Disable_Trickle_Feed : <genbool> := not Gen_Haswell; + Pipe_Enabled_Workaround : <hswbool> := CPU_Broadwell; + Has_EDP_Transcoder : <genbool> := Haswell_On; + Use_PDW_For_EDP_Scaling : <hswbool> := CPU_Haswell; + Has_Pipe_DDI_Func : <genbool> := Haswell_On; + Has_Trans_Clk_Sel : <genbool> := Haswell_On; + Has_Pipe_MSA_Misc : <genbool> := Haswell_On; + Has_Pipeconf_Misc : <hswbool> := Broadwell_On; + Has_Pipeconf_BPC : <hswbool> := not CPU_Haswell; + Has_Plane_Control : <genbool> := Broxton_On; + Has_DSP_Linoff : <genbool> := Up_To_Ironlake; + Has_PF_Pipe_Select : <ilkhswbool> := CPU_Ivybridge or CPU_Haswell; + Has_Cursor_FBC_Control : <ilkbool> := Ivybridge_On; + VGA_Plane_Workaround : <ilkbool> := CPU_Ivybridge; + Has_GMCH_DP_Transcoder : <genbool> := Gen_G45; + Has_GMCH_VGACNTRL : <genbool> := Gen_G45; + Has_GMCH_PFIT_CONTROL : <genbool> := Gen_G45; - ----- Panel power: ----- - Has_PP_Write_Protection : constant Boolean := Up_To_Ironlake; - Has_PP_Port_Select : constant Boolean := Up_To_Ironlake; - Use_PP_VDD_Override : constant Boolean := Up_To_Ironlake; - Has_PCH_Panel_Power : constant Boolean := Ironlake_On; + --------- Panel power: ------- + Has_PP_Write_Protection : <genbool> := Up_To_Ironlake; + Has_PP_Port_Select : <genbool> := Up_To_Ironlake; + Use_PP_VDD_Override : <genbool> := Up_To_Ironlake; + Has_PCH_Panel_Power : <genbool> := Ironlake_On; - ----- PCH/FDI: --------- - Has_PCH : constant Boolean := not Gen_Broxton and not Gen_G45; - Has_PCH_DAC : constant Boolean := + ----------- PCH/FDI: --------- + Has_PCH : <genbool> := not Gen_Broxton and not Gen_G45; + Has_PCH_DAC : <hswbool> := (Gen_Ironlake or (Gen_Haswell and then not Is_ULT)); - Has_PCH_Aux_Channels : constant Boolean := Gen_Ironlake or Gen_Haswell; + Has_PCH_Aux_Channels : <genbool> := Gen_Ironlake or Gen_Haswell; - VGA_Has_Sync_Disable : constant Boolean := Up_To_Ironlake; + VGA_Has_Sync_Disable : <genbool> := Up_To_Ironlake; - Has_Trans_Timing_Ovrrde : constant Boolean := Sandybridge_On; + Has_Trans_Timing_Ovrrde : <ilkbool> := Sandybridge_On; - Has_DPLL_SEL : constant Boolean := Gen_Ironlake; - Has_FDI_BPC : constant Boolean := Gen_Ironlake; - Has_FDI_Composite_Sel : constant Boolean := CPU_Ivybridge; - Has_New_FDI_Sink : constant Boolean := Sandybridge_On; - Has_New_FDI_Source : constant Boolean := Ivybridge_On; - Has_Trans_DP_Ctl : constant Boolean := CPU_Sandybridge or CPU_Ivybridge; - Has_FDI_C : constant Boolean := CPU_Ivybridge; + Has_DPLL_SEL : <genbool> := Gen_Ironlake; + Has_FDI_BPC : <genbool> := Gen_Ironlake; + Has_FDI_Composite_Sel : <ilkbool> := CPU_Ivybridge; + Has_New_FDI_Sink : <ilkbool> := Sandybridge_On; + Has_New_FDI_Source : <ilkbool> := Ivybridge_On; + Has_Trans_DP_Ctl : <ilkbool> := CPU_Sandybridge or CPU_Ivybridge; + Has_FDI_C : <ilkbool> := CPU_Ivybridge; - Has_FDI_RX_Power_Down : constant Boolean := Gen_Haswell; + Has_FDI_RX_Power_Down : <genbool> := Gen_Haswell; - Has_GMCH_RawClk : constant Boolean := Gen_G45; + Has_GMCH_RawClk : <genbool> := Gen_G45; - ----- DDI: ------------- - End_EDP_Training_Late : constant Boolean := Gen_Haswell; - Has_Per_DDI_Clock_Sel : constant Boolean := Gen_Haswell; - Has_HOTPLUG_CTL : constant Boolean := Gen_Haswell; - Has_SHOTPLUG_CTL_A : constant Boolean := + ----------- DDI: ------------- + End_EDP_Training_Late : <genbool> := Gen_Haswell; + Has_Per_DDI_Clock_Sel : <genbool> := Gen_Haswell; + Has_HOTPLUG_CTL : <genbool> := Gen_Haswell; + Has_SHOTPLUG_CTL_A : <hswbool> := ((Gen_Haswell and then Is_ULT) or Skylake_On); - Has_DDI_PHYs : constant Boolean := Gen_Broxton; + Has_DDI_PHYs : <genbool> := Gen_Broxton; - Has_DDI_D : constant Boolean := + Has_DDI_D : <hswsklbool> := ((Gen_Haswell or Gen_Skylake) and then not Is_ULT); - Has_DDI_E : constant Boolean := -- might be disabled by x4 eDP - Has_DDI_D; + -- might be disabled by x4 eDP: + Has_DDI_E : <hswsklbool> := Has_DDI_D; - Has_DDI_Buffer_Trans : constant Boolean := Haswell_On and - not Gen_Broxton; - Has_Low_Voltage_Swing : constant Boolean := Broxton_On; - Has_Iboost_Config : constant Boolean := Skylake_On; + Has_DDI_Buffer_Trans : <genbool> := Haswell_On and not Has_DDI_PHYs; + Has_Low_Voltage_Swing : <genbool> := Broxton_On; + Has_Iboost_Config : <genbool> := Skylake_On; - Need_DP_Aux_Mutex : constant Boolean := False; -- Skylake & (PSR | GTC) + Need_DP_Aux_Mutex : <genbool> := False; -- Skylake & (PSR | GTC) - ----- GMBUS: ----------- - Ungate_GMBUS_Unit_Level : constant Boolean := Skylake_On; - GMBUS_Alternative_Pins : constant Boolean := Gen_Broxton; - Has_PCH_GMBUS : constant Boolean := Ironlake_On; + ----------- GMBUS: ----------- + Ungate_GMBUS_Unit_Level : <genbool> := Skylake_On; + GMBUS_Alternative_Pins : <genbool> := Gen_Broxton; + Has_PCH_GMBUS : <genbool> := Ironlake_On; - ----- Power: ----------- - Has_IPS : constant Boolean := + ----------- Power: ----------- + Has_IPS : <hswbool> := (Gen_Haswell and then ((CPU_Haswell and Is_ULT) or CPU_Broadwell)); - Has_IPS_CTL_Mailbox : constant Boolean := CPU_Broadwell; + Has_IPS_CTL_Mailbox : <hswbool> := CPU_Broadwell; - Has_Per_Pipe_SRD : constant Boolean := Broadwell_On; + Has_Per_Pipe_SRD : <hswbool> := Broadwell_On; - ----- GTT: ------------- - Has_64bit_GTT : constant Boolean := Broadwell_On; + ----------- GTT: ------------- + Has_64bit_GTT : <hswbool> := Broadwell_On; ---------------------------------------------------------------------------- - Max_Pipe : constant Pipe_Index := + Max_Pipe : <ilkvar> Pipe_Index := (if Has_Tertiary_Pipe then Tertiary else Secondary); - Last_Digital_Port : constant Digital_Port := + Last_Digital_Port : <hswsklvar> Digital_Port := (if Has_DDI_E then DIGI_E else DIGI_C); ---------------------------------------------------------------------------- type FDI_Per_Port is array (Port_Type) of Boolean; - Is_FDI_Port : constant FDI_Per_Port := + Is_FDI_Port : <hswvar> FDI_Per_Port := (Disabled => False, Internal => Gen_Ironlake and Internal_Is_LVDS, DP1 .. HDMI3 => Gen_Ironlake, @@ -218,14 +235,14 @@ (DIGI_D => DP_Lane_Count_2, others => (if Gen_Ironlake then DP_Lane_Count_4 else DP_Lane_Count_2)); - FDI_Training : constant FDI_Training_Type := + FDI_Training : <ilkvar> FDI_Training_Type := (if CPU_Ironlake then Simple_Training elsif CPU_Sandybridge then Full_Training else Auto_Training); ---------------------------------------------------------------------------- - Default_DDI_HDMI_Buffer_Translation : constant DDI_HDMI_Buf_Trans_Range := + Default_DDI_HDMI_Buffer_Translation : <hswvar> DDI_HDMI_Buf_Trans_Range := (if CPU_Haswell then 6 elsif CPU_Broadwell then 7 elsif Broxton_On then 8 @@ -233,7 +250,7 @@ ---------------------------------------------------------------------------- - Default_CDClk_Freq : constant Frequency_Type := + Default_CDClk_Freq : <ilkvar> Frequency_Type := (if Gen_G45 then 320_000_000 -- unused elsif CPU_Ironlake or Gen_Haswell then 450_000_000 elsif CPU_Sandybridge or CPU_Ivybridge then 400_000_000 @@ -241,7 +258,7 @@ elsif Gen_Skylake then 337_500_000 else Frequency_Type'First); - Default_RawClk_Freq : constant Frequency_Type := + Default_RawClk_Freq : <hswvar> Frequency_Type := (if Gen_G45 then 100_000_000 -- unused, depends on FSB elsif Gen_Ironlake then 125_000_000 elsif Gen_Haswell then (if Is_ULT then 24_000_000 else 125_000_000) @@ -256,7 +273,7 @@ type Width_Per_Pipe is array (Pipe_Index) of Width_Type; - Maximum_Scalable_Width : constant Width_Per_Pipe := + Maximum_Scalable_Width : <hswvar> Width_Per_Pipe := (if Gen_G45 then -- TODO: Is this true? (Primary => 4096, Secondary => 2048, @@ -271,9 +288,10 @@ Tertiary => 4096)); -- Maximum X position of hardware cursors - Maximum_Cursor_X : constant := (case Gen is - when G45 .. Ironlake => 4095, - when Haswell .. Skylake => 8191); + Maximum_Cursor_X : constant := + (case Gen is + when G45 .. Ironlake => 4095, + when Haswell .. Skylake => 8191); Maximum_Cursor_Y : constant := 4095; @@ -285,12 +303,12 @@ ---------------------------------------------------------------------------- - GTT_PTE_Size : constant := (if Has_64bit_GTT then 8 else 4); + GTT_PTE_Size : <hswvar> := (if Has_64bit_GTT then 8 else 4); - Fence_Base : constant := + Fence_Base : <ilkvar> := (if not Sandybridge_On then 16#0000_3000# else 16#0010_0000#); - Fence_Count : constant := + Fence_Count : <ilkvar> := (if not Ivybridge_On then 16 else 32); ---------------------------------------------------------------------------- -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Iaa50987c51dc62ab2eb8b31e8f223b8a94e8ac12 Gerrit-Change-Number: 27067 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...libgfxinit[master]: gma config: Initialize stateful configs late
by Nico Huber (Code Review) 08 May '19

08 May '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/libgfxinit/+/27066 ) Change subject: gma config: Initialize stateful configs late ...................................................................... gma config: Initialize stateful configs late Defer initialization of config variables until GMA.Initialize(). Change-Id: I9192c9a7c4d67e4af7f3e26659489f58998ae832 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/27066 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma.adb M common/hw-gfx-gma.ads 3 files changed, 13 insertions(+), 19 deletions(-) Approvals: Nico Huber: Verified Arthur Heymans: Looks good to me, approved diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index ea42443..d12a9f1 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -12,10 +12,7 @@ -- GNU General Public License for more details. -- -private package HW.GFX.GMA.Config -with - Initializes => Variable -is +private package HW.GFX.GMA.Config is Gen : constant Generation := <<GEN>>; @@ -64,11 +61,11 @@ Raw_Clock : Frequency_Type; end record; - Variable : Variable_Config := + Initial_Settings : constant Variable_Config := (Valid_Port => (others => False), - Raw_Clock => Frequency_Type'First) - with - Part_Of => GMA.Config_State; + Raw_Clock => Frequency_Type'First); + + Variable : Variable_Config with Part_Of => GMA.Config_State; Valid_Port : Valid_Port_Array renames Variable.Valid_Port; Raw_Clock : Frequency_Type renames Variable.Raw_Clock; diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index b62ebce..1d97adb 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -370,13 +370,11 @@ Success : out Boolean) with Refined_Global => - (In_Out => - (Config.Variable, Dev.PCI_State, - Registers.Register_State, Port_IO.State), - Input => - (Time.State), + (Input => (Time.State), + In_Out => (Dev.PCI_State, Registers.Register_State, Port_IO.State), Output => - (Dev.Address_State, + (Config.Variable, + Dev.Address_State, Registers.Address_State, PLLs.State, Panel.Panel_State, Cur_Configs, Allocated_PLLs, @@ -444,6 +442,7 @@ Framebuffer => HW.GFX.Default_FB, Cursor => Default_Cursor, Mode => HW.GFX.Invalid_Mode)); + Config.Variable := Config.Initial_Settings; PLLs.Initialize; Dev.Initialize (Success); diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index db7f2bf..7c40dd9 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -25,9 +25,7 @@ Init_State, Config_State, (Device_State with External)), - Initializes => - (Init_State, - Config_State) + Initializes => Init_State is GTT_Page_Size : constant := 4096; @@ -101,8 +99,8 @@ Success : out Boolean) with Global => - (In_Out => (Config_State, Device_State, Port_IO.State), - Output => (State, Init_State), + (In_Out => (Device_State, Port_IO.State), + Output => (State, Init_State, Config_State), Input => (Time.State)), Post => Success = Is_Initialized; function Is_Initialized return Boolean -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I9192c9a7c4d67e4af7f3e26659489f58998ae832 Gerrit-Change-Number: 27066 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit May 2019