coreboot-gerrit May 2019

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Change in ...coreboot[master]: {src,util}: Remove duplicated includes
by HAOUAS Elyes (Code Review) 07 May '19

07 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32566 Change subject: {src,util}: Remove duplicated includes ...................................................................... {src,util}: Remove duplicated includes Change-Id: Id09cec6b2aae58b131b208e96fec539d068ff68a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/sandybridge/raminit_common.c M util/cbmem/cbmem.c M util/ectool/ectool.c M util/romcc/romcc.c 4 files changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/32566/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index cbbd231..5347c5c 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -23,7 +23,7 @@ #include <northbridge/intel/sandybridge/chip.h> #include <device/pci_def.h> #include <delay.h> -#include <arch/cpu.h> + #include "raminit_native.h" #include "raminit_common.h" #include "sandybridge.h" diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index ae1d212..52fdc9b 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -19,7 +19,6 @@ #include <stdlib.h> #include <string.h> #include <unistd.h> -#include <inttypes.h> #include <getopt.h> #include <dirent.h> #include <errno.h> diff --git a/util/ectool/ectool.c b/util/ectool/ectool.c index bc3d46c..2af45c3 100644 --- a/util/ectool/ectool.c +++ b/util/ectool/ectool.c @@ -22,7 +22,6 @@ #include <sys/io.h> #endif #include <ec.h> -#include <stdlib.h> #if defined __NetBSD__ || defined __OpenBSD__ diff --git a/util/romcc/romcc.c b/util/romcc/romcc.c index 4cb2aad..43be171 100644 --- a/util/romcc/romcc.c +++ b/util/romcc/romcc.c @@ -16,7 +16,6 @@ #include <sys/stat.h> #include <fcntl.h> #include <unistd.h> -#include <stdio.h> #include <string.h> #include <limits.h> #include <locale.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/32566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id09cec6b2aae58b131b208e96fec539d068ff68a Gerrit-Change-Number: 32566 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/stoneyridge: Finish read/write misc registers
by Martin Roth (Code Review) 07 May '19

07 May '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32646 ) Change subject: soc/amd/stoneyridge: Finish read/write misc registers ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I296c521ea7f43210db406013bbe79362545ce6f3 Gerrit-Change-Number: 32646 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 07 May 2019 16:14:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/lenovo/t520: Add SMBIOS type 9 fields
by Patrick Rudolph (Code Review) 07 May '19

07 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32309 Change subject: mb/lenovo/t520: Add SMBIOS type 9 fields ...................................................................... mb/lenovo/t520: Add SMBIOS type 9 fields Change-Id: I43fb481512a54ee054c6fd0189053028fb3c3ec2 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/t520/variants/t520/devicetree.cb 1 file changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/32309/1 diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb index cf8e7ce..88495fb 100644 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb @@ -78,9 +78,17 @@ device pci 1a.0 on end # USB2 EHCI #2 device pci 1b.0 on end # High Definition Audio device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN + device pci 1c.1 on + slot_designation "Below keyboard" + slot_type "21" + slot_data_width "8" + end # PCIe Port #2 Integrated Wireless LAN device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 Express Card + device pci 1c.3 on + slot_designation "Right side" + slot_type "7" + slot_data_width "8" + end # PCIe Port #4 Express Card device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394 device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY device pci 1c.6 off end # PCIe Port #7 USB 3.0 only W520 -- To view, visit https://review.coreboot.org/c/coreboot/+/32309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43fb481512a54ee054c6fd0189053028fb3c3ec2 Gerrit-Change-Number: 32309 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Add SMBIOS type 9 fields
by Patrick Georgi (Code Review) 07 May '19

07 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32389 ) Change subject: mb/google/sarien: Add SMBIOS type 9 fields ...................................................................... mb/google/sarien: Add SMBIOS type 9 fields Fill SMBIOS type 9 fields for both sarien and arcada platform. BUG=b:129485789 TEST=Boot up into OS and check with dmidecode -t 9 to we do have entry. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e Reviewed-on: https://review.coreboot.org/c/coreboot/+/32389 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/soc/intel/cannonlake/chip.h 3 files changed, 13 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved HAOUAS Elyes: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 77bd82a..0cc9970 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -349,11 +349,15 @@ device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 on end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on end # PCI Express Port 13 (x4) + device pci 1d.4 on + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index e9786f1..3807047 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -378,11 +378,15 @@ device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 on end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" + end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on end # PCI Express Port 13 (x4) + device pci 1d.4 on + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" + end # PCI Express Port 13 (x4) device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 40d9f71..b17df4b 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -21,6 +21,7 @@ #include <intelblocks/chip.h> #include <drivers/i2c/designware/dw_i2c.h> #include <intelblocks/gspi.h> +#include <smbios.h> #include <stdint.h> #include <soc/gpio.h> #include <soc/pch.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/32389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e Gerrit-Change-Number: 32389 Gerrit-PatchSet: 6 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/sarien: Add SMBIOS type 9 fields
by Patrick Georgi (Code Review) 07 May '19

07 May '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32389 ) Change subject: mb/google/sarien: Add SMBIOS type 9 fields ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e Gerrit-Change-Number: 32389 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 07 May 2019 16:06:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP]smbios: Walk over PCI devicetree to fill type 9
by Patrick Rudolph (Code Review) 07 May '19

07 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32308 Change subject: [WIP]smbios: Walk over PCI devicetree to fill type 9 ...................................................................... [WIP]smbios: Walk over PCI devicetree to fill type 9 Use the devicetree values for type 9 slots. Change-Id: I1961d8af2d21f755ff52ad58804ea9b31d2a5b9b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/smbios.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/32308/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 10feb15..c565462 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -996,6 +996,19 @@ dev_name(dev)); len += dev->ops->get_smbios_data(dev, handle, current); } + if (dev->path.type == DEVICE_PATH_PCI) { + if (dev->smbios_slot_type || + dev->smbios_slot_data_width || + dev->smbios_slot_designation) { + len += smbios_write_type9(current, handle, + dev->smbios_slot_designation, + dev->smbios_slot_type, + 1, + 0, + dev->bus->secondary, + dev->path.pci.devfn); + } + } } return len; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1961d8af2d21f755ff52ad58804ea9b31d2a5b9b Gerrit-Change-Number: 32308 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: device: ignore NONE devices behind bridge
by Patrick Rudolph (Code Review) 07 May '19

07 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32441 Change subject: device: ignore NONE devices behind bridge ...................................................................... device: ignore NONE devices behind bridge Ignore NONE devices in dev_is_active_bridge that are commonly used to indicate hotplug capable ports. Tested on Lenovo T520: The empty ExpressCard Slot is no longer marked as active bridge. Change-Id: I23347270aaab17647023969091ce4bcdd41dd57a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/device/device_util.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/32441/1 diff --git a/src/device/device_util.c b/src/device/device_util.c index 5c4f911..47df305 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -628,7 +628,7 @@ /* * Returns true if the device is an enabled bridge that has at least - * one enabled device on its secondary bus. + * one enabled device on its secondary bus that is not of type NONE. */ bool dev_is_active_bridge(struct device *dev) { @@ -643,6 +643,9 @@ for (link = dev->link_list; link; link = link->next) { for (child = link->children; child; child = child->sibling) { + if (child->path.type == DEVICE_PATH_NONE) + continue; + if (child->enabled) return 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23347270aaab17647023969091ce4bcdd41dd57a Gerrit-Change-Number: 32441 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP]sconfig: Add SMBIOS type 9 entries
by Patrick Rudolph (Code Review) 07 May '19

07 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32307 Change subject: [WIP]sconfig: Add SMBIOS type 9 entries ...................................................................... [WIP]sconfig: Add SMBIOS type 9 entries Add the new fields: * slot_type that corresponds to SMBIOS type 9 'Slot Type' * slot_data_width that corresponds to SMBIOS type 9 'Slot Data Bus Width' Runtime code will be able to iterate over the PCI tree and fill in 'Bus Number', 'Device/Function', 'Slot Data Bus Width', 'Slot Type' and 'Current Usage'. Change-Id: If95aae3c322d3da47637613b9a872ba1f7af9080 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/include/device/device.h M util/sconfig/main.c M util/sconfig/sconfig.h M util/sconfig/sconfig.l M util/sconfig/sconfig.y 5 files changed, 127 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32307/1 diff --git a/src/include/device/device.h b/src/include/device/device.h index 39a4d56..32c41a4 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -141,6 +141,11 @@ #if !DEVTREE_EARLY struct chip_operations *chip_ops; const char *name; +#if CONFIG(GENERATE_SMBIOS_TABLES) + u8 smbios_slot_type; + u8 smbios_slot_data_width; + const char* smbios_slot_designation; +#endif #endif DEVTREE_CONST void *chip_info; }; diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 4ac935e..22dfa59 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -622,6 +622,43 @@ } } +void add_slot_type(struct bus *bus, char *val) +{ + + struct device *dev = bus->dev; + + if (dev->bustype != PCI && dev->bustype != DOMAIN) { + printf("ERROR: 'slot_type' only allowed for PCI devices\n"); + exit(1); + } + + dev->smbios_slot_type = val; +} + +void add_slot_data_width(struct bus *bus, char *val) +{ + struct device *dev = bus->dev; + + if (dev->bustype != PCI && dev->bustype != DOMAIN) { + printf("ERROR: 'slot_data_width' only allowed for PCI devices\n"); + exit(1); + } + + dev->smbios_slot_data_width = val; +} + +void add_slot_designation(struct bus *bus, char *val) +{ + struct device *dev = bus->dev; + + if (dev->bustype != PCI && dev->bustype != DOMAIN) { + printf("ERROR: 'slot_designation' only allowed for PCI devices\n"); + exit(1); + } + + dev->smbios_slot_designation = val; +} + void add_pci_subsystem_ids(struct bus *bus, int vendor, int device, int inherit) { @@ -831,7 +868,26 @@ fprintf(fil, "\t.chip_info = &%s_info_%d,\n", chip_ins->chip->name_underscore, chip_ins->id); if (next) - fprintf(fil, "\t.next=&%s\n", next->name); + fprintf(fil, "\t.next=&%s,\n", next->name); + if (ptr->smbios_slot_type || ptr->smbios_slot_data_width || + ptr->smbios_slot_designation) { + fprintf(fil, "#if !DEVTREE_EARLY\n"); + fprintf(fil, "#if CONFIG(GENERATE_SMBIOS_TABLES)\n"); + } + /* SMBIOS types start at 1, if zero it hasn't been set */ + if (ptr->smbios_slot_type) + fprintf(fil, "\t.smbios_slot_type = %s,\n", + ptr->smbios_slot_type); + if (ptr->smbios_slot_data_width) + fprintf(fil, "\t.smbios_slot_data_width = %s,\n", + ptr->smbios_slot_data_width); + if (ptr->smbios_slot_designation) + fprintf(fil, "\t.smbios_slot_designation = %s,\n", + ptr->smbios_slot_designation); + if (ptr->smbios_slot_type || ptr->smbios_slot_data_width) { + fprintf(fil, "#endif\n"); + fprintf(fil, "#endif\n"); + } fprintf(fil, "};\n"); emit_resources(fil, ptr); diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index 389d697..6abb90f 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -141,6 +141,15 @@ struct bus *bus; /* Pointer to last bus under this device. */ struct bus *last_bus; + + /* SMBIOS slot type */ + char *smbios_slot_type; + + /* SMBIOS slot data width */ + char *smbios_slot_data_width; + + /* SMBIOS slot description for reference designation */ + char *smbios_slot_designation; }; extern struct bus *root_parent; @@ -158,6 +167,12 @@ void add_ioapic_info(struct bus *bus, int apicid, const char *_srcpin, int irqpin); +void add_slot_type(struct bus *bus, char *val); + +void add_slot_data_width(struct bus *bus, char *val); + +void add_slot_designation(struct bus *bus, char *val); + void yyrestart(FILE *input_file); /* Add chip data to tail of queue. */ diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l index b21cca5..491eab9 100755 --- a/util/sconfig/sconfig.l +++ b/util/sconfig/sconfig.l @@ -21,40 +21,43 @@ %} %option nodebug %% -[ \t]+ {} -#.*\n {linenum++;} -\r?\n {linenum++;} -chip {return(CHIP);} -device {return(DEVICE);} -register {return(REGISTER);} -on {yylval.number=1; return(BOOL);} -off {yylval.number=0; return(BOOL);} -hidden {yylval.number=3; return(HIDDEN);} -pci {yylval.number=PCI; return(BUS);} -ioapic {yylval.number=IOAPIC; return(BUS);} -pnp {yylval.number=PNP; return(BUS);} -i2c {yylval.number=I2C; return(BUS);} -lapic {yylval.number=APIC; return(BUS);} -cpu_cluster {yylval.number=CPU_CLUSTER; return(BUS);} -cpu {yylval.number=CPU; return(BUS);} -domain {yylval.number=DOMAIN; return(BUS);} -generic {yylval.number=GENERIC; return(BUS);} -mmio {yylval.number=MMIO; return(BUS);} -spi {yylval.number=SPI; return(BUS);} -usb {yylval.number=USB; return(BUS);} -irq {yylval.number=IRQ; return(RESOURCE);} -drq {yylval.number=DRQ; return(RESOURCE);} -io {yylval.number=IO; return(RESOURCE);} -ioapic_irq {return(IOAPIC_IRQ);} -inherit {return(INHERIT);} -subsystemid {return(SUBSYSTEMID);} -end {return(END);} -= {return(EQUALS);} -0x[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} -[0-9.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} -[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} -INT[A-D] {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} -\"\"[^\"]+\"\" {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} -\"[^\"]+\" {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} -[^ \n\t]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} +[ \t]+ {} +#.*\n {linenum++;} +\r?\n {linenum++;} +chip {return(CHIP);} +device {return(DEVICE);} +register {return(REGISTER);} +on {yylval.number=1; return(BOOL);} +off {yylval.number=0; return(BOOL);} +hidden {yylval.number=3; return(HIDDEN);} +pci {yylval.number=PCI; return(BUS);} +ioapic {yylval.number=IOAPIC; return(BUS);} +pnp {yylval.number=PNP; return(BUS);} +i2c {yylval.number=I2C; return(BUS);} +lapic {yylval.number=APIC; return(BUS);} +cpu_cluster {yylval.number=CPU_CLUSTER; return(BUS);} +cpu {yylval.number=CPU; return(BUS);} +domain {yylval.number=DOMAIN; return(BUS);} +generic {yylval.number=GENERIC; return(BUS);} +mmio {yylval.number=MMIO; return(BUS);} +spi {yylval.number=SPI; return(BUS);} +usb {yylval.number=USB; return(BUS);} +irq {yylval.number=IRQ; return(RESOURCE);} +drq {yylval.number=DRQ; return(RESOURCE);} +io {yylval.number=IO; return(RESOURCE);} +ioapic_irq {return(IOAPIC_IRQ);} +inherit {return(INHERIT);} +subsystemid {return(SUBSYSTEMID);} +end {return(END);} +slot_type {return(SLOT_TYPE);} +slot_data_width {return(SLOT_DATA_WIDTH);} +slot_designation {return(SLOT_DESIGNATION);} += {return(EQUALS);} +0x[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +[0-9.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +[0-9a-fA-F.]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +INT[A-D] {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} +\"\"[^\"]+\"\" {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +\"[^\"]+\" {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +[^ \n\t]+ {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} %% diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index 3a6e9ab..cbb8be5 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -31,13 +31,13 @@ int number; } -%token CHIP DEVICE REGISTER BOOL HIDDEN BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO +%token CHIP DEVICE REGISTER BOOL HIDDEN BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESIGNATION SLOT_TYPE SLOT_DATA_WIDTH IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO %% devtree: { cur_parent = root_parent; } chip; chipchildren: chipchildren device | chipchildren chip | chipchildren registers | /* empty */ ; -devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | /* empty */ ; +devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | devicechildren slot_type | devicechildren slot_data_width | devicechildren slot_designation | /* empty */ ; chip: CHIP STRING /* == path */ { $<chip_instance>$ = new_chip_instance($<string>2); @@ -72,4 +72,13 @@ ioapic_irq: IOAPIC_IRQ NUMBER PCIINT NUMBER { add_ioapic_info(cur_parent, strtol($<string>2, NULL, 16), $<string>3, strtol($<string>4, NULL, 16)); }; + +slot_designation: SLOT_DESIGNATION STRING + { add_slot_designation(cur_parent, $<string>2); }; + +slot_type: SLOT_TYPE STRING + { add_slot_type(cur_parent, $<string>2); }; + +slot_data_width: SLOT_DATA_WIDTH STRING + { add_slot_data_width(cur_parent, $<string>2); }; %% -- To view, visit https://review.coreboot.org/c/coreboot/+/32307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If95aae3c322d3da47637613b9a872ba1f7af9080 Gerrit-Change-Number: 32307 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/bd82x6x: Fix flashconsole after lockdown
by Patrick Georgi (Code Review) 07 May '19

07 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/25660 ) Change subject: sb/intel/bd82x6x: Fix flashconsole after lockdown ...................................................................... sb/intel/bd82x6x: Fix flashconsole after lockdown SMM final locks the SPI BAR, which causes flashconsole to hang. Re-init it like SMM does with CONFIG_SPI_FLASH_SMM. Change-Id: Ib802d7ee32f1fb0a68a84b0280480dcaefa9831f Signed-off-by: Dan Elkouby <streetwalkermc(a)gmail.com> Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25660 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/bd82x6x/lpc.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index e9e4964..f7bb7e4 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -908,6 +908,12 @@ if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) { outb(APM_CNT_FINALIZE, APM_CNT); + if (CONFIG(CONSOLE_SPI_FLASH)) + /* Re-init SPI driver to handle locked BAR. + This prevents flashconsole from hanging. + If other code needs to use SPI during + ramstage, whitelist it here. */ + spi_init(); } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/25660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib802d7ee32f1fb0a68a84b0280480dcaefa9831f Gerrit-Change-Number: 25660 Gerrit-PatchSet: 8 Gerrit-Owner: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dan Elkouby <streetwalkermc(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: soc/intel/skylake: remove PrimaryDisplay check
by Maxim Polyakov (Code Review) 07 May '19

07 May '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32615 Change subject: soc/intel/skylake: remove PrimaryDisplay check ...................................................................... soc/intel/skylake: remove PrimaryDisplay check Checking the PrimaryDisplay parameter (added by patch with Change Id Ie3f9362676105e41c69139a094dbb9e8b865689f) isn`t required. The display connected to PEG works even if IGD is primary for output image and at the same time this device is disabled Tested on Asrock H110M-DVS with NVIDIA GTX 1060 GPU Payload: tianocore edk2-stable201811-216-g51be9d0 Change-Id: I5615597881a151bb004676d914fbf40874ac1f68 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/skylake/romstage/romstage_fsp20.c 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/32615/1 diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index c166e3a..2f75479 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -304,10 +304,6 @@ */ m_cfg->InternalGfx = 0; m_cfg->IgdDvmt50PreAlloc = 0; - if (config->PrimaryDisplay == Display_iGFX) - m_cfg->PrimaryDisplay = Display_Auto; - else - m_cfg->PrimaryDisplay = config->PrimaryDisplay; } else { m_cfg->InternalGfx = 1; /* @@ -319,8 +315,8 @@ * a high resolution panel */ m_cfg->IgdDvmt50PreAlloc = 2; - m_cfg->PrimaryDisplay = config->PrimaryDisplay; } + m_cfg->PrimaryDisplay = config->PrimaryDisplay; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/c/coreboot/+/32615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5615597881a151bb004676d914fbf40874ac1f68 Gerrit-Change-Number: 32615 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit May 2019