coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

1 participants
1485 discussions

Change in ...coreboot[master]: [DoNotMerge]soc/intel/cannonlake: Enable Debugging
by Lijian Zhao (Code Review) 10 May '19

10 May '19

Lijian Zhao has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29523 ) Change subject: [DoNotMerge]soc/intel/cannonlake: Enable Debugging ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5986007f3f36bc7fdc8e427fa311f98890069cd3 Gerrit-Change-Number: 29523 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

Change in ...coreboot[master]: mb/google/poppy/variants/rammus: Support new onboard Hynix memory
by Ken Lu (Code Review) 10 May '19

10 May '19

Ken Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32674 ) Change subject: mb/google/poppy/variants/rammus: Support new onboard Hynix memory ...................................................................... Patch Set 2: > Patch Set 1: > > (1 comment) Done -- To view, visit https://review.coreboot.org/c/coreboot/+/32674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd02953d0c6ac62fa4d7751fd8b103b74433aa73 Gerrit-Change-Number: 32674 Gerrit-PatchSet: 2 Gerrit-Owner: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Fri, 10 May 2019 02:13:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/google/poppy/variants/rammus: Support new onboard Hynix memory
by Ken Lu (Code Review) 10 May '19

10 May '19

Ken Lu has uploaded a new patch set (#2) to the change originally created by YanRu Chen. ( https://review.coreboot.org/c/coreboot/+/32674 ) Change subject: mb/google/poppy/variants/rammus: Support new onboard Hynix memory ...................................................................... mb/google/poppy/variants/rammus: Support new onboard Hynix memory Add hynix_dimm_H9CCNNNCLGALAR-NVD for new onboard memory support. BUG=b:130337306 BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Signed-off-by: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: Ibd02953d0c6ac62fa4d7751fd8b103b74433aa73 --- A src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex M src/mainboard/google/poppy/variants/rammus/Makefile.inc 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/32674/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd02953d0c6ac62fa4d7751fd8b103b74433aa73 Gerrit-Change-Number: 32674 Gerrit-PatchSet: 2 Gerrit-Owner: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: sdm845: Port I2C driver
by Julius Werner (Code Review) 10 May '19

10 May '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29104 ) Change subject: sdm845: Port I2C driver ...................................................................... Patch Set 32: (1 comment) https://review.coreboot.org/#/c/29104/24/src/mainboard/google/cheza/mainboa… File src/mainboard/google/cheza/mainboard.c: https://review.coreboot.org/#/c/29104/24/src/mainboard/google/cheza/mainboa… PS24, Line 42: i2c_init(12, 400 * KHz, 1); > According to our discussion, qup enum should be defined in clock driver and qup drivers should inclu […] I don't understand the problem here to be honest. The QUPs have a well-known numbering and it has to be defined somewhere. I would say that numbering clearly belongs more to the QUPs than to the clock controller, although the clock controller also uses it of course. If it's a patch dependency problem, it's fine to add the qcom_qup_se.h file in the clock patch with just the enum definition and nothing else, and then have a later QUP patch to add the other stuff. -- To view, visit https://review.coreboot.org/c/coreboot/+/29104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb76564d8a11427423dd14d8ba7c8c7d500ef346 Gerrit-Change-Number: 29104 Gerrit-PatchSet: 32 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 10 May 2019 01:09:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/gigabyte/GA-SBCAP3450: add mainboard
by Marius Genheimer (Code Review) 09 May '19

09 May '19

Marius Genheimer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32712 Change subject: mb/gigabyte/GA-SBCAP3450: add mainboard ...................................................................... mb/gigabyte/GA-SBCAP3450: add mainboard Change-Id: I04fe3a9849b99225b78c38d46434e7b2e629c582 Signed-off-by: Marius Genheimer <mail(a)f0wl.cc> --- A src/mainboard/gigabyte/ga-sbcap3450/Kconfig A src/mainboard/gigabyte/ga-sbcap3450/Kconfig.name A src/mainboard/gigabyte/ga-sbcap3450/board_info.txt 3 files changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/32712/1 diff --git a/src/mainboard/gigabyte/ga-sbcap3450/Kconfig b/src/mainboard/gigabyte/ga-sbcap3450/Kconfig new file mode 100644 index 0000000..7ea0547 --- /dev/null +++ b/src/mainboard/gigabyte/ga-sbcap3450/Kconfig @@ -0,0 +1,68 @@ +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Intel Corporation +## Copyright (C) 2015 Google Inc. +## Copyright (C) 2019 Marius Genheimer <mail(a)f0wl.cc> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +if BOARD_GIGABYTE_SBCAP3450 + +config BOARD_SPECIFIC_OPTIONS + + def_bool y + select ADD_FSP_BINARIES + select BOARD_ROMSIZE_KB_8192 + select FSP_USE_REPO + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select ONBOARD_VGA_IS_PRIMARY + select SOC_INTEL_APOLLOLAKE + select USE_BLOBS + +config MAINBOARD_DIR + string + default "gigabyte/ga-sbcap3450" + +config MAINBOARD_PART_NUMBER + string + default "SBCAP3450" + +config MAINBOARD_FAMILY + string + default "Gigabyte_SBC" + +config SUBSYSTEM_VENDOR_ID + hex + default 0x1458 + +config SUBSYSTEM_DEVICE_ID + hex + default 0xb005 + +config MAX_CPUS + int + default 4 + +config DIMM_MAX + int + default 1 + +config DIMM_SPD_SIZE + int + default 256 #DDR3 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +endif diff --git a/src/mainboard/gigabyte/ga-sbcap3450/Kconfig.name b/src/mainboard/gigabyte/ga-sbcap3450/Kconfig.name new file mode 100644 index 0000000..16f0432 --- /dev/null +++ b/src/mainboard/gigabyte/ga-sbcap3450/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GIGABYTE_SBCAP3450 + bool "GA-SBCAP3450" diff --git a/src/mainboard/gigabyte/ga-sbcap3450/board_info.txt b/src/mainboard/gigabyte/ga-sbcap3450/board_info.txt new file mode 100644 index 0000000..762164c --- /dev/null +++ b/src/mainboard/gigabyte/ga-sbcap3450/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Gigabyte +Board name: GA-SBCAP3450 +Category: desktop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +ROM package: SOIC-8 +Release year: 2018 -- To view, visit https://review.coreboot.org/c/coreboot/+/32712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04fe3a9849b99225b78c38d46434e7b2e629c582 Gerrit-Change-Number: 32712 Gerrit-PatchSet: 1 Gerrit-Owner: Marius Genheimer <mail(a)f0wl.cc> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: soc/intel/cannonlake: Fix pcie clock number
by Lijian Zhao (Code Review) 09 May '19

09 May '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32672 Change subject: soc/intel/cannonlake: Fix pcie clock number ...................................................................... soc/intel/cannonlake: Fix pcie clock number Cannonlake PCH LP have total 6 pcie clocks and Cannonlake PCH H have total 16 pcie clocks. It is different with pcie root port numbers. BUG=CID 1381814 TEST=Build and boot up fine on sarien platform. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I909b5b584c596e6fe878ffe24d9cabc53c4576ed --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/chip.h 2 files changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/32672/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index c06b91e..e524275 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -183,6 +183,11 @@ default 24 if SOC_INTEL_CANNONLAKE_PCH_H default 16 +config MAX_PCIE_CLOCKS + int + default 16 if SOC_INTEL_CANNONLAKE_PCH_H + default 6 + config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index b17df4b..f34528a 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -168,10 +168,10 @@ /* PCIe output clocks type to Pcie devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ - uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to * clksrc. */ - uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; /* PCIe LTR(Latency Tolerance Reporting) mechanism */ uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; /* Enable/Disable HotPlug support for Root Port */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I909b5b584c596e6fe878ffe24d9cabc53c4576ed Gerrit-Change-Number: 32672 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

6 5

Change in ...coreboot[master]: vendorcode/google/chromeos: Use explicit zero check in ACPI code
by Duncan Laurie (Code Review) 09 May '19

09 May '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32694 Change subject: vendorcode/google/chromeos: Use explicit zero check in ACPI code ...................................................................... vendorcode/google/chromeos: Use explicit zero check in ACPI code The ASL 2.0 syntax for "!X" resolves to "LNot(X)" which will evaluate the object as an integer and turn into a boolean. This may not do the right thing if the object is actually a string and it can lead to unexpected behavior. Instead be specific about the object type and check for zero or an empty string depending on what is being returned. This fixes an issue where some VPD keys were causing the search to stop and miss subsequent entries. Change-Id: I1688842964f9c2f81ca31073da9c2d71a8c81767 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/vendorcode/google/chromeos/acpi/amac.asl M src/vendorcode/google/chromeos/acpi/vpd.asl 2 files changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/32694/1 diff --git a/src/vendorcode/google/chromeos/acpi/amac.asl b/src/vendorcode/google/chromeos/acpi/amac.asl index 51159f5..c87862f 100644 --- a/src/vendorcode/google/chromeos/acpi/amac.asl +++ b/src/vendorcode/google/chromeos/acpi/amac.asl @@ -42,6 +42,7 @@ /* Get "dock_passthru" value from RW_VPD */ Local0 = \VPD.VPDF ("RW", "dock_passthru") + Local1 = Zero Switch (ToString (Local0)) { Case ("ethernet_mac0") { @@ -55,7 +56,7 @@ Local1 = \VPD.VPDF ("RO", "dock_mac") } } - If (!Local1) { + If (Local1 == Zero) { Return (Zero) } Printf ("MAC address returned from VPD: %o", Local1) diff --git a/src/vendorcode/google/chromeos/acpi/vpd.asl b/src/vendorcode/google/chromeos/acpi/vpd.asl index 3b262f7..8f8b0e5 100644 --- a/src/vendorcode/google/chromeos/acpi/vpd.asl +++ b/src/vendorcode/google/chromeos/acpi/vpd.asl @@ -139,7 +139,7 @@ Local1 <<= 7 Local1 |= Local2 & 0x7f } - If (!Local1) { + If (Local1 == Zero) { Return (Zero) } @@ -162,7 +162,7 @@ */ Method (VPDS, 0, Serialized) { - Name (VPKV, Package () { Zero, Zero }) + Name (VPKV, Package () { "", "" }) /* Read the VPD type and ensure it is a string */ If (^VPRB () != ^VPES) { @@ -193,14 +193,14 @@ /* End address of VPD region */ ^VEND = ^VPTR + DerefOf (Local0[1]) - If (!^VPTR || !^VEND) { + If (^VPTR == Zero || ^VEND == Zero) { Printf ("Unable to find VPD region") Return (Zero) } /* Verify VPD info header and save size */ Local0 = VVPD (^VPTR) - If (!Local0) { + If (Local0 == Zero) { Printf ("VPD region %o did not verify", Arg0) Return (Zero) } @@ -213,7 +213,7 @@ While (Local1 != ToString (Arg1)) { Local2 = VPDS () Local1 = DerefOf (Local2[0]) - If (!Local1) { + If (Local1 == "") { Printf ("VPD KEY %o not found", Arg1) Return (Zero) } -- To view, visit https://review.coreboot.org/c/coreboot/+/32694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1688842964f9c2f81ca31073da9c2d71a8c81767 Gerrit-Change-Number: 32694 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

2 4

Change in ...coreboot[master]: mb/google/sarien: Enable LTR for PCIe NVMe root port
by Duncan Laurie (Code Review) 09 May '19

09 May '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32456 Change subject: mb/google/sarien: Enable LTR for PCIe NVMe root port ...................................................................... mb/google/sarien: Enable LTR for PCIe NVMe root port Enable LTR for NVMe so it can use ASPM L1.2. BUG=b:127593309 TEST=build and boot on sarien and check L1 substate with lspci before: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+ after: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ Change-Id: I9842beda6767f758556747f83cfcedbd00612698 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/32456/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 426bdae..77bd82a 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -196,6 +196,7 @@ # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[4]" = "12" register "PcieClkSrcClkReq[4]" = "4" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 27c0913..96146ba 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -197,6 +197,7 @@ # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2" -- To view, visit https://review.coreboot.org/c/coreboot/+/32456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9842beda6767f758556747f83cfcedbd00612698 Gerrit-Change-Number: 32456 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: mb/google/poppy/variants/rammus: Support new onboard Hynix memory
by Sumeet R Pawnikar (Code Review) 09 May '19

09 May '19

Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32674 ) Change subject: mb/google/poppy/variants/rammus: Support new onboard Hynix memory ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/32674/1/src/mainboard/google/poppy/spd/hyni… File src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex: https://review.coreboot.org/#/c/32674/1/src/mainboard/google/poppy/spd/hyni… PS1, Line 17: Do we need this last extra empty line, if not, please remove it. -- To view, visit https://review.coreboot.org/c/coreboot/+/32674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd02953d0c6ac62fa4d7751fd8b103b74433aa73 Gerrit-Change-Number: 32674 Gerrit-PatchSet: 1 Gerrit-Owner: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Thu, 09 May 2019 15:26:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: Change the guard for bootblock_systemagent_early_init to ENV_BOOTBLOCK
by ron minnich (Code Review) 09 May '19

09 May '19

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32697 Change subject: Change the guard for bootblock_systemagent_early_init to ENV_BOOTBLOCK ...................................................................... Change the guard for bootblock_systemagent_early_init to ENV_BOOTBLOCK The definition of bootblock_systemagent_early_init was guarded by !ENV_RAMSTAGE. But it's only called in the bootblock. So guard it with ENV_BOOTBLOCK instead. Change-Id: I143cf72e4a63b176e4772575e7a60a2a611e4ad9 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- M src/soc/intel/common/block/systemagent/systemagent_early.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/32697/1 diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 61f14a9..c12c64a 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -24,7 +24,7 @@ #include "systemagent_def.h" -#if !ENV_RAMSTAGE +#if ENV_BOOTBLOCK void bootblock_systemagent_early_init(void) { uint32_t reg; -- To view, visit https://review.coreboot.org/c/coreboot/+/32697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I143cf72e4a63b176e4772575e7a60a2a611e4ad9 Gerrit-Change-Number: 32697 Gerrit-PatchSet: 1 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

3 3

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2019