coreboot-gerrit May 2019

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Change in ...coreboot[master]: sb/i82801gx: Don't rewrite over BCTRL
by HAOUAS Elyes (Code Review) 10 May '19

10 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32699 Change subject: sb/i82801gx: Don't rewrite over BCTRL ...................................................................... sb/i82801gx: Don't rewrite over BCTRL PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h>, and BCTRL also at 0x3e, is real registry name for D30:F0 (see ICH7 Family Datasheet page 355) The write on that register is already done some lines above. So remove wrong register name and the wrong code line. Change-Id: Ib8a0514200f424049503bb8e4bc076ee6ae86ce3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/pci.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/32699/1 diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index c54769f..22c5165 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -46,9 +46,6 @@ reg8 |= (0x04 << 3); pci_write_config8(dev, SMLT, reg8); - /* Will this improve throughput of bus masters? */ - pci_write_config8(dev, PCI_MIN_GNT, 0x06); - /* Clear errors in status registers */ reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900; -- To view, visit https://review.coreboot.org/c/coreboot/+/32699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8a0514200f424049503bb8e4bc076ee6ae86ce3 Gerrit-Change-Number: 32699 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/nami: Add VBT blobs and include them in cbfs
by Arthur Heymans (Code Review) 10 May '19

10 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30427 Change subject: mb/google/nami: Add VBT blobs and include them in cbfs ...................................................................... mb/google/nami: Add VBT blobs and include them in cbfs Change-Id: Iaf49bdee7ae82a0a61192327351267f098eb5ab1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/poppy/variants/nami/Makefile.inc R src/mainboard/google/poppy/variants/nami/akali-data.vbt A src/mainboard/google/poppy/variants/nami/data.vbt A src/mainboard/google/poppy/variants/nami/patheon-data.vbt A src/mainboard/google/poppy/variants/nami/vayne-data.vbt 5 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/30427/1 diff --git a/src/mainboard/google/poppy/variants/nami/Makefile.inc b/src/mainboard/google/poppy/variants/nami/Makefile.inc index 7f86bb7..8f4ef0c 100644 --- a/src/mainboard/google/poppy/variants/nami/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nami/Makefile.inc @@ -41,3 +41,15 @@ cbfs-files-y += oem.bin oem.bin-file := $(call strip_quotes,$(CONFIG_OEM_BIN_FILE)) oem.bin-type := raw + +add_vbt_to_cbfs= \ + $(eval cbfs-files-y += $1) \ + $(eval $1-file := $2) \ + $(eval $1-type := raw) \ + $(eval $1-compression := lzma) + +$(call add_vbt_to_cbfs, akali-data.vbt, akali-vbt.bin) +$(call add_vbt_to_cbfs, pantheon-data.vbt, pantheon-vbt.bin) +$(call add_vbt_to_cbfs, pantheon-data.vbt, pantheon-vbt.bin) +$(call add_vbt_to_cbfs, vayne-data.vbt, vayne-vbt.bin) +$(call add_vbt_to_cbfs, data.vbt, vbt.bin) diff --git a/src/mainboard/google/poppy/variants/nami/vbt-akali.bin b/src/mainboard/google/poppy/variants/nami/akali-data.vbt similarity index 100% rename from src/mainboard/google/poppy/variants/nami/vbt-akali.bin rename to src/mainboard/google/poppy/variants/nami/akali-data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/nami/data.vbt b/src/mainboard/google/poppy/variants/nami/data.vbt new file mode 100644 index 0000000..8406362 --- /dev/null +++ b/src/mainboard/google/poppy/variants/nami/data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/nami/patheon-data.vbt b/src/mainboard/google/poppy/variants/nami/patheon-data.vbt new file mode 100644 index 0000000..7e4fb0a --- /dev/null +++ b/src/mainboard/google/poppy/variants/nami/patheon-data.vbt Binary files differ diff --git a/src/mainboard/google/poppy/variants/nami/vayne-data.vbt b/src/mainboard/google/poppy/variants/nami/vayne-data.vbt new file mode 100644 index 0000000..7e4fb0a --- /dev/null +++ b/src/mainboard/google/poppy/variants/nami/vayne-data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/30427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf49bdee7ae82a0a61192327351267f098eb5ab1 Gerrit-Change-Number: 30427 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien/variants/arcada: Set tcc offset value
by Bonnie Lin (Code Review) 10 May '19

10 May '19

Bonnie Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32680 Change subject: mb/google/sarien/variants/arcada: Set tcc offset value ...................................................................... mb/google/sarien/variants/arcada: Set tcc offset value Set tcc offset value to 1 degree celsius for Arcada system. BRANCH=None BUG=b:122636962 TEST=Built and tested on Arcada system Change-Id: I3ca4be2f7b92e29fb133ecc32023526b177d2ac2 --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/32680/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 0cc9970..27c61f3 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -161,7 +161,7 @@ #| I2C4 | H1 TPM | #+-------------------+---------------------------+ - register "tcc_offset" = "10" + register "tcc_offset" = "1" register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, -- To view, visit https://review.coreboot.org/c/coreboot/+/32680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ca4be2f7b92e29fb133ecc32023526b177d2ac2 Gerrit-Change-Number: 32680 Gerrit-PatchSet: 1 Gerrit-Owner: Bonnie Lin <bonnie_ty_lin(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Fine tune Goodix touch screen timing
by Dtrain Hsu (Code Review) 10 May '19

10 May '19

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32665 Change subject: mb/google/hatch: Fine tune Goodix touch screen timing ...................................................................... mb/google/hatch: Fine tune Goodix touch screen timing According to Goodix GT7375P datasheet, fine tune Goodix touch screen timing. BUG=b:129727745 BRANCH=None TEST=local build and tested with Goodix touch screen worked under coldboot(10 times), warmboot(10 times), S3(10 times). Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I4bf081bab5e89d3ce336c6432da5ba71279fa98d --- M src/mainboard/google/hatch/variants/hatch/overridetree.cb M src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/32665/1 diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 42752e6..562bb8b 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -78,8 +78,8 @@ register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "30" - register "generic.reset_off_delay_ms" = "3" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end diff --git a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb index 115a513..eec7880 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb @@ -63,8 +63,8 @@ register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "30" - register "generic.reset_off_delay_ms" = "3" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end -- To view, visit https://review.coreboot.org/c/coreboot/+/32665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bf081bab5e89d3ce336c6432da5ba71279fa98d Gerrit-Change-Number: 32665 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Fix GBB_HWID for kohaku
by Furquan Shaikh (Code Review) 10 May '19

10 May '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32690 Change subject: mb/google/hatch: Fix GBB_HWID for kohaku ...................................................................... mb/google/hatch: Fix GBB_HWID for kohaku This change fixes the typo in CB:32161 (mb/google/hatch: Add Kohaku board) that defaults GBB_HWID incorrectly for kohaku using BOARD_GOOGLE_HATCH_WHL. Change-Id: I387879619ac4f79fad422e5f1f047dfe3c7b5b22 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/32690/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 07ae7d2..09f79212 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -64,7 +64,7 @@ depends on CHROMEOS default "HATCH TEST 1823" if BOARD_GOOGLE_HATCH default "HATCH_WHL TEST 2374" if BOARD_GOOGLE_HATCH_WHL - default "KOHAKU TEST 1953" if BOARD_GOOGLE_HATCH_WHL + default "KOHAKU TEST 1953" if BOARD_GOOGLE_KOHAKU config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/32690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I387879619ac4f79fad422e5f1f047dfe3c7b5b22 Gerrit-Change-Number: 32690 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/i945: Use macro instead of magic number
by HAOUAS Elyes (Code Review) 10 May '19

10 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31027 Change subject: nb/intel/i945: Use macro instead of magic number ...................................................................... nb/intel/i945: Use macro instead of magic number Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/raminit.c 2 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31027/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 09a18e3..bc2f6f9 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -160,10 +160,10 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* GC: Enable GPIOs */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), GPIO_CNTL, 0x10); /* GC: Enable GPIOs */ setup_pch_gpios(&mainboard_gpio_map); printk(BIOS_DEBUG, " done.\n"); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 64c87da..ff866aa 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -246,13 +246,13 @@ u8 reg8; u8 do_reset = 0; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); if (reg8 & ((1<<7)|(1<<2))) { if (reg8 & (1<<2)) { printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n"); /* Write back clears bit 2 */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); do_reset = 1; } @@ -260,14 +260,14 @@ if (reg8 & (1<<7)) { printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n"); reg8 &= ~(1<<7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); do_reset = 1; } /* Set SLP_S3# Assertion Stretch Enable */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */ + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); reg8 |= (1 << 3); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); if (do_reset) { printk(BIOS_DEBUG, "Reset required.\n"); @@ -278,9 +278,9 @@ } /* Set DRAM initialization bit in ICH7 */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 |= (1<<7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); /* clear self refresh status if check is disabled or not a resume */ if (!CONFIG_CHECK_SLFRCS_ON_RESUME @@ -1810,9 +1810,9 @@ */ goto cache_code; vco_update: - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); clkcfg &= ~(1 << 10); MCHBAR32(CLKCFG) = clkcfg; @@ -2415,7 +2415,7 @@ MCHBAR32(REPC) |= (1 << 0); /* enable upper CMOS */ - RCBA32(0x3400) = (1 << 2); + RCBA32(RC) = (1 << 2); /* Program Receive Enable Timings */ if (sysinfo->boot_path == BOOT_PATH_RESUME) { @@ -2829,9 +2829,9 @@ sdram_enable_rcomp(); /* Tell ICH7 that we're done */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2); reg8 &= ~(1 << 7); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_2, reg8); printk(BIOS_DEBUG, "RAM initialization finished.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/31027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I028013bd7511b5b9fc80e5f744fcad584cb25fd3 Gerrit-Change-Number: 31027 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/google/kahlee: Fix Micron MT40A512M16TB-062E:J SPD CRC error
by Kevin Chiu (Code Review) 10 May '19

10 May '19

Hello Kevin Chiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32678 to review the following change. Change subject: mainboard/google/kahlee: Fix Micron MT40A512M16TB-062E:J SPD CRC error ...................................................................... mainboard/google/kahlee: Fix Micron MT40A512M16TB-062E:J SPD CRC error Correct Micron MT40A512M16TB-062E:J SPD CRC to 0x5330 to fix post hang in AGESA TestPoint:05 TpProcMemSPDChecking. BUG=b:127394249 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Change-Id: I8fa49e6e938b3195945b3199438cc53f3e9c92e7 --- M src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16TB-062E-J.spd.hex 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/32678/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16TB-062E-J.spd.hex b/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16TB-062E-J.spd.hex index d4afea7..67640fe 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16TB-062E-J.spd.hex +++ b/src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16TB-062E-J.spd.hex @@ -6,7 +6,7 @@ 16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 60 5B +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 30 53 0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/32678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fa49e6e938b3195945b3199438cc53f3e9c92e7 Gerrit-Change-Number: 32678 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/braswell/smbus: Init SMBus
by Michał Żygowski (Code Review) 10 May '19

10 May '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32062 Change subject: soc/intel/braswell/smbus: Init SMBus ...................................................................... soc/intel/braswell/smbus: Init SMBus Using Intel southbridge common implementation to retrieve SPD from DIMMs causes FSP memory init to hang. Initialize SMBus as in Intel SoC common before issuing any transactions to let FSP properly initialize memory. Also make Intel common southbridge smbus API compatible with SPD library. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I92a2c5a6d0b38e5658cfdc017041f12717dabdd5 --- M src/soc/intel/braswell/Makefile.inc A src/soc/intel/braswell/include/soc/smbus.h M src/soc/intel/braswell/romstage/romstage.c A src/soc/intel/braswell/smbus.c 4 files changed, 92 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/32062/1 diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index a538f7d..554af41 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -14,6 +14,7 @@ romstage-y += lpc_init.c romstage-y += memmap.c romstage-y += pmutil.c +romstage-y += smbus.c romstage-y += tsc_freq.c postcar-y += tsc_freq.c @@ -38,6 +39,7 @@ ramstage-y += sata.c ramstage-y += scc.c ramstage-y += sd.c +ramstage-y += smbus.c ramstage-y += smm.c ramstage-y += southcluster.c ramstage-y += spi.c diff --git a/src/soc/intel/braswell/include/soc/smbus.h b/src/soc/intel/braswell/include/soc/smbus.h new file mode 100644 index 0000000..f5075e1 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/smbus.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 3mdeb + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#ifndef _SOC_SMBUS_H_ +#define _SOC_SMBUS_H_ + +#include <soc/pci_devs.h> + +#if !defined(__SIMPLE_DEVICE__) +#include <device/device.h> +#define PCH_DEV_SMBUS dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)) +#else + +#include <device/pci_type.h> +#define PCH_DEV_SMBUS PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC) +#endif + +#define HOSTC 0x40 +#define HST_EN (1 << 0) + +void smbus_common_init(void); + +#endif /* _SOC_SMBUS_H_ */ diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index ca1eb40..6a0226e 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -40,6 +40,7 @@ #include <soc/lpc.h> #include <soc/pci_devs.h> #include <soc/romstage.h> +#include <soc/smbus.h> #include <soc/smm.h> #include <soc/spi.h> #include <build.h> @@ -194,6 +195,7 @@ spi_init(); lpc_init(); + smbus_common_init(); } /* SOC initialization after RAM is enabled */ diff --git a/src/soc/intel/braswell/smbus.c b/src/soc/intel/braswell/smbus.c new file mode 100644 index 0000000..454c3f6 --- /dev/null +++ b/src/soc/intel/braswell/smbus.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2019 3mdeb + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/early_smbus.h> +#include <device/pci_def.h> +#include <reg_script.h> +#include <soc/iomap.h> +#include <soc/smbus.h> +#include <southbridge/intel/common/smbus.h> + +static const struct reg_script smbus_init_script[] = { + /* Set SMBus I/O base address */ + REG_PCI_WRITE32(PCI_BASE_ADDRESS_4, SMBUS_BASE_ADDRESS), + /* Set SMBus enable */ + REG_PCI_WRITE8(HOSTC, HST_EN), + /* Enable I/O access */ + REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO), + /* Disable interrupts */ + REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0), + /* Clear errors */ + REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff), + /* Indicate the end of this array by REG_SCRIPT_END */ + REG_SCRIPT_END, +}; + +u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) +{ + return do_smbus_read_byte(SMBUS_BASE_ADDRESS, addr, offset); +} + +u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value) +{ + return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value); +} + +void smbus_common_init(void) +{ + reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92a2c5a6d0b38e5658cfdc017041f12717dabdd5 Gerrit-Change-Number: 32062 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/i82801gx: Remove duplicated 'define PMBASE'
by HAOUAS Elyes (Code Review) 10 May '19

10 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32677 Change subject: sb/i82801gx: Remove duplicated 'define PMBASE' ...................................................................... sb/i82801gx: Remove duplicated 'define PMBASE' Change-Id: If08bea821043bc8e661bf5327f4fe2cef3a65be8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/i82801gx.h 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/32677/1 diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 3db5d49..b693b75 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -89,7 +89,6 @@ #define RTC_POWER_FAILED (1 << 1) #define SLEEP_AFTER_POWER_FAIL (1 << 0) -#define PMBASE 0x40 #define ACPI_CNTL 0x44 #define ACPI_EN (1 << 7) #define BIOS_CNTL 0xDC -- To view, visit https://review.coreboot.org/c/coreboot/+/32677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If08bea821043bc8e661bf5327f4fe2cef3a65be8 Gerrit-Change-Number: 32677 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: src/mainboard/libretrend/lt1000: Initial commit
by Michał Żygowski (Code Review) 10 May '19

10 May '19

Hello Patrick Rudolph, Piotr Król, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30360 to look at the new patch set (#7). Change subject: src/mainboard/libretrend/lt1000: Initial commit ...................................................................... src/mainboard/libretrend/lt1000: Initial commit Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- A src/mainboard/libretrend/Kconfig A src/mainboard/libretrend/Kconfig.name A src/mainboard/libretrend/lt1000/Kconfig A src/mainboard/libretrend/lt1000/Kconfig.name A src/mainboard/libretrend/lt1000/Makefile.inc A src/mainboard/libretrend/lt1000/acpi/ec.asl A src/mainboard/libretrend/lt1000/acpi/mainboard.asl A src/mainboard/libretrend/lt1000/acpi/superio.asl A src/mainboard/libretrend/lt1000/acpi_tables.c A src/mainboard/libretrend/lt1000/board_info.txt A src/mainboard/libretrend/lt1000/bootblock.c A src/mainboard/libretrend/lt1000/devicetree.cb A src/mainboard/libretrend/lt1000/dsdt.asl A src/mainboard/libretrend/lt1000/gpio.h A src/mainboard/libretrend/lt1000/hda_verb.c A src/mainboard/libretrend/lt1000/mainboard.c A src/mainboard/libretrend/lt1000/ramstage.c A src/mainboard/libretrend/lt1000/romstage.c 18 files changed, 955 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/30360/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/30360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Gerrit-Change-Number: 30360 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit May 2019