coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

1 participants
1485 discussions

Change in ...coreboot[master]: {bd82x6x,i82801gx,ibexpeak,lynxpoint}: Remove dead code and use macro
by HAOUAS Elyes (Code Review) 12 May '19

12 May '19

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29990 to look at the new patch set (#2). Change subject: {bd82x6x,i82801gx,ibexpeak,lynxpoint}: Remove dead code and use macro ...................................................................... {bd82x6x,i82801gx,ibexpeak,lynxpoint}: Remove dead code and use macro Use BIOS_CNTL defined macro instead of magic number. Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/fsp_baytrail/southcluster.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 8 files changed, 6 insertions(+), 108 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/29990/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6 Gerrit-Change-Number: 29990 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: sb/{bd82x6x,i82801gx,ibexpeak,lynxpoint}: Use BIOS_CNTL macro
by HAOUAS Elyes (Code Review) 12 May '19

12 May '19

HAOUAS Elyes has restored this change. ( https://review.coreboot.org/c/coreboot/+/29990 ) Change subject: sb/{bd82x6x,i82801gx,ibexpeak,lynxpoint}: Use BIOS_CNTL macro ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/29990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6 Gerrit-Change-Number: 29990 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: restore

1 0

Change in ...coreboot[master]: boot_device: Constify argument
by Patrick Rudolph (Code Review) 12 May '19

12 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32703 Change subject: boot_device: Constify argument ...................................................................... boot_device: Constify argument Add const qualifier to first argument. Change-Id: I6655e04401b6a7aa5cafb717ff6f46b80b96646e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/spi/boot_device_rw_nommap.c M src/include/boot_device.h M src/lib/boot_device.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/32703/1 diff --git a/src/drivers/spi/boot_device_rw_nommap.c b/src/drivers/spi/boot_device_rw_nommap.c index d01d778..cc8fbf7 100644 --- a/src/drivers/spi/boot_device_rw_nommap.c +++ b/src/drivers/spi/boot_device_rw_nommap.c @@ -109,7 +109,7 @@ return car_get_var_ptr(&sfg); } -int boot_device_wp_region(struct region_device *rd, +int boot_device_wp_region(const struct region_device *rd, const enum bootdev_prot_type type) { uint32_t ctrlr_pr; diff --git a/src/include/boot_device.h b/src/include/boot_device.h index c882968..f392c10 100644 --- a/src/include/boot_device.h +++ b/src/include/boot_device.h @@ -65,7 +65,7 @@ * by the region device. * Returns 0 on success, < 0 on error. */ -int boot_device_wp_region(struct region_device *rd, +int boot_device_wp_region(const struct region_device *rd, const enum bootdev_prot_type type); /* diff --git a/src/lib/boot_device.c b/src/lib/boot_device.c index 429a6d8..e91a97f 100644 --- a/src/lib/boot_device.c +++ b/src/lib/boot_device.c @@ -20,7 +20,7 @@ /* Provide weak do-nothing init. */ } -int __weak boot_device_wp_region(struct region_device *rd, +int __weak boot_device_wp_region(const struct region_device *rd, const enum bootdev_prot_type type) { /* return a failure, make aware WP is not implemented */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6655e04401b6a7aa5cafb717ff6f46b80b96646e Gerrit-Change-Number: 32703 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: src: Remove unneeded include <arch/io.h>
by HAOUAS Elyes (Code Review) 12 May '19

12 May '19

Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29307 to look at the new patch set (#21). Change subject: src: Remove unneeded include <arch/io.h> ...................................................................... src: Remove unneeded include <arch/io.h> Change-Id: Ia18c77876121594a272a07d56acfaa863d0ccb25 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/xgi/common/vb_init.c M src/drivers/xgi/common/vb_setmode.c M src/drivers/xgi/common/vb_util.c M src/drivers/xgi/common/xgi_coreboot.h M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/northbridge/intel/gm45/early_reset.c M src/northbridge/intel/gm45/romstage.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/x4x/raminit.c M src/soc/amd/stoneyridge/enable_usbdebug.c M src/soc/amd/stoneyridge/southbridge.c M src/southbridge/intel/bd82x6x/early_usb.c M util/autoport/bd82x6x.go 28 files changed, 4 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/29307/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/29307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia18c77876121594a272a07d56acfaa863d0ccb25 Gerrit-Change-Number: 29307 Gerrit-PatchSet: 21 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: src: Remove unneeded include <arch/io.h>
by HAOUAS Elyes (Code Review) 12 May '19

12 May '19

HAOUAS Elyes has restored this change. ( https://review.coreboot.org/c/coreboot/+/29307 ) Change subject: src: Remove unneeded include <arch/io.h> ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/29307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia18c77876121594a272a07d56acfaa863d0ccb25 Gerrit-Change-Number: 29307 Gerrit-PatchSet: 20 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: restore

1 0

Change in ...coreboot[master]: lib/timestamp: Make timestamp_sync_cache_to_cbmem() in postcar
by Subrata Banik (Code Review) 12 May '19

12 May '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32726 Change subject: lib/timestamp: Make timestamp_sync_cache_to_cbmem() in postcar ...................................................................... lib/timestamp: Make timestamp_sync_cache_to_cbmem() in postcar This patch ensures to have correct timestamp value if plan to skip ramstage using CONFIG_RAMPAYLOAD. Change-Id: I3ba3a54c20dfcdaf5b87818cc5da9a812f5f2edf Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/lib/timestamp.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/32726/1 diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index cf882b8..74548ab 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -353,6 +353,9 @@ } ROMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) +#if CONFIG(RAMPAYLOAD) +POSTCAR_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) +#endif RAMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) /* Provide default timestamp implementation using monotonic timer. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ba3a54c20dfcdaf5b87818cc5da9a812f5f2edf Gerrit-Change-Number: 32726 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 6

Change in ...coreboot[master]: Kconfig: Enable coreboot lite firmware flow
by Subrata Banik (Code Review) 12 May '19

12 May '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32618 Change subject: Kconfig: Enable coreboot lite firmware flow ...................................................................... Kconfig: Enable coreboot lite firmware flow This patch enables coreboot flow to skip ramstage as individual stage to load payload. Instead it is expected to load payload from postcar stage. Change-Id: I839f2d34a93b69ca6bf3de6594e2ad9f66ee7135 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/Kconfig 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/32618/1 diff --git a/src/Kconfig b/src/Kconfig index b4898bd..4642b85 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1198,3 +1198,11 @@ config CBFS_SIZE default ROM_SIZE + +config COREBOOT_LITE + bool "Enable Coreboot Lite flow (remove ramstage)" + default n + help + If this option is enabled, coreboot flow will skip ramstage + loading and execute ramstage to load payload. + Instead it is expected to load payload from postcar stage itself. -- To view, visit https://review.coreboot.org/c/coreboot/+/32618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I839f2d34a93b69ca6bf3de6594e2ad9f66ee7135 Gerrit-Change-Number: 32618 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

5 11

Change in ...coreboot[master]: arch/cpu: Rename mp_get_apic_id() function
by Subrata Banik (Code Review) 12 May '19

12 May '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32701 Change subject: arch/cpu: Rename mp_get_apic_id() function ...................................................................... arch/cpu: Rename mp_get_apic_id() function This patch renames mp_get_apic_id() to cpu_get_apic_id() in order access it outside CONFIG_PARALLEL_MP kconfig scope. Also make below changes 1. Make sure add_cpu_map_entry() function saves default_apic_id before calling SMM relocation. 2. Use dev_find_path() to get cpu device path. 3. Remove redundent add_cpu_map_entry() call from BSP and AP. Move this function call into cpu_initialize() Change-Id: I6a6c85df055bc0b5fc8c850cfa04d50859067088 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/cpu.c M src/cpu/x86/mp_init.c M src/include/cpu/cpu.h M src/include/cpu/x86/mp.h 4 files changed, 32 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/32701/1 diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 80d4d0d..f1b14d5 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -219,6 +219,30 @@ cpu->ops = driver ? driver->ops : NULL; } +struct cpu_map { + struct device *dev; + /* Keep track of default apic ids for SMM. */ + int default_apic_id; +}; + +/* Keep track of APIC and device structure for each CPU. */ +static struct cpu_map cpus[CONFIG_MAX_CPUS]; + +static inline void add_cpu_map_entry(const struct cpu_info *info) +{ + cpus[info->index].dev = info->cpu; + cpus[info->index].default_apic_id = cpuid_ebx(1) >> 24; +} + +/* Returns APIC id for coreboot CPU number or < 0 on failure. */ +int cpu_get_apic_id(int logical_cpu) +{ + if (logical_cpu >= CONFIG_MAX_CPUS || logical_cpu < 0) + return -1; + + return cpus[logical_cpu].default_apic_id; +} + void cpu_initialize(unsigned int index) { /* Because we busy wait at the printk spinlock. @@ -231,6 +255,8 @@ struct cpuinfo_x86 c; info = cpu_info(); + /* Track cpus in cpu_map structures. */ + add_cpu_map_entry(info); printk(BIOS_INFO, "Initializing CPU #%d\n", index); diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 9d51b3e..28e50d0 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -135,21 +135,6 @@ static int global_num_aps; static struct mp_flight_plan mp_info; -struct cpu_map { - struct device *dev; - /* Keep track of default apic ids for SMM. */ - int default_apic_id; -}; - -/* Keep track of APIC and device structure for each CPU. */ -static struct cpu_map cpus[CONFIG_MAX_CPUS]; - -static inline void add_cpu_map_entry(const struct cpu_info *info) -{ - cpus[info->index].dev = info->cpu; - cpus[info->index].default_apic_id = cpuid_ebx(1) >> 24; -} - static inline void barrier_wait(atomic_t *b) { while (atomic_read(b) == 0) @@ -212,9 +197,8 @@ info = cpu_info(); info->index = cpu; - info->cpu = cpus[cpu].dev; + info->cpu = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); - add_cpu_map_entry(info); thread_init_cpu_info_non_bsp(info); /* Fix up APIC id with reality. */ @@ -411,7 +395,6 @@ continue; } new->name = processor_name; - cpus[i].dev = new; } return max_cpus; @@ -587,9 +570,6 @@ if (info->index != 0) printk(BIOS_CRIT, "BSP index(%d) != 0!\n", info->index); - - /* Track BSP in cpu_map structures. */ - add_cpu_map_entry(info); } /* @@ -667,15 +647,6 @@ cpu_initialize(info->index); } -/* Returns APIC id for coreboot CPU number or < 0 on failure. */ -int mp_get_apic_id(int logical_cpu) -{ - if (logical_cpu >= CONFIG_MAX_CPUS || logical_cpu < 0) - return -1; - - return cpus[logical_cpu].default_apic_id; -} - void smm_initiate_relocation_parallel(void) { if ((lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY)) { @@ -769,7 +740,7 @@ struct smm_runtime *runtime = smm_params->runtime; for (i = 0; i < CONFIG_MAX_CPUS; i++) - runtime->apic_id_to_cpu[i] = mp_get_apic_id(i); + runtime->apic_id_to_cpu[i] = cpu_get_apic_id(i); } static int install_relocation_handler(int num_cpus, size_t save_state_size) @@ -1001,12 +972,12 @@ } static struct mp_flight_record mp_steps[] = { + /* Initialize each CPU through the driver framework. */ + MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), /* Once the APs are up load the SMM handlers. */ MP_FR_BLOCK_APS(NULL, load_smm_handlers), /* Perform SMM relocation. */ MP_FR_NOBLOCK_APS(trigger_smm_relocation, trigger_smm_relocation), - /* Initialize each CPU through the driver framework. */ - MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), /* Wait for APs to finish then optionally start looking for work. */ MP_FR_BLOCK_APS(ap_wait_for_instruction, NULL), }; diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index 60940f0..7cdbbd3 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -5,6 +5,8 @@ #if !defined(__ROMCC__) void cpu_initialize(unsigned int cpu_index); +/* Returns APIC id for coreboot CPU number or < 0 on failure. */ +int cpu_get_apic_id(int logical_cpu); struct bus; void initialize_cpus(struct bus *cpu_bus); asmlinkage void secondary_cpu_init(unsigned int cpu_index); diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index 9789910..c04252e 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -145,9 +145,6 @@ */ int mp_park_aps(void); -/* Returns APIC id for coreboot CPU number or < 0 on failure. */ -int mp_get_apic_id(int logical_cpu); - /* * SMM helpers to use with initializing CPUs. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a6c85df055bc0b5fc8c850cfa04d50859067088 Gerrit-Change-Number: 32701 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 16

Change in ...coreboot[master]: src/arch/x86: Use core apic id to get cpu_index()
by Nico Huber (Code Review) 11 May '19

11 May '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26346 ) Change subject: src/arch/x86: Use core apic id to get cpu_index() ...................................................................... Patch Set 17: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/26346/16/src/arch/x86/cpu.c File src/arch/x86/cpu.c: https://review.coreboot.org/#/c/26346/16/src/arch/x86/cpu.c@344 PS16, Line 344: */ > done Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/26346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Gerrit-Change-Number: 26346 Gerrit-PatchSet: 17 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Sat, 11 May 2019 14:30:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: src/arch/x86: Use core apic id to get cpu_index()
by Subrata Banik (Code Review) 11 May '19

11 May '19

Hello Aaron Durbin, Patrick Rudolph, ron minnich, Paul Menzel, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/26346 to look at the new patch set (#17). Change subject: src/arch/x86: Use core apic id to get cpu_index() ...................................................................... src/arch/x86: Use core apic id to get cpu_index() This cpu_index() implementation assumes that cpu_index() function might always getting called from coreboot context (ESP stack pointer will always refer to coreboot). This might not be true in case of proposed PI spec MP_SERVICES_PPI implementation, where FSP context (stack pointer refers to fsp) will request to get cpu_index(), natural alignment logic will use ESP and retrieve struct cpu_info *ci from (stack_top - 8 byte). This is not the place where cpu_index is actually stored by ramstage c_start.S Hence this patch tries to remove those dependencies while retrieving cpu_index(), rather it uses cpuid to fetch lapic id and matches with cpus_default_apic_id[] variable to return correct cpu_index(). BRANCH=none BUG=b:79562868 TEST=Ensures functions can be run on APs without any failure and cpu_index() also provides correct index number. Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/cpu.c M src/arch/x86/include/arch/cpu.h 2 files changed, 38 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/26346/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/26346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Gerrit-Change-Number: 26346 Gerrit-PatchSet: 17 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2019