coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
by Arthur Heymans (Code Review) 12 May '19

12 May '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30383 ) Change subject: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK ...................................................................... Patch Set 39: (3 comments) https://review.coreboot.org/#/c/30383/37/src/soc/intel/broadwell/Kconfig File src/soc/intel/broadwell/Kconfig: https://review.coreboot.org/#/c/30383/37/src/soc/intel/broadwell/Kconfig@117 PS37, Line 117: default 0x2000 > Tested? I think the linker tells you if that is not enough? https://review.coreboot.org/#/c/30383/37/src/soc/intel/broadwell/bootblock/… File src/soc/intel/broadwell/bootblock/cpu.c: https://review.coreboot.org/#/c/30383/37/src/soc/intel/broadwell/bootblock/… PS37, Line 51: > Was this redundant with `non-evic/cache_as_ram. […] The only reason this was done, was to speed up finding the microcode updates. cache_as_ram.S cleared it anyway. Now cache_as_ram.S updates the microcode itself (also after caching the rom to speed up things) https://review.coreboot.org/#/c/30383/37/src/soc/intel/broadwell/romstage/r… File src/soc/intel/broadwell/romstage/romstage.c: https://review.coreboot.org/#/c/30383/37/src/soc/intel/broadwell/romstage/r… PS37, Line 68: struct romstage_params rp = { : .bist = 0, /* checking done in the bootblock */ : .pei_data = NULL, : }; > If I read this correctly, we are effectively passing […] At the moment we try to have the same romstage interface with or without romcc bootblock (which passes on BIST) for all cpu/intel/car/ users. I'll clean it up when that is done for all platforms. OTOH it looks like broadwell has everything in soc/intel/broadwell so a cleanup now, seems like a good idea. -- To view, visit https://review.coreboot.org/c/coreboot/+/30383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935 Gerrit-Change-Number: 30383 Gerrit-PatchSet: 39 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 12 May 2019 10:31:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
by Nico Huber (Code Review) 12 May '19

12 May '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30383 ) Change subject: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK ...................................................................... Patch Set 39: Code-Review+1 (3 comments) +2 if this is tested https://review.coreboot.org/#/c/30383/37/src/soc/intel/broadwell/Kconfig File src/soc/intel/broadwell/Kconfig: https://review.coreboot.org/#/c/30383/37/src/soc/intel/broadwell/Kconfig@117 PS37, Line 117: default 0x2000 Tested? https://review.coreboot.org/#/c/30383/37/src/soc/intel/broadwell/bootblock/… File src/soc/intel/broadwell/bootblock/cpu.c: https://review.coreboot.org/#/c/30383/37/src/soc/intel/broadwell/bootblock/… PS37, Line 51: Was this redundant with `non-evic/cache_as_ram.S`? https://review.coreboot.org/#/c/30383/37/src/soc/intel/broadwell/romstage/r… File src/soc/intel/broadwell/romstage/romstage.c: https://review.coreboot.org/#/c/30383/37/src/soc/intel/broadwell/romstage/r… PS37, Line 68: struct romstage_params rp = { : .bist = 0, /* checking done in the bootblock */ : .pei_data = NULL, : }; If I read this correctly, we are effectively passing 2x 0 to mainboard_romstage_entry(). Is this going to be cleaned up somewhere? -- To view, visit https://review.coreboot.org/c/coreboot/+/30383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935 Gerrit-Change-Number: 30383 Gerrit-PatchSet: 39 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 12 May 2019 10:21:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/broadwell: Enable LPC/SIO setup in bootblock
by Arthur Heymans (Code Review) 12 May '19

12 May '19

Hello Patrick Rudolph, Felix Held, Matt DeVillier, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30385 to look at the new patch set (#43). Change subject: soc/intel/broadwell: Enable LPC/SIO setup in bootblock ...................................................................... soc/intel/broadwell: Enable LPC/SIO setup in bootblock This allows for serial console during the bootblock and enables bootblock console by default. Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/jecht/Makefile.inc A src/mainboard/google/jecht/bootblock.c M src/mainboard/google/jecht/romstage.c M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/bootblock/pch.c A src/soc/intel/broadwell/include/soc/bootblock.h M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/romstage/romstage.c 8 files changed, 112 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/30385/43 -- To view, visit https://review.coreboot.org/c/coreboot/+/30385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde Gerrit-Change-Number: 30385 Gerrit-PatchSet: 43 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
by Arthur Heymans (Code Review) 12 May '19

12 May '19

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30383 to look at the new patch set (#39). Change subject: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK ...................................................................... soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK This puts the cache-as-ram init in the bootblock. Before setting up cache as ram the microcode updates are applied. This removes the possibility for a normal/fallback setup although implementing this should be quite easy. Setting up LPC in the bootblock to output console on SuperIOs is not done in this patch, therefore BOOTBLOCK_CONSOLE is not yet selected. Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/bootblock/cpu.c M src/soc/intel/broadwell/bootblock/pch.c M src/soc/intel/broadwell/bootblock/systemagent.c M src/soc/intel/broadwell/romstage/Makefile.inc M src/soc/intel/broadwell/romstage/romstage.c 7 files changed, 28 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/30383/39 -- To view, visit https://review.coreboot.org/c/coreboot/+/30383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935 Gerrit-Change-Number: 30383 Gerrit-PatchSet: 39 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/broadwell: Enable LPC/SIO setup in bootblock
by Arthur Heymans (Code Review) 12 May '19

12 May '19

Hello Patrick Rudolph, Felix Held, Matt DeVillier, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30385 to look at the new patch set (#42). Change subject: soc/intel/broadwell: Enable LPC/SIO setup in bootblock ...................................................................... soc/intel/broadwell: Enable LPC/SIO setup in bootblock This allows for serial console during the bootblock and enables bootblock console by default. Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/jecht/Makefile.inc A src/mainboard/google/jecht/bootblock.c M src/mainboard/google/jecht/romstage.c M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/bootblock/pch.c A src/soc/intel/broadwell/include/soc/bootblock.h M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/romstage/romstage.c 8 files changed, 112 insertions(+), 65 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/30385/42 -- To view, visit https://review.coreboot.org/c/coreboot/+/30385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde Gerrit-Change-Number: 30385 Gerrit-PatchSet: 42 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
by Arthur Heymans (Code Review) 12 May '19

12 May '19

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30383 to look at the new patch set (#38). Change subject: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK ...................................................................... soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK This puts the cache-as-ram init in the bootblock. Before setting up cache as ram the microcode updates are applied. This removes the possibility for a normal/fallback setup although implementing this should be quite easy. Setting up LPC in the bootblock to output console on SuperIOs is not done in this patch, therefore BOOTBLOCK_CONSOLE is not yet selected. Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/bootblock/cpu.c M src/soc/intel/broadwell/bootblock/pch.c M src/soc/intel/broadwell/bootblock/systemagent.c M src/soc/intel/broadwell/romstage/Makefile.inc M src/soc/intel/broadwell/romstage/romstage.c 7 files changed, 27 insertions(+), 89 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/30383/38 -- To view, visit https://review.coreboot.org/c/coreboot/+/30383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935 Gerrit-Change-Number: 30383 Gerrit-PatchSet: 38 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/broadwell: Enable LPC/SIO setup in bootblock
by Arthur Heymans (Code Review) 12 May '19

12 May '19

Hello Patrick Rudolph, Felix Held, Matt DeVillier, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30385 to look at the new patch set (#41). Change subject: soc/intel/broadwell: Enable LPC/SIO setup in bootblock ...................................................................... soc/intel/broadwell: Enable LPC/SIO setup in bootblock This allows for serial console during the bootblock and enables bootblock console by default. Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/jecht/Makefile.inc A src/mainboard/google/jecht/bootblock.c M src/mainboard/google/jecht/romstage.c M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/bootblock/pch.c A src/soc/intel/broadwell/include/soc/bootblock.h M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/romstage/romstage.c 8 files changed, 109 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/30385/41 -- To view, visit https://review.coreboot.org/c/coreboot/+/30385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde Gerrit-Change-Number: 30385 Gerrit-PatchSet: 41 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: nb/intel/broadwell: Add an option for where verstage starts
by Arthur Heymans (Code Review) 12 May '19

12 May '19

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30384 to look at the new patch set (#40). Change subject: nb/intel/broadwell: Add an option for where verstage starts ...................................................................... nb/intel/broadwell: Add an option for where verstage starts Previously broadwell used a romcc bootblock and starting verstage in romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also possible to have a separate verstage. This selects using a separate verstage by default but still keeps the option around to use verstage in romstage. Also make sure mrc.bin is only added to the COREBOOT fmap region as it requires to be run at a specific offset. This means that coreboot will have to jump from a RW region to the RO region for that binary and back to that RW region after that binary is done initializing the memory. Change-Id: I900233cadb3c76da329fb98f93917570e633365f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/auron/Makefile.inc M src/mainboard/google/jecht/Makefile.inc M src/mainboard/intel/wtm2/Makefile.inc M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/romstage/raminit.c 6 files changed, 35 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/30384/40 -- To view, visit https://review.coreboot.org/c/coreboot/+/30384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I900233cadb3c76da329fb98f93917570e633365f Gerrit-Change-Number: 30384 Gerrit-PatchSet: 40 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
by Arthur Heymans (Code Review) 12 May '19

12 May '19

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30383 to look at the new patch set (#37). Change subject: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK ...................................................................... soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK This puts the cache-as-ram init in the bootblock. Before setting up cache as ram the microcode updates are applied. This removes the possibility for a normal/fallback setup although implementing this should be quite easy. Setting up LPC in the bootblock to output console on SuperIOs is not done in this patch, therefore BOOTBLOCK_CONSOLE is not yet selected. Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/bootblock/cpu.c M src/soc/intel/broadwell/bootblock/pch.c M src/soc/intel/broadwell/bootblock/systemagent.c M src/soc/intel/broadwell/romstage/Makefile.inc M src/soc/intel/broadwell/romstage/romstage.c 7 files changed, 29 insertions(+), 92 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/30383/37 -- To view, visit https://review.coreboot.org/c/coreboot/+/30383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935 Gerrit-Change-Number: 30383 Gerrit-PatchSet: 37 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: {bd82x6x,i82801gx,ibexpeak,lynxpoint}: Remove dead code and use macro
by Patrick Rudolph (Code Review) 12 May '19

12 May '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29990 ) Change subject: {bd82x6x,i82801gx,ibexpeak,lynxpoint}: Remove dead code and use macro ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6 Gerrit-Change-Number: 29990 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 12 May 2019 08:17:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2019