coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: vboot: Make vboot_logic_executed() a bit more precise
by Julius Werner (Code Review) 10 May '19

10 May '19

Hello Aaron Durbin, Frans Hendriks, Philipp Deppenwiese, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32714 to review the following change. Change subject: vboot: Make vboot_logic_executed() a bit more precise ...................................................................... vboot: Make vboot_logic_executed() a bit more precise This patch adds another check to vboot_logic_executed() to make sure we only do a runtime check for verstage_should_load() if CONFIG_VBOOT_RETURN_FROM_VERSTAGE is enabled. That's the only case where the stage that's loading the verstage can execute after verification has run (because the verstage will return to it when it's done). In the other case, the stage that loads verstage really just loads it and will never do anything again after hand-off, so it's guaranteed to always execute before verification. This change may allow extra dead-code elimination in some cases. Change-Id: I7019b6f7b0acfbf0a8173914b53364751b08f2cf Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/security/vboot/vboot_loader.c 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/32714/1 diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 0640ebd..3bbb3da 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -64,9 +64,11 @@ int vboot_logic_executed(void) { - /* If we are in a stage that would load the verstage or execute the - vboot logic directly, we store the answer in a global. */ - if (verstage_should_load() || verification_should_run()) + /* If we are in the stage that runs verification, or in the stage that + both loads the verstage and is returned to from it afterwards, we + need to check a global to see if verfication has run. */ + if (verification_should_run() || + (verstage_should_load() && CONFIG(VBOOT_RETURN_FROM_VERSTAGE))) return car_get_var(vboot_executed); if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/32714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7019b6f7b0acfbf0a8173914b53364751b08f2cf Gerrit-Change-Number: 32714 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: ====
by Richard Spiegel (Code Review) 10 May '19

10 May '19

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32710 ) Change subject: ==== ...................................................................... Patch Set 1: This belonged to patch c97801d. Somehow id got a separate changeid... please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/32710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b588c23b793a10b4301064bbeffab51737cca4b Gerrit-Change-Number: 32710 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Fri, 10 May 2019 20:53:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sdm845: Port I2C driver
by T.Michael Turney (Code Review) 10 May '19

10 May '19

Hello mturney mturney, Akash Asthana, Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29104 to look at the new patch set (#33). Change subject: sdm845: Port I2C driver ...................................................................... sdm845: Port I2C driver Add I2C functionality in coreboot Change-Id: Ifb76564d8a11427423dd14d8ba7c8c7d500ef346 Signed-off-by: Akash Asthana <akashast(a)codeaurora.org> --- M src/mainboard/google/cheza/mainboard.c M src/soc/qualcomm/sdm845/Makefile.inc A src/soc/qualcomm/sdm845/i2c.c A src/soc/qualcomm/sdm845/include/soc/i2c.h M src/soc/qualcomm/sdm845/include/soc/qcom_qup_se.h M src/soc/qualcomm/sdm845/include/soc/qupv3_fw_config.h M src/soc/qualcomm/sdm845/qupv3_fw_config.c M src/soc/qualcomm/sdm845/spi_qup.c 8 files changed, 229 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/29104/33 -- To view, visit https://review.coreboot.org/c/coreboot/+/29104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb76564d8a11427423dd14d8ba7c8c7d500ef346 Gerrit-Change-Number: 29104 Gerrit-PatchSet: 33 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: sdm845: Add SPI QUP driver
by T.Michael Turney (Code Review) 10 May '19

10 May '19

Hello mturney mturney, Mukesh Savaliya, Vin Kamath, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/27483 to look at the new patch set (#53). Change subject: sdm845: Add SPI QUP driver ...................................................................... sdm845: Add SPI QUP driver This implements the SPI driver for the Qualcomm Universal Peripheral (QUP) core. Change-Id: I35061727d5ccc550eaeb06caef4524bc4cf25b54 Signed-off-by: Mukesh Savaliya <msavaliy(a)codeaurora.org> Signed-off-by: Akash Asthana <akashast(a)codeaurora.org> --- M src/mainboard/google/cheza/bootblock.c M src/soc/qualcomm/sdm845/Makefile.inc M src/soc/qualcomm/sdm845/bootblock.c M src/soc/qualcomm/sdm845/include/soc/addressmap.h A src/soc/qualcomm/sdm845/include/soc/qcom_qup_se.h A src/soc/qualcomm/sdm845/include/soc/spi_qup_qcom.h A src/soc/qualcomm/sdm845/qcom_qup_se.c M src/soc/qualcomm/sdm845/spi.c A src/soc/qualcomm/sdm845/spi_qup.c 9 files changed, 939 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/27483/53 -- To view, visit https://review.coreboot.org/c/coreboot/+/27483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35061727d5ccc550eaeb06caef4524bc4cf25b54 Gerrit-Change-Number: 27483 Gerrit-PatchSet: 53 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Vin Kamath <vink(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/amd/stoneyridge: Add IO access functions for PMx
by Marshall Dawson (Code Review) 10 May '19

10 May '19

Hello Richard Spiegel, Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32648 to review the following change. Change subject: soc/amd/stoneyridge: Add IO access functions for PMx ...................................................................... soc/amd/stoneyridge: Add IO access functions for PMx Replace locations in the source that explicitely use the CD6/CD7 index/data pair with utility function calls. Change-Id: I6e7ba472ef2551e363987d18a79408fcd2074de4 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/enable_usbdebug.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/sb_util.c M src/soc/amd/stoneyridge/southbridge.c 4 files changed, 57 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/32648/1 diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c index ce84a47..90bd6e8 100644 --- a/src/soc/amd/stoneyridge/enable_usbdebug.c +++ b/src/soc/amd/stoneyridge/enable_usbdebug.c @@ -26,10 +26,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) { - /* Enable all of the USB controllers */ - outb(PM_USB_ENABLE, PM_INDEX); - outb(PM_USB_ALL_CONTROLLERS, PM_DATA); - + pm_io_write8(PM_USB_ENABLE, PM_USB_ALL_CONTROLLERS); return SOC_EHCI1_DEV; } diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index f755c0a..618a5de 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -491,6 +491,12 @@ void sb_tpm_decode_spi(void); void lpc_wideio_512_window(uint16_t base); void lpc_wideio_16_window(uint16_t base); +uint8_t pm_io_read8(uint8_t reg); +uint16_t pm_io_read16(uint8_t reg); +uint32_t pm_io_read32(uint8_t reg); +void pm_io_write8(uint8_t reg, uint8_t value); +void pm_io_write16(uint8_t reg, uint16_t value); +void pm_io_write32(uint8_t reg, uint32_t value); u8 pm_read8(u8 reg); u16 pm_read16(u8 reg); u32 pm_read32(u8 reg); diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index 41ebb37..8781617 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -18,6 +18,52 @@ #include <arch/acpi.h> #include <soc/southbridge.h> +/* PM registers are accessed a byte at a time via CD6/CD7 */ +uint8_t pm_io_read8(uint8_t reg) +{ + outb(reg, PM_INDEX); + return inb(PM_DATA); +} + +uint16_t pm_io_read16(uint8_t reg) +{ + int i; + uint16_t value = 0; + for (i = sizeof(value) - 1 ; i >= 0 ; i--) + value = (value << 8) | pm_io_read8(reg + i); + return value; +} + +uint32_t pm_io_read32(uint8_t reg) +{ + uint32_t value = pm_io_read16(reg + sizeof(uint16_t)) << 16; + return value | pm_io_read16(reg); +} + +void pm_io_write8(uint8_t reg, uint8_t value) +{ + outb(reg, PM_INDEX); + outb(value, PM_DATA); +} + +void pm_io_write16(uint8_t reg, uint16_t value) +{ + int i; + for (i = 0 ; i < sizeof(value) ; i++) { + pm_io_write8(reg + i, value & 0xff); + value >>= 8; + } +} + +void pm_io_write32(uint8_t reg, uint32_t value) +{ + int i; + for (i = 0 ; i < sizeof(value) ; i++) { + pm_io_write8(reg + i, value & 0xff); + value >>= 8; + } +} + /* smbus pci read/write - access registers at 0xfed80000 - currently unused */ /* smi read/write - access registers at 0xfed80200 */ diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index b590178..8dfef8b 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -329,11 +329,9 @@ u8 byte; /* Enable LPC controller */ - outb(PM_LPC_GATING, PM_INDEX); - byte = inb(PM_DATA); + byte = pm_io_read8(PM_LPC_GATING); byte |= PM_LPC_ENABLE; - outb(PM_LPC_GATING, PM_INDEX); - outb(byte, PM_DATA); + pm_io_write8(PM_LPC_GATING, byte); /* Enable port 80 LPC decode in pci function 3 configuration space. */ byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); @@ -367,11 +365,9 @@ uint8_t byte; /* Enable ACPI MMIO range 0xfed80000 - 0xfed81fff */ - outb(PM_ISA_CONTROL, PM_INDEX); - byte = inb(PM_DATA); + byte = pm_io_read8(PM_ISA_CONTROL); byte |= MMIO_EN; - outb(PM_ISA_CONTROL, PM_INDEX); - outb(byte, PM_DATA); + pm_io_write8(PM_ISA_CONTROL, byte); } static void sb_enable_cf9_io(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/32648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e7ba472ef2551e363987d18a79408fcd2074de4 Gerrit-Change-Number: 32648 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Fix s5 touchscreen power leakage
by Lijian Zhao (Code Review) 10 May '19

10 May '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32367 Change subject: mb/google/sarien: Fix s5 touchscreen power leakage ...................................................................... mb/google/sarien: Fix s5 touchscreen power leakage Leakage power is observed from 3V_TSP_S0_FUSE during S5. To avoid leakage power, GPP_E7 needs to be turned off before S5 entry. BUG=b:129899315 TEST=Measure leakage power in S5 from both Arcada and Sarien Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: Ie4229477b7149c0a75f4a8c6c7c453a37cc1c78c --- M src/mainboard/google/sarien/dsdt.asl A src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl A src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl 3 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/32367/1 diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl index e5b0cca..09ffd91 100644 --- a/src/mainboard/google/sarien/dsdt.asl +++ b/src/mainboard/google/sarien/dsdt.asl @@ -39,6 +39,8 @@ { #include <soc/intel/cannonlake/acpi/northbridge.asl> #include <soc/intel/cannonlake/acpi/southbridge.asl> + /* Per board variant mainboard hooks. */ + #include <variant/acpi/mainboard.asl> } } diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..2d6260b --- /dev/null +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define TS_PD GPP_E7 + +/* Method called from _PTS prior to enter sleep state */ +Method(MPTS, 1) { + /* Before enter S5 soft off state */ + If (Arg0 == 5) { + /* Clear touch screen pd pin to avoid leakage */ + CTXS(TS_PD) + } /*S5 soft off state*/ +} diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..2d6260b --- /dev/null +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define TS_PD GPP_E7 + +/* Method called from _PTS prior to enter sleep state */ +Method(MPTS, 1) { + /* Before enter S5 soft off state */ + If (Arg0 == 5) { + /* Clear touch screen pd pin to avoid leakage */ + CTXS(TS_PD) + } /*S5 soft off state*/ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4229477b7149c0a75f4a8c6c7c453a37cc1c78c Gerrit-Change-Number: 32367 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard/libretrend/lt1000: Initial commit
by Patrick Rudolph (Code Review) 10 May '19

10 May '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30360 ) Change subject: src/mainboard/libretrend/lt1000: Initial commit ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/#/c/30360/7/src/mainboard/libretrend/lt1000/dev… File src/mainboard/libretrend/lt1000/devicetree.cb: https://review.coreboot.org/#/c/30360/7/src/mainboard/libretrend/lt1000/dev… PS7, Line 214: device pci 1c.0 on end # PCI Express Port 1 add smbios_slot_desc for M.2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Gerrit-Change-Number: 30360 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 10 May 2019 16:04:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/poppy/variants/rammus: Support new onboard Hynix memory
by Furquan Shaikh (Code Review) 10 May '19

10 May '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32674 ) Change subject: mb/google/poppy/variants/rammus: Support new onboard Hynix memory ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/32674/2/src/mainboard/google/poppy/spd/hyni… File src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex: PS2: File permissions seem to be incorrect? -- To view, visit https://review.coreboot.org/c/coreboot/+/32674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd02953d0c6ac62fa4d7751fd8b103b74433aa73 Gerrit-Change-Number: 32674 Gerrit-PatchSet: 2 Gerrit-Owner: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Fri, 10 May 2019 16:00:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: superio/ite: Add IT8786E-I
by Patrick Rudolph (Code Review) 10 May '19

10 May '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30335 ) Change subject: superio/ite: Add IT8786E-I ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7317da6a72db64f95f9a790ef96ed7a5f93b3aea Gerrit-Change-Number: 30335 Gerrit-PatchSet: 6 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 10 May 2019 15:53:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/bd82x6x: Don't rewrite over BCTRL
by HAOUAS Elyes (Code Review) 10 May '19

10 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32700 Change subject: sb/bd82x6x: Don't rewrite over BCTRL ...................................................................... sb/bd82x6x: Don't rewrite over BCTRL PCI_MIN_GNT doesn't exist for PCI bridges. PCI_MIN_GNT is defined at 0x3e, and at that offset, we have BCTRL register. Some lines obove that code line, the "write" on BCTRL is already done. Change-Id: I8f1b98ba627947ab6652a4ba31d2acb159dd3e32 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/pci.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/32700/1 diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index c3b8257..2186287 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -47,9 +47,6 @@ reg8 |= (0x04 << 3); pci_write_config8(dev, SMLT, reg8); - /* Will this improve throughput of bus masters? */ - pci_write_config8(dev, PCI_MIN_GNT, 0x06); - /* Clear errors in status registers */ reg16 = pci_read_config16(dev, PSTS); //reg16 |= 0xf900; -- To view, visit https://review.coreboot.org/c/coreboot/+/32700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f1b98ba627947ab6652a4ba31d2acb159dd3e32 Gerrit-Change-Number: 32700 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit May 2019