coreboot-gerrit May 2019

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Change in ...libgfxinit[master]: gma: Add Kaby Lake support
by Nico Huber (Code Review) 09 May '19

09 May '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/28763 ) Change subject: gma: Add Kaby Lake support ...................................................................... Patch Set 7: Verified+1 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/28763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Ice05e07b016cebc7258a9790e38e079e63227a4b Gerrit-Change-Number: 28763 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 09 May 2019 14:37:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/pcengines/alix/romstage.c: clean up the transition to RAM
by Michał Żygowski (Code Review) 09 May '19

09 May '19

Michał Żygowski has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/27749 ) Change subject: mb/pcengines/alix/romstage.c: clean up the transition to RAM ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/27749 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21f2341091d49d105026a12022c52d811d71feeb Gerrit-Change-Number: 27749 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: mb/pcengines/apu2/mainboard.c: enable power on after fail
by Michał Żygowski (Code Review) 09 May '19

09 May '19

Michał Żygowski has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/27663 ) Change subject: mb/pcengines/apu2/mainboard.c: enable power on after fail ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/27663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b35db16e2090484e58d1307dc29049a1325c65f Gerrit-Change-Number: 27663 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: src/mainboard/pcengines/apu2/Kconfig: increase pre-CBMEM console size
by Michał Żygowski (Code Review) 09 May '19

09 May '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31419 Change subject: src/mainboard/pcengines/apu2/Kconfig: increase pre-CBMEM console size ...................................................................... src/mainboard/pcengines/apu2/Kconfig: increase pre-CBMEM console size The default 0xc00 size of pre-CBMEM console is too small to fit whole console log from romstage. Increase the size in order to avoid log truncation when checking console with cbmem utility. The size was adjusted by compiling and running the coreboot on apu2 with SPEW loglevel. Additionally unset the SQUELCH_EARLY_SMP option to get console output between amdinitreset and amdinitearly. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0a21850e9dc9e9611b462e09b4190258e9bd0a04 --- M src/mainboard/pcengines/apu2/Kconfig 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/31419/1 diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 6e65a6e..3c04b05 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -113,4 +113,16 @@ int default 128 +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0x3000 + help + Increase this value if preram cbmem console is getting truncated + +config SQUELCH_EARLY_SMP + bool + default n + help + When selected only the BSP CPU will output to early console. + endif # BOARD_PCENGINES_APU2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a21850e9dc9e9611b462e09b4190258e9bd0a04 Gerrit-Change-Number: 31419 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/arch/x86: Use core apic id to get cpu_index()
by Subrata Banik (Code Review) 09 May '19

09 May '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26346 ) Change subject: src/arch/x86: Use core apic id to get cpu_index() ...................................................................... Patch Set 13: (1 comment) https://review.coreboot.org/#/c/26346/12/src/arch/x86/cpu.c File src/arch/x86/cpu.c: https://review.coreboot.org/#/c/26346/12/src/arch/x86/cpu.c@314 PS12, Line 314: #if CONFIG(PARALLEL_MP) > Why is PARALLEL_MP needed as a dependency at all? Just because that's how things currently are? Can' […] Can you please look at CL: https://review.coreboot.org/#/c/coreboot/+/32701/ https://review.coreboot.org/#/c/coreboot/+/32702/ -- To view, visit https://review.coreboot.org/c/coreboot/+/26346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Gerrit-Change-Number: 26346 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 09 May 2019 11:49:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/arch/x86: Use core apic id to get cpu_index()
by Subrata Banik (Code Review) 09 May '19

09 May '19

Hello Aaron Durbin, Patrick Rudolph, ron minnich, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/26346 to look at the new patch set (#13). Change subject: src/arch/x86: Use core apic id to get cpu_index() ...................................................................... src/arch/x86: Use core apic id to get cpu_index() This cpu_index() implementation assumes that cpu_index() function might always getting called from coreboot context (ESP stack pointer will always refer to coreboot). This might not true incase of proposed PI spec MP_SERVICES_PPI implementation, where FSP context (stack pointer refers to fsp) will request to get cpu_index(), natural alignment logic will use ESP and retrieve struct cpu_info *ci from (stack_top - 8 byte). This is not the place where cpu_index is actually stored by ramstage c_start.S Hence this patch tries to remove those dependencies while retriving cpu_index(), rather it uses cpuid to fetch lapic id and matches with cpu_mp structure to get correct cpu_index() BRANCH=none BUG=b:79562868 TEST=Ensures functions can be run on APs without any failure and cpu_index() also provides correct index number. Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/cpu.c M src/arch/x86/include/arch/cpu.h 2 files changed, 14 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/26346/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/26346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Gerrit-Change-Number: 26346 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src/cpu/amd/pi/00730F01: Add microcode update infrastructure for fam1...
by build bot (Jenkins) (Code Review) 09 May '19

09 May '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29272 ) Change subject: src/cpu/amd/pi/00730F01: Add microcode update infrastructure for fam16h PI ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29272/2/src/cpu/amd/pi/00730F01/update_micr… File src/cpu/amd/pi/00730F01/update_microcode.c: https://review.coreboot.org/#/c/29272/2/src/cpu/amd/pi/00730F01/update_micr… PS2, Line 4: * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic15cba06f3cd9cfbc538b6764b158fa699f0ecf6 Gerrit-Change-Number: 29272 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 09 May 2019 09:29:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/cpu/amd/pi/00730F01: Add microcode update infrastructure for fam1...
by Michał Żygowski (Code Review) 09 May '19

09 May '19

Hello Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Felix Held, Piotr Król, Paul Menzel, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29272 to look at the new patch set (#2). Change subject: src/cpu/amd/pi/00730F01: Add microcode update infrastructure for fam16h PI ...................................................................... src/cpu/amd/pi/00730F01: Add microcode update infrastructure for fam16h PI Code is based on microcode update procedure from fam10-15h with necessary microcode blob structure updates for fam16h. Currently updating microcode in romstage seem to be impossible. AGESA is overriding the microcode patch regardles of the current microcode revision patched on CPU. Use ramstage CPU init procedures to update microcode easily. Tested with microcode blob 07030106 released 2018-02-09 from platomav/CPUMicrocodes GitHub repository on apu2 platform. TEST=boot Linux kernel 4.14.50 on PC Engines apu2 and run dmesg to see patch_level=0x07030106 on all cores Change-Id: Ic15cba06f3cd9cfbc538b6764b158fa699f0ecf6 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/cpu/amd/pi/00730F01/Kconfig M src/cpu/amd/pi/00730F01/Makefile.inc A src/cpu/amd/pi/00730F01/microcode_fam16h.c M src/cpu/amd/pi/00730F01/model_16_init.c A src/cpu/amd/pi/00730F01/update_microcode.c 5 files changed, 229 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/29272/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic15cba06f3cd9cfbc538b6764b158fa699f0ecf6 Gerrit-Change-Number: 29272 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: vboot: include vb2_sha.h when required
by Joel Kitching (Code Review) 09 May '19

09 May '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32454 Change subject: vboot: include vb2_sha.h when required ...................................................................... vboot: include vb2_sha.h when required Should include vb2_sha.h header when SHA library functions or constants are required. This replaces NEED_VB2_SHA_LIBRARY. BUG=b:124141368, chromium:956474 TEST=make clean && make test-abuild BRANCH=none Change-Id: I9f32174dbf3de05fbe5279cb8017888757abf368 Signed-off-by: Joel Kitching <kitching(a)google.com> Cq-Depend: chromium:1583820 --- M src/commonlib/cbfs.c M src/security/tpm/tspi/tspi.c M src/security/vboot/antirollback.h M util/cbfstool/Makefile.inc M util/cbfstool/cbfs_image.c 5 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/32454/1 diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index 250a72a..7bb98dd 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -18,6 +18,7 @@ #include <commonlib/endian.h> #include <commonlib/helpers.h> #include <string.h> +#include <vb2_sha.h> #if !defined(ERROR) #define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index e466eb8..4698a4d 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -22,6 +22,7 @@ #include <stdlib.h> #if CONFIG(VBOOT) #include <vb2_api.h> +#include <vb2_sha.h> #include <assert.h> #endif diff --git a/src/security/vboot/antirollback.h b/src/security/vboot/antirollback.h index 6ea2c13..62d2e20 100644 --- a/src/security/vboot/antirollback.h +++ b/src/security/vboot/antirollback.h @@ -37,6 +37,7 @@ #include <types.h> #include <security/tpm/tspi.h> +#include <vb2_sha.h> struct vb2_context; enum vb2_pcr_digest; diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 1787eb1..7928520 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -81,7 +81,6 @@ TOOLCPPFLAGS += -I$(objutil)/cbfstool TOOLCPPFLAGS += -I$(top)/src/commonlib/include TOOLCPPFLAGS += -include $(top)/src/commonlib/include/commonlib/compiler.h -TOOLCPPFLAGS += -DNEED_VB2_SHA_LIBRARY TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/firmware/include TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/firmware/2lib/include # UEFI header file support. It's not pretty, but that's what we currently diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 6ccc4f9..a7223a2 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -22,6 +22,7 @@ #include <string.h> #include <strings.h> #include <commonlib/endian.h> +#include <vb2_sha.h> #include "common.h" #include "cbfs_image.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/32454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f32174dbf3de05fbe5279cb8017888757abf368 Gerrit-Change-Number: 32454 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vboot: communicate display requirements with vb2api_fw_phase1
by Joel Kitching (Code Review) 09 May '19

09 May '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32324 Change subject: vboot: communicate display requirements with vb2api_fw_phase1 ...................................................................... vboot: communicate display requirements with vb2api_fw_phase1 Input: tell vb2api_fw_phase1 if display unconditionally available Output: vb2api_fw_phase1 tells coreboot if it shall declare display as being available, based on some internal request Move the vboot_set_declares_display call into verstage_main. BUG=b:124141368, b:124192753, chromium:948529 TEST=make clean && make test-abuild CQ-DEPEND=CL:1564232 BRANCH=none Change-Id: I81c82c46303564b63b8a32e7f80beb9d891a4628 Cq-Depend: chromium:1564232 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/vboot_handoff.c M src/security/vboot/vboot_logic.c 2 files changed, 13 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/32324/1 diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c index 85b1611..ddf0a78 100644 --- a/src/security/vboot/vboot_handoff.c +++ b/src/security/vboot/vboot_handoff.c @@ -76,14 +76,11 @@ vb_sd->flags |= VBSD_BOOT_DEV_SWITCH_ON; vb_sd->flags |= VBSD_LF_DEV_SWITCH_ON; } - /* Inform vboot if the display was requested by vboot kernel phase - or enabled by dev/rec mode. */ + /* TODO(chromium:948529): Remove these two flags after downstream + vboot code longer reads them. */ if (vboot_wants_oprom() || vb2_sd->recovery_reason || - vb2_sd->flags & VB2_SD_FLAG_DEV_MODE_ENABLED) { - vboot_get_working_data()->flags |= VBOOT_FLAG_DISPLAY_REQUESTED; + vb2_sd->flags & VB2_SD_FLAG_DEV_MODE_ENABLED) vb_sd->flags |= VBSD_OPROM_LOADED; - } - /* TODO: Remove when depthcharge no longer reads this flag. */ if (CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) vb_sd->flags |= VBSD_OPROM_MATTERS; diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 2a8e619..ef6b82c 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -336,6 +336,10 @@ if (CONFIG(VBOOT_LID_SWITCH) && !get_lid_switch()) ctx.flags |= VB2_CONTEXT_NOFAIL_BOOT; + /* Mainboard/SoC always initializes display. */ + if (!CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) + ctx.flags |= VB2_CONTEXT_DISPLAY_REQUESTED; + /* Do early init (set up secdata and NVRAM, load GBB) */ printk(BIOS_INFO, "Phase 1\n"); rv = vb2api_fw_phase1(&ctx); @@ -360,6 +364,12 @@ vboot_reboot(); } + /* Is vboot declaring that display is available? If so, we should mark + it down, so that the mainboard/SoC knows to initialize display. */ + if (ctx.flags & VB2_CONTEXT_DISPLAY_REQUESTED) + vboot_get_working_data()->flags + |= VBOOT_FLAGS_DISPLAY_REQUESTED; + /* Determine which firmware slot to boot (based on NVRAM) */ printk(BIOS_INFO, "Phase 2\n"); rv = vb2api_fw_phase2(&ctx); -- To view, visit https://review.coreboot.org/c/coreboot/+/32324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81c82c46303564b63b8a32e7f80beb9d891a4628 Gerrit-Change-Number: 32324 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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