coreboot-gerrit May 2019

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Change in ...coreboot[master]: soc/skl/memmap: calculate mem size even if IGD undefined in devtree
by Maxim Polyakov (Code Review) 07 May '19

07 May '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32614 Change subject: soc/skl/memmap: calculate mem size even if IGD undefined in devtree ...................................................................... soc/skl/memmap: calculate mem size even if IGD undefined in devtree The DRAM base memory should be calculated even if IGD isn`t defined in the board device tree Tested on Asrock H110M-DVS Change-Id: I3da51473e6c06da803bd969a4a6dff792c18f962 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/skylake/memmap.c 1 file changed, 8 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/32614/1 diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index fde916a..40c52fe 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -170,13 +170,13 @@ } /* Calculate Intel Traditional Memory size based on GSM, DSM, TSEG and DPR. */ -static size_t calculate_traditional_mem_size(uintptr_t dram_base, - const struct device *dev) +static size_t calculate_traditional_mem_size(uintptr_t dram_base) { + const struct device *idg_dev = dev_find_slot(0, SA_DEVFN_IGD); uintptr_t traditional_mem_base = dram_base; size_t traditional_mem_size; - if (dev->enabled) { + if (idg_dev && idg_dev->enabled) { /* Read BDSM from Host Bridge */ traditional_mem_base -= sa_get_dsm_size(); @@ -200,14 +200,14 @@ * Calculate Intel Reserved Memory size based on * PRMRR size, Trace Hub config and PTT selection. */ -static size_t calculate_reserved_mem_size(uintptr_t dram_base, - const struct device *dev) +static size_t calculate_reserved_mem_size(uintptr_t dram_base) { + const struct device *root_dev = dev_find_slot(0, SA_DEVFN_ROOT); uintptr_t reserve_mem_base = dram_base; size_t reserve_mem_size; const struct soc_intel_skylake_config *config; - config = dev->chip_info; + config = root_dev->chip_info; /* Get PRMRR size */ reserve_mem_base -= get_prmrr_size(reserve_mem_base, config); @@ -259,20 +259,15 @@ static uintptr_t calculate_dram_base(size_t *reserved_mem_size) { uintptr_t dram_base; - const struct device *dev; - - dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0)); - if (!dev) - die("ERROR - IGD device not found!"); /* Read TOLUD from Host Bridge offset */ dram_base = sa_get_tolud_base(); /* Get Intel Traditional Memory Range Size */ - dram_base -= calculate_traditional_mem_size(dram_base, dev); + dram_base -= calculate_traditional_mem_size(dram_base); /* Get Intel Reserved Memory Range Size */ - *reserved_mem_size = calculate_reserved_mem_size(dram_base, dev); + *reserved_mem_size = calculate_reserved_mem_size(dram_base); dram_base -= *reserved_mem_size; -- To view, visit https://review.coreboot.org/c/coreboot/+/32614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3da51473e6c06da803bd969a4a6dff792c18f962 Gerrit-Change-Number: 32614 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

4 9

Change in ...coreboot[master]: sb/i82801gx/watchdog: Use {read,write}_pmbase function
by HAOUAS Elyes (Code Review) 07 May '19

07 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32533 Change subject: sb/i82801gx/watchdog: Use {read,write}_pmbase function ...................................................................... sb/i82801gx/watchdog: Use {read,write}_pmbase function Use already defined common/pmbase functions. Also magic numbers replaced by macro and includes sorted. Change-Id: I704780b6ae7238560dcb72fc027addc1089e0674 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/watchdog.c 1 file changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/32533/1 diff --git a/src/southbridge/intel/i82801gx/watchdog.c b/src/southbridge/intel/i82801gx/watchdog.c index 12284b4..6b2a204 100644 --- a/src/southbridge/intel/i82801gx/watchdog.c +++ b/src/southbridge/intel/i82801gx/watchdog.c @@ -14,37 +14,37 @@ * GNU General Public License for more details. */ -#include <console/console.h> #include <arch/io.h> -#include <device/pci_ops.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <southbridge/intel/common/pmbase.h> #include <watchdog.h> +#include "i82801gx.h" + void watchdog_off(void) { struct device *dev; - unsigned long value, base; + unsigned long value; - /* Turn off the ICH7 watchdog. */ dev = pcidev_on_root(0x1f, 0); /* Enable I/O space. */ - value = pci_read_config16(dev, 0x04); - value |= (1 << 10); - pci_write_config16(dev, 0x04, value); - - /* Get TCO base. */ - base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60; + value = pci_read_config16(dev, PCI_COMMAND); + value |= PCI_COMMAND_INT_DISABLE; + pci_write_config16(dev, PCI_COMMAND, value); /* Disable the watchdog timer. */ - value = inw(base + 0x08); + value = read_pmbase16(TCO1_CNT); value |= 1 << 11; - outw(value, base + 0x08); + write_pmbase16(TCO1_CNT, value); /* Clear TCO timeout status. */ - outw(0x0008, base + 0x04); - outw(0x0002, base + 0x06); + write_pmbase16(TCO1_CNT + 0x04, (1 << 3)); + write_pmbase16(TCO1_CNT + 0x06, (1 << 2)); printk(BIOS_DEBUG, "ICH7 watchdog disabled\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I704780b6ae7238560dcb72fc027addc1089e0674 Gerrit-Change-Number: 32533 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 28

Change in ...coreboot[master]: google/kukui: Enable boot sound support
by Jiaxin Yu (Code Review) 07 May '19

07 May '19

Jiaxin Yu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32459 Change subject: google/kukui: Enable boot sound support ...................................................................... google/kukui: Enable boot sound support Config enable gpio for speaker amp max98357a. BUG=b:117254418 TEST=Build pass and verified on kukui p1 board BRANCH=None Change-Id: I97655702dff402245326d2eff71fae0e336df9f5 Signed-off-by: Jiaxin Yu <jiaxin.yu(a)mediatek.com> --- M src/mainboard/google/kukui/chromeos.c M src/mainboard/google/kukui/gpio.h M src/mainboard/google/kukui/mainboard.c 3 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/32459/1 diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index 44e75e2..ad2edaa 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -27,6 +27,7 @@ gpio_input_pullup(EC_IRQ); gpio_input_pullup(CR50_IRQ); gpio_output(GPIO_RESET, 0); + gpio_output(EN_SPK_AMP, 0); } void fill_lb_gpios(struct lb_gpios *gpios) @@ -38,6 +39,7 @@ {EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"}, {EC_IRQ.id, ACTIVE_LOW, -1, "EC interrupt"}, {CR50_IRQ.id, ACTIVE_HIGH, -1, "TPM interrupt"}, + {EN_SPK_AMP.id, ACTIVE_HIGH, -1, "SPK enable"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } diff --git a/src/mainboard/google/kukui/gpio.h b/src/mainboard/google/kukui/gpio.h index 92d238e..0a98997 100644 --- a/src/mainboard/google/kukui/gpio.h +++ b/src/mainboard/google/kukui/gpio.h @@ -23,6 +23,7 @@ #define EC_IN_RW GPIO(PERIPHERAL_EN14) #define CR50_IRQ GPIO(PERIPHERAL_EN3) #define GPIO_RESET GPIO(PERIPHERAL_EN8) +#define EN_SPK_AMP GPIO(PERIPHERAL_EN12) void setup_chromeos_gpios(void); diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index e1d8f5f..40b8a49 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -16,6 +16,7 @@ #include <device/device.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> +#include <soc/mtcmos.h> #include <soc/usb.h> static void configure_emmc(void) @@ -37,10 +38,22 @@ setup_usb_host(); } +static void configure_audio(void) +{ + /* Audio PWR*/ + mtcmos_audio_power_on(); + + /* SoC I2S */ + gpio_set_mode(GPIO(CAM_RST0), PAD_CAM_RST0_FUNC_I2S2_LRCK); + gpio_set_mode(GPIO(CAM_PDN1), PAD_CAM_PDN1_FUNC_I2S2_BCK); + gpio_set_mode(GPIO(CAM_PDN0), PAD_CAM_PDN0_FUNC_I2S2_MCK); + gpio_set_mode(GPIO(EINT3), PAD_EINT3_FUNC_I2S3_DO); +} static void mainboard_init(struct device *dev) { configure_emmc(); configure_usb(); + configure_audio(); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/32459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97655702dff402245326d2eff71fae0e336df9f5 Gerrit-Change-Number: 32459 Gerrit-PatchSet: 1 Gerrit-Owner: Jiaxin Yu <jiaxin.yu(a)mediatek.com> Gerrit-MessageType: newchange

5 9

Change in ...coreboot[master]: intel/fsp1_1: Drop remnants of `pei_data`
by Nico Huber (Code Review) 07 May '19

07 May '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32596 Change subject: intel/fsp1_1: Drop remnants of `pei_data` ...................................................................... intel/fsp1_1: Drop remnants of `pei_data` `pei_data` was a struct with blob parameters from pre-FSP times. Somehow, it sneaked into upstream FSP1.1 support (probably because early board ports were written for a different blob). When added upstream, its usage was already perverted. It was declared at SoC level but mostly used to pass mainboard data from mainboard code to itself and FSP data from FSP code to itself. Now that no board/ SoC code uses it anymore, we can finally drop it. Change-Id: Ib0bc402703188539cf2254bdc395cca9dd32d863 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/drivers/intel/fsp1_1/romstage.c M src/mainboard/intel/kblrvp/spd/spd_util.c D src/soc/intel/braswell/include/soc/pei_data.h D src/soc/intel/braswell/include/soc/pei_wrapper.h M src/soc/intel/braswell/include/soc/romstage.h M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/include/fsp11/soc/romstage.h D src/soc/intel/skylake/include/soc/pei_data.h D src/soc/intel/skylake/include/soc/pei_wrapper.h D src/soc/intel/skylake/pei_data.c M src/soc/intel/skylake/romstage/romstage.c 12 files changed, 0 insertions(+), 249 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/32596/1 diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index 2e45f40..fbd956a 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -25,13 +25,11 @@ #include <fsp/car.h> #include <fsp/util.h> #include <soc/intel/common/mma.h> -#include <soc/pei_wrapper.h> #include <soc/pm.h> /* chip_power_state */ struct romstage_params { uint32_t fsp_version; struct chipset_power_state *power_state; - struct pei_data *pei_data; void *chipset_context; /* Fast boot and S3 resume MRC data */ diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index ff93565..ba7806e 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -41,9 +41,7 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih) { void *top_of_stack; - struct pei_data pei_data; struct romstage_params params = { - .pei_data = &pei_data, .chipset_context = fih, }; @@ -55,8 +53,6 @@ if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS)) intel_update_microcode_from_cbfs(); - memset(&pei_data, 0, sizeof(pei_data)); - /* Display parameters */ if (!CONFIG(NO_MMCONF_SUPPORT)) printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c index 1004384..f22dcaa 100644 --- a/src/mainboard/intel/kblrvp/spd/spd_util.c +++ b/src/mainboard/intel/kblrvp/spd/spd_util.c @@ -16,8 +16,6 @@ #include <arch/byteorder.h> #include <stdint.h> #include <string.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> #include "../board_id.h" #include "spd.h" diff --git a/src/soc/intel/braswell/include/soc/pei_data.h b/src/soc/intel/braswell/include/soc/pei_data.h deleted file mode 100644 index df18dc0..0000000 --- a/src/soc/intel/braswell/include/soc/pei_data.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * UEFI PEI wrapper - * - * Copyright (C) 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Google Inc. nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _PEI_DATA_H_ -#define _PEI_DATA_H_ - -#include <types.h> - -#define PEI_VERSION 22 - -#define ABI_X86 __attribute__((regparm(0))) - -typedef void ABI_X86(*tx_byte_func)(unsigned char byte); - -struct pei_data { - /* Chip settings */ - void *spd_data_ch0; - void *spd_data_ch1; - uint8_t spd_ch0_config; - uint8_t spd_ch1_config; -}; - -typedef struct pei_data PEI_DATA; - -#endif /* _PEI_DATA_H_ */ diff --git a/src/soc/intel/braswell/include/soc/pei_wrapper.h b/src/soc/intel/braswell/include/soc/pei_wrapper.h deleted file mode 100644 index 3222328..0000000 --- a/src/soc/intel/braswell/include/soc/pei_wrapper.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_PEI_WRAPPER_H_ -#define _SOC_PEI_WRAPPER_H_ - -#include <soc/pei_data.h> - -typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data); - -void broadwell_fill_pei_data(struct pei_data *pei_data); -void mainboard_fill_pei_data(struct pei_data *pei_data); - -#endif diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index 2512430..633233e 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -20,14 +20,12 @@ #include <stdint.h> #include <fsp/romstage.h> #include <fsp/util.h> -#include <soc/pei_data.h> #include <soc/pm.h> void gfx_init(void); void tco_disable(void); void punit_init(void); int early_spi_read_wpsr(u8 *sr); -void mainboard_fill_spd_data(struct pei_data *pei_data); void set_max_freq(void); /* romstage_common.c functions */ diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ee2c928..e9f555f 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -35,7 +35,6 @@ romstage-y += i2c.c romstage-y += memmap.c romstage-y += me.c -romstage-y += pei_data.c romstage-y += pmc.c romstage-y += pmutil.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c @@ -58,7 +57,6 @@ ramstage-y += me.c ramstage-y += memmap.c ramstage-y += p2sb.c -ramstage-y += pei_data.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c diff --git a/src/soc/intel/skylake/include/fsp11/soc/romstage.h b/src/soc/intel/skylake/include/fsp11/soc/romstage.h index 36825f7..3869310 100644 --- a/src/soc/intel/skylake/include/fsp11/soc/romstage.h +++ b/src/soc/intel/skylake/include/fsp11/soc/romstage.h @@ -24,6 +24,4 @@ void enable_smbus(void); int smbus_read_byte(unsigned int device, unsigned int address); -void mainboard_fill_spd_data(struct pei_data *pei_data); - #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pei_data.h b/src/soc/intel/skylake/include/soc/pei_data.h deleted file mode 100644 index 5ea2190..0000000 --- a/src/soc/intel/skylake/include/soc/pei_data.h +++ /dev/null @@ -1,89 +0,0 @@ -/* - * UEFI PEI wrapper - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Google Inc. nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _PEI_DATA_H_ -#define _PEI_DATA_H_ - -#include <types.h> - -#define PEI_VERSION 22 - -#define ABI_X86 __attribute__((regparm(0))) - -typedef void ABI_X86(*tx_byte_func)(unsigned char byte); - -struct pei_data { - uint32_t pei_version; - - int ec_present; - - /* Console output function */ - tx_byte_func tx_byte; - - /* - * DIMM SPD data for memory down configurations - * [CHANNEL][SLOT][SPD] - */ - uint8_t spd_data[2][2][512]; - - /* - * LPDDR3 DQ byte map - * [CHANNEL][ITERATION][2] - * - * Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side) - * DQByteMap[0] - ClkDQByteMap: - * - If clock is per rank, program to [0xFF, 0xFF] - * - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF] - * - If clock is shared by 2 ranks but does not go to all bytes, - * Entry[i] defines which DQ bytes Group i services - * DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB - * DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB - * DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB - * For DDR, DQByteMap[3:1] = [0xFF, 0] - * DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] - * since we have 1 CTL / rank - * DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] - * since we have 1 CA Vref - */ - uint8_t dq_map[2][12]; - - /* - * LPDDR3 Map from CPU DQS pins to SDRAM DQS pins - * [CHANNEL][MAX_BYTES] - */ - uint8_t dqs_map[2][8]; - uint16_t RcompResistor[3]; - uint16_t RcompTarget[5]; - - int mem_cfg_id; -} __packed; - -typedef struct pei_data PEI_DATA; - -#endif /* _PEI_DATA_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pei_wrapper.h b/src/soc/intel/skylake/include/soc/pei_wrapper.h deleted file mode 100644 index d53fe8b..0000000 --- a/src/soc/intel/skylake/include/soc/pei_wrapper.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_PEI_WRAPPER_H_ -#define _SOC_PEI_WRAPPER_H_ - -#include <soc/pei_data.h> - -typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data); - -void soc_fill_pei_data(struct pei_data *pei_data); -void mainboard_fill_pei_data(struct pei_data *pei_data); - -#endif diff --git a/src/soc/intel/skylake/pei_data.c b/src/soc/intel/skylake/pei_data.c deleted file mode 100644 index 7d314a1..0000000 --- a/src/soc/intel/skylake/pei_data.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/streams.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <stdlib.h> -#include <stdint.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> - -#include "chip.h" - -static void ABI_X86 send_to_console(unsigned char b) -{ - console_tx_byte(b); -} - -void soc_fill_pei_data(struct pei_data *pei_data) -{ - /* Set the parameters for MemoryInit */ - pei_data->pei_version = PEI_VERSION; - pei_data->tx_byte = &send_to_console; -} diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 8ec08c2..12239ae 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -26,7 +26,6 @@ #include <intelblocks/fast_spi.h> #include <intelblocks/pmclib.h> #include <soc/pci_devs.h> -#include <soc/pei_wrapper.h> #include <soc/pm.h> #include <soc/pmc.h> #include <soc/serialio.h> @@ -44,9 +43,6 @@ /* Program MCHBAR and DMIBAR */ systemagent_early_init(); - /* Prepare to initialize memory */ - soc_fill_pei_data(params->pei_data); - const struct device *const dev = pcidev_path_on_root(PCH_DEVFN_LPC); const struct soc_intel_skylake_config *const config = dev ? dev->chip_info : NULL; -- To view, visit https://review.coreboot.org/c/coreboot/+/32596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0bc402703188539cf2254bdc395cca9dd32d863 Gerrit-Change-Number: 32596 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: mb/purism/librem_skl: Refactor to get rid of `pei_data`
by Nico Huber (Code Review) 07 May '19

07 May '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32595 Change subject: mb/purism/librem_skl: Refactor to get rid of `pei_data` ...................................................................... mb/purism/librem_skl: Refactor to get rid of `pei_data` The SoC specific `struct pei_data` was filled with values that were never consumed anywhere again. So just merge the used code into `romstage.c` where it's effectively used. Change-Id: I499b3cfcdd5400ea132749555d433a2d8a9471a3 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/purism/librem_skl/Makefile.inc D src/mainboard/purism/librem_skl/pei_data.c D src/mainboard/purism/librem_skl/pei_data.h M src/mainboard/purism/librem_skl/romstage.c 4 files changed, 34 insertions(+), 93 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/32595/1 diff --git a/src/mainboard/purism/librem_skl/Makefile.inc b/src/mainboard/purism/librem_skl/Makefile.inc index 5a7131f..35f0f6c 100644 --- a/src/mainboard/purism/librem_skl/Makefile.inc +++ b/src/mainboard/purism/librem_skl/Makefile.inc @@ -13,8 +13,5 @@ ## GNU General Public License for more details. ## -romstage-y += pei_data.c - -ramstage-y += pei_data.c ramstage-y += ramstage.c ramstage-y += hda_verb.c diff --git a/src/mainboard/purism/librem_skl/pei_data.c b/src/mainboard/purism/librem_skl/pei_data.c deleted file mode 100644 index 0be917d..0000000 --- a/src/mainboard/purism/librem_skl/pei_data.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2015 Intel Corporation - * Copyright (C) 2017 Purism SPC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include "pei_data.h" - -void mainboard_fill_dq_map_data(void *dq_map_ptr) -{ - /* DQ byte map */ - const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, - 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); -} - -void mainboard_fill_dqs_map_data(void *dqs_map_ptr) -{ - /* DQS CPU<>DRAM map */ - const u8 dqs_map[2][8] = { - { 0, 1, 3, 2, 4, 5, 6, 7 }, - { 1, 0, 4, 5, 2, 3, 6, 7 } }; - memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); -} - -void mainboard_fill_rcomp_res_data(void *rcomp_ptr) -{ - /* Rcomp resistor */ - const u16 RcompResistor[3] = { 121, 81, 100 }; - memcpy(rcomp_ptr, RcompResistor, - sizeof(RcompResistor)); -} - -void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) -{ - /* Rcomp target */ - const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; - memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); -} - -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - mainboard_fill_dq_map_data(&pei_data->dq_map); - mainboard_fill_dqs_map_data(&pei_data->dqs_map); - mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); - mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); -} diff --git a/src/mainboard/purism/librem_skl/pei_data.h b/src/mainboard/purism/librem_skl/pei_data.h deleted file mode 100644 index 320d980..0000000 --- a/src/mainboard/purism/librem_skl/pei_data.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Purism SPC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _MAINBOARD_PEI_DATA_H_ -#define _MAINBOARD_PEI_DATA_H_ - -void mainboard_fill_dq_map_data(void *dq_map_ptr); -void mainboard_fill_dqs_map_data(void *dqs_map_ptr); -void mainboard_fill_rcomp_res_data(void *rcomp_ptr); -void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); - -#endif diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c index 63d148a..9ff9e66 100644 --- a/src/mainboard/purism/librem_skl/romstage.c +++ b/src/mainboard/purism/librem_skl/romstage.c @@ -19,7 +19,40 @@ #include <assert.h> #include <soc/romstage.h> #include <spd_bin.h> -#include "pei_data.h" + +static void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} void mainboard_memory_init_params(FSPM_UPD *mupd) { -- To view, visit https://review.coreboot.org/c/coreboot/+/32595 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I499b3cfcdd5400ea132749555d433a2d8a9471a3 Gerrit-Change-Number: 32595 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: mb/google/glados: Refactor to get rid of `pei_data`
by Nico Huber (Code Review) 07 May '19

07 May '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32594 Change subject: mb/google/glados: Refactor to get rid of `pei_data` ...................................................................... mb/google/glados: Refactor to get rid of `pei_data` The SoC specific `struct pei_data` was filled with values that were later only consumed by the mainboard code again. Avoid jumping through this hoop and fill FSP UPDs directly. Change-Id: I040f4a55b4f4bad3f6072920e5e2eceded4cb9bb Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/google/glados/romstage.c M src/mainboard/google/glados/spd/spd.c A src/mainboard/google/glados/spd/spd_util.h M src/mainboard/google/glados/variants/asuka/variant.c M src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h M src/mainboard/google/glados/variants/caroline/variant.c M src/mainboard/google/glados/variants/cave/variant.c M src/mainboard/google/glados/variants/chell/variant.c M src/mainboard/google/glados/variants/glados/variant.c M src/mainboard/google/glados/variants/lars/variant.c M src/mainboard/google/glados/variants/sentry/variant.c 11 files changed, 126 insertions(+), 109 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/32594/1 diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index 81f0866..b62cd21 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -18,13 +18,13 @@ #include <string.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> #include <soc/romstage.h> -#include "spd/spd.h" #include <variant/ec.h> #include <variant/gpio.h> +#include "spd/spd_util.h" +#include "spd/spd.h" + void mainboard_romstage_entry(struct romstage_params *params) { #ifdef EC_ENABLE_KEYBOARD_BACKLIGHT @@ -32,18 +32,6 @@ if (params->power_state->prev_sleep_state != ACPI_S3) google_chromeec_kbbacklight(25); #endif - /* Get SPD index */ - gpio_t spd_gpios[] = { - GPIO_MEM_CONFIG_0, - GPIO_MEM_CONFIG_1, - GPIO_MEM_CONFIG_2, - GPIO_MEM_CONFIG_3, - }; - params->pei_data->mem_cfg_id = - gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); - /* Fill out PEI DATA */ - mainboard_fill_pei_data(params->pei_data); - mainboard_fill_spd_data(params->pei_data); /* Initialize memory */ romstage_common(params); } @@ -51,26 +39,18 @@ void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { - if (params->pei_data->spd_data[0][0][0] != 0) { - memory_params->MemorySpdPtr00 = - (UINT32)(params->pei_data->spd_data[0][0]); - memory_params->MemorySpdPtr10 = - (UINT32)(params->pei_data->spd_data[1][0]); - } - memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0], - sizeof(params->pei_data->dq_map[0])); - memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1], - sizeof(params->pei_data->dq_map[1])); - memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0], - sizeof(params->pei_data->dqs_map[0])); - memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1], - sizeof(params->pei_data->dqs_map[1])); - memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor, - sizeof(params->pei_data->RcompResistor)); - memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget, - sizeof(params->pei_data->RcompTarget)); + /* Get SPD index */ + const gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + const int spd_idx = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); + memory_params->MemorySpdDataLen = SPD_LEN; memory_params->DqPinsInterleaved = FALSE; - if (CONFIG(BOARD_GOOGLE_CAROLINE)) - memory_params->DdrFreqLimit = 1600; + + variant_fill_memory_params(memory_params, spd_idx); + mainboard_fill_spd_data(memory_params, spd_idx); } diff --git a/src/mainboard/google/glados/spd/spd.c b/src/mainboard/google/glados/spd/spd.c index 391b702..4ed3d6f 100644 --- a/src/mainboard/google/glados/spd/spd.c +++ b/src/mainboard/google/glados/spd/spd.c @@ -19,10 +19,11 @@ #include <console/console.h> #include <gpio.h> #include <soc/gpio.h> -#include <soc/pei_data.h> #include <soc/romstage.h> #include <string.h> #include <baseboard/variant.h> + +#include "spd_util.h" #include "spd.h" static void mainboard_print_spd_info(uint8_t spd[]) @@ -83,13 +84,12 @@ } /* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *pei_data) +void mainboard_fill_spd_data( + MEMORY_INIT_UPD *const memory_params, const int spd_index) { char *spd_file; size_t spd_file_len; - int spd_index; - spd_index = pei_data->mem_cfg_id; printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ @@ -110,13 +110,13 @@ /* Assume same memory in both channels */ spd_index *= SPD_LEN; - memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN); + memory_params->MemorySpdPtr00 = spd_file + spd_index; if (is_dual_channel(spd_index)) - memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN); + memory_params->MemorySpdPtr10 = spd_file + spd_index; /* Make sure a valid SPD was found */ - if (pei_data->spd_data[0][0][0] == 0) + if (spd_file[spd_index] == 0) die("Invalid SPD data."); - mainboard_print_spd_info(pei_data->spd_data[0][0]); + mainboard_print_spd_info(spd_file + spd_index); } diff --git a/src/mainboard/google/glados/spd/spd_util.h b/src/mainboard/google/glados/spd/spd_util.h new file mode 100644 index 0000000..6cf1fe2 --- /dev/null +++ b/src/mainboard/google/glados/spd/spd_util.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SPD_UTIL_H +#define SPD_UTIL_H + +#include <fsp/soc_binding.h> + +void mainboard_fill_spd_data(MEMORY_INIT_UPD *, int spd_index); + +#endif /* SPD_UTIL_H */ diff --git a/src/mainboard/google/glados/variants/asuka/variant.c b/src/mainboard/google/glados/variants/asuka/variant.c index 13cfe4f..6b91877 100644 --- a/src/mainboard/google/glados/variants/asuka/variant.c +++ b/src/mainboard/google/glados/variants/asuka/variant.c @@ -17,10 +17,10 @@ #include <stdint.h> #include <string.h> #include <baseboard/variant.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <fsp/soc_binding.h> -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_fill_memory_params( + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -39,12 +39,14 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - memcpy(pei_data->RcompTarget, RcompTarget, - sizeof(RcompTarget)); + memcpy(memory_params->DqByteMapCh0, dq_map, + sizeof(memory_params->DqByteMapCh0) * 2); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, + sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->RcompResistor, RcompResistor, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, RcompTarget, + sizeof(memory_params->RcompTarget)); } int is_dual_channel(const int spd_index) diff --git a/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h b/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h index bbab7fc..3e2079b 100644 --- a/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h +++ b/src/mainboard/google/glados/variants/baseboard/include/baseboard/variant.h @@ -15,7 +15,10 @@ #ifndef GLADOS_VARIANT_H #define GLADOS_VARIANT_H +#include <fsp/soc_binding.h> + int is_dual_channel(const int spd_index); void mainboard_gpio_smi_sleep(void); +void variant_fill_memory_params(MEMORY_INIT_UPD *memory_params, int spd_index); #endif /* GLADOS_VARIANT_H */ diff --git a/src/mainboard/google/glados/variants/caroline/variant.c b/src/mainboard/google/glados/variants/caroline/variant.c index a00eacf..ee4d8a3 100644 --- a/src/mainboard/google/glados/variants/caroline/variant.c +++ b/src/mainboard/google/glados/variants/caroline/variant.c @@ -15,14 +15,14 @@ */ #include <baseboard/variant.h> +#include <fsp/soc_binding.h> #include <gpio.h> #include <stdint.h> #include <string.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> #include <variant/gpio.h> -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_fill_memory_params( + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -41,12 +41,15 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - memcpy(pei_data->RcompTarget, RcompTarget, - sizeof(RcompTarget)); + memcpy(memory_params->DqByteMapCh0, dq_map, + sizeof(memory_params->DqByteMapCh0) * 2); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, + sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->RcompResistor, RcompResistor, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, RcompTarget, + sizeof(memory_params->RcompTarget)); + memory_params->DdrFreqLimit = 1600; } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/cave/variant.c b/src/mainboard/google/glados/variants/cave/variant.c index 2ce0a900..181c4a4 100644 --- a/src/mainboard/google/glados/variants/cave/variant.c +++ b/src/mainboard/google/glados/variants/cave/variant.c @@ -15,14 +15,14 @@ */ #include <baseboard/variant.h> +#include <fsp/soc_binding.h> #include <gpio.h> #include <stdint.h> #include <string.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> #include <variant/gpio.h> -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_fill_memory_params( + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -41,12 +41,14 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - memcpy(pei_data->RcompTarget, RcompTarget, - sizeof(RcompTarget)); + memcpy(memory_params->DqByteMapCh0, dq_map, + sizeof(memory_params->DqByteMapCh0) * 2); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, + sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->RcompResistor, RcompResistor, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, RcompTarget, + sizeof(memory_params->RcompTarget)); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/chell/variant.c b/src/mainboard/google/glados/variants/chell/variant.c index da83ed0..3cb91b8 100644 --- a/src/mainboard/google/glados/variants/chell/variant.c +++ b/src/mainboard/google/glados/variants/chell/variant.c @@ -15,14 +15,14 @@ */ #include <baseboard/variant.h> +#include <fsp/soc_binding.h> #include <gpio.h> #include <stdint.h> #include <string.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> #include <variant/gpio.h> -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_fill_memory_params( + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -41,12 +41,14 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - memcpy(pei_data->RcompTarget, RcompTarget, - sizeof(RcompTarget)); + memcpy(memory_params->DqByteMapCh0, dq_map, + sizeof(memory_params->DqByteMapCh0) * 2); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, + sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->RcompResistor, RcompResistor, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, RcompTarget, + sizeof(memory_params->RcompTarget)); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/glados/variant.c b/src/mainboard/google/glados/variants/glados/variant.c index 2ce0a900..181c4a4 100644 --- a/src/mainboard/google/glados/variants/glados/variant.c +++ b/src/mainboard/google/glados/variants/glados/variant.c @@ -15,14 +15,14 @@ */ #include <baseboard/variant.h> +#include <fsp/soc_binding.h> #include <gpio.h> #include <stdint.h> #include <string.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> #include <variant/gpio.h> -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_fill_memory_params( + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -41,12 +41,14 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - memcpy(pei_data->RcompTarget, RcompTarget, - sizeof(RcompTarget)); + memcpy(memory_params->DqByteMapCh0, dq_map, + sizeof(memory_params->DqByteMapCh0) * 2); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, + sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->RcompResistor, RcompResistor, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, RcompTarget, + sizeof(memory_params->RcompTarget)); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/lars/variant.c b/src/mainboard/google/glados/variants/lars/variant.c index 4fe88ef..9f95e34 100644 --- a/src/mainboard/google/glados/variants/lars/variant.c +++ b/src/mainboard/google/glados/variants/lars/variant.c @@ -17,8 +17,7 @@ #include <stdint.h> #include <string.h> #include <baseboard/variant.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <fsp/soc_binding.h> #define K4E6E304EB_MEM_ID 0x5 @@ -29,7 +28,8 @@ #define MEM_SINGLE_CHANB 0xb #define MEM_SINGLE_CHANC 0xc -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_fill_memory_params( + MEMORY_INIT_UPD *const params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -54,17 +54,18 @@ /* Default Rcomp Target assignment */ const u16 *targeted_rcomp = RcompTarget; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - /* Override Rcomp Target assignment for specific SKU(s) */ - if (pei_data->mem_cfg_id == K4E6E304EB_MEM_ID) + if (spd_index == K4E6E304EB_MEM_ID) targeted_rcomp = StrengthendRcompTarget; - memcpy(pei_data->RcompTarget, targeted_rcomp, - sizeof(pei_data->RcompTarget)); + memcpy(params->DqByteMapCh0, dq_map, + sizeof(params->DqByteMapCh0) * 2); + memcpy(params->DqsMapCpu2DramCh0, dqs_map, + sizeof(params->DqsMapCpu2DramCh0) * 2); + memcpy(params->RcompResistor, RcompResistor, + sizeof(params->RcompResistor)); + memcpy(params->RcompTarget, targeted_rcomp, + sizeof(params->RcompTarget)); } int is_dual_channel(const int spd_index) diff --git a/src/mainboard/google/glados/variants/sentry/variant.c b/src/mainboard/google/glados/variants/sentry/variant.c index 00f49fe..f7640f3 100644 --- a/src/mainboard/google/glados/variants/sentry/variant.c +++ b/src/mainboard/google/glados/variants/sentry/variant.c @@ -17,12 +17,12 @@ #include <stdint.h> #include <string.h> #include <baseboard/variant.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> +#include <fsp/soc_binding.h> #define K4E6E304EE_MEM_ID 0x3 -void mainboard_fill_pei_data(struct pei_data *pei_data) +void variant_fill_memory_params( + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -47,15 +47,16 @@ /* Default Rcomp Target assignment */ const u16 *targeted_rcomp = RcompTarget; - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - /* Override Rcomp Target assignment for specific SKU(s) */ if (pei_data->mem_cfg_id == K4E6E304EE_MEM_ID) targeted_rcomp = StrengthendRcompTarget; - memcpy(pei_data->RcompTarget, targeted_rcomp, - sizeof(pei_data->RcompTarget)); + memcpy(memory_params->DqByteMapCh0, dq_map, + sizeof(memory_params->DqByteMapCh0) * 2); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, + sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->RcompResistor, RcompResistor, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, targeted_rcomp, + sizeof(memory_params->RcompTarget)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I040f4a55b4f4bad3f6072920e5e2eceded4cb9bb Gerrit-Change-Number: 32594 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: mb/google/cyan: Refactor to get rid of `pei_data`
by Nico Huber (Code Review) 07 May '19

07 May '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32593 Change subject: mb/google/cyan: Refactor to get rid of `pei_data` ...................................................................... mb/google/cyan: Refactor to get rid of `pei_data` The SoC specific `struct pei_data` was filled with values that were later only consumed by the mainboard code again. Avoid jumping through this hoop and fill FSP UPDs directly. The provided solution locates the SPD data in CBFS again to fill SMBIOS tables. This is not perfect. OTOH, this code isn't mainboard specific and doesn't belong here anyway. Change-Id: Ib6103d5b9550846fe17c926631a013ff80b9598f Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/google/cyan/romstage.c M src/mainboard/google/cyan/spd/spd.c M src/mainboard/google/cyan/spd/spd_util.h 3 files changed, 43 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/32593/1 diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c index 5470b9c..5d47339 100644 --- a/src/mainboard/google/cyan/romstage.c +++ b/src/mainboard/google/cyan/romstage.c @@ -17,13 +17,11 @@ #include <soc/romstage.h> #include <baseboard/variants.h> +#include "spd/spd_util.h" + /* All FSP specific code goes in this block */ void mainboard_romstage_entry(struct romstage_params *rp) { - struct pei_data *ps = rp->pei_data; - - mainboard_fill_spd_data(ps); - /* Call back into chipset code with platform values updated. */ romstage_common(rp); } @@ -31,16 +29,7 @@ void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { - /* Update SPD data */ - if (CONFIG(BOARD_GOOGLE_CYAN)) { - memory_params->PcdMemoryTypeEnable = MEM_DDR3; - memory_params->PcdMemorySpdPtr = - (u32)params->pei_data->spd_data_ch0; - } else - memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; - - memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; - memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; + mainboard_fill_spd_data(memory_params); /* Variant-specific memory params */ variant_memory_init_params(memory_params); diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index af694a4..01d8463 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -40,11 +40,24 @@ return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); } -static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) +static void *get_spd_pointer(int *dual) { + char *spd_file; + size_t spd_file_len; + int total_spds; int ram_id = 0; int spd_index = 0; + /* Find the SPD data in CBFS. */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + if (spd_file_len < SPD_PAGE_LEN) + die("Missing SPD data."); + total_spds = spd_file_len / SPD_PAGE_LEN; + ram_id = get_ramid(); printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); @@ -54,33 +67,20 @@ return NULL; } /* Return the serial product data for the RAM */ - return &spd_file_content[SPD_PAGE_LEN * spd_index]; + return &spd_file[SPD_PAGE_LEN * spd_index]; } /* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *ps) +void mainboard_fill_spd_data(MEMORY_INIT_UPD *memory_params) { - char *spd_file; - size_t spd_file_len; void *spd_content; int dual_channel = 0; - /* Find the SPD data in CBFS. */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < SPD_PAGE_LEN) - die("Missing SPD data."); - /* * Both channels are always present in SPD data. Always use matched * DIMMs so use the same SPD data for each DIMM. */ - spd_content = get_spd_pointer(spd_file, - spd_file_len / SPD_PAGE_LEN, - &dual_channel); + spd_content = get_spd_pointer(&dual_channel); if (CONFIG(DISPLAY_SPD_DATA) && spd_content != NULL) { printk(BIOS_DEBUG, "SPD Data:\n"); hexdump(spd_content, SPD_PAGE_LEN); @@ -94,18 +94,24 @@ * 2=DimmDisabled */ if (spd_content != NULL) { - ps->spd_data_ch0 = spd_content; - ps->spd_ch0_config = 1; + memory_params->PcdMemChannel0Config = 1; printk(BIOS_DEBUG, "Channel 0 DIMM soldered down\n"); if (dual_channel) { printk(BIOS_DEBUG, "Channel 1 DIMM soldered down\n"); - ps->spd_data_ch1 = spd_content; - ps->spd_ch1_config = 1; + memory_params->PcdMemChannel1Config = 1; } else { printk(BIOS_DEBUG, "Channel 1 DIMM not installed\n"); - ps->spd_ch1_config = 2; + memory_params->PcdMemChannel1Config = 2; } } + + /* Update SPD data */ + if (CONFIG(BOARD_GOOGLE_CYAN)) { + memory_params->PcdMemoryTypeEnable = MEM_DDR3; + memory_params->PcdMemorySpdPtr = spd_content; + } else { + memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; + } } static void set_dimm_info(uint8_t *spd, struct dimm_info *dimm) @@ -171,9 +177,15 @@ void mainboard_save_dimm_info(struct romstage_params *params) { + const void *spd_content; + int dual_channel; struct dimm_info *dimm; struct memory_info *mem_info; + spd_content = get_spd_pointer(&dual_channel); + if (spd_content == NULL) + return; + /* * Allocate CBMEM area for DIMM information used to populate SMBIOS * table 17 @@ -186,13 +198,13 @@ /* Describe the first channel memory */ dimm = &mem_info->dimm[0]; - set_dimm_info(params->pei_data->spd_data_ch0, dimm); + set_dimm_info(spd_content, dimm); mem_info->dimm_cnt = 1; /* Describe the second channel memory */ - if (params->pei_data->spd_ch1_config == 1) { + if (dual_channel) { dimm = &mem_info->dimm[1]; - set_dimm_info(params->pei_data->spd_data_ch1, dimm); + set_dimm_info(spd_content, dimm); dimm->channel_num = 1; mem_info->dimm_cnt = 2; } diff --git a/src/mainboard/google/cyan/spd/spd_util.h b/src/mainboard/google/cyan/spd/spd_util.h index 11d6eaa..42bd794 100644 --- a/src/mainboard/google/cyan/spd/spd_util.h +++ b/src/mainboard/google/cyan/spd/spd_util.h @@ -16,7 +16,10 @@ #ifndef SPD_UTIL_H #define SPD_UTIL_H +#include <fsp/soc_binding.h> + uint8_t get_ramid(void); int get_variant_spd_index(int ram_id, int *dual); +void mainboard_fill_spd_data(MEMORY_INIT_UPD *memory_params); #endif /* SPD_UTIL_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6103d5b9550846fe17c926631a013ff80b9598f Gerrit-Change-Number: 32593 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: soc/intel/bsw: Move memory init values into `romstage.h`
by Patrick Georgi (Code Review) 07 May '19

07 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32592 ) Change subject: soc/intel/bsw: Move memory init values into `romstage.h` ...................................................................... soc/intel/bsw: Move memory init values into `romstage.h` `chip.h` is usually used as devicetree interface. Change-Id: Ied30927d68927b86758a84ccf3f5fbd8cce632f1 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32592 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/cyan/romstage.c M src/mainboard/intel/strago/romstage.c M src/soc/intel/braswell/chip.h M src/soc/intel/braswell/include/soc/romstage.h 4 files changed, 4 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve Frans Hendriks: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c index aa20593..5470b9c 100644 --- a/src/mainboard/google/cyan/romstage.c +++ b/src/mainboard/google/cyan/romstage.c @@ -16,7 +16,6 @@ #include <soc/romstage.h> #include <baseboard/variants.h> -#include <chip.h> /* All FSP specific code goes in this block */ void mainboard_romstage_entry(struct romstage_params *rp) diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c index 0f3067e..ba0ff7b 100644 --- a/src/mainboard/intel/strago/romstage.c +++ b/src/mainboard/intel/strago/romstage.c @@ -17,7 +17,6 @@ #include <soc/gpio.h> #include <soc/pci_devs.h> #include <soc/romstage.h> -#include <chip.h> #include "onboard.h" #include <boardid.h> diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index bb06dd5..5a00328 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -32,9 +32,6 @@ #define SVID_CONFIG3 3 #define SVID_PMIC_CONFIG 8 -#define MEM_DDR3 0 -#define MEM_LPDDR3 1 - enum lpe_clk_src { LPE_CLK_SRC_XTAL, LPE_CLK_SRC_PLL, diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index 8fa9c8a..2512430 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -34,4 +34,8 @@ void program_base_addresses(void); int chipset_prev_sleep_state(struct chipset_power_state *ps); +/* Values for FSP's PcdMemoryTypeEnable */ +#define MEM_DDR3 0 +#define MEM_LPDDR3 1 + #endif /* _SOC_ROMSTAGE_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied30927d68927b86758a84ccf3f5fbd8cce632f1 Gerrit-Change-Number: 32592 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: soc/intel/bsw: Move memory init values into `romstage.h`
by Patrick Georgi (Code Review) 07 May '19

07 May '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32592 ) Change subject: soc/intel/bsw: Move memory init values into `romstage.h` ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied30927d68927b86758a84ccf3f5fbd8cce632f1 Gerrit-Change-Number: 32592 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 07 May 2019 15:57:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/intel/saddlebrook: Refactor to get rid of `pei_data`
by Patrick Georgi (Code Review) 07 May '19

07 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32591 ) Change subject: mb/intel/saddlebrook: Refactor to get rid of `pei_data` ...................................................................... mb/intel/saddlebrook: Refactor to get rid of `pei_data` The SoC specific `struct pei_data` was filled with values that were later only consumed by the mainboard code again. Avoid jumping through this hoop and fill FSP UPDs directly. Change-Id: I399dd89f85ccea43fdf90bd895e71324f4b409cc Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32591 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/intel/saddlebrook/Makefile.inc D src/mainboard/intel/saddlebrook/pei_data.c M src/mainboard/intel/saddlebrook/romstage.c M src/mainboard/intel/saddlebrook/spd/spd_util.c 4 files changed, 4 insertions(+), 46 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/intel/saddlebrook/Makefile.inc b/src/mainboard/intel/saddlebrook/Makefile.inc index 63889af..683462b 100644 --- a/src/mainboard/intel/saddlebrook/Makefile.inc +++ b/src/mainboard/intel/saddlebrook/Makefile.inc @@ -17,6 +17,5 @@ subdirs-y += spd bootblock-y += bootblock.c -romstage-y += pei_data.c ramstage-y += ramstage.c diff --git a/src/mainboard/intel/saddlebrook/pei_data.c b/src/mainboard/intel/saddlebrook/pei_data.c deleted file mode 100644 index ac4ce95..0000000 --- a/src/mainboard/intel/saddlebrook/pei_data.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include "spd/spd.h" - -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - mainboard_fill_dq_map_data(&pei_data->dq_map); - mainboard_fill_dqs_map_data(&pei_data->dqs_map); - mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); - mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); -} diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index d19629c..48d39db 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -19,8 +19,6 @@ #include <fsp/api.h> #include <string.h> #include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> #include <soc/pm.h> #include <soc/romstage.h> #include "spd/spd.h" @@ -38,8 +36,6 @@ void mainboard_romstage_entry(struct romstage_params *params) { post_code(0x31); - /* Fill out PEI DATA */ - mainboard_fill_pei_data(params->pei_data); romstage_common(params); } @@ -67,18 +63,10 @@ * should be set in the FSP flash image and should not need to be * changed. */ - memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0], - sizeof(params->pei_data->dq_map[0])); - memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1], - sizeof(params->pei_data->dq_map[1])); - memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0], - sizeof(params->pei_data->dqs_map[0])); - memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1], - sizeof(params->pei_data->dqs_map[1])); - memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor, - sizeof(params->pei_data->RcompResistor)); - memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget, - sizeof(params->pei_data->RcompTarget)); + mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); + mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); + mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); /* update spd length*/ memory_params->MemorySpdDataLen = blk.len; diff --git a/src/mainboard/intel/saddlebrook/spd/spd_util.c b/src/mainboard/intel/saddlebrook/spd/spd_util.c index 2c26d78..5055d9a 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd_util.c +++ b/src/mainboard/intel/saddlebrook/spd/spd_util.c @@ -15,8 +15,6 @@ #include <stdint.h> #include <string.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> #include "spd.h" void mainboard_fill_dq_map_data(void *dq_map_ptr) -- To view, visit https://review.coreboot.org/c/coreboot/+/32591 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I399dd89f85ccea43fdf90bd895e71324f4b409cc Gerrit-Change-Number: 32591 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit May 2019