coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

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1219 discussions

Change in ...coreboot[master]: soc/intel/braswell/acpi/lpc.asl: Allocate used ROM size only
by Frans Hendriks (Code Review) 10 Jul '19

10 Jul '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31822 Change subject: soc/intel/braswell/acpi/lpc.asl: Allocate used ROM size only ...................................................................... soc/intel/braswell/acpi/lpc.asl: Allocate used ROM size only Fixed ROM area is allocated. Reduce the ROM size using CONFIG_COREBOOT_ROMSIZE. BUG=N/A TEST=Facebook FBG-1701 booting Embedded Linux Change-Id: I7a47bf2600f546271c5a65641d29f868ff2748bf Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/acpi/lpc.asl 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/31822/1 diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index 6b2ecec..a28eb38 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2013 Google Inc. - * Copyright (C) 2018 Eltan B.V. + * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -44,7 +44,10 @@ Name (_HID, EISAID("INT0800")) Name (_CRS, ResourceTemplate() { - Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + Memory32Fixed(ReadOnly, 0xffffffff - + (CONFIG_COREBOOT_ROMSIZE_KB*1024) + 1, + CONFIG_COREBOOT_ROMSIZE_KB*1024) + }) } -- To view, visit https://review.coreboot.org/c/coreboot/+/31822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a47bf2600f546271c5a65641d29f868ff2748bf Gerrit-Change-Number: 31822 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

4 19

Change in ...coreboot[master]: qemu-q35: die if started on wrong machine
by Patrick Rudolph (Code Review) 08 Jul '19

08 Jul '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31425 Change subject: qemu-q35: die if started on wrong machine ...................................................................... qemu-q35: die if started on wrong machine The QEMU machine "PC" doesn't support MCFG. Die in bootblock if the user selected the wrong qemu machine and print a message to use the correct machine type. Without this patch ramstage dies with non-helpful message: "get_pbus: dev is NULL!" Change-Id: I9d1b24176de971c5f827091bc5bc1bac8426f3f6 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/emulation/qemu-q35/bootblock.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/31425/1 diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index 18a083d..96d3457 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -14,6 +14,7 @@ #include <arch/io.h> #include <bootblock_common.h> #include <southbridge/intel/i82801ix/i82801ix.h> +#include <console/console.h> /* Just define these here, there is no gm35.h file to include. */ #define D0F0_PCIEXBAR_LO 0x60 @@ -39,6 +40,11 @@ pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg); reg = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 256MiB - 0-255 buses. */ pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg); + + /* MCFG is now active. If it's not qemu was started for machine PC */ + if (pci_read_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO) != + (CONFIG_MMCONF_BASE_ADDRESS | 1)) + die("You must run qemu for machine Q35"); } static void enable_spi_prefetch(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/31425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d1b24176de971c5f827091bc5bc1bac8426f3f6 Gerrit-Change-Number: 31425 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 11

Change in ...coreboot[master]: mb/google/hatch: Update GPIO settings
by Krishna P Bhat D (Code Review) 08 Jul '19

08 Jul '19

Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32176 Change subject: mb/google/hatch: Update GPIO settings ...................................................................... mb/google/hatch: Update GPIO settings This patch updates the following GPIO settings. 1. Set Native termination for GPP_G0 - G4 SD card pins. 2. Disable I2C #2 in devicetree. 3. Set GPP_B19, GPP_G7 to NF1. BUG=b:123907904 Change-Id: I4549ac7377d7f58f51cda0eb96a62604fd31d2f2 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/hatch/overridetree.cb M src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb 3 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/32176/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 4d1c87e..10f851b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -106,8 +106,8 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* B19 : GPP_B19 ==> NC */ - PAD_NC(GPP_B19, NONE), + /* B19 : Set to NF1 */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* B20 : PCH_SPI_FPMCU_CLK_R */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* B21 : PCH_SPI_FPMCU_MISO */ @@ -329,21 +329,21 @@ PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ - PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G0, NATIVE, DEEP, NF1), /* G1 : SD_DATA0 */ - PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G1, NATIVE, DEEP, NF1), /* G2 : SD_DATA1 */ - PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G2, NATIVE, DEEP, NF1), /* G3 : SD_DATA2 */ - PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G3, NATIVE, DEEP, NF1), /* G4 : SD_DATA3 */ - PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G4, NATIVE, DEEP, NF1), /* G5 : SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), - /* G7 : SD_WP => NC */ - PAD_NC(GPP_G7, DN_20K), + /* G7 : Set to NF1 */ + PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), /* * H0 : HP_INT_L diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 28644d1..57daba2 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -69,7 +69,7 @@ device i2c 49 on end end end # I2C #1 - device pci 15.2 on + device pci 15.2 off chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_A8)" diff --git a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb index 9b772c2..098bca6 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb @@ -54,7 +54,7 @@ device i2c 49 on end end end # I2C #1 - device pci 15.2 on + device pci 15.2 off chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_A8)" -- To view, visit https://review.coreboot.org/c/coreboot/+/32176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4549ac7377d7f58f51cda0eb96a62604fd31d2f2 Gerrit-Change-Number: 32176 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: WIP: mediatek/mt8183: update dcxo setting
by Weiyi Lu (Code Review) 07 Jul '19

07 Jul '19

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32323 to review the following change. Change subject: WIP: mediatek/mt8183: update dcxo setting ...................................................................... WIP: mediatek/mt8183: update dcxo setting Disable unused DCXO and power mode. BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I2e5ce181ad327ccf852979da53baca4f249912fe Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> --- M src/soc/mediatek/mt8183/include/soc/rtc.h M src/soc/mediatek/mt8183/rtc.c 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/32323/1 diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 3d115fe..a721ff8 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -140,6 +140,7 @@ PMIC_RG_DCXO_CW15 = 0x07AE, PMIC_RG_DCXO_CW16 = 0x07B0, PMIC_RG_DCXO_CW21 = 0x07BA, + PMIC_RG_DCXO_CW23 = 0x07BE, PMIC_RG_DCXO_ELR0 = 0x07C4 }; diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 62256eb..57f26e8 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -281,9 +281,10 @@ rtc_write(PMIC_RG_DCXO_CW16, 0x9855); /* 26M enable control */ - /* Enable clock buffer XO_SOC, XO_CEL */ - rtc_write(PMIC_RG_DCXO_CW00, 0x4805); + /* Enable clock buffer XO_SOC */ + rtc_write(PMIC_RG_DCXO_CW00, 0x4005); rtc_write(PMIC_RG_DCXO_CW11, 0x8000); + rtc_write(PMIC_RG_DCXO_CW23, 0x0053); /* Load thermal coefficient */ rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7); -- To view, visit https://review.coreboot.org/c/coreboot/+/32323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e5ce181ad327ccf852979da53baca4f249912fe Gerrit-Change-Number: 32323 Gerrit-PatchSet: 1 Gerrit-Owner: Weiyi Lu <weiyi.lu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/mips: Make MIPS specific options depend on select ARCH_MIPS
by Arthur Heymans (Code Review) 07 Jul '19

07 Jul '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31312 Change subject: arch/mips: Make MIPS specific options depend on select ARCH_MIPS ...................................................................... arch/mips: Make MIPS specific options depend on select ARCH_MIPS Also don't define the default as this result in spurious lines in the .config. Change-Id: I7f35a5a9dcbc7b25b7806056e2b8e822fa94e428 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/mips/Kconfig M src/soc/imgtec/pistachio/Kconfig 2 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/31312/1 diff --git a/src/arch/mips/Kconfig b/src/arch/mips/Kconfig index 9e51d9c..b8570c1 100644 --- a/src/arch/mips/Kconfig +++ b/src/arch/mips/Kconfig @@ -16,12 +16,12 @@ config ARCH_MIPS bool - default n + +if ARCH_MIPS config ARCH_BOOTBLOCK_MIPS bool default n - select ARCH_MIPS select BOOTBLOCK_CUSTOM select C_ENVIRONMENT_BOOTBLOCK @@ -36,3 +36,5 @@ config ARCH_RAMSTAGE_MIPS bool default n + +endif # if ARCH_MIPS diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig index 333216d..40b63c3 100644 --- a/src/soc/imgtec/pistachio/Kconfig +++ b/src/soc/imgtec/pistachio/Kconfig @@ -15,6 +15,7 @@ # config CPU_IMGTEC_PISTACHIO + select ARCH_MIPS select ARCH_BOOTBLOCK_MIPS select ARCH_VERSTAGE_MIPS select ARCH_ROMSTAGE_MIPS -- To view, visit https://review.coreboot.org/c/coreboot/+/31312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f35a5a9dcbc7b25b7806056e2b8e822fa94e428 Gerrit-Change-Number: 31312 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mediatek/mt8183: Enable RTC eosc calibration feature to save power
by Ran Bi (Code Review) 06 Jul '19

06 Jul '19

Ran Bi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32339 Change subject: mediatek/mt8183: Enable RTC eosc calibration feature to save power ...................................................................... mediatek/mt8183: Enable RTC eosc calibration feature to save power When system shutdown, RTC enable eosc calibration feature to save power. Then coreboot RTC driver need to call rtc_enable_dcxo function at every boot up to switch RTC clock source to a more accurate one. BUG=b:128467245 BRANCH=none TEST=Boots correctly on Kukui Change-Id: Iee21e7611df8959cbbc63b6e6655cfb462147748 Signed-off-by: Ran Bi <ran.bi(a)mediatek.com> --- M src/soc/mediatek/mt8183/rtc.c 1 file changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/32339/1 diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 62256eb..ba05f86 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -197,12 +197,6 @@ goto err; } - /* using dcxo 32K clock */ - if (!rtc_enable_dcxo()) { - ret = -RTC_STATUS_OSC_SETTING_FAIL; - goto err; - } - if (recover) mdelay(20); @@ -311,6 +305,10 @@ pwrap_write_field(PMIC_RG_DCXO_CW02, 0xF, 0xF, 0); pwrap_write_field(PMIC_RG_SCK_TOP_CON0, 0x1, 0x1, 0); + /* using dcxo 32K clock */ + if (!rtc_enable_dcxo()) + rtc_info("rtc_enable_dcxo() fail\n"); + rtc_boot_common(); rtc_bbpu_power_on(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee21e7611df8959cbbc63b6e6655cfb462147748 Gerrit-Change-Number: 32339 Gerrit-PatchSet: 1 Gerrit-Owner: Ran Bi <ran.bi(a)mediatek.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/riscv: Don't select ARCH_RISCV_M on non-ARCH_RISCV platforms
by Arthur Heymans (Code Review) 02 Jul '19

02 Jul '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31311 Change subject: arch/riscv: Don't select ARCH_RISCV_M on non-ARCH_RISCV platforms ...................................................................... arch/riscv: Don't select ARCH_RISCV_M on non-ARCH_RISCV platforms Change-Id: I3e8c1cc5696d621e243696a3b5e34f62ab69a688 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/riscv/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/31311/1 diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 9d325af..f5253bb 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -24,6 +24,7 @@ # one implementation that will not have it due # to security concerns. bool + depends on ARCH_RISCV default n if ARCH_RISCV_M_DISABLED default y -- To view, visit https://review.coreboot.org/c/coreboot/+/31311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e8c1cc5696d621e243696a3b5e34f62ab69a688 Gerrit-Change-Number: 31311 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/picasso: Stub out bootblock
by Martin Roth (Code Review) 02 Jul '19

02 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32413 Change subject: soc/amd/picasso: Stub out bootblock ...................................................................... soc/amd/picasso: Stub out bootblock Because memory is already initialized when the X86 comes out of reset, we don't need the bootblock. The plan is to jump directly to Romstage. The bootblock may be used to initialize hardware blocks beeded for verstage, but in that case, it will run on the PSP, not on the X86. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I8edf45c02dc5bfcdca03abf1294db4be508682cf --- M src/soc/amd/picasso/bootblock/bootblock.c 1 file changed, 1 insertion(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/32413/1 diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 9239030..62e4e15 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -1,9 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation.. - * Copyright (C) 2017 Advanced Micro Devices - * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -14,109 +11,9 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <assert.h> -#include <console/console.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/msr.h> -#include <cpu/x86/mtrr.h> -#include <smp/node.h> #include <bootblock_common.h> -#include <amdblocks/agesawrapper.h> -#include <amdblocks/agesawrapper_call.h> -#include <soc/pci_devs.h> -#include <soc/cpu.h> -#include <soc/northbridge.h> -#include <soc/southbridge.h> -#include <amdblocks/psp.h> -#include <timestamp.h> -#include <halt.h> - -#if CONFIG_PI_AGESA_TEMP_RAM_BASE < 0x100000 -#error "Error: CONFIG_PI_AGESA_TEMP_RAM_BASE must be >= 1MB" -#endif -#if CONFIG_PI_AGESA_CAR_HEAP_BASE < 0x100000 -#error "Error: CONFIG_PI_AGESA_CAR_HEAP_BASE must be >= 1MB" -#endif - -/* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */ -static void amd_initmmio(void) -{ - msr_t mmconf; - msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); - int mtrr; - - mmconf.hi = 0; - mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN - | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; - wrmsr(MMIO_CONF_BASE, mmconf); - - /* - * todo: AGESA currently writes variable MTRRs. Once that is - * corrected, un-hardcode this MTRR. - * - * Be careful not to use get_free_var_mtrr/set_var_mtrr pairs - * where all cores execute the path. Both cores within a compute - * unit share MTRRs. Programming core0 has the appearance of - * modifying core1 too. Using the pair again will create - * duplicate copies. - */ - mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_FLASH; - set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); - - mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_CAR_HEAP; - set_var_mtrr(mtrr, CONFIG_PI_AGESA_CAR_HEAP_BASE, - CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_WRBACK); - - mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - SOC_EARLY_VMTRR_TEMPRAM; - set_var_mtrr(mtrr, CONFIG_PI_AGESA_TEMP_RAM_BASE, - CONFIG_PI_AGESA_HEAP_SIZE, MTRR_TYPE_UNCACHEABLE); -} asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { - amd_initmmio(); - /* - * Call lib/bootblock.c main with BSP, shortcut for APs - */ - if (!boot_cpu()) { - void (*ap_romstage_entry)(void) = - (void (*)(void))get_ap_entry_ptr(); - - ap_romstage_entry(); /* execution does not return */ - halt(); - } - - /* TSC cannot be relied upon. Override the TSC value passed in. */ - bootblock_main_with_timestamp(timestamp_get(), NULL, 0); -} - -void bootblock_soc_early_init(void) -{ - /* - * This call (sb_reset_i2c_slaves) was originally early at - * bootblock_c_entry, but had to be moved here. There was an - * unexplained delay in the middle of the i2c transaction when - * we had it in bootblock_c_entry. Moving it to this point - * (or adding delays) fixes the issue. It seems like the processor - * just pauses but we don't know why. - */ - sb_reset_i2c_slaves(); - bootblock_fch_early_init(); - post_code(0x90); -} - -void bootblock_soc_init(void) -{ - if (CONFIG(STONEYRIDGE_UART)) - assert(CONFIG_UART_FOR_CONSOLE >= 0 - && CONFIG_UART_FOR_CONSOLE <= 1); - - u32 val = cpuid_eax(1); - printk(BIOS_DEBUG, "Family_Model: %08x\n", val); - - bootblock_fch_init(); - - /* Initialize any early i2c buses. */ - i2c_soc_early_init(); + /* This function is here for building/linking only */ } -- To view, visit https://review.coreboot.org/c/coreboot/+/32413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8edf45c02dc5bfcdca03abf1294db4be508682cf Gerrit-Change-Number: 32413 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/picasso: Rename makefile.inc back to Makefile.inc
by Martin Roth (Code Review) 02 Jul '19

02 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32411 Change subject: soc/amd/picasso: Rename makefile.inc back to Makefile.inc ...................................................................... soc/amd/picasso: Rename makefile.inc back to Makefile.inc Now that the Makefile is updated, we can change the name back without it affecting the Stoney build. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I18ee48865fb64265f38179560265827783d50820 --- R src/soc/amd/picasso/Makefile.inc 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/32411/1 diff --git a/src/soc/amd/picasso/makefile.inc b/src/soc/amd/picasso/Makefile.inc similarity index 100% rename from src/soc/amd/picasso/makefile.inc rename to src/soc/amd/picasso/Makefile.inc -- To view, visit https://review.coreboot.org/c/coreboot/+/32411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18ee48865fb64265f38179560265827783d50820 Gerrit-Change-Number: 32411 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/picasso: Change SOC_AMD_STONEY* to SOC_AMD_PICASSO
by Martin Roth (Code Review) 02 Jul '19

02 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32410 Change subject: soc/amd/picasso: Change SOC_AMD_STONEY* to SOC_AMD_PICASSO ...................................................................... soc/amd/picasso: Change SOC_AMD_STONEY* to SOC_AMD_PICASSO TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Ie466bc39ed6aa9d2a8651bd9290090b83cd97d74 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/makefile.inc 2 files changed, 6 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/32410/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 29ab149..feaabac 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -13,17 +13,12 @@ ## GNU General Public License for more details. ## -config SOC_AMD_STONEYRIDGE_FP4 +config SOC_AMD_PICASSO bool help - AMD Stoney Ridge FP4 support + AMD Picasso support -config SOC_AMD_STONEYRIDGE_FT4 - bool - help - AMD Stoney Ridge FT4 support - -if SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 +if SOC_AMD_PICASSO config CPU_SPECIFIC_OPTIONS def_bool y @@ -379,4 +374,4 @@ return to S0. Otherwise the system will remain in S5 once power is restored. -endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 +endif # SOC_AMD_PICASSO diff --git a/src/soc/amd/picasso/makefile.inc b/src/soc/amd/picasso/makefile.inc index cc8be37..470960b 100644 --- a/src/soc/amd/picasso/makefile.inc +++ b/src/soc/amd/picasso/makefile.inc @@ -27,7 +27,7 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # #***************************************************************************** -ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +ifeq ($(CONFIG_SOC_AMD_PICASSO),y) subdirs-y += ../../../cpu/amd/mtrr/ subdirs-y += ../../../cpu/x86/tsc @@ -314,4 +314,4 @@ endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) -endif # ($(CONFIG_SOC_AMD_STONEYRIDGE_FP4)$(CONFIG_SOC_AMD_STONEYRIDGE_FT4),y) +endif # ($(CONFIG_SOC_AMD_PICASSO),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/32410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie466bc39ed6aa9d2a8651bd9290090b83cd97d74 Gerrit-Change-Number: 32410 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2019