coreboot-gerrit April 2019

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Change in ...libgfxinit[master]: gma: Add support for ULX variants
by Nico Huber (Code Review) 20 Jul '19

20 Jul '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/31452 Change subject: gma: Add support for ULX variants ...................................................................... gma: Add support for ULX variants On Haswell and Broadwell, the ULX variants differ only in the available CD clock frequencies and, on Haswell, the maximum DP link rate. On newer generations (Skylake+), they differ only in output buffer tuning. Also update the PCI IDs from Haswell to Skylake. Still untested, which was the original reason to skip ULX. Change-Id: I08e6689ff8c0f2d58b51363886d4cab956f44e03 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/haswell/hw-gfx-gma-plls.adb M common/haswell_shared/hw-gfx-gma-connectors-ddi.adb M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma.ads M common/skylake/hw-gfx-gma-connectors-ddi-buffers.adb 5 files changed, 136 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/52/31452/1 diff --git a/common/haswell/hw-gfx-gma-plls.adb b/common/haswell/hw-gfx-gma-plls.adb index 3a91bdd..0450238 100644 --- a/common/haswell/hw-gfx-gma-plls.adb +++ b/common/haswell/hw-gfx-gma-plls.adb @@ -1,5 +1,5 @@ -- --- Copyright (C) 2015-2016 secunet Security Networks AG +-- Copyright (C) 2015-2016, 2019 secunet Security Networks AG -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -12,6 +12,7 @@ -- GNU General Public License for more details. -- +with HW.GFX.GMA.Config; with HW.GFX.GMA.PLLs.LCPLL; with HW.GFX.GMA.PLLs.WRPLL; @@ -87,8 +88,13 @@ PLL := Invalid; Success := True; elsif Port_Cfg.Display = DP then - PLL := LCPLL.Fixed_LCPLLs (Port_Cfg.DP.Bandwidth); - Success := True; + if Port_Cfg.DP.Bandwidth <= Config.DP_Max_Link_Rate then + PLL := LCPLL.Fixed_LCPLLs (Port_Cfg.DP.Bandwidth); + Success := True; + else + PLL := Invalid; + Success := False; + end if; else Alloc_Configurable (Port_Cfg.Mode, PLL, Success); end if; diff --git a/common/haswell_shared/hw-gfx-gma-connectors-ddi.adb b/common/haswell_shared/hw-gfx-gma-connectors-ddi.adb index 88f2b22..ef6d568 100644 --- a/common/haswell_shared/hw-gfx-gma-connectors-ddi.adb +++ b/common/haswell_shared/hw-gfx-gma-connectors-ddi.adb @@ -298,7 +298,7 @@ procedure Initialize is - Iboost_Value : constant Word32 := 1; + Iboost_Value : constant := Config.DDI_Buffer_Iboost; begin if Config.Has_DDI_Buffer_Trans then declare diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index a922b05..b190a78 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -1,5 +1,5 @@ -- --- Copyright (C) 2015-2018 secunet Security Networks AG +-- Copyright (C) 2015-2019 secunet Security Networks AG -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -42,6 +42,8 @@ Have_DVI_I : constant Boolean := Analog_I2C_Port /= PCH_DAC; Has_Presence_Straps : constant Boolean := CPU /= Broxton; Is_ULT : constant Boolean := CPU_Var = ULT; + Is_ULX : constant Boolean := CPU_Var = ULX; + Is_LP : constant Boolean := Is_ULT or Is_ULX; ----- CPU pipe: -------- Has_Tertiary_Pipe : constant Boolean := CPU >= Ivybridge; @@ -74,7 +76,7 @@ Has_PCH : constant Boolean := CPU /= Broxton and CPU /= G45; Has_PCH_DAC : constant Boolean := CPU in Ironlake .. Ivybridge or (CPU in Haswell .. Broadwell - and not Is_ULT); + and not Is_LP); Has_PCH_Aux_Channels : constant Boolean := CPU in Ironlake .. Broadwell; @@ -98,13 +100,13 @@ Has_Per_DDI_Clock_Sel : constant Boolean := CPU in Haswell .. Broadwell; Has_HOTPLUG_CTL : constant Boolean := CPU in Haswell .. Broadwell; Has_SHOTPLUG_CTL_A : constant Boolean := (CPU in Haswell .. Broadwell - and Is_ULT) or + and Is_LP) or CPU >= Skylake; Has_DDI_PHYs : constant Boolean := CPU = Broxton; Has_DDI_D : constant Boolean := CPU >= Haswell and - not Is_ULT and + not Is_LP and not Has_DDI_PHYs; Has_DDI_E : constant Boolean := -- might be disabled by x4 eDP Has_DDI_D; @@ -122,7 +124,7 @@ Has_PCH_GMBUS : constant Boolean := CPU >= Ironlake; ----- Power: ----------- - Has_IPS : constant Boolean := (CPU = Haswell and Is_ULT) or + Has_IPS : constant Boolean := (CPU = Haswell and Is_LP) or CPU = Broadwell; Has_IPS_CTL_Mailbox : constant Boolean := CPU = Broadwell; @@ -220,6 +222,8 @@ ---------------------------------------------------------------------------- + DDI_Buffer_Iboost : constant := (if Is_ULX then 3 else 1); + Default_DDI_HDMI_Buffer_Translation : constant DDI_HDMI_Buf_Trans_Range := (case CPU is when Haswell => 6, @@ -233,11 +237,11 @@ Default_CDClk_Freq : constant Frequency_Type := (case CPU is when G45 => 320_000_000, -- unused - when Ironlake | - Haswell | - Broadwell => 450_000_000, + when Ironlake => 450_000_000, when Sandybridge | Ivybridge => 400_000_000, + when Haswell | + Broadwell => (if Is_ULX then 337_500_000 else 450_000_000), when Broxton => 288_000_000, when Skylake => 337_500_000); @@ -248,7 +252,7 @@ Sandybridge | Ivybridge => 125_000_000, when Haswell | - Broadwell => (if Is_ULT then 24_000_000 else 125_000_000), + Broadwell => (if Is_LP then 24_000_000 else 125_000_000), when Broxton => Frequency_Type'First, -- none needed when Skylake => 24_000_000); @@ -286,6 +290,11 @@ ---------------------------------------------------------------------------- + DP_Max_Link_Rate : constant DP_Bandwidth := + (if CPU < Haswell or (CPU = Haswell and Is_ULX) + then DP_Bandwidth_2_7 + else DP_Bandwidth_5_4); + -- FIXME: Unknown for Broxton, Linux' i915 contains a fixme too :-D HDMI_Max_Clock_24bpp : constant Frequency_Type := (if CPU >= Haswell then 300_000_000 else 225_000_000); @@ -318,15 +327,50 @@ use type HW.Word16; - function Is_Broadwell_H (Device_Id : Word16) return Boolean is - (Device_Id = 16#1612# or Device_Id = 16#1622# or Device_Id = 16#162a#); + -- GMA PCI IDs: + -- + -- Rather catch too much here than too little, it's + -- mostly used to distinguish generations. Best public + -- reference for these IDs is Linux' i915. + -- + -- Since Sandybridge, bits 4 and 5 encode the compu- + -- tational capabilities and can mostly be ignored. + -- From Haswell on, we have to distinguish between + -- Normal, ULT (U CPU lines) and ULX (Y CPU lines). + function Is_Haswell_Y (Device_Id : Word16) return Boolean is + ((Device_Id and 16#ffef#) = 16#0a0e#); + function Is_Haswell_U (Device_Id : Word16) return Boolean is + (((Device_Id and 16#ffc3#) = 16#0a02# or + (Device_Id and 16#ffcf#) = 16#0a0b#) and + not Is_Haswell_Y (Device_Id)); + function Is_Haswell (Device_Id : Word16) return Boolean is + ((Device_Id and 16#ffc3#) = 16#0402# or + (Device_Id and 16#ffcf#) = 16#040b# or + (Device_Id and 16#ffc3#) = 16#0c02# or + (Device_Id and 16#ffcf#) = 16#0c0b# or + (Device_Id and 16#ffc3#) = 16#0d02# or + (Device_Id and 16#ffcf#) = 16#0d0b#); + + function Is_Broadwell_Y (Device_Id : Word16) return Boolean is + ((Device_Id and 16#ffcf#) = 16#160e#); + function Is_Broadwell_U (Device_Id : Word16) return Boolean is + ((Device_Id and 16#ffcf#) = 16#1606# or + (Device_Id and 16#ffcf#) = 16#160b#); + function Is_Broadwell (Device_Id : Word16) return Boolean is + ((Device_Id and 16#ffc7#) = 16#1602# or + (Device_Id and 16#ffcf#) = 16#160d#); + + function Is_Skylake_Y (Device_Id : Word16) return Boolean is + ((Device_Id and 16#ffcf#) = 16#190e#); function Is_Skylake_U (Device_Id : Word16) return Boolean is - (Device_Id = 16#1906# or Device_Id = 16#1916# or Device_Id = 16#1923# or - Device_Id = 16#1926# or Device_Id = 16#1927#); + ((Device_Id and 16#ffc9#) = 16#1901# or + (Device_Id and 16#ffcf#) = 16#1906#); + function Is_Skylake (Device_Id : Word16) return Boolean is + ((Device_Id and 16#ffc7#) = 16#1902# or + (Device_Id and 16#ffcf#) = 16#190b# or + (Device_Id and 16#ffcf#) = 16#190d#); - -- Rather catch too much here than too little, - -- it's only used to distinguish generations. function Is_GPU (Device_Id : Word16; CPU : CPU_Type; CPU_Var : CPU_Variant) return Boolean is (case CPU is @@ -335,25 +379,19 @@ when Ironlake => (Device_Id and 16#fff3#) = 16#0042#, when Sandybridge => (Device_Id and 16#ffc2#) = 16#0102#, when Ivybridge => (Device_Id and 16#ffc3#) = 16#0142#, - when Haswell => - (case CPU_Var is - when Normal => (Device_Id and 16#ffc3#) = 16#0402# or - (Device_Id and 16#ffc3#) = 16#0d02#, - when ULT => (Device_Id and 16#ffc3#) = 16#0a02#), - when Broadwell => ((Device_Id and 16#ffc3#) = 16#1602# or - (Device_Id and 16#ffcf#) = 16#160b# or - (Device_Id and 16#ffcf#) = 16#160d#) and - (case CPU_Var is - when Normal => Is_Broadwell_H (Device_Id), - when ULT => not Is_Broadwell_H (Device_Id)), + when Haswell => (case CPU_Var is + when Normal => Is_Haswell (Device_Id), + when ULT => Is_Haswell_U (Device_Id), + when ULX => Is_Haswell_Y (Device_Id)), + when Broadwell => (case CPU_Var is + when Normal => Is_Broadwell (Device_Id), + when ULT => Is_Broadwell_U (Device_Id), + when ULX => Is_Broadwell_Y (Device_Id)), when Broxton => (Device_Id and 16#fffe#) = 16#5a84#, - when Skylake => ((Device_Id and 16#ffc3#) = 16#1902# or - (Device_Id and 16#ffcf#) = 16#190b# or - (Device_Id and 16#ffcf#) = 16#190d# or - (Device_Id and 16#fff9#) = 16#1921#) and - (case CPU_Var is - when Normal => not Is_Skylake_U (Device_Id), - when ULT => Is_Skylake_U (Device_Id))); + when Skylake => (case CPU_Var is + when Normal => Is_Skylake (Device_Id), + when ULT => Is_Skylake_U (Device_Id), + when ULX => Is_Skylake_Y (Device_Id))); function Compatible_GPU (Device_Id : Word16) return Boolean is (Is_GPU (Device_Id, CPU, CPU_Var)); diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 1f81ece..d9023ad 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -44,7 +44,7 @@ Broxton, Skylake); - type CPU_Variant is (Normal, ULT); + type CPU_Variant is (Normal, ULT, ULX); type Port_Type is (Disabled, diff --git a/common/skylake/hw-gfx-gma-connectors-ddi-buffers.adb b/common/skylake/hw-gfx-gma-connectors-ddi-buffers.adb index 5e72a3b..6ab755b 100644 --- a/common/skylake/hw-gfx-gma-connectors-ddi-buffers.adb +++ b/common/skylake/hw-gfx-gma-connectors-ddi-buffers.adb @@ -1,5 +1,5 @@ -- --- Copyright (C) 2017 secunet Security Networks AG +-- Copyright (C) 2017, 2019 secunet Security Networks AG -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -51,6 +51,18 @@ 16#0000_5013#, 16#0000_009f#, 16#0000_0018#, 16#0000_00df#); + Skylake_Y_Trans_EDP : constant Buf_Trans_Array := + (16#0000_0018#, 16#0000_00a8#, + 16#0000_4013#, 16#0000_00ab#, + 16#0000_7011#, 16#0000_00a4#, + 16#0000_9010#, 16#0000_00df#, + 16#0000_0018#, 16#0000_00aa#, + 16#0000_6013#, 16#0000_00a4#, + 16#0000_7011#, 16#0000_009d#, + 16#0000_0018#, 16#0000_00a0#, + 16#0000_6012#, 16#0000_00df#, + 16#0000_0018#, 16#0000_008a#); + Skylake_Trans_DP : constant Buf_Trans_Array := (16#0000_2016#, 16#0000_00a0#, 16#0000_5012#, 16#0000_009b#, @@ -75,6 +87,18 @@ 16#8000_5012#, 16#0000_00c0#, others => 0); + Skylake_Y_Trans_DP : constant Buf_Trans_Array := + (16#0000_0018#, 16#0000_00a2#, + 16#0000_5012#, 16#0000_0088#, + 16#8000_7011#, 16#0000_00cd#, + 16#8000_9010#, 16#0000_00c0#, + 16#0000_0018#, 16#0000_009d#, + 16#8000_5012#, 16#0000_00c0#, + 16#8000_7011#, 16#0000_00c0#, + 16#0000_0018#, 16#0000_0088#, + 16#8000_5012#, 16#0000_00c0#, + others => 0); + Skylake_Trans_HDMI : constant HDMI_Buf_Trans_Array := ((16#0000_0018#, 16#0000_00ac#), (16#0000_5012#, 16#0000_009d#), @@ -88,6 +112,19 @@ (16#8000_3015#, 16#0000_00c0#), (16#8000_0018#, 16#0000_00c0#)); + Skylake_Y_Trans_HDMI : constant HDMI_Buf_Trans_Array := + ((16#0000_0018#, 16#0000_00a1#), + (16#0000_5012#, 16#0000_00df#), + (16#8000_7011#, 16#0000_00cb#), + (16#0000_0018#, 16#0000_00a4#), + (16#0000_0018#, 16#0000_009d#), + (16#0000_4013#, 16#0000_0080#), + (16#8000_6013#, 16#0000_00c0#), + (16#0000_0018#, 16#0000_008a#), + (16#8000_3015#, 16#0000_00c0#), + (16#8000_3015#, 16#0000_00c0#), + (16#8000_0018#, 16#0000_00c0#)); + ---------------------------------------------------------------------------- procedure Translations (Trans : out Buf_Trans_Array; Port : Digital_Port) @@ -101,17 +138,26 @@ else Config.Default_DDI_HDMI_Buffer_Translation); begin Trans := - (if not Config.Is_ULT then + (if Config.Is_ULX then (if DDIA_Low_Voltage_Swing - then Skylake_Trans_EDP - else Skylake_Trans_DP) - else + then Skylake_Y_Trans_EDP + else Skylake_Y_Trans_DP) + elsif Config.Is_ULT then (if DDIA_Low_Voltage_Swing then Skylake_U_Trans_EDP - else Skylake_U_Trans_DP)); + else Skylake_U_Trans_DP) + else + (if DDIA_Low_Voltage_Swing + then Skylake_Trans_EDP + else Skylake_Trans_DP)); if not DDIA_Low_Voltage_Swing then - Trans (18) := Skylake_Trans_HDMI (HDMI_Trans).Trans1; - Trans (19) := Skylake_Trans_HDMI (HDMI_Trans).Trans2; + if Config.Is_ULX then + Trans (18) := Skylake_Y_Trans_HDMI (HDMI_Trans).Trans1; + Trans (19) := Skylake_Y_Trans_HDMI (HDMI_Trans).Trans2; + else + Trans (18) := Skylake_Trans_HDMI (HDMI_Trans).Trans1; + Trans (19) := Skylake_Trans_HDMI (HDMI_Trans).Trans2; + end if; end if; end Translations; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/31452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I08e6689ff8c0f2d58b51363886d4cab956f44e03 Gerrit-Change-Number: 31452 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 6

Change in ...coreboot[master]: security/tpm/tss/tcg-2.0: Add function to return TMP2 capabilities.
by Frans Hendriks (Code Review) 19 Jul '19

19 Jul '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30826 Change subject: security/tpm/tss/tcg-2.0: Add function to return TMP2 capabilities. ...................................................................... security/tpm/tss/tcg-2.0: Add function to return TMP2 capabilities. Add function tlcl_getcapability() to return capability, used by measured boot. In function unmarshal_get_capability handling of TPM_CAP_PCRS has been added for TPM2 get capability commands. BUG=N/A TEST=Build binary and verified logging on Facebook FBG-1701 Change-Id: I85e1bd2822aa6e7fd95ff2b9faa25cf183e6de37 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/security/tpm/tss.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_structures.h 4 files changed, 302 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/30826/1 diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index c4f2608..610a99c 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -1,4 +1,5 @@ /* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2018 Eltan B.V. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -122,6 +123,35 @@ uint32_t tlcl_continue_self_test(void); /** + * Issue tpm get capability command + */ +uint32_t tlcl_getcapability(TPM_CAP capability, uint32_t property, + uint32_t propertyCount, TPMI_YES_NO *moreData, + TPMS_CAPABILITY_DATA *capabilityData); + +/** + * Issue more flexible process command + */ +void *tpm_process_command_ex(TPM_CC command, void *command_body, + size_t command_size, size_t *response_size, + bool marshal); + +/* + * tlcl_extend command that allows more digests to be passed in at the same + * time + */ +uint32_t tlcl_extend_ex(int pcr_num, const TPML_DIGEST_VALUES *in_digests); + +/** + * Return size of digest. + * + * @param[in] HashAlgo Hash algorithm + * + * @return size of digest + */ +uint16_t tlcl_get_hash_size_from_algo(TPMI_ALG_HASH hashAlgo); + +/** * Write [length] bytes of [data] to space at [index]. The TPM error code is * returned. */ @@ -144,7 +174,7 @@ uint32_t tlcl_physical_presence_cmd_enable(void); /** - * Finalize the physical presence settings: sofware PP is enabled, hardware PP + * Finalize the physical presence settings: software PP is enabled, hardware PP * is disabled, and the lifetime lock is set. The TPM error code is returned. */ uint32_t tlcl_finalize_physical_presence(void); diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index e579bff..87f38e1 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -1,5 +1,6 @@ /* * Copyright 2016 The Chromium OS Authors. All rights reserved. + * Copyright 2017-2018 Eltan B.V. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -15,6 +16,12 @@ #include "tss_structures.h" #include "tss_marshaling.h" +static INTERNAL_HASH_INFO mHashInfo[] = { + {TPM_ALG_ERROR, 1}, + {TPM_ALG_SHA1, SHA1_DIGEST_SIZE}, + {TPM_ALG_SHA256, SHA256_DIGEST_SIZE}, +}; + /* * This file provides interface between firmware and TPM2 device. The TPM1.2 * API was copied as is and relevant functions modified to comply with the @@ -53,6 +60,48 @@ return tpm_unmarshal_response(command, &ib); } +void *tpm_process_command_ex(TPM_CC command, void *command_body, + size_t command_size, size_t *response_size, bool marshal) +{ + struct obuf ob; + struct ibuf ib; + size_t out_size; + size_t in_size; + const uint8_t *sendb; + /* Command/response buffer. */ + static uint8_t cr_buffer[TPM_BUFFER_SIZE] CAR_GLOBAL; + + uint8_t *cr_buffer_ptr = car_get_var_ptr(cr_buffer); + + if (marshal) { + obuf_init(&ob, cr_buffer_ptr, sizeof(cr_buffer)); + if (tpm_marshal_command(command, command_body, &ob) < 0) { + printk(BIOS_ERR, "command %#x\n", command); + return NULL; + } + sendb = obuf_contents(&ob, &out_size); + } else { + sendb = command_body; + out_size = command_size; + } + + in_size = sizeof(cr_buffer); + if (tis_sendrecv(sendb, out_size, cr_buffer_ptr, &in_size)) { + printk(BIOS_ERR, "tpm transaction failed\n"); + return NULL; + } + + ibuf_init(&ib, cr_buffer_ptr, in_size); + + if (response_size) + *response_size = in_size; + + if (marshal) + return tpm_unmarshal_response(command, &ib); + else + return cr_buffer_ptr; +} + static uint32_t tlcl_send_startup(TPM_SU type) { struct tpm2_startup startup; @@ -139,7 +188,7 @@ pcr_ext_cmd.digests.count = 1; pcr_ext_cmd.digests.digests[0].hashAlg = TPM_ALG_SHA256; memcpy(pcr_ext_cmd.digests.digests[0].digest.sha256, in_digest, - sizeof(pcr_ext_cmd.digests.digests[0].digest.sha256)); + sizeof(TPMU_HA)); response = tpm_process_command(TPM2_PCR_Extend, &pcr_ext_cmd); @@ -151,6 +200,65 @@ return TPM_SUCCESS; } +/* + * Handle multiple digests (SHA1 and SHA256 at the moment) + */ +uint32_t tlcl_extend_ex(int pcr_num, const TPML_DIGEST_VALUES *in_digests) +{ + struct tpm2_pcr_extend_cmd pcr_ext_cmd; + struct tpm2_response *response; + int i; + + pcr_ext_cmd.pcrHandle = HR_PCR + pcr_num; + pcr_ext_cmd.digests.count = in_digests->count; + + printk(BIOS_SPEW, "%s: pcr = %d\n", __func__, pcr_num); + printk(BIOS_SPEW, "%s: in_digests->count = %d\n", __func__, + in_digests->count); + + for (i = 0; i < in_digests->count ; i++) { + pcr_ext_cmd.digests.digests[i].hashAlg = + in_digests->digests[i].hashAlg; + memcpy((void *) pcr_ext_cmd.digests.digests[i].digest.sha256, + (void *) in_digests->digests[i].digest.sha256, + sizeof(TPMU_HA)); + + printk(BIOS_SPEW, "%s: in_digests[%d]->hash_alg = 0x%x\n", + __func__, i, in_digests->digests[i].hashAlg); + } + + response = tpm_process_command(TPM2_PCR_Extend, &pcr_ext_cmd); + + /* + * Check if we are invalidating the pcrs, ignore the error if this is + * the case + */ + if (in_digests->count == 1) { + if (in_digests->digests[0].hashAlg == TPM_ALG_ERROR) { + if (in_digests->digests[0].digest.invalidate_pcrs == + 1) { + if (response) { + if ((response->hdr.tpm_code & + ~TPM_RC_N_MASK) == (TPM_RC_P | + TPM_RC_HASH)){ + printk(BIOS_SPEW, "%s:" + " TPM_RC_HASH returned this is" + " expected\n", __func__); + return TPM_SUCCESS; + } + } + } + } + } + + printk(BIOS_INFO, "%s: response is 0x%x\n", + __func__, response ? response->hdr.tpm_code : -1); + if (!response || response->hdr.tpm_code) + return TPM_E_IOERROR; + + return TPM_SUCCESS; +} + uint32_t tlcl_finalize_physical_presence(void) { /* Nothing needs to be done with tpm2. */ @@ -178,13 +286,22 @@ uint32_t tlcl_lib_init(void) { uint8_t done = car_get_var(tlcl_init_done); + + printk(BIOS_SPEW, "%s: tlcl_init_done is %d\n", __func__, done); if (done) return VB2_SUCCESS; - if (tis_init()) + printk(BIOS_SPEW, "%s: calling tis_init\n", __func__); + if (tis_init()) { + printk(BIOS_ERR, "%s: tis_init returned error\n", __func__); return VB2_ERROR_UNKNOWN; - if (tis_open()) + } + + printk(BIOS_SPEW, "%s: calling tis_open\n", __func__); + if (tis_open()) { + printk(BIOS_ERR, "%s: tis_open returned error\n", __func__); return VB2_ERROR_UNKNOWN; + } car_set_var(tlcl_init_done, 1); @@ -361,3 +478,61 @@ return TPM_SUCCESS; } + +/* + * Issue the tpm2 get capability command + * + * Please note that the capabilityData is not unmarshalled. + */ +uint32_t tlcl_getcapability(TPM_CAP capability, uint32_t property, + uint32_t propertyCount, TPMI_YES_NO *moreData, + TPMS_CAPABILITY_DATA *capabilityData) +{ + struct tpm2_get_capability cmd; + struct tpm2_response *response; + size_t response_size; + + cmd.capability = capability; + cmd.property = property; + cmd.propertyCount = propertyCount; + + if (propertyCount > 1) { + printk(BIOS_ERR, "%s: PropertyCount more than one not supported" + " yet\n", __func__); + } + + response = tpm_process_command_ex(TPM2_GetCapability, &cmd, 0, + &response_size, 1); + + if (!response) { + printk(BIOS_ERR, "%s: Command Failed\n", __func__); + return TPM_E_IOERROR; + } + + if (moreData) + *moreData = response->gc.more_data; + memcpy(capabilityData, &response->gc.cd, response_size - + sizeof(TPMI_YES_NO) - sizeof(struct tpm_header)); + return TPM_SUCCESS; +} + +/** + Return size of digest. + + @param[in] HashAlgo Hash algorithm + + @return size of digest +**/ + +uint16_t tlcl_get_hash_size_from_algo(TPMI_ALG_HASH hashAlgo) +{ + uint16_t index; + + for (index = 0; index < ARRAY_SIZE(mHashInfo); index++) + if (mHashInfo[index].hashAlgo == hashAlgo) + return mHashInfo[index].hashSize; + + printk(BIOS_SPEW, "%s: unknown hash algorithm %d\n", __func__, + hashAlgo); + return 0; +} diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 49ac5e8..b4518d20 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -1,5 +1,6 @@ /* * Copyright 2016 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2018 Eltan B.V. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -12,6 +13,7 @@ #include "tss_marshaling.h" #include <security/tpm/tss/vendor/cr50/cr50.h> +#include <security/tpm/tss.h> static uint16_t tpm_tag CAR_GLOBAL; /* Depends on the command type. */ @@ -82,7 +84,7 @@ rc |= marshal_TPMI_ALG_HASH(ob, tpmtha->hashAlg); rc |= obuf_write(ob, tpmtha->digest.sha256, - sizeof(tpmtha->digest.sha256)); + tlcl_get_hash_size_from_algo(tpmtha->hashAlg)); return rc; } @@ -398,6 +400,22 @@ rc |= ibuf_read_be32(ib, &pp->value); } break; + case TPM_CAP_PCRS: + if (ibuf_read_be32(ib, &gcr->cd.data.assignedPCR.count)) + return -1; + if (gcr->cd.data.assignedPCR.count > ARRAY_SIZE + (gcr->cd.data.assignedPCR.pcrSelections)) { + printk(BIOS_INFO, "%s:%s:%d - %d - too many properties\n", + __FILE__, __func__, __LINE__, + gcr->cd.data.assignedPCR.count); + return -1; + } + for (i = 0; i < gcr->cd.data.assignedPCR.count; i++) { + TPMS_PCR_SELECTION *pp = + gcr->cd.data.assignedPCR.pcrSelections + i; + rc |= ibuf_read(ib, pp, sizeof(TPMS_PCR_SELECTION)); + } + break; default: printk(BIOS_ERR, "%s:%d - unable to unmarshal capability response", @@ -448,12 +466,12 @@ } /* - * Let's ignore the authorisation section. It should be 5 bytes total, + * Let's ignore the authorization section. It should be 5 bytes total, * just confirm that this is the case and report any discrepancy. */ if (ibuf_remaining(ib) != 5) printk(BIOS_ERR, - "%s:%d - unexpected authorisation seciton size %zd\n", + "%s:%d - unexpected authorization section size %zd\n", __func__, __LINE__, ibuf_remaining(ib)); ibuf_oob_drain(ib, ibuf_remaining(ib)); diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 2bac633..e70ae02 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -1,5 +1,6 @@ /* * Copyright 2016 The Chromium OS Authors. All rights reserved. + * Copyright 2017-2018 Eltan B.V. * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -22,6 +23,12 @@ #define TPM2_RC_SUCCESS 0 #define TPM2_RC_NV_DEFINED 0x14c +// +// We set this to two here as we only support SHA1 and SHA256 right now. +// Should be updated when additional algorithms are supported +// +#define HASH_COUNT 2 + /* Basic TPM2 types. */ typedef uint16_t TPM_SU; typedef uint16_t TPM_ALG_ID; @@ -36,12 +43,28 @@ typedef TPM_HANDLE TPM_RH; /* Some hardcoded algorithm values. */ -#define TPM_ALG_HMAC ((TPM_ALG_ID)0x0005) -#define TPM_ALG_NULL ((TPM_ALG_ID)0x0010) -#define TPM_ALG_SHA1 ((TPM_ALG_ID)0x0004) -#define TPM_ALG_SHA256 ((TPM_ALG_ID)0x000b) +// Table 7 - TPM_ALG_ID Constants +#define TPM_ALG_ERROR ((TPM_ALG_ID)0x0000) +#define TPM_ALG_HMAC ((TPM_ALG_ID)0x0005) +#define TPM_ALG_NULL ((TPM_ALG_ID)0x0010) +#define TPM_ALG_SHA1 ((TPM_ALG_ID)0x0004) +#define TPM_ALG_SHA256 ((TPM_ALG_ID)0x000b) +#define TPM_ALG_SHA384 ((TPM_ALG_ID)0x000C) +#define TPM_ALG_SHA512 ((TPM_ALG_ID)0x000D) +#define TPM_ALG_SM3_256 ((TPM_ALG_ID)0x0012) +// Annex A Algorithm Constants + +// Table 205 - Defines for SHA1 Hash Values +#define SHA1_DIGEST_SIZE 20 +// Table 206 - Defines for SHA256 Hash Values #define SHA256_DIGEST_SIZE 32 +// Table 207 - Defines for SHA384 Hash Values +//#define SHA384_DIGEST_SIZE 48 +// Table 208 - Defines for SHA512 Hash Values +#define SHA512_DIGEST_SIZE 64 +// Table 209 - Defines for SM3_256 Hash Values +//#define SM3_256_DIGEST_SIZE 32 /* Some hardcoded hierarchies. */ #define TPM_RH_NULL 0x40000007 @@ -79,6 +102,12 @@ space is defined by the lower 16 bits. */ #define TPM_CC_VENDOR_BIT_MASK 0x20000000 +// Table 15 - TPM_RC Constants (Actions) +#define RC_FMT1 (TPM_RC)(0x080) +#define TPM_RC_HASH (TPM_RC)(RC_FMT1 + 0x003) +#define TPM_RC_P (TPM_RC)(0x040) +#define TPM_RC_N_MASK (TPM_RC)(0xF00) + /* Startup values. */ #define TPM_SU_CLEAR 0 #define TPM_SU_STATE 1 @@ -144,7 +173,9 @@ }; /* Various TPM capability types to use when querying the device. */ +// Table 21 - TPM_CAP Constants typedef uint32_t TPM_CAP; +#define TPM_CAP_PCRS ((TPM_CAP)0x00000005) #define TPM_CAP_TPM_PROPERTIES ((TPM_CAP)0x00000006) typedef TPM_HANDLE TPMI_RH_NV_AUTH; @@ -224,16 +255,37 @@ sizeof(TPMI_YES_NO) - sizeof(TPM_CAP) - sizeof(uint32_t)) #define MAX_TPM_PROPERTIES (MAX_CAP_DATA/sizeof(TPMS_TAGGED_PROPERTY)) +#define IMPLEMENTATION_PCR 24 +#define PLATFORM_PCR 24 + +#define PCR_SELECT_MIN ((PLATFORM_PCR + 7) / 8) +#define PCR_SELECT_MAX ((IMPLEMENTATION_PCR + 7) / 8) + /* Somewhat arbitrary, leave enough room for command wrappers. */ #define MAX_NV_BUFFER_SIZE (TPM_BUFFER_SIZE - sizeof(struct tpm_header) - 50) +// Table 81 - TPMS_PCR_SELECTION Structure typedef struct { - uint32_t count; - TPMS_TAGGED_PROPERTY tpmProperty[MAX_TPM_PROPERTIES]; + TPMI_ALG_HASH hash; + uint8_t sizeofSelect; + uint8_t pcrSelect[PCR_SELECT_MAX]; +} __packed TPMS_PCR_SELECTION; + +// Table 98 - TPML_PCR_SELECTION Structure +typedef struct { + uint32_t count; + TPMS_PCR_SELECTION pcrSelections[HASH_COUNT]; +} __packed TPML_PCR_SELECTION; + +// Table 100 - TPML_TAGGED_TPM_PROPERTY Structure +typedef struct { + uint32_t count; + TPMS_TAGGED_PROPERTY tpmProperty[MAX_TPM_PROPERTIES]; } TPML_TAGGED_TPM_PROPERTY; typedef union { - TPML_TAGGED_TPM_PROPERTY tpmProperties; + TPML_TAGGED_TPM_PROPERTY tpmProperties; + TPML_PCR_SELECTION assignedPCR; } TPMU_CAPABILITIES; typedef struct { @@ -271,22 +323,30 @@ } TPM2B_MAX_NV_BUFFER; /* - * This is a union, but as of now we support just one digest - sha256, so - * there is just one element. + * This is a union, but as of now we support just sha1 and sha256 */ +// Table 66 - TPMU_HA Union typedef union { - uint8_t sha256[SHA256_DIGEST_SIZE]; + uint8_t invalidate_pcrs; + uint8_t sha1[SHA1_DIGEST_SIZE]; + uint8_t sha256[SHA256_DIGEST_SIZE]; } TPMU_HA; typedef struct { + TPMI_ALG_HASH hashAlgo; + uint16_t hashSize; +} INTERNAL_HASH_INFO; + +typedef struct { TPMI_ALG_HASH hashAlg; TPMU_HA digest; } TPMT_HA; +// Table 96 -- TPML_DIGEST_VALUES Structure <I/O> typedef struct { uint32_t count; - TPMT_HA digests[1]; /* Limit max number of hashes to 1. */ -} TPML_DIGEST_VALUES; + TPMT_HA digests[HASH_COUNT]; +} __packed TPML_DIGEST_VALUES; struct nv_read_response { uint32_t params_size; -- To view, visit https://review.coreboot.org/c/coreboot/+/30826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85e1bd2822aa6e7fd95ff2b9faa25cf183e6de37 Gerrit-Change-Number: 30826 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/sandybridge/acpi: Don't use defines for memory ranges
by Patrick Rudolph (Code Review) 18 Jul '19

18 Jul '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32074 Change subject: nb/intel/sandybridge/acpi: Don't use defines for memory ranges ...................................................................... nb/intel/sandybridge/acpi: Don't use defines for memory ranges Read the northbridge BARs from device PCI0:0.0. Change-Id: I27bfb5721d9ae3dc5629942ebac29b12a7308441 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/acpi/hostbridge.asl M src/northbridge/intel/sandybridge/acpi/sandybridge.asl 2 files changed, 22 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/32074/1 diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl index 09b8892..44fd36c 100644 --- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl @@ -103,7 +103,7 @@ Name (CTCD, 1) /* CTDP Down Select */ Name (CTCU, 2) /* CTDP Up Select */ - OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000) + OperationRegion (MCHB, SystemMemory, \_SB.PCI0.MCHC.MHBR << 14, 0x8000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x5930), diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index dce9f67..93e0722 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include "../sandybridge.h" #include "hostbridge.asl" #include "peg.asl" @@ -27,12 +26,13 @@ Name (PDRS, ResourceTemplate() { Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA - Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00008000) - Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) - Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000) + // Filled by _CRS + Memory32Fixed(ReadWrite, 0, 0x00008000, MCHB) + Memory32Fixed(ReadWrite, 0, 0x00001000, DMIB) + Memory32Fixed(ReadWrite, 0, 0x00001000, EGPB) + Memory32Fixed(ReadWrite, 0, 0x04000000, PCIX) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH - Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH + Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // TPM TIS Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH #if CONFIG(CHROMEOS_RAMOOPS) @@ -48,6 +48,21 @@ // Current Resource Settings Method (_CRS, 0, Serialized) { + CreateDwordField (PDRS, ^MCHB._BAS, MBR0) + MBR0 = \_SB.PCI0.MCHC.MHBR << 14 + + CreateDwordField (PDRS, ^DMIB._BAS, DBR0) + DBR0 = \_SB.PCI0.MCHC.DMBR << 13 + + CreateDwordField (PDRS, ^EGPB._BAS, EBR0) + EBR0 = \_SB.PCI0.MCHC.DMBR << 12 + + CreateDwordField (PDRS, ^PCIX._BAS, XBR0) + XBR0 = \_SB.PCI0.MCHC.PXBR << 26 + + CreateDwordField (PDRS, ^PCIX._LEN, XSZ0) + XSZ0 = 0x10000000 << \_SB.PCI0.MCHC.PXSZ + Return(PDRS) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/32074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27bfb5721d9ae3dc5629942ebac29b12a7308441 Gerrit-Change-Number: 32074 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Update arm-trusted-firmware submodule to upstream master
by Martin Roth (Code Review) 14 Jul '19

14 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32341 Change subject: Update arm-trusted-firmware submodule to upstream master ...................................................................... Update arm-trusted-firmware submodule to upstream master Updating from commit id 693e278e: 2018-02-01 18:15:53 +0000 - (Merge pull request #1245 from antonio-nino-diaz-arm/an/checkpatch) to commit id 5d149bdb: 2019-04-16 14:48:55 +0100 - (Temporarily disable shared Mbed TLS heap for SGM) This brings in 2316 new commits. Change-Id: Iaeec22d062e451f014b1800b473bfda94fa40530 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M 3rdparty/arm-trusted-firmware 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/32341/1 diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 693e278..5d149bd 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 693e278e308441d716f7f5116c43aa150955da31 +Subproject commit 5d149bdb18c0c6fb0aa76f32e0ffbb9f9269c994 -- To view, visit https://review.coreboot.org/c/coreboot/+/32341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeec22d062e451f014b1800b473bfda94fa40530 Gerrit-Change-Number: 32341 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: Update chromeec submodule to upstream master
by Martin Roth (Code Review) 14 Jul '19

14 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32342 Change subject: Update chromeec submodule to upstream master ...................................................................... Update chromeec submodule to upstream master Updating from commit id 11bd4c0f4: 2018-05-22 21:57:16 -0700 - (bip: enabled PPC interrupts) to commit id 8841b815c: 2019-04-17 13:33:39 +0000 - (ish: add missing EOI in LAPIC error irq handler) This brings in 2056 new commits. Change-Id: I13e1ce005f20aa6e68f2e6ef7f94222a9173eb16 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M 3rdparty/chromeec 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32342/1 diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 11bd4c0..8841b81 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 11bd4c0f4d11357ab830982d7dec164813c886dd +Subproject commit 8841b815c195aadacb8f0f6e625041c3427bbd97 -- To view, visit https://review.coreboot.org/c/coreboot/+/32342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13e1ce005f20aa6e68f2e6ef7f94222a9173eb16 Gerrit-Change-Number: 32342 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: Update fsp submodule to upstream master
by Martin Roth (Code Review) 14 Jul '19

14 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32343 Change subject: Update fsp submodule to upstream master ...................................................................... Update fsp submodule to upstream master Updating from commit id 162719b: 2018-09-27 10:55:19 -0700 - (Add SplitFspBin.py) to commit id 8699794: 2019-04-04 15:19:28 -0700 - (Denverton-NS Production Validated 004) This brings in 10 new commits. Change-Id: Ibb185df3bf1f4657256c7b8885a3f0c7695cc798 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M 3rdparty/fsp 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32343/1 diff --git a/3rdparty/fsp b/3rdparty/fsp index 162719b..8699794 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 162719b6cb5efc6c50dcb23dfdb378358573e2b6 +Subproject commit 86997945d03e1471f5dcdbbbb8d6118e5a6ecd38 -- To view, visit https://review.coreboot.org/c/coreboot/+/32343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb185df3bf1f4657256c7b8885a3f0c7695cc798 Gerrit-Change-Number: 32343 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: [TEST] udelay() in postcar
by Kyösti Mälkki (Code Review) 12 Jul '19

12 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31327 Change subject: [TEST] udelay() in postcar ...................................................................... [TEST] udelay() in postcar Change-Id: I7aeaa8487a15be92b259c6902a7142d7b04e52c2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/postcar.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/31327/1 diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index ea05824..957ca92 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -19,6 +19,7 @@ #include <cpu/x86/mtrr.h> #include <main_decl.h> #include <program_loading.h> +#include <delay.h> /* * Systems without a native coreboot cache-as-ram teardown may implement @@ -28,6 +29,8 @@ void main(void) { + udelay(1); + late_car_teardown(); console_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/31327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aeaa8487a15be92b259c6902a7142d7b04e52c2 Gerrit-Change-Number: 31327 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel soc/intel: Fix udelay() for postcar
by Kyösti Mälkki (Code Review) 12 Jul '19

12 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31326 Change subject: cpu/intel soc/intel: Fix udelay() for postcar ...................................................................... cpu/intel soc/intel: Fix udelay() for postcar We need tsc_freq_mhz() in postcar stage. Change-Id: I56bc98c1ad91928c319839f03c361d15ce20b719 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/broadwell/Makefile.inc 5 files changed, 12 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/31326/1 diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index c317c09..8a2f960 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,10 +1,12 @@ -ramstage-y += haswell_init.c -ramstage-y += tsc_freq.c romstage-y += romstage.c romstage-y += tsc_freq.c romstage-y += ../car/romstage.c +postcar-y += tsc_freq.c + ramstage-y += acpi.c +ramstage-y += haswell_init.c +ramstage-y += tsc_freq.c ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index ec8643a..73c51dc 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -10,8 +10,9 @@ subdirs-y += ../smm/gen1 subdirs-y += ../common -ramstage-y += tsc_freq.c romstage-y += tsc_freq.c +postcar-y += tsc_freq.c +ramstage-y += tsc_freq.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c ramstage-y += acpi.c diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index d193e60..ec08c81 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -17,8 +17,9 @@ romstage-y += common.c smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c -ramstage-y += tsc_freq.c romstage-y += tsc_freq.c +postcar-y += tsc_freq.c +ramstage-y += tsc_freq.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 1debea9..cb721ea 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -12,8 +12,9 @@ ramstage-y += memmap.c romstage-y += memmap.c postcar-y += memmap.c -ramstage-y += tsc_freq.c romstage-y += tsc_freq.c +postcar-y += tsc_freq.c +ramstage-y += tsc_freq.c smm-y += tsc_freq.c ramstage-y += spi.c smm-y += spi.c diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index acb71fe..f360b96 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -58,8 +58,9 @@ romstage-y += stage_cache.c postcar-y += stage_cache.c ramstage-y += systemagent.c -ramstage-y += tsc_freq.c +postcar-y += tsc_freq.c romstage-y += tsc_freq.c +ramstage-y += tsc_freq.c smm-y += tsc_freq.c bootblock-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c -- To view, visit https://review.coreboot.org/c/coreboot/+/31326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56bc98c1ad91928c319839f03c361d15ce20b719 Gerrit-Change-Number: 31326 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: include: Implement abs()
by Patrick Rudolph (Code Review) 11 Jul '19

11 Jul '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32501 Change subject: include: Implement abs() ...................................................................... include: Implement abs() There are a few external libraries that make use of this simple function. Change-Id: I0719de6558cf9224ecbbd46b6f8a8040e8225a79 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/include/stdlib.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/32501/1 diff --git a/src/include/stdlib.h b/src/include/stdlib.h index 34ef93a..a396a3b 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -11,4 +11,9 @@ /* We never free memory */ static inline void free(void *ptr) {} +static inline int abs(int i) +{ + return i < 0 ? -i : i; +} + #endif /* STDLIB_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0719de6558cf9224ecbbd46b6f8a8040e8225a79 Gerrit-Change-Number: 32501 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vendorcode/eltan Add hashing library used for measured and verified b...
by Frans Hendriks (Code Review) 10 Jul '19

10 Jul '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30831 Change subject: vendorcode/eltan Add hashing library used for measured and verified boot. ...................................................................... vendorcode/eltan Add hashing library used for measured and verified boot. To avoid having the whole 3rdparty/vboot/firmware included a small hashing library has been created. Create library which is a 'wrapper' using only sha1, sha256 and sha512 of 3rdparty/vboot/firmware. Fucntions cb_sha1(), cb_sha256() and cb_sha512 can be used for hashing. BUG=N/A TEST=Created binary and verify logging on Facebok FBG-1701 Change-Id: If828bde54c79e836a5b05ff0447645d7e06e819a Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- A src/vendorcode/eltan/security/include/cb_sha1.h A src/vendorcode/eltan/security/include/cb_sha256.h A src/vendorcode/eltan/security/include/cb_sha512.h A src/vendorcode/eltan/security/include/cryptolib.h A src/vendorcode/eltan/security/lib/Makefile.inc A src/vendorcode/eltan/security/lib/cb_sha1.c A src/vendorcode/eltan/security/lib/cb_sha256.c A src/vendorcode/eltan/security/lib/cb_sha512.c 8 files changed, 297 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30831/1 diff --git a/src/vendorcode/eltan/security/include/cb_sha1.h b/src/vendorcode/eltan/security/include/cb_sha1.h new file mode 100644 index 0000000..3b72355 --- /dev/null +++ b/src/vendorcode/eltan/security/include/cb_sha1.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018. Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SECURITY_SHA1_H__ +#define __SECURITY_SHA1_H__ + +uint8_t *cb_sha1(const uint8_t *data, uint64_t len, uint8_t *digest); + +#endif diff --git a/src/vendorcode/eltan/security/include/cb_sha256.h b/src/vendorcode/eltan/security/include/cb_sha256.h new file mode 100644 index 0000000..3b45f73 --- /dev/null +++ b/src/vendorcode/eltan/security/include/cb_sha256.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018. Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SECURITY_SHA256_H__ +#define __SECURITY_SHA256_H__ + +uint8_t *cb_sha256(const uint8_t *data, uint64_t len, uint8_t *digest); +uint8_t *cb_sha256_ex(const uint8_t *data, uint64_t len, uint8_t *digest, + bool endian); + +#endif diff --git a/src/vendorcode/eltan/security/include/cb_sha512.h b/src/vendorcode/eltan/security/include/cb_sha512.h new file mode 100644 index 0000000..a383cf0 --- /dev/null +++ b/src/vendorcode/eltan/security/include/cb_sha512.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018. Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SECURITY_SHA512_H__ +#define __SECURITY_SHA512_H__ + +uint8_t *cb_sha512(const uint8_t *data, uint64_t len, uint8_t *digest); +uint8_t *cb_sha512_ex(const uint8_t *data, uint64_t len, uint8_t *digest, + bool endian); + +#endif diff --git a/src/vendorcode/eltan/security/include/cryptolib.h b/src/vendorcode/eltan/security/include/cryptolib.h new file mode 100644 index 0000000..ac1668a --- /dev/null +++ b/src/vendorcode/eltan/security/include/cryptolib.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018. Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SECURITY_CRYPTOLIB_H__ +#define __SECURITY_CRYPTOLIB_H__ + +#define NEED_VB2_SHA_LIBRARY + +#include <2rsa.h> +#include <vb21_common.h> +#include <vb2_api.h> + +#include "cb_sha1.h" +#include "cb_sha512.h" +#include "cb_sha256.h" + +#endif \ No newline at end of file diff --git a/src/vendorcode/eltan/security/lib/Makefile.inc b/src/vendorcode/eltan/security/lib/Makefile.inc new file mode 100644 index 0000000..9e2fc39 --- /dev/null +++ b/src/vendorcode/eltan/security/lib/Makefile.inc @@ -0,0 +1,52 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2018 Eltan B.V. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +SECURITYLIB_INCLUDES = -I3rdparty/vboot/firmware/2lib/include -I3rdparty/vboot/firmware/lib21/include + +CPPFLAGS_common+=$(SECURITYLIB_INCLUDES) + +ifeq ($(CONFIG_VERIFIED_BOOT),y) +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2common.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2rsa.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2sha_utility.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/lib21/packed_key.c +ifeq ($(CONFIG_VERIFIED_BOOT_USE_SHA512),y) +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += cb_sha512.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2sha512.c +else +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += cb_sha256.c +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += $(top)/3rdparty/vboot/firmware/2lib/2sha256.c +endif +endif + +ifeq ($(CONFIG_MBOOT),y) +ramstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha1.c +ramstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha512.c +ramstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha256.c +ramstage-y += cb_sha1.c +ramstage-y += cb_sha512.c +ramstage-y += cb_sha256.c + +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2common.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2rsa.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha1.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha256.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha512.c +romstage-y += $(top)/3rdparty/vboot/firmware/2lib/2sha_utility.c +romstage-y += $(top)/3rdparty/vboot/firmware/lib21/packed_key.c +romstage-y += cb_sha1.c +romstage-y += cb_sha512.c +romstage-y += cb_sha256.c +endif \ No newline at end of file diff --git a/src/vendorcode/eltan/security/lib/cb_sha1.c b/src/vendorcode/eltan/security/lib/cb_sha1.c new file mode 100644 index 0000000..fd96943 --- /dev/null +++ b/src/vendorcode/eltan/security/lib/cb_sha1.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cryptolib.h> + +uint8_t *cb_sha1(const uint8_t *data, uint64_t len, uint8_t *digest) +{ + struct vb2_sha1_context ctx; + + vb2_sha1_init(&ctx); + vb2_sha1_update(&ctx, data, len); + vb2_sha1_finalize(&ctx, digest); + + return digest; +} diff --git a/src/vendorcode/eltan/security/lib/cb_sha256.c b/src/vendorcode/eltan/security/lib/cb_sha256.c new file mode 100644 index 0000000..b02ebb2 --- /dev/null +++ b/src/vendorcode/eltan/security/lib/cb_sha256.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cryptolib.h> + +uint8_t *cb_sha256_ex(const uint8_t *data, uint64_t len, uint8_t *digest, + bool endian) +{ + int i; + const uint8_t *input_ptr; + uint8_t result[VB2_SHA256_DIGEST_SIZE]; + uint8_t *result_ptr; + uint64_t remaining_len; + struct vb2_sha256_context ctx; + + vb2_sha256_init(&ctx); + + input_ptr = data; + remaining_len = len; + + /* Process data in at most UINT32_MAX byte chunks at a time. */ + while (remaining_len) { + uint32_t block_size; + block_size = (uint32_t) ((remaining_len >= UINT32_MAX) ? + UINT32_MAX : remaining_len); + vb2_sha256_update(&ctx, input_ptr, block_size); + remaining_len -= block_size; + input_ptr += block_size; + } + + result_ptr = result; + vb2_sha256_finalize(&ctx, result_ptr); + for (i = 0; i < VB2_SHA256_DIGEST_SIZE; ++i) { + if (endian) { + /* use big endian here */ + digest[i] = *result_ptr++; + } else { + /* use little endian here */ + digest[VB2_SHA256_DIGEST_SIZE - i - 1] = *result_ptr++; + } + } + return digest; +} + +uint8_t *cb_sha256(const uint8_t *data, uint64_t len, uint8_t *digest) +{ + /* Returned the little endian SHA256 digest */ + return cb_sha256_ex(data, len, digest, 0); +} \ No newline at end of file diff --git a/src/vendorcode/eltan/security/lib/cb_sha512.c b/src/vendorcode/eltan/security/lib/cb_sha512.c new file mode 100644 index 0000000..9d713e7 --- /dev/null +++ b/src/vendorcode/eltan/security/lib/cb_sha512.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Eltan B.V. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cryptolib.h> + +uint8_t *cb_sha512_ex(const uint8_t *data, uint64_t len, uint8_t *digest, + bool endian) +{ + int i; + const uint8_t *input_ptr; + uint8_t result[VB2_SHA512_DIGEST_SIZE]; + uint8_t *result_ptr; + uint64_t remaining_len; + struct vb2_sha512_context ctx; + + vb2_sha512_init(&ctx); + + input_ptr = data; + remaining_len = len; + + /* Process data in at most UINT32_MAX byte chunks at a time. */ + while (remaining_len) { + uint32_t block_size; + block_size = (uint32_t) ((remaining_len >= UINT32_MAX) ? + UINT32_MAX : remaining_len); + vb2_sha512_update(&ctx, input_ptr, block_size); + remaining_len -= block_size; + input_ptr += block_size; + } + + result_ptr = result; + vb2_sha512_finalize(&ctx, result_ptr); + for (i = 0; i < VB2_SHA512_DIGEST_SIZE; ++i) { + if (endian) { + /* use big endian here */ + digest[i] = *result_ptr++; + } else { + /* use little endian here */ + digest[VB2_SHA512_DIGEST_SIZE - i - 1] = *result_ptr++; + } + } + return digest; +} + +uint8_t *cb_sha512(const uint8_t *data, uint64_t len, uint8_t *digest) +{ + /* Returned the little endian SHA512 digest */ + return cb_sha512_ex(data, len, digest, 0); +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/30831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If828bde54c79e836a5b05ff0447645d7e06e819a Gerrit-Change-Number: 30831 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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