coreboot-gerrit April 2019

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Change in ...coreboot[master]: fu540: add code to initialize flash
by Xiang Wang (Code Review) 02 Aug '19

02 Aug '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30466 Change subject: fu540: add code to initialize flash ...................................................................... fu540: add code to initialize flash SiFive's ZSBL has initialized flash, but only 16MB of space is available. I fixed it to use all 32MB. Change-Id: I8cd803369da5526eff90400c15b91bbf6b477c69 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/mainboard/sifive/hifive-unleashed/Makefile.inc A src/mainboard/sifive/hifive-unleashed/bootblock.c A src/mainboard/sifive/hifive-unleashed/flash.c M src/mainboard/sifive/hifive-unleashed/romstage.c M src/soc/sifive/fu540/Makefile.inc A src/soc/sifive/fu540/include/soc/spi.h A src/soc/sifive/fu540/include/soc/spi_flash.h A src/soc/sifive/fu540/spi.c 8 files changed, 506 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/30466/1 diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc index 27ddcba..2dac283 100644 --- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc +++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc @@ -11,6 +11,10 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. +bootblock-y += flash.c +bootblock-y += bootblock.c + +romstage-y += flash.c romstage-y += romstage.c bootblock-y += memlayout.ld diff --git a/src/mainboard/sifive/hifive-unleashed/bootblock.c b/src/mainboard/sifive/hifive-unleashed/bootblock.c new file mode 100644 index 0000000..777b2aa --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/bootblock.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/addressmap.h> +#include <soc/spi.h> +#include <soc/spi_flash.h> +#include <soc/clock.h> + +extern void flash_init(void); +extern void bootblock_mainboard_init(void); + +void bootblock_mainboard_init(void) +{ + flash_init(); +} diff --git a/src/mainboard/sifive/hifive-unleashed/flash.c b/src/mainboard/sifive/hifive-unleashed/flash.c new file mode 100644 index 0000000..a29ac24 --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/flash.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/addressmap.h> +#include <soc/spi.h> +#include <soc/spi_flash.h> +#include <soc/clock.h> + +extern void flash_init(void); + +const static spi_reg_ffmt ffmt= { + .cmd_en = 1, + .addr_len = 4, + .pad_cnt = 8, + .command_proto = SPI_PROTO_S, + .addr_proto = SPI_PROTO_S, + .data_proto = SPI_PROTO_Q, + .command_code = 0x6c +}; + + +void flash_init(void) +{ + initialize_spi_flash_mmap_quad( + (spi_ctrl*)FU540_QSPI0, + clock_get_tlclk_khz(), + ffmt.raw_bits, + 0x66, + 0x99); +} diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c index 8277141..1675aca 100644 --- a/src/mainboard/sifive/hifive-unleashed/romstage.c +++ b/src/mainboard/sifive/hifive-unleashed/romstage.c @@ -21,6 +21,8 @@ #include <soc/clock.h> #include <soc/sdram.h> +extern void flash_init(void); + void main(void) { console_init(); @@ -39,6 +41,7 @@ if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) uart_init(CONFIG_UART_FOR_CONSOLE); + flash_init(); sdram_init(); cbmem_initialize_empty(); diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc index 4f62f3e..83c7b1c 100644 --- a/src/soc/sifive/fu540/Makefile.inc +++ b/src/soc/sifive/fu540/Makefile.inc @@ -18,6 +18,7 @@ bootblock-y += media.c bootblock-y += bootblock.c bootblock-y += clock.c +bootblock-y += spi.c romstage-y += uart.c romstage-y += clint.c @@ -26,6 +27,7 @@ romstage-y += cbmem.c romstage-y += otp.c romstage-y += clock.c +romstage-y += spi.c ramstage-y += uart.c ramstage-y += clint.c @@ -34,6 +36,7 @@ ramstage-y += cbmem.c ramstage-y += otp.c ramstage-y += clock.c +ramstage-y += spi.c CPPFLAGS_common += -Isrc/soc/sifive/fu540/include diff --git a/src/soc/sifive/fu540/include/soc/spi.h b/src/soc/sifive/fu540/include/soc/spi.h new file mode 100644 index 0000000..c40ae7c --- /dev/null +++ b/src/soc/sifive/fu540/include/soc/spi.h @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef __SOC_SIFIVE_HIFIVE_U_SPI_H__ +#define __SOC_SIFIVE_HIFIVE_U_SPI_H__ + +#include <stdint.h> + +#define _ASSERT_SIZEOF(type, size) _Static_assert(sizeof(type) == (size), #type " must be " #size " bytes wide") + +typedef union +{ + struct + { + uint32_t pha : 1; + uint32_t pol : 1; + uint32_t reserved : 30; + }; + uint32_t raw_bits; +} spi_reg_sckmode; +_ASSERT_SIZEOF(spi_reg_sckmode, 4); + + +typedef union +{ + struct + { + uint32_t mode : 2; + uint32_t reserved : 30; + }; + uint32_t raw_bits; +} spi_reg_csmode; +_ASSERT_SIZEOF(spi_reg_csmode, 4); + + +typedef union +{ + struct + { + uint32_t cssck : 8; + uint32_t reserved0 : 8; + uint32_t sckcs : 8; + uint32_t reserved1 : 8; + }; + uint32_t raw_bits; +} spi_reg_delay0; +_ASSERT_SIZEOF(spi_reg_delay0, 4); + + +typedef union +{ + struct + { + uint32_t intercs : 8; + uint32_t reserved0 : 8; + uint32_t interxfr : 8; + uint32_t reserved1 : 8; + }; + uint32_t raw_bits; +} spi_reg_delay1; +_ASSERT_SIZEOF(spi_reg_delay1, 4); + + +typedef union +{ + struct + { + uint32_t proto : 2; + uint32_t endian : 1; + uint32_t dir : 1; + uint32_t reserved0 : 12; + uint32_t len : 4; + uint32_t reserved1 : 12; + }; + uint32_t raw_bits; +} spi_reg_fmt; +_ASSERT_SIZEOF(spi_reg_fmt, 4); + + +typedef union +{ + struct + { + uint32_t data : 8; + uint32_t reserved : 23; + uint32_t full : 1; + }; + uint32_t raw_bits; +} spi_reg_txdata; +_ASSERT_SIZEOF(spi_reg_txdata, 4); + + +typedef union +{ + struct + { + uint32_t data : 8; + uint32_t reserved : 23; + uint32_t empty : 1; + }; + uint32_t raw_bits; +} spi_reg_rxdata; +_ASSERT_SIZEOF(spi_reg_rxdata, 4); + + +typedef union +{ + struct + { + uint32_t txmark : 3; + uint32_t reserved : 29; + }; + uint32_t raw_bits; +} spi_reg_txmark; +_ASSERT_SIZEOF(spi_reg_txmark, 4); + + +typedef union +{ + struct + { + uint32_t rxmark : 3; + uint32_t reserved : 29; + }; + uint32_t raw_bits; +} spi_reg_rxmark; +_ASSERT_SIZEOF(spi_reg_rxmark, 4); + + +typedef union +{ + struct + { + uint32_t en : 1; + uint32_t reserved : 31; + }; + uint32_t raw_bits; +} spi_reg_fctrl; +_ASSERT_SIZEOF(spi_reg_fctrl, 4); + + +typedef union +{ + struct + { + uint32_t cmd_en : 1; + uint32_t addr_len : 3; + uint32_t pad_cnt : 4; + uint32_t command_proto : 2; + uint32_t addr_proto : 2; + uint32_t data_proto : 2; + uint32_t reserved : 2; + uint32_t command_code : 8; + uint32_t pad_code : 8; + }; + uint32_t raw_bits; +} spi_reg_ffmt; +_ASSERT_SIZEOF(spi_reg_ffmt, 4); + + +typedef union +{ + struct + { + uint32_t txwm : 1; + uint32_t rxwm : 1; + uint32_t reserved : 30; + }; + uint32_t raw_bits; +} spi_reg_ie; +typedef spi_reg_ie spi_reg_ip; +_ASSERT_SIZEOF(spi_reg_ie, 4); +_ASSERT_SIZEOF(spi_reg_ip, 4); + +#undef _ASSERT_SIZEOF + + +/** + * SPI control register memory map. + * + * All functions take a pointer to a SPI device's control registers. + */ +typedef volatile struct +{ + uint32_t sckdiv; + spi_reg_sckmode sckmode; + uint32_t reserved08; + uint32_t reserved0c; + + uint32_t csid; + uint32_t csdef; + spi_reg_csmode csmode; + uint32_t reserved1c; + + uint32_t reserved20; + uint32_t reserved24; + spi_reg_delay0 delay0; + spi_reg_delay1 delay1; + + uint32_t reserved30; + uint32_t reserved34; + uint32_t reserved38; + uint32_t reserved3c; + + spi_reg_fmt fmt; + uint32_t reserved44; + spi_reg_txdata txdata; + spi_reg_rxdata rxdata; + + spi_reg_txmark txmark; + spi_reg_rxmark rxmark; + uint32_t reserved58; + uint32_t reserved5c; + + spi_reg_fctrl fctrl; + spi_reg_ffmt ffmt; + uint32_t reserved68; + uint32_t reserved6c; + + spi_reg_ie ie; + spi_reg_ip ip; +} spi_ctrl; + + +void spi_tx(spi_ctrl* spictrl, uint8_t in); +uint8_t spi_rx(spi_ctrl* spictrl); +uint8_t spi_txrx(spi_ctrl* spictrl, uint8_t in); + +// Inlining header functions in C +// https://stackoverflow.com/a/23699777/7433423 + +/** + * Get smallest clock divisor that divides input_khz to a quotient less than or + * equal to max_target_khz; + */ +static inline unsigned int spi_min_clk_divisor(unsigned int input_khz, unsigned int max_target_khz) +{ + // f_sck = f_in / (2 * (div + 1)) => div = (f_in / (2*f_sck)) - 1 + // + // The nearest integer solution for div requires rounding up as to not exceed + // max_target_khz. + // + // div = ceil(f_in / (2*f_sck)) - 1 + // = floor((f_in - 1 + 2*f_sck) / (2*f_sck)) - 1 + // + // This should not overflow as long as (f_in - 1 + 2*f_sck) does not exceed + // 2^32 - 1, which is unlikely since we represent frequencies in kHz. + unsigned int quotient = (input_khz + 2 * max_target_khz - 1) / (2 * max_target_khz); + // Avoid underflow + if (quotient == 0) + return 0; + return quotient - 1; +} + +#endif /* __SOC_SIFIVE_HIFIVE_U_SPI_H__ */ diff --git a/src/soc/sifive/fu540/include/soc/spi_flash.h b/src/soc/sifive/fu540/include/soc/spi_flash.h new file mode 100644 index 0000000..9926b82 --- /dev/null +++ b/src/soc/sifive/fu540/include/soc/spi_flash.h @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * Copyright (C) 2018 HardenedLinux + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_SIFIVE_HIFIVE_U_SPI_FLASH_H__ +#define __SOC_SIFIVE_HIFIVE_U_SPI_FLASH_H__ + +#include <soc/spi.h> +#include <stdint.h> + +#define SPI_PROTO_S 0 +#define SPI_PROTO_D 1 +#define SPI_PROTO_Q 2 + +/** + * Set up SPI for direct, non-memory-mapped access. + */ + +static inline int initialize_spi_flash_direct( + spi_ctrl* spictrl, + unsigned int spi_clk_input_khz, + unsigned int command_enable, + unsigned int command_reset) +{ + // Max desired SPI clock is 10MHz + spictrl->sckdiv = spi_min_clk_divisor(spi_clk_input_khz, 10000); + + spictrl->fctrl.en = 0; + + spi_txrx(spictrl, command_enable); + spi_txrx(spictrl, command_reset); + + return 0; +} + +static inline int _initialize_spi_flash_mmap( + spi_ctrl* spictrl, + unsigned int spi_clk_input_khz, + uint32_t ffmt_rawbits, + unsigned int command_enable, + unsigned int command_reset) +{ + // Max desired SPI clock is 10MHz + spictrl->sckdiv = spi_min_clk_divisor(spi_clk_input_khz, 10000); + + spictrl->fctrl.en = 0; + + spi_txrx(spictrl, command_enable); + spi_txrx(spictrl, command_reset); + + spictrl->ffmt.raw_bits = ffmt_rawbits; + + spictrl->fctrl.en = 1; + __asm__ __volatile__ ("fence io, io"); + return 0; +} + + +static inline int initialize_spi_flash_mmap_single( + spi_ctrl* spictrl, + unsigned int spi_clk_input_khz, + uint32_t ffmt_rawbits, + unsigned int command_enable, + unsigned int command_reset) +{ + return _initialize_spi_flash_mmap( + spictrl, + spi_clk_input_khz, + ffmt_rawbits, + command_enable, + command_reset); +} + + +static inline int initialize_spi_flash_mmap_quad( + spi_ctrl* spictrl, + unsigned int spi_clk_input_khz, + uint32_t ffmt_rawbits, + unsigned int command_enable, + unsigned int command_reset) +{ + return _initialize_spi_flash_mmap( + spictrl, + spi_clk_input_khz, + ffmt_rawbits, + command_enable, + command_reset); +} + +#endif /* __SOC_SIFIVE_HIFIVE_U_SPI_FLASH_H__ */ + diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c new file mode 100644 index 0000000..01a58dd --- /dev/null +++ b/src/soc/sifive/fu540/spi.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/spi.h> + +/** + * Wait until SPI is ready for transmission and transmit byte. + */ +void spi_tx(spi_ctrl* spictrl, uint8_t in) +{ +#if __riscv_atomic + int32_t r; + do { + asm volatile ( + "amoor.w %0, %2, %1\n" + : "=r" (r), "+A" (spictrl->txdata.raw_bits) + : "r" (in) + ); + } while (r < 0); +#else + while ((int32_t) spictrl->txdata.raw_bits < 0); + spictrl->txdata.data = in; +#endif +} + + +/** + * Wait until SPI receive queue has data and read byte. + */ +uint8_t spi_rx(spi_ctrl* spictrl) +{ + int32_t out; + while ((out = (int32_t) spictrl->rxdata.raw_bits) < 0); + return (uint8_t) out; +} + + +/** + * Transmit a byte and receive a byte. + */ +uint8_t spi_txrx(spi_ctrl* spictrl, uint8_t in) +{ + spi_tx(spictrl, in); + return spi_rx(spictrl); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/30466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cd803369da5526eff90400c15b91bbf6b477c69 Gerrit-Change-Number: 30466 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/kukui: Enable config for coreboot display
by yongqiang niu (Code Review) 31 Jul '19

31 Jul '19

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31521 Change subject: google/kukui: Enable config for coreboot display ...................................................................... google/kukui: Enable config for coreboot display BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I478e06686158dd77b075bcef8a41763ae26c79f9 Signed-off-by: Yongqiang Niu <yongqiang.niu(a)mediatek.com> --- M src/mainboard/google/kukui/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31521/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 9f477e5..9d2634a 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -37,6 +37,9 @@ select EC_GOOGLE_CHROMEEC_SPI select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT select MAINBOARD_HAS_TPM2 if VBOOT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/31521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I478e06686158dd77b075bcef8a41763ae26c79f9 Gerrit-Change-Number: 31521 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: payloads/external: add opensbi for risc-v
by Xiang Wang (Code Review) 29 Jul '19

29 Jul '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32393 Change subject: payloads/external: add opensbi for risc-v ...................................................................... payloads/external: add opensbi for risc-v Change-Id: I501584ed0dc1dc528ea2e95e1b93b32b71a470d7 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- A payloads/external/opensbi/COPYING.BSD A payloads/external/opensbi/Makefile A payloads/external/opensbi/README.md A payloads/external/opensbi/docs/contributing.md A payloads/external/opensbi/docs/doxygen.cfg A payloads/external/opensbi/docs/firmware/fw.md A payloads/external/opensbi/docs/firmware/fw_jump.md A payloads/external/opensbi/docs/firmware/fw_payload.md A payloads/external/opensbi/docs/firmware/payload_linux.md A payloads/external/opensbi/docs/firmware/payload_uboot.md A payloads/external/opensbi/docs/library_usage.md A payloads/external/opensbi/docs/platform/platform.md A payloads/external/opensbi/docs/platform/qemu_sifive_u.md A payloads/external/opensbi/docs/platform/qemu_virt.md A payloads/external/opensbi/docs/platform/sifive_fu540.md A payloads/external/opensbi/docs/platform_guide.md A payloads/external/opensbi/firmware/external_deps.mk A payloads/external/opensbi/firmware/fw_base.S A payloads/external/opensbi/firmware/fw_base.ldS A payloads/external/opensbi/firmware/fw_jump.S A payloads/external/opensbi/firmware/fw_jump.elf.ldS A payloads/external/opensbi/firmware/fw_payload.S A payloads/external/opensbi/firmware/fw_payload.elf.ldS A payloads/external/opensbi/firmware/objects.mk A payloads/external/opensbi/firmware/payloads/objects.mk A payloads/external/opensbi/firmware/payloads/test.elf.ldS A payloads/external/opensbi/firmware/payloads/test_head.S A payloads/external/opensbi/firmware/payloads/test_main.c A payloads/external/opensbi/include/sbi/riscv_asm.h A payloads/external/opensbi/include/sbi/riscv_atomic.h A payloads/external/opensbi/include/sbi/riscv_barrier.h A payloads/external/opensbi/include/sbi/riscv_encoding.h A payloads/external/opensbi/include/sbi/riscv_fp.h A payloads/external/opensbi/include/sbi/riscv_io.h A payloads/external/opensbi/include/sbi/riscv_locks.h A payloads/external/opensbi/include/sbi/sbi_bitops.h A payloads/external/opensbi/include/sbi/sbi_bits.h A payloads/external/opensbi/include/sbi/sbi_console.h A payloads/external/opensbi/include/sbi/sbi_const.h A payloads/external/opensbi/include/sbi/sbi_ecall.h A payloads/external/opensbi/include/sbi/sbi_ecall_interface.h A payloads/external/opensbi/include/sbi/sbi_emulate_csr.h A payloads/external/opensbi/include/sbi/sbi_error.h A payloads/external/opensbi/include/sbi/sbi_hart.h A payloads/external/opensbi/include/sbi/sbi_illegal_insn.h A payloads/external/opensbi/include/sbi/sbi_init.h A payloads/external/opensbi/include/sbi/sbi_ipi.h A payloads/external/opensbi/include/sbi/sbi_misaligned_ldst.h A payloads/external/opensbi/include/sbi/sbi_platform.h A payloads/external/opensbi/include/sbi/sbi_scratch.h A payloads/external/opensbi/include/sbi/sbi_system.h A payloads/external/opensbi/include/sbi/sbi_timer.h A payloads/external/opensbi/include/sbi/sbi_trap.h A payloads/external/opensbi/include/sbi/sbi_types.h A payloads/external/opensbi/include/sbi/sbi_unpriv.h A payloads/external/opensbi/include/sbi/sbi_version.h A payloads/external/opensbi/lib/objects.mk A payloads/external/opensbi/lib/riscv_asm.c A payloads/external/opensbi/lib/riscv_atomic.c A payloads/external/opensbi/lib/riscv_hardfp.S A payloads/external/opensbi/lib/riscv_locks.c A payloads/external/opensbi/lib/sbi_console.c A payloads/external/opensbi/lib/sbi_ecall.c A payloads/external/opensbi/lib/sbi_emulate_csr.c A payloads/external/opensbi/lib/sbi_hart.c A payloads/external/opensbi/lib/sbi_illegal_insn.c A payloads/external/opensbi/lib/sbi_init.c A payloads/external/opensbi/lib/sbi_ipi.c A payloads/external/opensbi/lib/sbi_misaligned_ldst.c A payloads/external/opensbi/lib/sbi_system.c A payloads/external/opensbi/lib/sbi_timer.c A payloads/external/opensbi/lib/sbi_trap.c A payloads/external/opensbi/platform/common/include/plat/irqchip/plic.h A payloads/external/opensbi/platform/common/include/plat/serial/sifive-uart.h A payloads/external/opensbi/platform/common/include/plat/serial/uart8250.h A payloads/external/opensbi/platform/common/include/plat/string.h A payloads/external/opensbi/platform/common/include/plat/sys/clint.h A payloads/external/opensbi/platform/common/include/plat/tinyfdt.h A payloads/external/opensbi/platform/common/irqchip/objects.mk A payloads/external/opensbi/platform/common/irqchip/plic.c A payloads/external/opensbi/platform/common/libc/objects.mk A payloads/external/opensbi/platform/common/libc/string.c A payloads/external/opensbi/platform/common/libfdt/Makefile.libfdt A payloads/external/opensbi/platform/common/libfdt/TODO A payloads/external/opensbi/platform/common/libfdt/fdt.c A payloads/external/opensbi/platform/common/libfdt/fdt.h A payloads/external/opensbi/platform/common/libfdt/fdt_addresses.c A payloads/external/opensbi/platform/common/libfdt/fdt_empty_tree.c A payloads/external/opensbi/platform/common/libfdt/fdt_overlay.c A payloads/external/opensbi/platform/common/libfdt/fdt_ro.c A payloads/external/opensbi/platform/common/libfdt/fdt_rw.c A payloads/external/opensbi/platform/common/libfdt/fdt_strerror.c A payloads/external/opensbi/platform/common/libfdt/fdt_sw.c A payloads/external/opensbi/platform/common/libfdt/fdt_wip.c A payloads/external/opensbi/platform/common/libfdt/libfdt.h A payloads/external/opensbi/platform/common/libfdt/libfdt_env.h A payloads/external/opensbi/platform/common/libfdt/libfdt_internal.h A payloads/external/opensbi/platform/common/libfdt/objects.mk A payloads/external/opensbi/platform/common/libfdt/version.lds A payloads/external/opensbi/platform/common/objects.mk A payloads/external/opensbi/platform/common/serial/objects.mk A payloads/external/opensbi/platform/common/serial/sifive-uart.c A payloads/external/opensbi/platform/common/serial/uart8250.c A payloads/external/opensbi/platform/common/sys/clint.c A payloads/external/opensbi/platform/common/sys/objects.mk A payloads/external/opensbi/platform/common/tinyfdt.c A payloads/external/opensbi/platform/kendryte/k210/config.mk A payloads/external/opensbi/platform/kendryte/k210/k210.dts A payloads/external/opensbi/platform/kendryte/k210/objects.mk A payloads/external/opensbi/platform/kendryte/k210/platform.c A payloads/external/opensbi/platform/kendryte/k210/platform.h A payloads/external/opensbi/platform/kendryte/k210/sysctl.c A payloads/external/opensbi/platform/kendryte/k210/sysctl.h A payloads/external/opensbi/platform/kendryte/k210/uarths.c A payloads/external/opensbi/platform/kendryte/k210/uarths.h A payloads/external/opensbi/platform/qemu/sifive_u/config.mk A payloads/external/opensbi/platform/qemu/sifive_u/objects.mk A payloads/external/opensbi/platform/qemu/sifive_u/platform.c A payloads/external/opensbi/platform/qemu/virt/config.mk A payloads/external/opensbi/platform/qemu/virt/objects.mk A payloads/external/opensbi/platform/qemu/virt/platform.c A payloads/external/opensbi/platform/sifive/fu540/HiFiveUnleashed-MicroSemi-Expansion.dts A payloads/external/opensbi/platform/sifive/fu540/config.mk A payloads/external/opensbi/platform/sifive/fu540/objects.mk A payloads/external/opensbi/platform/sifive/fu540/platform.c A payloads/external/opensbi/platform/template/config.mk A payloads/external/opensbi/platform/template/objects.mk A payloads/external/opensbi/platform/template/platform.c A payloads/external/opensbi/scripts/create-binary-archive.sh 129 files changed, 20,462 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/32393/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I501584ed0dc1dc528ea2e95e1b93b32b71a470d7 Gerrit-Change-Number: 32393 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

2 7

Change in ...coreboot[master]: payloads/external/opensbi: fix to boot for fu540
by Xiang Wang (Code Review) 29 Jul '19

29 Jul '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32395 Change subject: payloads/external/opensbi: fix to boot for fu540 ...................................................................... payloads/external/opensbi: fix to boot for fu540 1. Fix link address to prevent conflict with coreboot 2. Correct source fdt alignment to prevent copy errors Change-Id: I3477dd8fd44026753c061f34c060700bbcda4f4b Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M payloads/external/opensbi/firmware/fw_base.S M payloads/external/opensbi/platform/sifive/fu540/config.mk 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/32395/1 diff --git a/payloads/external/opensbi/firmware/fw_base.S b/payloads/external/opensbi/firmware/fw_base.S index 3bf7c6a..ffd9878 100644 --- a/payloads/external/opensbi/firmware/fw_base.S +++ b/payloads/external/opensbi/firmware/fw_base.S @@ -113,7 +113,7 @@ */ beqz a1, _fdt_reloc_done /* Mask values in a3 and a4 */ - li a3, ~0xf + li a3, ~(__SIZEOF_POINTER__ - 1) li a4, 0xff /* t1 = destination FDT start address */ add s0, a0, zero diff --git a/payloads/external/opensbi/platform/sifive/fu540/config.mk b/payloads/external/opensbi/platform/sifive/fu540/config.mk index 352c156..18a2c37 100644 --- a/payloads/external/opensbi/platform/sifive/fu540/config.mk +++ b/payloads/external/opensbi/platform/sifive/fu540/config.mk @@ -19,13 +19,13 @@ PLATFORM_SYS_CLINT=y # Blobs to build -FW_TEXT_START=0x80000000 +FW_TEXT_START=0x82000000 FW_JUMP=y -FW_JUMP_ADDR=0x80200000 -FW_JUMP_FDT_ADDR=0x82200000 +FW_JUMP_ADDR=0x82200000 +FW_JUMP_FDT_ADDR=0x84200000 FW_PAYLOAD=y FW_PAYLOAD_OFFSET=0x200000 -FW_PAYLOAD_FDT_ADDR=0x82200000 +FW_PAYLOAD_FDT_ADDR=0x84200000 # External Libraries to include PLATFORM_INCLUDE_LIBFDT=y -- To view, visit https://review.coreboot.org/c/coreboot/+/32395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3477dd8fd44026753c061f34c060700bbcda4f4b Gerrit-Change-Number: 32395 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: google/kukui: Init SSPM
by Erin Lo (Code Review) 26 Jul '19

26 Jul '19

Erin Lo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31835 Change subject: google/kukui: Init SSPM ...................................................................... google/kukui: Init SSPM Load SSPM firmware and boot up SSPM. BUG=b:80501386 BRANCH=none Test=We can see "sspm is alive" in ATF stage if SSPM enabled and ipi success Change-Id: I9285034fc8ce38b40134f5eb7b986a663175e620 Signed-off-by: Erin Lo <erin.lo(a)mediatek.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/mainboard.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31835/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index a0556c1..807a11d 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -25,3 +25,8 @@ ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c + +cbfs-files-y += sspm.bin +sspm.bin-file := 3rdparty/blobs/mainboard/google/kukui/sspm.bin +sspm.bin-type := raw +sspm.bin-compression := $(CBFS_COMPRESS_FLAG) diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index e1d8f5f..6447223 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -16,6 +16,7 @@ #include <device/device.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> +#include <soc/sspm.h> #include <soc/usb.h> static void configure_emmc(void) @@ -41,6 +42,7 @@ { configure_emmc(); configure_usb(); + sspm_init(); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/31835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9285034fc8ce38b40134f5eb7b986a663175e620 Gerrit-Change-Number: 31835 Gerrit-PatchSet: 1 Gerrit-Owner: Erin Lo <erin.lo(a)mediatek.com> Gerrit-MessageType: newchange

7 29

Change in ...coreboot[master]: crossgcc: Upgrade Python to version 3.7.3
by HAOUAS Elyes (Code Review) 25 Jul '19

25 Jul '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32077 Change subject: crossgcc: Upgrade Python to version 3.7.3 ...................................................................... crossgcc: Upgrade Python to version 3.7.3 Change-Id: I2d4a93fa43cf662685d4c439bcff04e338d51375 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/Python-3.7.2.tar.xz.cksum A util/crossgcc/sum/Python-3.7.3.tar.xz.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/32077/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index e901c37..1b94c33 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -55,7 +55,7 @@ BINUTILS_VERSION=2.32 GDB_VERSION=8.2.1 IASL_VERSION=20190215 -PYTHON_VERSION=3.7.2 +PYTHON_VERSION=3.7.3 EXPAT_VERSION=2.2.6 # CLANG version number CLANG_VERSION=7.0.1 diff --git a/util/crossgcc/sum/Python-3.7.2.tar.xz.cksum b/util/crossgcc/sum/Python-3.7.2.tar.xz.cksum deleted file mode 100644 index 4519f88..0000000 --- a/util/crossgcc/sum/Python-3.7.2.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -c3dc6928516bcb934cf4740461044c79c7c35494 tarballs/Python-3.7.2.tar.xz \ No newline at end of file diff --git a/util/crossgcc/sum/Python-3.7.3.tar.xz.cksum b/util/crossgcc/sum/Python-3.7.3.tar.xz.cksum new file mode 100644 index 0000000..10679ac --- /dev/null +++ b/util/crossgcc/sum/Python-3.7.3.tar.xz.cksum @@ -0,0 +1 @@ +e3584650a06ae2765da0678176deae9d133f1b3d tarballs/Python-3.7.3.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/32077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d4a93fa43cf662685d4c439bcff04e338d51375 Gerrit-Change-Number: 32077 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 10

Change in ...coreboot[master]: google/kukui: boot up sspm
by Erin Lo (Code Review) 22 Jul '19

22 Jul '19

Erin Lo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31516 Change subject: google/kukui: boot up sspm ...................................................................... google/kukui: boot up sspm Load sspm firmware form cbfs and bring up it. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui. Change-Id: I4ae6034454326f5115cd3948819adc448b67fb1c Signed-off-by: Erin Lo <erin.lo(a)mediatek.com> --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/mainboard.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/sspm.h A src/soc/mediatek/mt8183/sspm.c 7 files changed, 94 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/31516/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 9f477e5..0dcdb20 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -65,4 +65,8 @@ default "KUKUI TEST 9847" if BOARD_GOOGLE_KUKUI default "FLAPJACK TEST 4147" if BOARD_GOOGLE_FLAPJACK +config SSPM_BIN_FILE + string "SSPM BIN FILE" + default "" + endif diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index a0556c1..565c3f7 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -25,3 +25,8 @@ ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c + +cbfs-files-y += sspm +sspm-file := $(call strip_quotes,$(CONFIG_SSPM_BIN_FILE)) +sspm-type := raw +sspm-compression :=$(CBFS_COMPRESS_FLAG) diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index e1d8f5f..5aaab8b 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -13,10 +13,13 @@ * GNU General Public License for more details. */ +#include <console/console.h> +#include <cbfs.h> #include <device/device.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> #include <soc/usb.h> +#include <soc/sspm.h> static void configure_emmc(void) { @@ -37,10 +40,29 @@ setup_usb_host(); } +#define BUF_SIZE (64 * KiB) +unsigned char buf[BUF_SIZE]; + +static void sspm_boot(void) +{ + size_t fw_size = cbfs_boot_load_file("sspm", buf, sizeof(buf), + CBFS_TYPE_RAW); + + if (fw_size == 0) + printk(BIOS_DEBUG, "no sspm\n"); + else + printk(BIOS_DEBUG, "sspm[0]=%#x, [%zd]=%#x\n", + buf[0], fw_size - 1, buf[fw_size - 1]); + + sspm_init(buf, BUF_SIZE); + +} + static void mainboard_init(struct device *dev) { configure_emmc(); configure_usb(); + sspm_boot(); } static void mainboard_enable(struct device *dev) diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 5770a83..199b22d 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -49,6 +49,7 @@ ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c ramstage-y += ../common/wdt.c +ramstage-y += sspm.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index d41b2b9..f812224 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -34,6 +34,7 @@ EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CH_BASE = IO_PHYS + 0x00228000, + SSPM_BASE = IO_PHYS + 0x00440000, AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, diff --git a/src/soc/mediatek/mt8183/include/soc/sspm.h b/src/soc/mediatek/mt8183/include/soc/sspm.h new file mode 100644 index 0000000..f006ca2 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/sspm.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_SSPM_H +#define SOC_MEDIATEK_MT8183_SSPM_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8183_sspm_regs { + u32 sw_rstn; +}; +static struct mt8183_sspm_regs *const mt8183_sspm = (void *)SSPM_BASE; +#define CFG_SSPM_SRAM 0x10400000 +s32 sspm_init(unsigned char *buf, int len); +#endif /* SOC_MEDIATEK_MT8183_SSPM_H */ diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/mt8183/sspm.c new file mode 100644 index 0000000..a42a0f5 --- /dev/null +++ b/src/soc/mediatek/mt8183/sspm.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/barrier.h> +#include <arch/io.h> +#include <soc/gpio.h> +#include <soc/sspm.h> +#include <string.h> + +#define SSPM_UART 1 +s32 sspm_init(unsigned char *buf, int len) +{ + memcpy((void*)CFG_SSPM_SRAM, buf, len); +#if SSPM_UART + gpio_set_mode(GPIO(EINT4), PAD_EINT4_FUNC_SSPM_UTXD_AO); + gpio_set_mode(GPIO(EINT5), PAD_EINT5_FUNC_SSPM_URXD_AO); +#endif + mb(); + write32(&mt8183_sspm->sw_rstn, 0x1); + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ae6034454326f5115cd3948819adc448b67fb1c Gerrit-Change-Number: 31516 Gerrit-PatchSet: 1 Gerrit-Owner: Erin Lo <erin.lo(a)mediatek.com> Gerrit-MessageType: newchange

9 67

Change in ...libgfxinit[master]: gma: Add more PCI IDs for Coffee/Whiskey/Amber Lake
by Nico Huber (Code Review) 20 Jul '19

20 Jul '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/31453 Change subject: gma: Add more PCI IDs for Coffee/Whiskey/Amber Lake ...................................................................... gma: Add more PCI IDs for Coffee/Whiskey/Amber Lake These seem to be 100% compatible to Kaby Lake wrt. modesetting. So treat them as the latter for now. Untested. Didn't look at documented workarounds, yet. Change-Id: If01883ba95246f9bfd66049772597e0317e294d2 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-config.ads.template 1 file changed, 18 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/53/31453/1 diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index d91d9c7..c3f3a7c 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -390,6 +390,14 @@ (Device_Id and 16#ffcf#) = 16#590b# or (Device_Id and 16#ffcf#) = 16#590d#); + function Is_Coffee_Lake_Y_AML (Device_Id : Word16) return Boolean is + (Device_Id = 16#87ca#); + -- Including Whiskey Lake: + function Is_Coffee_Lake_U (Device_Id : Word16) return Boolean is + ((Device_Id and 16#fff0#) = 16#3ea0#); + function Is_Coffee_Lake (Device_Id : Word16) return Boolean is + ((Device_Id and 16#fff0#) = 16#3e90#); + function Is_GPU (Device_Id : Word16; CPU : CPU_Type; CPU_Var : CPU_Variant) return Boolean is (case CPU is @@ -412,10 +420,16 @@ when ULT => Is_Skylake_U (Device_Id), when ULX => Is_Skylake_Y (Device_Id)), when Kabylake => (case CPU_Var is - when Normal => Is_Kaby_Lake (Device_Id), - when ULT => Is_Kaby_Lake_U (Device_Id), - when ULX => Is_Kaby_Lake_Y (Device_Id) or - Is_Kaby_Lake_Y_AML (Device_Id))); + when Normal => + Is_Kaby_Lake (Device_Id) or + Is_Coffee_Lake (Device_Id), + when ULT => + Is_Kaby_Lake_U (Device_Id) or + Is_Coffee_Lake_U (Device_Id), + when ULX => + Is_Kaby_Lake_Y (Device_Id) or + Is_Kaby_Lake_Y_AML (Device_Id) or + Is_Coffee_Lake_Y_AML (Device_Id))); function Compatible_GPU (Device_Id : Word16) return Boolean is (Is_GPU (Device_Id, CPU, CPU_Var)); -- To view, visit https://review.coreboot.org/c/libgfxinit/+/31453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: If01883ba95246f9bfd66049772597e0317e294d2 Gerrit-Change-Number: 31453 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

4 14

Change in ...libgfxinit[master]: gma i2c: Try to clear NAK indicator
by Nico Huber (Code Review) 20 Jul '19

20 Jul '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/32491 Change subject: gma i2c: Try to clear NAK indicator ...................................................................... gma i2c: Try to clear NAK indicator Change-Id: I7df80d8757e1d14e288d9424240e873cf5a5fd29 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-i2c.adb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/91/32491/1 diff --git a/common/hw-gfx-gma-i2c.adb b/common/hw-gfx-gma-i2c.adb index d8cdf44..e5cf010 100644 --- a/common/hw-gfx-gma-i2c.adb +++ b/common/hw-gfx-gma-i2c.adb @@ -251,6 +251,10 @@ (Register => GMBUS_Regs (2), Mask => GMBUS2_GMBUS_ACTIVE); end if; + if (GMBUS2 and GMBUS2_NAK_INDICATOR) /= 0 then + Reset_GMBUS (Success); + Success := False; + end if; end if; Length := Transfered; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/32491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I7df80d8757e1d14e288d9424240e873cf5a5fd29 Gerrit-Change-Number: 32491 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...libgfxinit[master]: gma: Publish Read_EDID()
by Nico Huber (Code Review) 20 Jul '19

20 Jul '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/31454 Change subject: gma: Publish Read_EDID() ...................................................................... gma: Publish Read_EDID() Might be useful in coreboot to read the raw EDID. Change-Id: I13d28a4434de3b0699a3475dd96febfdf75639f0 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-display_probing.adb M common/hw-gfx-gma-display_probing.ads M common/hw-gfx-gma.ads 3 files changed, 11 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/54/31454/1 diff --git a/common/hw-gfx-gma-display_probing.adb b/common/hw-gfx-gma-display_probing.adb index 9f756f6..cd2a452 100644 --- a/common/hw-gfx-gma-display_probing.adb +++ b/common/hw-gfx-gma-display_probing.adb @@ -13,7 +13,6 @@ -- with HW.GFX.I2C; -with HW.GFX.EDID; with HW.GFX.GMA.Config; with HW.GFX.GMA.Config_Helpers; with HW.GFX.GMA.I2C; @@ -56,8 +55,6 @@ (Raw_EDID : out EDID.Raw_EDID_Data; Port : in Active_Port_Type; Success : out Boolean) - with - Post => (if Success then EDID.Valid (Raw_EDID)) is Raw_EDID_Length : GFX.I2C.Transfer_Length := Raw_EDID'Length; begin diff --git a/common/hw-gfx-gma-display_probing.ads b/common/hw-gfx-gma-display_probing.ads index f5cd839..e51de88 100644 --- a/common/hw-gfx-gma-display_probing.ads +++ b/common/hw-gfx-gma-display_probing.ads @@ -12,6 +12,8 @@ -- GNU General Public License for more details. -- +with HW.GFX.EDID; + package HW.GFX.GMA.Display_Probing is @@ -20,6 +22,13 @@ All_Ports : constant Port_List := (DP1, DP2, DP3, HDMI1, HDMI2, HDMI3, Analog, Internal); + procedure Read_EDID + (Raw_EDID : out EDID.Raw_EDID_Data; + Port : in Active_Port_Type; + Success : out Boolean) + with + Post => (if Success then EDID.Valid (Raw_EDID)); + procedure Scan_Ports (Configs : out Pipe_Configs; Ports : in Port_List := All_Ports; diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 7ca0ca1..d3792a2 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -57,6 +57,8 @@ HDMI2, -- or DVI HDMI3, -- or DVI Analog); + subtype Active_Port_Type is Port_Type + range Port_Type'Succ (Disabled) .. Port_Type'Last; type Cursor_Mode is (No_Cursor, ARGB_Cursor); type Cursor_Size is (Cursor_64x64, Cursor_128x128, Cursor_256x256); @@ -171,9 +173,6 @@ ---------------------------------------------------------------------------- -- Internal representation of a single pipe's configuration - subtype Active_Port_Type is Port_Type - range Port_Type'Succ (Disabled) .. Port_Type'Last; - type GPU_Port is (DIGI_A, DIGI_B, DIGI_C, DIGI_D, DIGI_E, LVDS, VGA); subtype Digital_Port is GPU_Port range DIGI_A .. DIGI_E; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/31454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I13d28a4434de3b0699a3475dd96febfdf75639f0 Gerrit-Change-Number: 31454 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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coreboot-gerrit April 2019