coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

1 participants
1219 discussions

Change in ...coreboot[master]: WIP: riscv: Implement FIT for RISC-V
by Philipp Hug (Code Review) 08 Aug '19

08 Aug '19

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31215 Change subject: WIP: riscv: Implement FIT for RISC-V ...................................................................... WIP: riscv: Implement FIT for RISC-V Change-Id: Ic50f14a4f483d904db590ecd53bb1fc5bdeb06d6 --- M payloads/Kconfig M src/arch/riscv/Makefile.inc A src/arch/riscv/fit_payload.c M src/soc/sifive/fu540/Kconfig 4 files changed, 171 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/31215/1 diff --git a/payloads/Kconfig b/payloads/Kconfig index c7a7ba6..0c5ce8f 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -30,7 +30,7 @@ config PAYLOAD_FIT bool "A FIT payload" - depends on ARCH_ARM64 + depends on ARCH_ARM64 || ARCH_RISCV select PAYLOAD_FIT_SUPPORT help Select this option if you have a payload image (a FIT file) which diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index e4c8468..12609d4 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -139,6 +139,7 @@ ramstage-y += tables.c ramstage-y += payload.S ramstage-$(ARCH_RISCV_PMP) += pmp.c +ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c new file mode 100644 index 0000000..2176095 --- /dev/null +++ b/src/arch/riscv/fit_payload.c @@ -0,0 +1,166 @@ +/* + * Copyright 2013 Google Inc. + * Copyright 2018 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <bootmem.h> +#include <stdlib.h> +#include <program_loading.h> +#include <string.h> +#include <commonlib/compression.h> +#include <commonlib/cbfs_serialized.h> +#include <lib.h> +#include <fit.h> +#include <endian.h> + +#define MAX_KERNEL_SIZE (64*MiB) + +static bool fit_place_kernel(const struct range_entry *r, void *arg) +{ + struct region *region = arg; + resource_t start; + + if (range_entry_tag(r) != BM_MEM_RAM) + return true; + + /** + * The Image must be placed text_offset bytes from a 2MB aligned base + * address anywhere in usable system RAM and called there. The region + * between the 2 MB aligned base address and the start of the image has + * no special significance to the kernel, and may be used for other + * purposes. + * + * If the reserved memory (BL31 for example) is smaller than text_offset + * we can use the 2 MiB base address, otherwise use the next 2 MiB page. + * It's not mandatory, but wastes less memory below the kernel. + */ + start = ALIGN_DOWN(range_entry_base(r), 2 * MiB); + + if (start < range_entry_base(r)) + start += 2 * MiB; + /** + * At least image_size bytes from the start of the image must be free + * for use by the kernel. + */ + if (start + region->size < range_entry_end(r)) { + region->offset = (size_t)start; + return false; + } + + return true; +} + +/** + * Place the region in free memory range. + * + * The caller has to set region->offset to the minimum allowed address. + * The region->offset is usually 0 on kernel >v4.6 and kernel_base + kernel_size + * on kernel <v4.6. + */ +static bool fit_place_mem(const struct range_entry *r, void *arg) +{ + struct region *region = arg; + resource_t start; + + if (range_entry_tag(r) != BM_MEM_RAM) + return true; + + /* Linux 4.15 doesn't like 4KiB alignment. Align to 1 MiB for now. */ + start = ALIGN_UP(MAX(region->offset, range_entry_base(r)), 1 * MiB); + + if (start + region->size < range_entry_end(r)) { + region->offset = (size_t)start; + return false; + } + + return true; +} + +bool fit_payload_arch(struct prog *payload, struct fit_config_node *config, + struct region *kernel, + struct region *fdt, + struct region *initrd) +{ + bool place_anywhere; + void *arg = NULL; + + if (!config->fdt || !fdt) { + printk(BIOS_CRIT, "CRIT: Providing a valid FDT is mandatory to " + "boot an RISCV kernel!\n"); + return false; + } + + /* Update kernel size from image header, if possible */ + kernel->size = 0x2000000; //get_kernel_size(config->kernel_node); + printk(BIOS_DEBUG, "FIT: Using kernel size of 0x%zx bytes\n", + kernel->size); + + + /** + * The code assumes that bootmem_walk provides a sorted list of memory + * regions, starting from the lowest address. + * The order of the calls here doesn't matter, as the placement is + * enforced in the called functions. + * For details check code on top. + */ + + if (!bootmem_walk(fit_place_kernel, kernel)) + return false; + + /* Mark as reserved for future allocations. */ + bootmem_add_range(kernel->offset, kernel->size, BM_MEM_PAYLOAD); + + /** + * NOTE: versions prior to v4.6 cannot make use of memory below the + * physical offset of the Image so it is recommended that the Image be + * placed as close as possible to the start of system RAM. + * + * For kernel <v4.6 the INITRD and FDT can't be placed below the kernel. + * In that case set region offset to an address on top of kernel. + */ + + place_anywhere = false; + printk(BIOS_DEBUG, "FIT: Placing FDT and INITRD %s\n", + place_anywhere ? "anywhere" : "on top of kernel"); + + /* Place INITRD */ + if (config->ramdisk) { + initrd->offset = 0; + + if (!bootmem_walk(fit_place_mem, initrd)) + return false; + /* Mark as reserved for future allocations. */ + bootmem_add_range(initrd->offset, initrd->size, BM_MEM_PAYLOAD); + } + + /* Place FDT */ + if (place_anywhere) + fdt->offset = 0; + else + fdt->offset = kernel->offset + kernel->size; + + if (!bootmem_walk(fit_place_mem, fdt)) + return false; + /* Mark as reserved for future allocations. */ + bootmem_add_range(fdt->offset, fdt->size, BM_MEM_PAYLOAD); + + /* Kernel expects FDT as argument */ + arg = (void *)fdt->offset; + + prog_set_entry(payload, (void *)kernel->offset, arg); + + bootmem_dump_ranges(); + + return true; +} diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 6ebde33..20645da 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -49,4 +49,7 @@ int default 0 +config HEAP_SIZE + default 0x10000 + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic50f14a4f483d904db590ecd53bb1fc5bdeb06d6 Gerrit-Change-Number: 31215 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: kukui/mainboard: Add mt8183 display usecase
by yongqiang niu (Code Review) 07 Aug '19

07 Aug '19

yongqiang niu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31517 Change subject: kukui/mainboard: Add mt8183 display usecase ...................................................................... kukui/mainboard: Add mt8183 display usecase BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I4b3f04cc2d044789bab4c3f0f03b3a904714158f Signed-off-by: Yongqiang Niu <yongqiang.niu(a)mediatek.com> --- M src/mainboard/google/kukui/mainboard.c 1 file changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/31517/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index e1d8f5f..950dca4 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -13,9 +13,14 @@ * GNU General Public License for more details. */ +#include <bootmode.h> +#include <console/console.h> #include <device/device.h> +#include <edid.h> +#include <soc/ddp.h> #include <soc/gpio.h> #include <soc/mmu_operations.h> +#include <soc/mtcmos.h> #include <soc/usb.h> static void configure_emmc(void) @@ -37,8 +42,31 @@ setup_usb_host(); } +static void display_startup(void) +{ + struct edid edid; + + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); + + mtk_ddp_init(); + + mtk_ddp_mode_set(&edid); + + set_vbe_mode_info_valid(&edid, (uintptr_t)0); +} + static void mainboard_init(struct device *dev) { + if (display_init_required()) { + printk(BIOS_INFO, "Starting display init.\n"); + mtcmos_display_power_on(); + mtcmos_protect_display_bus(); + + display_startup(); + } else { + printk(BIOS_INFO, "Skipping display init.\n"); + } + configure_emmc(); configure_usb(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b3f04cc2d044789bab4c3f0f03b3a904714158f Gerrit-Change-Number: 31517 Gerrit-PatchSet: 1 Gerrit-Owner: yongqiang niu <yongqiang.niu(a)mediatek.com> Gerrit-MessageType: newchange

8 20

Change in ...coreboot[master]: mediatek/mt8183: Add I2C driver code
by wang qii (Code Review) 07 Aug '19

07 Aug '19

wang qii has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30976 Change subject: mediatek/mt8183: Add I2C driver code ...................................................................... mediatek/mt8183: Add I2C driver code This patch implements i2c driver for MT8183. BUG=b:80501386 BRANCH=none TEST=Boot correctly on kukui. Change-Id: I0a4d78b494819f45951f78e5a618021000cf3463 Signed-off-by: qii wang <qii.wang(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/i2c.c M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/i2c.h 4 files changed, 236 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/30976/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 9aa1733..b0a148f 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -5,6 +5,7 @@ bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/timer.c bootblock-y += ../common/uart.c bootblock-y += ../common/wdt.c @@ -16,6 +17,7 @@ verstage-y += auxadc.c verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +verstage-y += ../common/i2c.c i2c.c verstage-y += ../common/timer.c verstage-y += ../common/uart.c verstage-y += ../common/wdt.c @@ -31,6 +33,7 @@ romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/timer.c romstage-y += ../common/uart.c romstage-y += ../common/wdt.c @@ -42,6 +45,7 @@ ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += ../common/i2c.c i2c.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c diff --git a/src/soc/mediatek/mt8183/i2c.c b/src/soc/mediatek/mt8183/i2c.c new file mode 100644 index 0000000..f389caf --- /dev/null +++ b/src/soc/mediatek/mt8183/i2c.c @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <arch/io.h> +#include <soc/pll.h> +#include <soc/i2c.h> +#include <soc/gpio.h> + +#define I2C_CLK_HZ (UNIVPLL_HZ / 30) + +struct mtk_i2c mtk_i2c_bus_controller[] = { + /* i2c0 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x2000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE), + }, + + /* i2c1 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0xc000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x400), + }, + + /* i2c2 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x4000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x200), + }, + + /* i2c3 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0xa000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x380), + }, + + /* i2c4 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x3000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x80), + }, + + /* i2c5 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x11000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x480), + }, + + /* i2c6 setting */ + { + .i2c_regs = (void *)(I2C_BASE), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x580), + }, + + /* i2c7 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x15000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x600), + }, + + /* i2c8 setting */ + { + .i2c_regs = (void *)(I2C_BASE + 0x16000), + .i2c_dma_regs = (void *)(I2C_DMA_BASE + 0x680), + } +}; + +#define I2C_BUS_NUMBER ARRAY_SIZE(mtk_i2c_bus_controller) + +struct pad_func { + gpio_t gpio; + u8 func; +}; + +#define PAD_FUNC(name, func) {GPIO(name), PAD_##name##_FUNC_##func} + +static const struct pad_func i2c_funcs[I2C_BUS_NUMBER][2] = { + { + PAD_FUNC(SDA0, SDA0), + PAD_FUNC(SCL0, SCL0), + }, + { + PAD_FUNC(SDA1, SDA1), + PAD_FUNC(SCL1, SCL1), + }, + { + PAD_FUNC(SDA2, SDA2), + PAD_FUNC(SCL2, SCL2), + }, + { + PAD_FUNC(SDA3, SDA3), + PAD_FUNC(SCL3, SCL3), + }, + { + PAD_FUNC(SDA4, SDA4), + PAD_FUNC(SCL4, SCL4), + }, + { + PAD_FUNC(SDA5, SDA5), + PAD_FUNC(SCL5, SCL5), + }, + { + PAD_FUNC(CONN_TOP_DATA, SDA6), + PAD_FUNC(CONN_TOP_CLK, SCL6), + }, + { + }, + { + PAD_FUNC(CAM_RST2, SDA8), + PAD_FUNC(CAM_CLK2, SCL8), + }, +}; + +static void mtk_i2c_set_gpio_pinmux(uint8_t bus) +{ + assert(bus < I2C_BUS_NUMBER && bus != 7); + + const struct pad_func *ptr = i2c_funcs[bus]; + for (size_t i = 0; i < 2; i++) { + gpio_set_mode(ptr[i].gpio, ptr[i].func); + gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); + if (bus < 6) { + gpio_set_i2c_eh(ptr[i].gpio, 0); + gpio_set_i2c_rsel(ptr[i].gpio, 3); + } + } +} + +static void mtk_i2c_speed_init(uint8_t bus) +{ + uint8_t step_div; + const uint8_t clock_div = 5; + const uint8_t sample_div = 1; + uint32_t i2c_freq; + + assert(bus < ARRAY_SIZE(mtk_i2c_bus_controller)); + + /* Calculate i2c frequency */ + step_div = DIV_ROUND_UP(I2C_CLK_HZ, + (400 * KHz * sample_div * 2) * clock_div); + i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2 * clock_div); + assert(sample_div < 8 && step_div < 64 && i2c_freq <= 400 * KHz && + i2c_freq >= 380 * KHz); + + /* Init i2c bus Timing register */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->timing, + (sample_div - 1) << 8 | (step_div - 1)); + write32(&mtk_i2c_bus_controller[bus].i2c_regs->ltiming, + (sample_div - 1) << 6 | (step_div - 1)); + + /* Init i2c bus clock_div register */ + write32(&mtk_i2c_bus_controller[bus].i2c_regs->clock_div, clock_div - 1); +} + +void mtk_i2c_init(uint8_t bus) +{ + mtk_i2c_speed_init(bus); + mtk_i2c_set_gpio_pinmux(bus); +} diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index d41b2b9..aaa77a3 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -34,8 +34,10 @@ EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CH_BASE = IO_PHYS + 0x00228000, + I2C_DMA_BASE = IO_PHYS + 0x01000080, AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01002000, + I2C_BASE = IO_PHYS + 0x01005000, SPI0_BASE = IO_PHYS + 0x0100A000, SPI1_BASE = IO_PHYS + 0x01010000, SPI2_BASE = IO_PHYS + 0x01012000, diff --git a/src/soc/mediatek/mt8183/include/soc/i2c.h b/src/soc/mediatek/mt8183/include/soc/i2c.h new file mode 100755 index 0000000..dbf9cbf --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/i2c.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_I2C_H +#define SOC_MEDIATEK_MT8183_I2C_H + +#include <soc/i2c_common.h> + +/* I2C Register */ +struct mt_i2c_regs { + uint32_t data_port; + uint32_t slave_addr; + uint32_t intr_mask; + uint32_t intr_stat; + uint32_t control; + uint32_t transfer_len; + uint32_t transac_len; + uint32_t delay_len; + uint32_t timing; + uint32_t start; + uint32_t ext_conf; + uint32_t ltiming; + uint32_t hs; + uint32_t io_config; + uint32_t fifo_addr_clr; + uint32_t reserved0[2]; + uint32_t transfer_aux_len; + uint32_t clock_div; + uint32_t time_out; + uint32_t softreset; + uint32_t reserved1[36]; + uint32_t debug_stat; + uint32_t debug_ctrl; + uint32_t reserved2[2]; + uint32_t fifo_stat; + uint32_t fifo_thresh; + uint32_t reserved3[932]; + uint32_t multi_dma; + uint32_t reserved4[2]; + uint32_t rollback; +}; + +check_member(mt_i2c_regs, multi_dma, 0xf8c); + +void mtk_i2c_init(uint8_t bus); + +#endif /* SOC_MEDIATEK_MT8183_I2C_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a4d78b494819f45951f78e5a618021000cf3463 Gerrit-Change-Number: 30976 Gerrit-PatchSet: 1 Gerrit-Owner: wang qii <Qii.Wang(a)mediatek.com> Gerrit-MessageType: newchange

7 22

Change in ...coreboot[master]: drivers/intel/gma: Export Read_EDID() to C
by Nico Huber (Code Review) 05 Aug '19

05 Aug '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31458 Change subject: drivers/intel/gma: Export Read_EDID() to C ...................................................................... drivers/intel/gma: Export Read_EDID() to C Change-Id: Icf802904c569e621ca3b3105b6107936776c5cee Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/drivers/intel/gma/Kconfig M src/drivers/intel/gma/Makefile.inc A src/drivers/intel/gma/gma.adb M src/drivers/intel/gma/gma.ads M src/drivers/intel/gma/libgfxinit.h 5 files changed, 67 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/31458/1 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 4f897fa..f8f50c3 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -54,6 +54,9 @@ Select this option for Atom-based platforms which use the SWSMISCI register (0xe0) rather than the SWSCI register (0xe8). +config INTEL_GMA_LIBGFXINIT_EDID + bool + config GFX_GMA_ANALOG_I2C_HDMI_B bool @@ -69,7 +72,7 @@ || NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE \ || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL \ || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE - depends on MAINBOARD_USE_LIBGFXINIT + depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID select RAMSTAGE_LIBHWBASE config GFX_GMA_INTERNAL_IS_EDP diff --git a/src/drivers/intel/gma/Makefile.inc b/src/drivers/intel/gma/Makefile.inc index e128ad6..cea319e 100644 --- a/src/drivers/intel/gma/Makefile.inc +++ b/src/drivers/intel/gma/Makefile.inc @@ -50,7 +50,7 @@ subdirs-y += ../../../../3rdparty/libgfxinit -ramstage-y += gma.ads +ramstage-y += gma.ads gma.adb ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-gfx_init.ads ifeq ($(CONFIG_LINEAR_FRAMEBUFFER),y) diff --git a/src/drivers/intel/gma/gma.adb b/src/drivers/intel/gma/gma.adb new file mode 100644 index 0000000..10885e6 --- /dev/null +++ b/src/drivers/intel/gma/gma.adb @@ -0,0 +1,37 @@ +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; + +package body GMA is + + function read_edid + (raw_edid : out HW.GFX.EDID.Raw_EDID_Data; + port : in Interfaces.C.int) + return Interfaces.C.int + is + use type Interfaces.C.int; + success : Boolean := true; + begin + if port not in Active_Port_Type'Pos (Active_Port_Type'First) + .. Active_Port_Type'Pos (Active_Port_Type'Last) + then + raw_edid := (others => 0); + return -2; + else + if not HW.GFX.GMA.Is_Initialized then + HW.GFX.GMA.Initialize (Success => success); + end if; + if success then + HW.GFX.GMA.Display_Probing.Read_EDID + (raw_edid, Active_Port_Type'Val (port), success); + end if; + if success then + return 0; + else + return -1; + end if; + end if; + end read_edid; + +end GMA; diff --git a/src/drivers/intel/gma/gma.ads b/src/drivers/intel/gma/gma.ads index a6ce3a4..0b4b66b 100644 --- a/src/drivers/intel/gma/gma.ads +++ b/src/drivers/intel/gma/gma.ads @@ -1,2 +1,14 @@ +with Interfaces.C; + +with HW.GFX.EDID; + package GMA is + + function read_edid + (raw_edid : out HW.GFX.EDID.Raw_EDID_Data; + Port : in Interfaces.C.int) + return Interfaces.C.int + with + Export, Convention => C, External_Name => "gma_read_edid"; + end GMA; diff --git a/src/drivers/intel/gma/libgfxinit.h b/src/drivers/intel/gma/libgfxinit.h index c67870e..c4a8a5b 100644 --- a/src/drivers/intel/gma/libgfxinit.h +++ b/src/drivers/intel/gma/libgfxinit.h @@ -14,6 +14,19 @@ #ifndef DRIVERS_INTEL_GMA_LIBGFXINIT_H #define DRIVERS_INTEL_GMA_LIBGFXINIT_H +enum { + GMA_PORT_DISABLED, + GMA_PORT_INTERNAL, + GMA_PORT_DP1, + GMA_PORT_DP2, + GMA_PORT_DP3, + GMA_PORT_HDMI1, /* or DVI */ + GMA_PORT_HDMI2, /* or DVI */ + GMA_PORT_HDMI3, /* or DVI */ + GMA_PORT_ANALOG, +}; + void gma_gfxinit(int *lightup_ok); +int gma_read_edid(unsigned char edid[], int port); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf802904c569e621ca3b3105b6107936776c5cee Gerrit-Change-Number: 31458 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 10

Change in ...coreboot[master]: drivers/intel/gma: Enable Kabylake+ libgfxinit support
by Nico Huber (Code Review) 05 Aug '19

05 Aug '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31464 Change subject: drivers/intel/gma: Enable Kabylake+ libgfxinit support ...................................................................... drivers/intel/gma: Enable Kabylake+ libgfxinit support Kaby, Coffee and Whiskey Lake are all supported by the same code path in libgfxinit. TEST=Played Tint on clevo/kbl-u(n130bu). Change-Id: Ic911bda3dd62c4d37a1b74a87fb51adc6c9d6ad4 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/drivers/intel/gma/Kconfig 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/31464/1 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 4f897fa..2dbed01 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -68,7 +68,9 @@ depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \ || NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE \ || NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL \ - || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE + || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE \ + || SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEE_LAKE \ + || SOC_INTEL_WHISKEY_LAKE depends on MAINBOARD_USE_LIBGFXINIT select RAMSTAGE_LIBHWBASE @@ -88,6 +90,7 @@ config GFX_GMA_CPU string + default "Kabylake" if SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEE_LAKE || SOC_INTEL_WHISKEY_LAKE default "Broxton" if SOC_INTEL_APOLLOLAKE default "Skylake" if SOC_INTEL_SKYLAKE default "Broadwell" if SOC_INTEL_BROADWELL @@ -99,7 +102,10 @@ config GFX_GMA_CPU_VARIANT string - default "ULT" if (SOC_INTEL_SKYLAKE && !SKYLAKE_SOC_PCH_H) || SOC_INTEL_BROADWELL || NORTHBRIDGE_INTEL_HASWELL + default "ULT" if ((SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEY_LAKE) \ + && !SOC_INTEL_CANNONLAKE_PCH_H) \ + || ((SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE) && !SKYLAKE_SOC_PCH_H) \ + || SOC_INTEL_BROADWELL || NORTHBRIDGE_INTEL_HASWELL default "Normal" config GFX_GMA_INTERNAL_PORT -- To view, visit https://review.coreboot.org/c/coreboot/+/31464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic911bda3dd62c4d37a1b74a87fb51adc6c9d6ad4 Gerrit-Change-Number: 31464 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

7 15

Change in ...coreboot[master]: [WIP] 3rdparty/libgfxinit: Update submodule pointer
by Nico Huber (Code Review) 05 Aug '19

05 Aug '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31457 Change subject: [WIP] 3rdparty/libgfxinit: Update submodule pointer ...................................................................... [WIP] 3rdparty/libgfxinit: Update submodule pointer Update libgfxinit: o Add support for ULX (CPU Y series) variants o Add support for Kaby/Coffee/Whiskey/Amber Lakes o Publish Read_EDID() procedure Change-Id: Ib252303708d2bb0524ecc47f498df45902ba774f Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M 3rdparty/libgfxinit 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/31457/1 diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index f70edda..47fa150 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit f70eddafbc2c6045a14e2f8bbb3273ee738fbaf7 +Subproject commit 47fa150df7ffee54659aebfdc78ff644ad319894 -- To view, visit https://review.coreboot.org/c/coreboot/+/31457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib252303708d2bb0524ecc47f498df45902ba774f Gerrit-Change-Number: 31457 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

3 8

Change in ...coreboot[master]: riscv: add support to boot linux kernel binary using opensbi
by Xiang Wang (Code Review) 03 Aug '19

03 Aug '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32394 Change subject: riscv: add support to boot linux kernel binary using opensbi ...................................................................... riscv: add support to boot linux kernel binary using opensbi Change-Id: I2a178595bd2aa2e1f114cbc69e8eadd46955b54d Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M payloads/Kconfig M payloads/external/Makefile.inc M src/arch/riscv/Makefile.inc M src/arch/riscv/boot.c M src/soc/sifive/fu540/Kconfig 5 files changed, 49 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/32394/1 diff --git a/payloads/Kconfig b/payloads/Kconfig index d0f8a44..4cf9d1e 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -28,6 +28,18 @@ You will be able to specify the location and file name of the payload image later. +config PAYLOAD_RISCV_LINUX_BINARY + bool "An linux binary payload" + depends on ARCH_RISCV + help + Select this option if you have a payload image (an binary file) + which coreboot should run as soon as the basic hardware + initialization is completed. This image will be used as the + payload of opensbi and will be started by coreboot. + + You will be able to specify the location and file name of the + payload image later. + config PAYLOAD_FIT bool "A FIT payload" depends on ARCH_ARM64 @@ -57,9 +69,10 @@ config PAYLOAD_FILE string "Payload path and filename" - depends on PAYLOAD_ELF || PAYLOAD_FIT + depends on PAYLOAD_ELF || PAYLOAD_FIT || PAYLOAD_RISCV_LINUX_BINARY default "payload.elf" if PAYLOAD_ELF default "uImage" if PAYLOAD_FIT + default "payload.bin" if PAYLOAD_RISCV_LINUX_BINARY help The path and filename of the ELF executable file to use as payload. diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 5f9d800..3b29b41 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -48,7 +48,11 @@ endif cbfs-files-y += $(CONFIG_CBFS_PREFIX)/payload +ifeq ($(CONFIG_PAYLOAD_RISCV_LINUX_BINARY),y) +$(CONFIG_CBFS_PREFIX)/payload-file := $(obj)/opensbi.elf +else $(CONFIG_CBFS_PREFIX)/payload-file := $(CONFIG_PAYLOAD_FILE) +endif ifeq ($(CONFIG_PAYLOAD_IS_FLAT_BINARY),y) $(CONFIG_CBFS_PREFIX)/payload-type := flat-binary else diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index d5f6295..d4d362b 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -174,4 +174,27 @@ endif #CONFIG_ARCH_RISCV_RV32 endif #CONFIG_ARCH_RAMSTAGE_RISCV + +ifeq ($(CONFIG_PAYLOAD_RISCV_LINUX_BINARY),y) + +OPENSBI := $(obj)/opensbi.elf +OPENSBI_SOURCE := $(top)/payloads/external/opensbi +OPENSBI_BUILD := $(abspath $(obj)/payloads/external/opensbi) +OPENSBI_TARGET := $(OPENSBI_BUILD)/platform/$(CONFIG_OPENSBI_PLATFORM)/firmware/fw_payload.elf + +$(OPENSBI):$(obj)/build.h + printf " MAKE $(subst $(obj)/,,$(@))\n" + mkdir -p $(OPENSBI_BUILD) + $(MAKE) \ + -C $(OPENSBI_SOURCE) \ + CROSS_COMPILE=riscv64-elf- \ + PLATFORM=$(CONFIG_OPENSBI_PLATFORM) \ + O=$(OPENSBI_BUILD) \ + FW_PAYLOAD_PATH=$(abspath $(CONFIG_PAYLOAD_FILE)) + cp $(OPENSBI_TARGET) $(abspath $@) + +.PHONY: $(OPENSBI) + +endif #CONFIG_PAYLOAD_RISCV_LINUX_BINARY + endif #CONFIG_ARCH_RISCV diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 535067e..9998255 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -49,7 +49,11 @@ fdt = HLS()->fdt; if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { +#if CONFIG(PAYLOAD_RISCV_LINUX_BINARY) + run_payload(prog, fdt, RISCV_PAYLOAD_MODE_M); +#else run_payload(prog, fdt, RISCV_PAYLOAD_MODE_S); +#endif return; } diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index 6ebde33..2e88150 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -49,4 +49,8 @@ int default 0 +config OPENSBI_PLATFORM + string + default "sifive/fu540" + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a178595bd2aa2e1f114cbc69e8eadd46955b54d Gerrit-Change-Number: 32394 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

5 27

Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: Mistral: Add board id detection using TPM
by Patrick Georgi (Code Review) 02 Aug '19

02 Aug '19

Hello nsekar(a)codeaurora.org, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32271 to review the following change. Change subject: TEMP: NOT FOR REVIEW: Mistral: Add board id detection using TPM ...................................................................... TEMP: NOT FOR REVIEW: Mistral: Add board id detection using TPM This patch adds support to select the board id based on the TPM availability. Change-Id: Ib75d51a21a6129e3650e2af24ff85f37a462591b Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/mainboard/google/mistral/boardid.c 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/32271/1 diff --git a/src/mainboard/google/mistral/boardid.c b/src/mainboard/google/mistral/boardid.c index 8258ac3..9a0d309 100644 --- a/src/mainboard/google/mistral/boardid.c +++ b/src/mainboard/google/mistral/boardid.c @@ -32,7 +32,22 @@ [1] = GPIO(106), [0] = GPIO(105)}; - bid = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins)); + if (is_tpm_detected() == 0) { + bid = 25; /* Assign 25 for EVB boards */ + printk(BIOS_DEBUG, "EVB Board ID: %d\n", bid); + } else { + bid = 0; /* Assign 0 for Proto boards */ + + /* The board id assigned for Proto boards is 0. + * Since gpios are not wired in the initial phase, + * we will get 0 whihch is a coincidence. + * To make sure it starts working, after gpios are + * wired, reassign the value read from gpios to id. + */ + bid = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins)); + + printk(BIOS_DEBUG, "Proto Board ID: %d\n", bid); + } return bid; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib75d51a21a6129e3650e2af24ff85f37a462591b Gerrit-Change-Number: 32271 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

3 11

Change in ...coreboot[master]: mediatek: Refactor I2C code among similar SOCs
by wang qii (Code Review) 02 Aug '19

02 Aug '19

wang qii has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30975 Change subject: mediatek: Refactor I2C code among similar SOCs ...................................................................... mediatek: Refactor I2C code among similar SOCs Refactor I2C code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot Change-Id: I407d5e2a9eb29562b40bb300e39f206a94afe76c Signed-off-by: qii wang <qii.wang(a)mediatek.com> --- A src/soc/mediatek/common/i2c.c A src/soc/mediatek/common/include/soc/i2c_common.h M src/soc/mediatek/mt8173/Makefile.inc M src/soc/mediatek/mt8173/i2c.c M src/soc/mediatek/mt8173/include/soc/i2c.h 5 files changed, 390 insertions(+), 354 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/30975/1 diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c new file mode 100644 index 0000000..73414ac --- /dev/null +++ b/src/soc/mediatek/common/i2c.c @@ -0,0 +1,273 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <assert.h> +#include <delay.h> +#include <timer.h> +#include <symbols.h> +#include <arch/io.h> +#include <soc/i2c.h> +#include <device/i2c_simple.h> + +static inline void i2c_dma_reset(struct mt_i2c_dma_regs *dma_regs) +{ + write32(&dma_regs->dma_rst, 0x1); + udelay(50); + write32(&dma_regs->dma_rst, 0x2); + udelay(50); + write32(&dma_regs->dma_rst, 0x0); + udelay(50); +} + +static inline void mtk_i2c_dump_info(uint8_t bus) +{ + struct mt_i2c_regs *regs; + + regs = mtk_i2c_bus_controller[bus].i2c_regs; + + printk(BIOS_ERR, "I2C register:\nSLAVE_ADDR %x\nINTR_MASK %x\n" + "INTR_STAT %x\nCONTROL %x\nTRANSFER_LEN %x\nTRANSAC_LEN %x\n" + "DELAY_LEN %x\nTIMING %x\nSTART %x\nFIFO_STAT %x\nIO_CONFIG %x\n" + "HS %x\nDEBUGSTAT %x\nEXT_CONF %x\n", + (read32(&regs->slave_addr)), + (read32(&regs->intr_mask)), + (read32(&regs->intr_stat)), + (read32(&regs->control)), + (read32(&regs->transfer_len)), + (read32(&regs->transac_len)), + (read32(&regs->delay_len)), + (read32(&regs->timing)), + (read32(&regs->start)), + (read32(&regs->fifo_stat)), + (read32(&regs->io_config)), + (read32(&regs->hs)), + (read32(&regs->debug_stat)), + (read32(&regs->ext_conf))); +} + +static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg, + enum i2c_modes read) +{ + uint32_t ret_code = I2C_OK; + uint16_t status; + uint32_t time_out_val = 0; + uint8_t addr; + uint32_t write_len = 0; + uint32_t read_len = 0; + uint8_t *write_buffer = NULL; + uint8_t *read_buffer = NULL; + struct mt_i2c_regs *regs; + struct mt_i2c_dma_regs *dma_regs; + struct stopwatch sw; + + regs = mtk_i2c_bus_controller[bus].i2c_regs; + dma_regs = mtk_i2c_bus_controller[bus].i2c_dma_regs; + + addr = seg[0].slave; + + switch (read) { + case I2C_WRITE_MODE: + assert(seg[0].len > 0 && seg[0].len <= 255); + write_len = seg[0].len; + write_buffer = seg[0].buf; + break; + + case I2C_READ_MODE: + assert(seg[0].len > 0 && seg[0].len <= 255); + read_len = seg[0].len; + read_buffer = seg[0].buf; + break; + + /* Must use special write-then-read mode for repeated starts. */ + case I2C_WRITE_READ_MODE: + assert(seg[0].len > 0 && seg[0].len <= 255); + assert(seg[1].len > 0 && seg[1].len <= 255); + write_len = seg[0].len; + read_len = seg[1].len; + write_buffer = seg[0].buf; + read_buffer = seg[1].buf; + break; + } + + /* Clear interrupt status */ + write32(&regs->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | + I2C_HS_NACKERR); + + write32(&regs->fifo_addr_clr, 0x1); + + /* Enable interrupt */ + write32(&regs->intr_mask, I2C_HS_NACKERR | I2C_ACKERR | + I2C_TRANSAC_COMP); + + switch (read) { + case I2C_WRITE_MODE: + memcpy(_dma_coherent, write_buffer, write_len); + + /* control registers */ + write32(&regs->control, ASYNC_MODE | DMAACK_EN | + ACK_ERR_DET_EN | DMA_EN | CLK_EXT | + REPEATED_START_FLAG); + + /* Set transfer and transaction len */ + write32(&regs->transac_len, 1); + write32(&regs->transfer_len, write_len); + + /* set i2c write slave address*/ + write32(&regs->slave_addr, addr << 1); + + /* Prepare buffer data to start transfer */ + write32(&dma_regs->dma_con, I2C_DMA_CON_TX); + write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_tx_len, write_len); + break; + + case I2C_READ_MODE: + /* control registers */ + write32(&regs->control, ASYNC_MODE | DMAACK_EN | + ACK_ERR_DET_EN | DMA_EN | CLK_EXT | + REPEATED_START_FLAG); + + /* Set transfer and transaction len */ + write32(&regs->transac_len, 1); + write32(&regs->transfer_len, read_len); + + /* set i2c read slave address*/ + write32(&regs->slave_addr, (addr << 1 | 0x1)); + + /* Prepare buffer data to start transfer */ + write32(&dma_regs->dma_con, I2C_DMA_CON_RX); + write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_rx_len, read_len); + break; + + case I2C_WRITE_READ_MODE: + memcpy(_dma_coherent, write_buffer, write_len); + + /* control registers */ + write32(&regs->control, ASYNC_MODE | DMAACK_EN | + DIR_CHG | ACK_ERR_DET_EN | DMA_EN | + CLK_EXT | REPEATED_START_FLAG); + + /* Set transfer and transaction len */ + write32(&regs->transfer_len, write_len); + write32(&regs->transfer_aux_len, read_len); + write32(&regs->transac_len, 2); + + /* set i2c write slave address*/ + write32(&regs->slave_addr, addr << 1); + + /* Prepare buffer data to start transfer */ + write32(&dma_regs->dma_con, I2C_DMA_CLR_FLAG); + write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_tx_len, write_len); + write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); + write32(&dma_regs->dma_rx_len, read_len); + break; + } + + write32(&dma_regs->dma_int_flag, I2C_DMA_CLR_FLAG); + write32(&dma_regs->dma_en, I2C_DMA_START_EN); + + /* start transfer transaction */ + write32(&regs->start, 0x1); + + stopwatch_init_msecs_expire(&sw, 100); + + /* polling mode : see if transaction complete */ + while (1) { + status = read32(&regs->intr_stat); + if (status & I2C_HS_NACKERR) { + ret_code = I2C_TRANSFER_FAIL_HS_NACKERR; + printk(BIOS_ERR, "[i2c%d] transfer NACK error\n", bus); + mtk_i2c_dump_info(bus); + break; + } else if (status & I2C_ACKERR) { + ret_code = I2C_TRANSFER_FAIL_ACKERR; + printk(BIOS_ERR, "[i2c%d] transfer ACK error\n", bus); + mtk_i2c_dump_info(bus); + break; + } else if (status & I2C_TRANSAC_COMP) { + ret_code = I2C_OK; + memcpy(read_buffer, _dma_coherent, read_len); + break; + } + + if (stopwatch_expired(&sw)) { + ret_code = I2C_TRANSFER_FAIL_TIMEOUT; + printk(BIOS_ERR, "[i2c%d] transfer timeout:%d\n", bus, + time_out_val); + mtk_i2c_dump_info(bus); + break; + } + } + + write32(&regs->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | + I2C_HS_NACKERR); + + /* clear bit mask */ + write32(&regs->intr_mask, I2C_HS_NACKERR | I2C_ACKERR | + I2C_TRANSAC_COMP); + + /* reset the i2c controller for next i2c transfer. */ + write32(&regs->softreset, 0x1); + + i2c_dma_reset(dma_regs); + + return ret_code; +} + +static uint8_t mtk_i2c_should_combine(struct i2c_msg *seg, int left_count) +{ + if (left_count >= 2 && + !(seg[0].flags & I2C_M_RD) && + (seg[1].flags & I2C_M_RD) && + seg[0].slave == seg[1].slave) + return 1; + else + return 0; +} + +int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, + int seg_count) +{ + int ret = 0; + int i; + int read; + + for (i = 0; i < seg_count; i++) { + if (mtk_i2c_should_combine(&segments[i], seg_count - i)) { + read = I2C_WRITE_READ_MODE; + } else { + read = (segments[i].flags & I2C_M_RD) ? + I2C_READ_MODE : I2C_WRITE_MODE; + } + + ret = mtk_i2c_transfer(bus, &segments[i], read); + + if (ret) + break; + + if (read == I2C_WRITE_READ_MODE) + i++; + } + + return ret; +} + +void mtk_i2c_bus_init(uint8_t bus) +{ + mtk_i2c_init(bus); +} diff --git a/src/soc/mediatek/common/include/soc/i2c_common.h b/src/soc/mediatek/common/include/soc/i2c_common.h new file mode 100755 index 0000000..e455f35 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/i2c_common.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MTK_COMMON_I2C_H +#define MTK_COMMON_I2C_H + +/* I2C DMA Registers */ +struct mt_i2c_dma_regs { + uint32_t dma_int_flag; + uint32_t dma_int_en; + uint32_t dma_en; + uint32_t dma_rst; + uint32_t reserved1; + uint32_t dma_flush; + uint32_t dma_con; + uint32_t dma_tx_mem_addr; + uint32_t dma_rx_mem_addr; + uint32_t dma_tx_len; + uint32_t dma_rx_len; +}; + +check_member(mt_i2c_dma_regs, dma_tx_len, 0x24); + +/* I2C Configuration */ +enum { + I2C_HS_DEFAULT_VALUE = 0x0102, +}; + +enum i2c_modes { + I2C_WRITE_MODE = 0, + I2C_READ_MODE = 1, + I2C_WRITE_READ_MODE = 2, +}; + +enum { + I2C_DMA_CON_TX = 0x0, + I2C_DMA_CON_RX = 0x1, + I2C_DMA_START_EN = 0x1, + I2C_DMA_INT_FLAG_NONE = 0x0, + I2C_DMA_CLR_FLAG = 0x0, + I2C_DMA_FLUSH_FLAG = 0x1, +}; + +enum { + I2C_TRANS_LEN_MASK = (0xff), + I2C_TRANS_AUX_LEN_MASK = (0x1f << 8), + I2C_CONTROL_MASK = (0x3f << 1) +}; + +/* Register mask */ +enum { + I2C_HS_NACKERR = (1 << 2), + I2C_ACKERR = (1 << 1), + I2C_TRANSAC_COMP = (1 << 0), +}; + +/* i2c control bits */ +enum { + ASYNC_MODE = (1 << 9), + DMAACK_EN = (1 << 8), + ACK_ERR_DET_EN = (1 << 5), + DIR_CHG = (1 << 4), + CLK_EXT = (1 << 3), + DMA_EN = (1 << 2), + REPEATED_START_FLAG = (1 << 1), + STOP_FLAG = (0 << 1) +}; + +/* I2C Status Code */ + +enum { + I2C_OK = 0x0000, + I2C_SET_SPEED_FAIL_OVER_SPEED = 0xA001, + I2C_TRANSFER_INVALID_LENGTH = 0xA002, + I2C_TRANSFER_FAIL_HS_NACKERR = 0xA003, + I2C_TRANSFER_FAIL_ACKERR = 0xA004, + I2C_TRANSFER_FAIL_TIMEOUT = 0xA005, + I2C_TRANSFER_INVALID_ARGUMENT = 0xA006 +}; + +struct mtk_i2c { + struct mt_i2c_regs *i2c_regs; + struct mt_i2c_dma_regs *i2c_dma_regs; +}; + +extern struct mtk_i2c mtk_i2c_bus_controller[]; + +void mtk_i2c_bus_init(uint8_t bus); +#endif diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index b004c27..5a54d6d 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -17,7 +17,7 @@ bootblock-y += bootblock.c bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c -bootblock-y += i2c.c +bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/pll.c pll.c bootblock-y += ../common/spi.c spi.c bootblock-y += ../common/timer.c @@ -32,7 +32,7 @@ ################################################################################ -verstage-y += i2c.c +verstage-y += ../common/i2c.c i2c.c verstage-y += ../common/spi.c spi.c verstage-y += ../common/uart.c @@ -49,7 +49,7 @@ romstage-y += ../common/pll.c pll.c romstage-y += ../common/timer.c romstage-y += timer.c -romstage-y += i2c.c +romstage-y += ../common/i2c.c i2c.c romstage-y += ../common/uart.c romstage-y += ../common/cbmem.c @@ -71,7 +71,8 @@ ramstage-y += ../common/timer.c ramstage-y += timer.c ramstage-y += ../common/uart.c -ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c i2c.c +ramstage-y += ../common/i2c.c i2c.c +ramstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6391.c ramstage-y += mt6311.c ramstage-y += da9212.c ramstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index b4c3aa9..85f676c 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -14,19 +14,13 @@ */ #include <assert.h> -#include <delay.h> -#include <device/i2c_simple.h> -#include <string.h> -#include <symbols.h> -#include <timer.h> #include <arch/io.h> -#include <soc/addressmap.h> -#include <soc/i2c.h> #include <soc/pll.h> +#include <soc/i2c.h> #define I2C_CLK_HZ (AXI_HZ / 16) -static struct mtk_i2c i2c[7] = { +struct mtk_i2c mtk_i2c_bus_controller[7] = { /* i2c0 setting */ { .i2c_regs = (void *)I2C_BASE, @@ -68,277 +62,21 @@ } }; -#define I2CTAG "[I2C][PL] " - -#if IS_ENABLED(CONFIG_DEBUG_I2C) -#define I2CLOG(fmt, arg...) printk(BIOS_INFO, I2CTAG fmt, ##arg) -#else -#define I2CLOG(fmt, arg...) -#endif /* CONFIG_DEBUG_I2C */ - -#define I2CERR(fmt, arg...) printk(BIOS_ERR, I2CTAG fmt, ##arg) - -static inline void i2c_dma_reset(struct mt8173_i2c_dma_regs *dma_regs) +void mtk_i2c_init(uint8_t bus) { - write32(&dma_regs->dma_rst, 0x1); - udelay(50); - write32(&dma_regs->dma_rst, 0x2); - udelay(50); - write32(&dma_regs->dma_rst, 0x0); - udelay(50); -} - -void mtk_i2c_bus_init(uint8_t bus) -{ - uint8_t sample_div; uint8_t step_div; uint32_t i2c_freq; + const uint8_t sample_div = 1; - assert(bus < ARRAY_SIZE(i2c)); + assert(bus < ARRAY_SIZE(mtk_i2c_bus_controller)); /* Calculate i2c frequency */ - sample_div = 1; step_div = DIV_ROUND_UP(I2C_CLK_HZ, (400 * KHz * sample_div * 2)); i2c_freq = I2C_CLK_HZ / (step_div * sample_div * 2); assert(sample_div < 8 && step_div < 64 && i2c_freq < 400 * KHz && i2c_freq >= 380 * KHz); /* Init i2c bus Timing register */ - write32(&i2c[bus].i2c_regs->timing, (sample_div - 1) << 8 | - (step_div - 1)); -} - -static inline void mtk_i2c_dump_info(uint8_t bus) -{ - struct mt8173_i2c_regs *regs; - - regs = i2c[bus].i2c_regs; - - I2CLOG("I2C register:\nSLAVE_ADDR %x\nINTR_MASK %x\nINTR_STAT %x\n" - "CONTROL %x\nTRANSFER_LEN %x\nTRANSAC_LEN %x\nDELAY_LEN %x\n" - "TIMING %x\nSTART %x\nFIFO_STAT %x\nIO_CONFIG %x\nHS %x\n" - "DEBUGSTAT %x\nEXT_CONF %x\n", - (read32(&regs->salve_addr)), - (read32(&regs->intr_mask)), - (read32(&regs->intr_stat)), - (read32(&regs->control)), - (read32(&regs->transfer_len)), - (read32(&regs->transac_len)), - (read32(&regs->delay_len)), - (read32(&regs->timing)), - (read32(&regs->start)), - (read32(&regs->fifo_stat)), - (read32(&regs->io_config)), - (read32(&regs->hs)), - (read32(&regs->debug_stat)), - (read32(&regs->ext_conf))); - - I2CLOG("addr address %x\n", (uint32_t)regs); -} - -static uint32_t mtk_i2c_transfer(uint8_t bus, struct i2c_msg *seg, - enum i2c_modes read) -{ - uint32_t ret_code = I2C_OK; - uint16_t status; - uint32_t time_out_val = 0; - uint8_t addr; - uint32_t write_len = 0; - uint32_t read_len = 0; - uint8_t *write_buffer = NULL; - uint8_t *read_buffer = NULL; - struct mt8173_i2c_regs *regs; - struct mt8173_i2c_dma_regs *dma_regs; - struct stopwatch sw; - - regs = i2c[bus].i2c_regs; - dma_regs = i2c[bus].i2c_dma_regs; - - addr = seg[0].slave; - - switch (read) { - case I2C_WRITE_MODE: - assert(seg[0].len > 0 && seg[0].len <= 255); - write_len = seg[0].len; - write_buffer = seg[0].buf; - break; - - case I2C_READ_MODE: - assert(seg[0].len > 0 && seg[0].len <= 255); - read_len = seg[0].len; - read_buffer = seg[0].buf; - break; - - /* Must use special write-then-read mode for repeated starts. */ - case I2C_WRITE_READ_MODE: - assert(seg[0].len > 0 && seg[0].len <= 255); - assert(seg[1].len > 0 && seg[1].len <= 255); - write_len = seg[0].len; - read_len = seg[1].len; - write_buffer = seg[0].buf; - read_buffer = seg[1].buf; - break; - } - - /* Clear interrupt status */ - write32(&regs->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | - I2C_HS_NACKERR); - - write32(&regs->fifo_addr_clr, 0x1); - - /* Enable interrupt */ - write32(&regs->intr_mask, I2C_HS_NACKERR | I2C_ACKERR | - I2C_TRANSAC_COMP); - - switch (read) { - case I2C_WRITE_MODE: - memcpy(_dma_coherent, write_buffer, write_len); - - /* control registers */ - write32(&regs->control, ACK_ERR_DET_EN | DMA_EN | CLK_EXT | - REPEATED_START_FLAG); - - /* Set transfer and transaction len */ - write32(&regs->transac_len, 1); - write32(&regs->transfer_len, write_len); - - /* set i2c write slave address*/ - write32(&regs->slave_addr, addr << 1); - - /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CON_TX); - write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); - write32(&dma_regs->dma_tx_len, write_len); - break; - - case I2C_READ_MODE: - /* control registers */ - write32(&regs->control, ACK_ERR_DET_EN | DMA_EN | CLK_EXT | - REPEATED_START_FLAG); - - /* Set transfer and transaction len */ - write32(&regs->transac_len, 1); - write32(&regs->transfer_len, read_len); - - /* set i2c read slave address*/ - write32(&regs->slave_addr, (addr << 1 | 0x1)); - - /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CON_RX); - write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); - write32(&dma_regs->dma_rx_len, read_len); - break; - - case I2C_WRITE_READ_MODE: - memcpy(_dma_coherent, write_buffer, write_len); - - /* control registers */ - write32(&regs->control, DIR_CHG | ACK_ERR_DET_EN | DMA_EN | - CLK_EXT | REPEATED_START_FLAG); - - /* Set transfer and transaction len */ - write32(&regs->transfer_len, write_len); - write32(&regs->transfer_aux_len, read_len); - write32(&regs->transac_len, 2); - - /* set i2c write slave address*/ - write32(&regs->slave_addr, addr << 1); - - /* Prepare buffer data to start transfer */ - write32(&dma_regs->dma_con, I2C_DMA_CLR_FLAG); - write32(&dma_regs->dma_tx_mem_addr, (uintptr_t)_dma_coherent); - write32(&dma_regs->dma_tx_len, write_len); - write32(&dma_regs->dma_rx_mem_addr, (uintptr_t)_dma_coherent); - write32(&dma_regs->dma_rx_len, read_len); - break; - } - - write32(&dma_regs->dma_int_flag, I2C_DMA_CLR_FLAG); - write32(&dma_regs->dma_en, I2C_DMA_START_EN); - - /* start transfer transaction */ - write32(&regs->start, 0x1); - - stopwatch_init_msecs_expire(&sw, 100); - - /* polling mode : see if transaction complete */ - while (1) { - status = read32(&regs->intr_stat); - if (status & I2C_HS_NACKERR) { - ret_code = I2C_TRANSFER_FAIL_HS_NACKERR; - I2CERR("[i2c%d transfer] transaction NACK error\n", - bus); - mtk_i2c_dump_info(bus); - break; - } else if (status & I2C_ACKERR) { - ret_code = I2C_TRANSFER_FAIL_ACKERR; - I2CERR("[i2c%d transfer] transaction ACK error\n", bus); - mtk_i2c_dump_info(bus); - break; - } else if (status & I2C_TRANSAC_COMP) { - ret_code = I2C_OK; - memcpy(read_buffer, _dma_coherent, read_len); - break; - } - - if (stopwatch_expired(&sw)) { - ret_code = I2C_TRANSFER_FAIL_TIMEOUT; - I2CERR("[i2c%d transfer] transaction timeout:%d\n", bus, - time_out_val); - mtk_i2c_dump_info(bus); - break; - } - } - - write32(&regs->intr_stat, I2C_TRANSAC_COMP | I2C_ACKERR | - I2C_HS_NACKERR); - - /* clear bit mask */ - write32(&regs->intr_mask, I2C_HS_NACKERR | I2C_ACKERR | - I2C_TRANSAC_COMP); - - /* reset the i2c controller for next i2c transfer. */ - write32(&regs->softreset, 0x1); - - i2c_dma_reset(dma_regs); - - return ret_code; -} - -static uint8_t mtk_i2c_should_combine(struct i2c_msg *seg, int left_count) -{ - if (left_count >= 2 && - !(seg[0].flags & I2C_M_RD) && - (seg[1].flags & I2C_M_RD) && - seg[0].slave == seg[1].slave) - return 1; - else - return 0; -} - -int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments, - int seg_count) -{ - int ret = 0; - int i; - int read; - - for (i = 0; i < seg_count; i++) { - if (mtk_i2c_should_combine(&segments[i], seg_count - i)) { - read = I2C_WRITE_READ_MODE; - } else { - read = (segments[i].flags & I2C_M_RD) ? - I2C_READ_MODE : I2C_WRITE_MODE; - } - - ret = mtk_i2c_transfer(bus, &segments[i], read); - - if (ret) - break; - - if (read == I2C_WRITE_READ_MODE) - i++; - } - - return ret; + write32(&mtk_i2c_bus_controller[bus].i2c_regs->timing, + (sample_div - 1) << 8 | (step_div - 1)); } diff --git a/src/soc/mediatek/mt8173/include/soc/i2c.h b/src/soc/mediatek/mt8173/include/soc/i2c.h old mode 100644 new mode 100755 index 5f46e9c..f2f9cf2 --- a/src/soc/mediatek/mt8173/include/soc/i2c.h +++ b/src/soc/mediatek/mt8173/include/soc/i2c.h @@ -16,47 +16,10 @@ #ifndef SOC_MEDIATEK_MT8173_I2C_H #define SOC_MEDIATEK_MT8173_I2C_H -#include <stddef.h> - -/* I2C Configuration */ -enum { - I2C_HS_DEFAULT_VALUE = 0x0102, -}; - -enum i2c_modes { - I2C_WRITE_MODE = 0, - I2C_READ_MODE = 1, - I2C_WRITE_READ_MODE = 2, -}; - -enum { - I2C_DMA_CON_TX = 0x0, - I2C_DMA_CON_RX = 0x1, - I2C_DMA_START_EN = 0x1, - I2C_DMA_INT_FLAG_NONE = 0x0, - I2C_DMA_CLR_FLAG = 0x0, - I2C_DMA_FLUSH_FLAG = 0x1, -}; - -/* I2C DMA Registers */ -struct mt8173_i2c_dma_regs { - uint32_t dma_int_flag; - uint32_t dma_int_en; - uint32_t dma_en; - uint32_t dma_rst; - uint32_t reserved1; - uint32_t dma_flush; - uint32_t dma_con; - uint32_t dma_tx_mem_addr; - uint32_t dma_rx_mem_addr; - uint32_t dma_tx_len; - uint32_t dma_rx_len; -}; - -check_member(mt8173_i2c_dma_regs, dma_tx_len, 0x24); +#include <soc/i2c_common.h> /* I2C Register */ -struct mt8173_i2c_regs { +struct mt_i2c_regs { uint32_t data_port; uint32_t slave_addr; uint32_t intr_mask; @@ -85,48 +48,8 @@ uint32_t transfer_aux_len; }; -check_member(mt8173_i2c_regs, debug_stat, 0x64); +check_member(mt_i2c_regs, debug_stat, 0x64); -struct mtk_i2c { - struct mt8173_i2c_regs *i2c_regs; - struct mt8173_i2c_dma_regs *i2c_dma_regs; -}; - -enum { - I2C_TRANS_LEN_MASK = (0xff), - I2C_TRANS_AUX_LEN_MASK = (0x1f << 8), - I2C_CONTROL_MASK = (0x3f << 1) -}; - -/* Register mask */ -enum { - I2C_HS_NACKERR = (1 << 2), - I2C_ACKERR = (1 << 1), - I2C_TRANSAC_COMP = (1 << 0), -}; - -/* i2c control bits */ -enum { - ACK_ERR_DET_EN = (1 << 5), - DIR_CHG = (1 << 4), - CLK_EXT = (1 << 3), - DMA_EN = (1 << 2), - REPEATED_START_FLAG = (1 << 1), - STOP_FLAG = (0 << 1) -}; - -/* I2C Status Code */ - -enum { - I2C_OK = 0x0000, - I2C_SET_SPEED_FAIL_OVER_SPEED = 0xA001, - I2C_TRANSFER_INVALID_LENGTH = 0xA002, - I2C_TRANSFER_FAIL_HS_NACKERR = 0xA003, - I2C_TRANSFER_FAIL_ACKERR = 0xA004, - I2C_TRANSFER_FAIL_TIMEOUT = 0xA005, - I2C_TRANSFER_INVALID_ARGUMENT = 0xA006 -}; - -void mtk_i2c_bus_init(uint8_t bus); +void mtk_i2c_init(uint8_t bus); #endif /* SOC_MEDIATEK_MT8173_I2C_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I407d5e2a9eb29562b40bb300e39f206a94afe76c Gerrit-Change-Number: 30975 Gerrit-PatchSet: 1 Gerrit-Owner: wang qii <Qii.Wang(a)mediatek.com> Gerrit-MessageType: newchange

7 29

Change in ...coreboot[master]: lb_tables: make lb_record_version_timestamp record sizes 64-bit aligned
by Xiang Wang (Code Review) 02 Aug '19

02 Aug '19

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31383 Change subject: lb_tables: make lb_record_version_timestamp record sizes 64-bit aligned ...................................................................... lb_tables: make lb_record_version_timestamp record sizes 64-bit aligned They were sized to 32-bit algnment, this grows them to 64 bit-aligned Change-Id: Id401ed7ac24d781329686cf0a339cf9e1ea15130 Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/lib/coreboot_table.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/31383/1 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index c2ae094..25d0afa 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -422,7 +422,7 @@ struct lb_timestamp *rec; rec = (struct lb_timestamp *)lb_new_record(header); rec->tag = LB_TAG_VERSION_TIMESTAMP; - rec->size = sizeof(*rec); + rec->size = ALIGN_UP(sizeof(*rec), 8); rec->timestamp = coreboot_version_timestamp; } -- To view, visit https://review.coreboot.org/c/coreboot/+/31383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id401ed7ac24d781329686cf0a339cf9e1ea15130 Gerrit-Change-Number: 31383 Gerrit-PatchSet: 1 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-MessageType: newchange

1 1

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2019