coreboot-gerrit April 2019

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Change in ...coreboot[master]: soc/amd/picasso: Change header guards from stoney to picasso
by Martin Roth (Code Review) 02 Jul '19

02 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32409 Change subject: soc/amd/picasso: Change header guards from stoney to picasso ...................................................................... soc/amd/picasso: Change header guards from stoney to picasso TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I32b7dbeae7538884311ccfc3a0e8db63c48fe356 --- M src/soc/amd/picasso/include/soc/acpi.h M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/include/soc/gpio.h M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/northbridge.h M src/soc/amd/picasso/include/soc/nvs.h M src/soc/amd/picasso/include/soc/pci_devs.h M src/soc/amd/picasso/include/soc/romstage.h M src/soc/amd/picasso/include/soc/smbus.h M src/soc/amd/picasso/include/soc/smi.h M src/soc/amd/picasso/include/soc/southbridge.h 11 files changed, 33 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/32409/1 diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 15a41ed..71fe10e 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -15,8 +15,8 @@ * GNU General Public License for more details. */ -#ifndef __SOC_STONEYRIDGE_ACPI_H__ -#define __SOC_STONEYRIDGE_ACPI_H__ +#ifndef __SOC_PICASSO_ACPI_H__ +#define __SOC_PICASSO_ACPI_H__ #include <arch/acpi.h> @@ -37,4 +37,4 @@ const char *soc_acpi_name(const struct device *dev); -#endif /* __SOC_STONEYRIDGE_ACPI_H__ */ +#endif /* __SOC_PICASSO_ACPI_H__ */ diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 934a9f2..d9d48ad 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef __STONEYRIDGE_CPU_H__ -#define __STONEYRIDGE_CPU_H__ +#ifndef __PICASSO_CPU_H__ +#define __PICASSO_CPU_H__ #include <device/device.h> @@ -32,4 +32,4 @@ void stoney_init_cpus(struct device *dev); void check_mca(void); -#endif /* __STONEYRIDGE_CPU_H__ */ +#endif /* __PICASSO_CPU_H__ */ diff --git a/src/soc/amd/picasso/include/soc/gpio.h b/src/soc/amd/picasso/include/soc/gpio.h index fe8240f..94d3eef 100644 --- a/src/soc/amd/picasso/include/soc/gpio.h +++ b/src/soc/amd/picasso/include/soc/gpio.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef __STONEYRIDGE_GPIO_H__ -#define __STONEYRIDGE_GPIO_H__ +#ifndef __PICASSO_GPIO_H__ +#define __PICASSO_GPIO_H__ #define GPIO_DEVICE_NAME "AMD0030" #define GPIO_DEVICE_DESC "GPIO Controller" @@ -605,4 +605,4 @@ int gpio_interrupt_status(gpio_t gpio); #endif /* __ACPI__ */ -#endif /* __STONEYRIDGE_GPIO_H__ */ +#endif /* __PICASSO_GPIO_H__ */ diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 613dd04..277a8fb 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#ifndef __SOC_STONEYRIDGE_IOMAP_H__ -#define __SOC_STONEYRIDGE_IOMAP_H__ +#ifndef __SOC_PICASSO_IOMAP_H__ +#define __SOC_PICASSO_IOMAP_H__ /* MMIO Ranges */ #define PSP_MAILBOX_BAR3_BASE 0xf0a00000 @@ -79,4 +79,4 @@ #define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ #define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ -#endif /* __SOC_STONEYRIDGE_IOMAP_H__ */ +#endif /* __SOC_PICASSO_IOMAP_H__ */ diff --git a/src/soc/amd/picasso/include/soc/northbridge.h b/src/soc/amd/picasso/include/soc/northbridge.h index 563dae0..8405e9c 100644 --- a/src/soc/amd/picasso/include/soc/northbridge.h +++ b/src/soc/amd/picasso/include/soc/northbridge.h @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__ -#define __PI_STONEYRIDGE_NORTHBRIDGE_H__ +#ifndef __PI_PICASSO_NORTHBRIDGE_H__ +#define __PI_PICASSO_NORTHBRIDGE_H__ #include <device/device.h> @@ -129,4 +129,4 @@ void set_warm_reset_flag(void); int is_warm_reset(void); -#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */ +#endif /* __PI_PICASSO_NORTHBRIDGE_H__ */ diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index 08d4697..8ce5da6 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -21,8 +21,8 @@ * */ -#ifndef __SOC_STONEYRIDGE_NVS_H__ -#define __SOC_STONEYRIDGE_NVS_H__ +#ifndef __SOC_PICASSO_NVS_H__ +#define __SOC_PICASSO_NVS_H__ #include <commonlib/helpers.h> #include <stdint.h> @@ -64,4 +64,4 @@ } __packed global_nvs_t; check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); -#endif /* __SOC_STONEYRIDGE_NVS_H__ */ +#endif /* __SOC_PICASSO_NVS_H__ */ diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 02fed7a..478a2cb 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef __PI_STONEYRIDGE_PCI_DEVS_H__ -#define __PI_STONEYRIDGE_PCI_DEVS_H__ +#ifndef __PI_PICASSO_PCI_DEVS_H__ +#define __PI_PICASSO_PCI_DEVS_H__ #include <device/pci_def.h> @@ -195,4 +195,4 @@ #define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) #define SOC_SD_DEV _SOC_DEV(SD_DEV, SD_FUNC) -#endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */ +#endif /* __PI_PICASSO_PCI_DEVS_H__ */ diff --git a/src/soc/amd/picasso/include/soc/romstage.h b/src/soc/amd/picasso/include/soc/romstage.h index 6ce79b4..d8b2900 100644 --- a/src/soc/amd/picasso/include/soc/romstage.h +++ b/src/soc/amd/picasso/include/soc/romstage.h @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ -#ifndef __STONEYRIDGE_ROMSTAGE_H__ -#define __STONEYRIDGE_ROMSTAGE_H__ +#ifndef __PICASSO_ROMSTAGE_H__ +#define __PICASSO_ROMSTAGE_H__ void mainboard_romstage_entry(int s3_resume); -#endif /* __STONEYRIDGE_ROMSTAGE_H__ */ +#endif /* __PICASSO_ROMSTAGE_H__ */ diff --git a/src/soc/amd/picasso/include/soc/smbus.h b/src/soc/amd/picasso/include/soc/smbus.h index 71f7faf..7b05610 100644 --- a/src/soc/amd/picasso/include/soc/smbus.h +++ b/src/soc/amd/picasso/include/soc/smbus.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef __STONEYRIDGE_SMBUS_H__ -#define __STONEYRIDGE_SMBUS_H__ +#ifndef __PICASSO_SMBUS_H__ +#define __PICASSO_SMBUS_H__ #include <stdint.h> #include <soc/iomap.h> @@ -55,4 +55,4 @@ void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val); -#endif /* __STONEYRIDGE_SMBUS_H__ */ +#endif /* __PICASSO_SMBUS_H__ */ diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index d22b8db..46c4a8c 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -15,8 +15,8 @@ * GNU General Public License for more details. */ -#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ -#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ +#ifndef __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ +#define __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ #define SMI_GEVENTS 24 @@ -238,4 +238,4 @@ void enable_smi_generation(void); #endif -#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */ +#endif /* __SOUTHBRIDGE_AMD_PI_PICASSO_SMI_H__ */ diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 9fa93c8..a6d144a 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#ifndef __STONEYRIDGE_H__ -#define __STONEYRIDGE_H__ +#ifndef __PICASSO_SB_H__ +#define __PICASSO_SB_H__ #include <types.h> #include <device/device.h> @@ -609,4 +609,4 @@ */ void set_pm1cnt_s5(void); -#endif /* __STONEYRIDGE_H__ */ +#endif /* __PICASSO_SB_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32409 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32b7dbeae7538884311ccfc3a0e8db63c48fe356 Gerrit-Change-Number: 32409 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/picasso: Remove files we're not using
by Martin Roth (Code Review) 02 Jul '19

02 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32408 Change subject: soc/amd/picasso: Remove files we're not using ...................................................................... soc/amd/picasso: Remove files we're not using Remove files that aren't needed for the picasso port. Picasso (and all AMD Zen processors) have a very different boot flow than the previous processors. The memory is initialized by the PSP before the X86 processor is released from reset. The SPD is read by the PSP, so it's not needed in coreboot. I discussed with AMD whether we could continue to let coreboot do the memory initialization instead of the PSP, but the ability to do Cache-as-RAM has been removed, so while it might be possible, it would have to be all written in ASM. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I743ffd6058982f8f182ea4d73172a029967f3ea5 --- D src/soc/amd/picasso/BiosCallOuts.c D src/soc/amd/picasso/enable_usbdebug.c M src/soc/amd/picasso/makefile.inc D src/soc/amd/picasso/nb_util.c D src/soc/amd/picasso/smbus_spd.c 5 files changed, 0 insertions(+), 334 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/32408/1 diff --git a/src/soc/amd/picasso/BiosCallOuts.c b/src/soc/amd/picasso/BiosCallOuts.c deleted file mode 100644 index 1027ae0..0000000 --- a/src/soc/amd/picasso/BiosCallOuts.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011, 2017 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * Copyright (C) 2017 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <device/pci_def.h> -#include <amdblocks/BiosCallOuts.h> -#include <soc/southbridge.h> -#include <soc/pci_devs.h> -#include <stdlib.h> - -#include <amdblocks/agesawrapper.h> -#include <amdblocks/dimm_spd.h> -#include "chip.h" -#include <amdblocks/car.h> - -void __weak platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset) {} - -AGESA_STATUS agesa_fch_initreset(uint32_t Func, uintptr_t FchData, - void *ConfigPtr) -{ - AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - - if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams_reset; - FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - - /* Get platform specific configuration changes */ - platform_FchParams_reset(FchParams_reset); - - printk(BIOS_DEBUG, "Done\n"); - } - - return AGESA_SUCCESS; -} - -AGESA_STATUS agesa_fch_initenv(uint32_t Func, uintptr_t FchData, - void *ConfigPtr) -{ - AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - const struct device *dev = pcidev_path_on_root(SATA_DEVFN); - - if (StdHeader->Func == AMD_INIT_ENV) { - FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - - /* XHCI configuration */ - if (CONFIG(STONEYRIDGE_XHCI_ENABLE)) - FchParams_env->Usb.Xhci0Enable = TRUE; - else - FchParams_env->Usb.Xhci0Enable = FALSE; - FchParams_env->Usb.Xhci1Enable = FALSE; - - /* SATA configuration */ - FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE; - if (dev && dev->enabled) { - switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) { - case SataRaid: - case SataAhci: - case SataAhci7804: - case SataLegacyIde: - FchParams_env->Sata.SataIdeMode = FALSE; - break; - case SataIde2Ahci: - case SataIde2Ahci7804: - default: /* SataNativeIde */ - FchParams_env->Sata.SataIdeMode = TRUE; - break; - } - } else - FchParams_env->Sata.SataIdeMode = FALSE; - - /* Platform updates */ - platform_FchParams_env(FchParams_env); - - printk(BIOS_DEBUG, "Done\n"); - } - - return AGESA_SUCCESS; -} - -AGESA_STATUS agesa_ReadSpd(uint32_t Func, uintptr_t Data, void *ConfigPtr) -{ - uint8_t spd_address; - int err; - DEVTREE_CONST struct device *dev; - DEVTREE_CONST struct soc_amd_stoneyridge_config *conf; - AGESA_READ_SPD_PARAMS *info = ConfigPtr; - - if (!ENV_ROMSTAGE) - return AGESA_UNSUPPORTED; - - dev = pcidev_path_on_root(DCT_DEVFN); - if (dev == NULL) - return AGESA_ERROR; - - conf = dev->chip_info; - if (conf == NULL) - return AGESA_ERROR; - - if (info->SocketId >= ARRAY_SIZE(conf->spd_addr_lookup)) - return AGESA_ERROR; - if (info->MemChannelId >= ARRAY_SIZE(conf->spd_addr_lookup[0])) - return AGESA_ERROR; - if (info->DimmId >= ARRAY_SIZE(conf->spd_addr_lookup[0][0])) - return AGESA_ERROR; - - spd_address = conf->spd_addr_lookup - [info->SocketId][info->MemChannelId][info->DimmId]; - if (spd_address == 0) - return AGESA_ERROR; - - err = mainboard_read_spd(spd_address, (void *)info->Buffer, - CONFIG_DIMM_SPD_SIZE); - - /* Read the SPD if the mainboard didn't fill the buffer */ - if (err || (*info->Buffer == 0)) - err = sb_read_spd(spd_address, (void *)info->Buffer, - CONFIG_DIMM_SPD_SIZE); - - if (err) - return AGESA_ERROR; - - return AGESA_SUCCESS; -} - -AGESA_STATUS agesa_HaltThisAp(uint32_t Func, uintptr_t Data, void *ConfigPtr) -{ - AGESA_HALT_THIS_AP_PARAMS *info = ConfigPtr; - uint32_t flags = 0; - - if (info->PrimaryCore == TRUE) - return AGESA_UNSUPPORTED; /* force normal path */ - if (info->ExecWbinvd == TRUE) - flags |= 1; - if (info->CacheEn == TRUE) - flags |= 2; - - ap_teardown_car(flags); /* does not return */ - - /* Should never reach here */ - return AGESA_UNSUPPORTED; -} - -/* Allow mainboards to fill the SPD buffer */ -__weak int mainboard_read_spd(uint8_t spdAddress, char *buf, - size_t len) -{ - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); - return -1; /* SPD not read */ -} diff --git a/src/soc/amd/picasso/enable_usbdebug.c b/src/soc/amd/picasso/enable_usbdebug.c deleted file mode 100644 index ce84a47..0000000 --- a/src/soc/amd/picasso/enable_usbdebug.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -// Use simple device model for this file even in ramstage -#define __SIMPLE_DEVICE__ - -#include <stdint.h> -#include <arch/io.h> -#include <device/pci_ops.h> -#include <device/pci_ehci.h> -#include <device/pci_def.h> -#include <soc/pci_devs.h> -#include <soc/southbridge.h> - -pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) -{ - /* Enable all of the USB controllers */ - outb(PM_USB_ENABLE, PM_INDEX); - outb(PM_USB_ALL_CONTROLLERS, PM_DATA); - - return SOC_EHCI1_DEV; -} - -void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) -{ - u32 reg32, value; - - value = (port & 0x3) << DEBUG_PORT_SELECT_SHIFT; - value |= DEBUG_PORT_ENABLE; - reg32 = pci_read_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4); - reg32 &= ~DEBUG_PORT_MASK; - reg32 |= value; - pci_write_config32(SOC_EHCI1_DEV, EHCI_HUB_CONFIG4, reg32); -} diff --git a/src/soc/amd/picasso/makefile.inc b/src/soc/amd/picasso/makefile.inc index 68dba09..cc8be37 100644 --- a/src/soc/amd/picasso/makefile.inc +++ b/src/soc/amd/picasso/makefile.inc @@ -38,7 +38,6 @@ subdirs-y += ../../../cpu/x86/smm bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c -bootblock-y += BiosCallOuts.c bootblock-y += bootblock/bootblock.c bootblock-y += gpio.c bootblock-y += i2c.c @@ -53,7 +52,6 @@ bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c -romstage-y += BiosCallOuts.c romstage-y += i2c.c romstage-y += romstage.c romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c @@ -68,7 +66,6 @@ romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c romstage-y += tsc_freq.c romstage-y += southbridge.c -romstage-y += nb_util.c romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c @@ -80,7 +77,6 @@ verstage-y += reset.c verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c verstage-y += tsc_freq.c -verstage-y += nb_util.c verstage-$(CONFIG_SPI_FLASH) += spi.c postcar-y += monotonic_timer.c @@ -91,12 +87,10 @@ postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c postcar-y += tsc_freq.c -ramstage-y += BiosCallOuts.c ramstage-y += i2c.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += mca.c -ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += gpio.c ramstage-y += hda.c @@ -119,7 +113,6 @@ ramstage-y += tsc_freq.c ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += finalize.c -ramstage-y += nb_util.c smm-y += monotonic_timer.c smm-y += smihandler.c @@ -128,7 +121,6 @@ smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c smm-$(CONFIG_SPI_FLASH) += spi.c -smm-y += nb_util.c smm-y += gpio.c CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge diff --git a/src/soc/amd/picasso/nb_util.c b/src/soc/amd/picasso/nb_util.c deleted file mode 100644 index d5de067..0000000 --- a/src/soc/amd/picasso/nb_util.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Advanced Micro Devices - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/northbridge.h> -#include <soc/pci_devs.h> -#include <device/pci_ops.h> - -uint32_t nb_ioapic_read(unsigned int index) -{ - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index); - return pci_read_config32(SOC_GNB_DEV, NB_IOAPIC_DATA); -} - -void nb_ioapic_write(unsigned int index, uint32_t value) -{ - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, index); - pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, value); -} - -void *get_ap_entry_ptr(void) -{ - return (void *)nb_ioapic_read(AP_SCRATCH_REG); -} - -void set_ap_entry_ptr(void *entry) -{ - nb_ioapic_write(AP_SCRATCH_REG, (uintptr_t)entry); -} diff --git a/src/soc/amd/picasso/smbus_spd.c b/src/soc/amd/picasso/smbus_spd.c deleted file mode 100644 index 63b457c..0000000 --- a/src/soc/amd/picasso/smbus_spd.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012, 2017 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <amdblocks/agesawrapper.h> -#include <device/pci_def.h> -#include <device/device.h> -#include <soc/southbridge.h> -#include <soc/smbus.h> -#include <amdblocks/dimm_spd.h> - -/* - * readspd - Read one or more SPD bytes from a DIMM. - * Start with offset zero and read sequentially. - * Optimization relies on autoincrement to avoid - * sending offset for every byte. - * Reads 128 bytes in 7-8 ms at 400 KHz. - */ -static int readspd(uint8_t SmbusSlaveAddress, char *buffer, size_t count) -{ - uint8_t dev_addr; - size_t index; - int error; - char *pbuf = buffer; - - printk(BIOS_SPEW, "-------------READING SPD-----------\n"); - printk(BIOS_SPEW, "SmbusSlave: 0x%08X, count: %zd\n", - SmbusSlaveAddress, count); - - /* - * Convert received device address to the format accepted by - * do_smbus_read_byte and do_smbus_recv_byte. - */ - dev_addr = (SmbusSlaveAddress >> 1); - - /* Read the first SPD byte */ - error = do_smbus_read_byte(SMBUS_MMIO_BASE, dev_addr, 0); - if (error < 0) { - printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); - return error; - } - *pbuf = (char) error; - pbuf++; - - /* Read the remaining SPD bytes using do_smbus_recv_byte for speed */ - for (index = 1 ; index < count ; index++) { - error = do_smbus_recv_byte(SMBUS_MMIO_BASE, dev_addr); - if (error < 0) { - printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n"); - return error; - } - *pbuf = (char) error; - pbuf++; - } - printk(BIOS_SPEW, "\n"); - printk(BIOS_SPEW, "-------------FINISHED READING SPD-----------\n"); - - return 0; -} - -int sb_read_spd(uint8_t spdAddress, char *buf, size_t len) -{ - return readspd(spdAddress, buf, len); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/32408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I743ffd6058982f8f182ea4d73172a029967f3ea5 Gerrit-Change-Number: 32408 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: soc/amd/picasso: Create picasso as a copy of stoneyridge
by Martin Roth (Code Review) 02 Jul '19

02 Jul '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32407 Change subject: soc/amd/picasso: Create picasso as a copy of stoneyridge ...................................................................... soc/amd/picasso: Create picasso as a copy of stoneyridge So that everyone can see what's being updated from stoney, we're starting with a direct copy of the stoney directory. There are arguments both for and against doing it this way, but I believe it's the most transparent Makefile.inc has been renamed as makefile.inc until it's updated. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b --- A src/soc/amd/picasso/BiosCallOuts.c A src/soc/amd/picasso/Kconfig A src/soc/amd/picasso/acpi.c A src/soc/amd/picasso/acpi/acpi_wake_source.asl A src/soc/amd/picasso/acpi/cpu.asl A src/soc/amd/picasso/acpi/globalnvs.asl A src/soc/amd/picasso/acpi/gpio_lib.asl A src/soc/amd/picasso/acpi/lpc.asl A src/soc/amd/picasso/acpi/northbridge.asl A src/soc/amd/picasso/acpi/pci_int.asl A src/soc/amd/picasso/acpi/pcie.asl A src/soc/amd/picasso/acpi/sb_fch.asl A src/soc/amd/picasso/acpi/sb_pci0_fch.asl A src/soc/amd/picasso/acpi/sleepstates.asl A src/soc/amd/picasso/acpi/soc.asl A src/soc/amd/picasso/acpi/usb.asl A src/soc/amd/picasso/bootblock/bootblock.c A src/soc/amd/picasso/chip.c A src/soc/amd/picasso/chip.h A src/soc/amd/picasso/cpu.c A src/soc/amd/picasso/enable_usbdebug.c A src/soc/amd/picasso/finalize.c A src/soc/amd/picasso/gpio.c A src/soc/amd/picasso/hda.c A src/soc/amd/picasso/i2c.c A src/soc/amd/picasso/include/soc/acpi.h A src/soc/amd/picasso/include/soc/amd_pci_int_defs.h A src/soc/amd/picasso/include/soc/cpu.h A src/soc/amd/picasso/include/soc/gpio.h A src/soc/amd/picasso/include/soc/iomap.h A src/soc/amd/picasso/include/soc/northbridge.h A src/soc/amd/picasso/include/soc/nvs.h A src/soc/amd/picasso/include/soc/pci_devs.h A src/soc/amd/picasso/include/soc/romstage.h A src/soc/amd/picasso/include/soc/smbus.h A src/soc/amd/picasso/include/soc/smi.h A src/soc/amd/picasso/include/soc/southbridge.h A src/soc/amd/picasso/iommu.c A src/soc/amd/picasso/lpc.c A src/soc/amd/picasso/makefile.inc A src/soc/amd/picasso/mca.c A src/soc/amd/picasso/monotonic_timer.c A src/soc/amd/picasso/nb_util.c A src/soc/amd/picasso/northbridge.c A src/soc/amd/picasso/pmutil.c A src/soc/amd/picasso/ramtop.c A src/soc/amd/picasso/reset.c A src/soc/amd/picasso/romstage.c A src/soc/amd/picasso/sata.c A src/soc/amd/picasso/sb_util.c A src/soc/amd/picasso/sm.c A src/soc/amd/picasso/smbus.c A src/soc/amd/picasso/smbus_spd.c A src/soc/amd/picasso/smi.c A src/soc/amd/picasso/smi_util.c A src/soc/amd/picasso/smihandler.c A src/soc/amd/picasso/southbridge.c A src/soc/amd/picasso/spi.c A src/soc/amd/picasso/tsc_freq.c A src/soc/amd/picasso/uart.c A src/soc/amd/picasso/usb.c 61 files changed, 11,242 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32407/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b Gerrit-Change-Number: 32407 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

10 37

Change in ...coreboot[master]: soc/intel/cannonlake: Set FSP-S Enable8254ClockGating using clock_gat...
by Jeremy Soller (Code Review) 01 Jul '19

01 Jul '19

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31534 Change subject: soc/intel/cannonlake: Set FSP-S Enable8254ClockGating using clock_gate_8254 devicetree parameter ...................................................................... soc/intel/cannonlake: Set FSP-S Enable8254ClockGating using clock_gate_8254 devicetree parameter Change-Id: Id346173ac7ae5246de0b38b9dd23be7b72e70f1e --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/31534/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index c276c86..534065f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -128,6 +128,10 @@ /* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; + /* Legacy 8254 timer support */ + params->Enable8254ClockGating = config->clock_gate_8254; + params->Enable8254ClockGatingOnS3 = config->clock_gate_8254; + /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); -- To view, visit https://review.coreboot.org/c/coreboot/+/31534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id346173ac7ae5246de0b38b9dd23be7b72e70f1e Gerrit-Change-Number: 31534 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jackpot51(a)gmail.com> Gerrit-MessageType: newchange

6 9

Change in ...coreboot[master]: soc/apl: Add devicetreee options for root ports
by Felix Singer (Code Review) 01 Jul '19

01 Jul '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32011 Change subject: soc/apl: Add devicetreee options for root ports ...................................................................... soc/apl: Add devicetreee options for root ports List of options: - PcieRpPmSci - PcieRpTransmitterHalfSwing - PcieRpLtrMaxSnoopLatency - PcieRpLtrMaxNonSnoopLatency - PcieRpAspm Change-Id: Ib08743f0bbf3bfaa935b153aaf161811eb148c6b Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/soc/intel/apollolake/chip.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/32011/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 30a537b..8b38895 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -695,6 +695,24 @@ memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable, sizeof(silconfig->PcieRpHotPlug)); + memcpy(silconfig->PcieRpPmSci, cfg->pcie_rp_pm_sci, + sizeof(silconfig->PcieRpPmSci)); + + memcpy(silconfig->PcieRpTransmitterHalfSwing, + cfg->pcie_rp_transmitter_halfswing, + sizeof(silconfig->PcieRpTransmitterHalfSwing)); + + memcpy(silconfig->PcieRpLtrMaxSnoopLatency, + cfg->pcie_rp_ltr_max_snoop_latency, + sizeof(silconfig->PcieRpLtrMaxSnoopLatency)); + + memcpy(silconfig->PcieRpLtrMaxNonSnoopLatency, + cfg->pcie_rp_ltr_max_snoop_latency, + sizeof(silconfig->PcieRpLtrMaxNonSnoopLatency)); + + memcpy(silconfig->PcieRpAspm, cfg->pcie_rp_aspm, + sizeof(silconfig->PcieRpAspm)); + switch (cfg->serirq_mode) { case SERIRQ_QUIET: silconfig->SirqEnable = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/32011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib08743f0bbf3bfaa935b153aaf161811eb148c6b Gerrit-Change-Number: 32011 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

1 4

Change in ...coreboot[master]: soc/apl: Add eMMC and Sdcard config options
by Felix Singer (Code Review) 01 Jul '19

01 Jul '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32049 Change subject: soc/apl: Add eMMC and Sdcard config options ...................................................................... soc/apl: Add eMMC and Sdcard config options Change-Id: I5e7df076d1e76358de5a899a3a44e8ca864882ba Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/32049/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 30a537b..3a405af 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -741,6 +741,9 @@ /* Disable FSP from locking access to the RTC NVRAM */ silconfig->RtcLock = 0; + silconfig->eMMCEnabled = cfg->emmc_enabled; + silconfig->SdcardEnabled = cfg->sdcard_enabled; + /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b9e368c..a995f2d 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -120,6 +120,9 @@ /* PL2 override value in mW for APL */ uint16_t tdp_pl2_override_mw; + uint8_t emmc_enabled; + uint8_t sdcard_enabled; + /* Configure Audio clk gate and power gate * IOSF-SB port ID 92 offset 0x530 [5] and [3] */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e7df076d1e76358de5a899a3a44e8ca864882ba Gerrit-Change-Number: 32049 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

2 5

Change in ...coreboot[master]: soc/apl: Add HdAudioDspUaaCompliance to devicetree
by Felix Singer (Code Review) 01 Jul '19

01 Jul '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32047 Change subject: soc/apl: Add HdAudioDspUaaCompliance to devicetree ...................................................................... soc/apl: Add HdAudioDspUaaCompliance to devicetree Change-Id: I1522ae81cba5fc08605f4eb349b2977facd3f669 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/32047/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 30a537b..5f83906 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -741,6 +741,8 @@ /* Disable FSP from locking access to the RTC NVRAM */ silconfig->RtcLock = 0; + silconfig->HdAudioDspUaaCompliance = cfg->hdaudio_dsp_uaa_compliance; + /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b9e368c..e3bcfe5 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -127,6 +127,8 @@ uint8_t hdaudio_pwr_gate_enable; uint8_t hdaudio_bios_config_lockdown; + uint8_t hdaudio_dsp_uaa_compliance; + /* SLP S3 minimum assertion width. */ int slp_s3_assertion_width_usecs; -- To view, visit https://review.coreboot.org/c/coreboot/+/32047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1522ae81cba5fc08605f4eb349b2977facd3f669 Gerrit-Change-Number: 32047 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

3 6

Change in ...coreboot[master]: soc/apl: Add C-States configuration options
by Felix Singer (Code Review) 01 Jul '19

01 Jul '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32050 Change subject: soc/apl: Add C-States configuration options ...................................................................... soc/apl: Add C-States configuration options FSP-S options: - C1e - PkgCStateLimit - CStateAutoDemotion - CStateUnDemotion - PkgCStateDemotion - PkgCStateUnDemotion Change-Id: I2ac16aa896fc851378cc049aaf385573e3a69320 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/32050/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 30a537b..15f2ba8 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -741,6 +741,13 @@ /* Disable FSP from locking access to the RTC NVRAM */ silconfig->RtcLock = 0; + silconfig->C1e = cfg->c1e; + silconfig->PkgCStateLimit = cfg->pkg_cstate_limit; + silconfig->CStateAutoDemotion = cfg->cstate_auto_demotion; + silconfig->CStateUnDemotion = cfg->cstate_undemotion; + silconfig->PkgCStateDemotion = cfg->pkg_cstate_demotion; + silconfig->PkgCStateUnDemotion = cfg->pkg_cstate_undemotion; + /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b9e368c..6015acf 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -120,6 +120,13 @@ /* PL2 override value in mW for APL */ uint16_t tdp_pl2_override_mw; + uint8_t c1e; + uint8_t pkg_cstate_limit; + uint8_t cstate_auto_demotion; + uint8_t cstate_undemotion; + uint8_t pkg_cstate_demotion; + uint8_t pkg_cstate_undemotion; + /* Configure Audio clk gate and power gate * IOSF-SB port ID 92 offset 0x530 [5] and [3] */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ac16aa896fc851378cc049aaf385573e3a69320 Gerrit-Change-Number: 32050 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: G505S AtomBIOS ROMs: known good binaries with a script to check their...
by mikeb mikeb (Code Review) 29 Jun '19

29 Jun '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31944 to review the following change. Change subject: G505S AtomBIOS ROMs: known good binaries with a script to check their SHA256 ...................................................................... G505S AtomBIOS ROMs: known good binaries with a script to check their SHA256 This change is a mirror for the known good AMD Lenovo G505S AtomBIOS ROMs from this repository - https://github.com/g505s-opensource-researcher/g505s-atombios AtomBIOS ROMs are required to enable the integrated and discrete VGA adapters, however to add the discrete GPU support you will also need to apply these patches: https://review.coreboot.org/c/coreboot/+/31929 G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches Here are the SHA256 checksums for these AtomBIOS ROMs: 6104e6989ea3f494d7bfa30573bf38e830f1068bab9980caec5e890e0ccbfced ./pci1002,990b.rom - for integrated GPU (iGPU) HD-8650G 6052b5def3fda2a93f6c4d55ec91b819429e212e26cdb8e0fcca54599c9c92ed ./pci1002,6663.rom - for discrete GPU (dGPU) HD-8570M 15d74515332bc512de66e0dc910d8600aeb134bf715bbc34a4faac0257f4a0dc ./pci1002,6665.rom - for discrete GPU (dGPU) R5-M230 Save to ./coreboot/ then run ./extract_atombios_roms.sh and ./check... . Could analyze these ROMs with AtomDis - https://cgit.freedesktop.org/~mhopf/AtomDis/ pci1002,990b.rom (for iGPU HD-8650G) has been taken from G505S with R5-M230, and despite the tiny voltage difference - it's working great for all G505S versions. https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/ GZNWISLFHUTYN6C7RTWSQUMJIFOUHMED/ Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I0cb38927e3f5ae0f0850ca8bc79be791c51ae503 --- A check_atombios_roms.sh A extract_atombios_roms.sh A pci1002,6663.rom.txt A pci1002,6665.rom.txt A pci1002,990b.rom.txt A sha256sums_atombios_correct.txt 6 files changed, 8,082 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/31944/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cb38927e3f5ae0f0850ca8bc79be791c51ae503 Gerrit-Change-Number: 31944 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: G505S dGPU support: scripts for applying the unofficial (not-merged-y...
by mikeb mikeb (Code Review) 29 Jun '19

29 Jun '19

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31929 to review the following change. Change subject: G505S dGPU support: scripts for applying the unofficial (not-merged-yet) updates ...................................................................... G505S dGPU support: scripts for applying the unofficial (not-merged-yet) updates These scripts will help you to securely and conveniently apply the three changes 31357, 31448, 31450 to add the discrete GPU support for AMD Lenovo G505S laptop. Save to ./coreboot/ then run ./get_dgpu_patches.sh , ./check... and ./apply... https://review.coreboot.org/c/coreboot/+/31357 src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware https://review.coreboot.org/c/coreboot/+/31448 src/device/pci: Add support for discrete VGA initialization and OpROM loading https://review.coreboot.org/c/coreboot/+/31450 lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I956f360681762b4321ba5d967f8a27b4a0387a73 --- A apply_dgpu_patches.sh A check_dgpu_patches.sh A get_dgpu_patches.sh A sha256sums_dgpu_correct.txt 4 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/31929/1 diff --git a/apply_dgpu_patches.sh b/apply_dgpu_patches.sh new file mode 100755 index 0000000..972800a --- /dev/null +++ b/apply_dgpu_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/31357 +### src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware +### +patch -p1 < f5c1e4d.diff +### +### https://review.coreboot.org/c/coreboot/+/31448 +### src/device/pci: Add support for discrete VGA initialization and OpROM loading +### +patch -p1 < 828c74a.diff +### +### https://review.coreboot.org/c/coreboot/+/31450 +### lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop +### +patch -p1 < 54dd729.diff diff --git a/check_dgpu_patches.sh b/check_dgpu_patches.sh new file mode 100755 index 0000000..cae1e9f --- /dev/null +++ b/check_dgpu_patches.sh @@ -0,0 +1,11 @@ +#!/bin/sh +rm -f ./sha256sums_dgpu_my.txt +sha256sum ./f5c1e4d.diff > ./sha256sums_dgpu_my.txt +sha256sum ./828c74a.diff >> ./sha256sums_dgpu_my.txt +sha256sum ./54dd729.diff >> ./sha256sums_dgpu_my.txt +if cmp -s "./sha256sums_dgpu_my.txt" "./sha256sums_dgpu_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_dgpu_patches.sh" +else + echo "! MISMATCH ! See ./sha256sums_dgpu_my.txt and ./sha256sums_dgpu_correct.txt" +fi diff --git a/get_dgpu_patches.sh b/get_dgpu_patches.sh new file mode 100755 index 0000000..c1703df --- /dev/null +++ b/get_dgpu_patches.sh @@ -0,0 +1,20 @@ +#!/bin/sh +rm -f ./*.diff && rm -f ./patch\?zip +### +### https://review.coreboot.org/c/coreboot/+/31357 +### src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware +### +wget https://review.coreboot.org/changes/31357/revisions/6/patch?zip +unzip ./patch\?zip && rm -f ./patch\?zip # && patch -p1 < f5c1e4d.diff +### +### https://review.coreboot.org/c/coreboot/+/31448 +### src/device/pci: Add support for discrete VGA initialization and OpROM loading +### +wget https://review.coreboot.org/changes/31448/revisions/8/patch?zip +unzip ./patch\?zip && rm -f ./patch\?zip # && patch -p1 < 828c74a.diff +### +### https://review.coreboot.org/c/coreboot/+/31450 +### lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop +### +wget https://review.coreboot.org/changes/31450/revisions/8/patch?zip +unzip ./patch\?zip && rm -f ./patch\?zip # && patch -p1 < 54dd729.diff diff --git a/sha256sums_dgpu_correct.txt b/sha256sums_dgpu_correct.txt new file mode 100644 index 0000000..b519a6a --- /dev/null +++ b/sha256sums_dgpu_correct.txt @@ -0,0 +1,3 @@ +1e6dff37ae1b8080c431f25b7a12c561bd949dfa68f6487a1bece39941f74195 ./f5c1e4d.diff +1879c633478c105eb9d66afa97fc59db0c850a813d4bcdb3693a6f52645092d8 ./828c74a.diff +a055e0d1fff668b95da68b7b6c7274d000bbf90572747b4f33de7f5f59a5bb44 ./54dd729.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/31929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I956f360681762b4321ba5d967f8a27b4a0387a73 Gerrit-Change-Number: 31929 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2019