coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: arch/x86/postcar: Configure MMU along with MTRRs
by Patrick Rudolph (Code Review) 01 Mar '19

01 Mar '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30501 ) Change subject: arch/x86/postcar: Configure MMU along with MTRRs ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/30501/3/src/arch/x86/postcar_loader.c File src/arch/x86/postcar_loader.c: https://review.coreboot.org/#/c/30501/3/src/arch/x86/postcar_loader.c@93 PS3, Line 93: */ > Ok.. I get the connection of PTE and MTRR now. […] The main problem I was seeing is that I don't know TOLM or TOM in a platform independent manner. It's possible to adjust the x86_64 pagetables at any time in ramstage and set different caching types. I'm going to update the comment and explain that those settings are not final nor perfect, but enough to have a basic 64bit ramstage. -- To view, visit https://review.coreboot.org/c/coreboot/+/30501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I235c70f05f63ed6d5146f093cf7f735879de4219 Gerrit-Change-Number: 30501 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 07:40:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86/mmu: Port armv8 MMU to x86_64
by Patrick Rudolph (Code Review) 01 Mar '19

01 Mar '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30119 ) Change subject: arch/x86/mmu: Port armv8 MMU to x86_64 ...................................................................... Patch Set 9: > Can you consolidate this with: src/cpu/x86/pae/pgtbl.c ? I didn't touch pae/pgtbl.c for the following reasons: * arch/x86/mmu.c generates long mode page tables, while pgtbl.c operates on 32bit/PAE page tables * arch/x86/mmu.c generates dynamic page tables, while pgtbl.c has static tables read from cbfs * arch/x86/mmu.c is intended for RAM environments, while pgtbl.c is for PRERAM environments * arch/x86/mmu.c is designed like the other arch/*/mmu.c I'm going to update the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/30119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992 Gerrit-Change-Number: 30119 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 07:34:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/braswell: Add support for FSP MR2
by Patrick Rudolph (Code Review) 01 Mar '19

01 Mar '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 ) Change subject: soc/intel/braswell: Add support for FSP MR2 ...................................................................... Patch Set 5: Instead of causing more mess by adding preprocessor directives, why not use 3rdparty/fsp for all non chrome devices and just keep the files in vendorcode/intel for the use by google. Then raise some awareness at google and intel that this issue with unknown UPDs should be fixed in MR3. -- To view, visit https://review.coreboot.org/c/coreboot/+/29661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Gerrit-Change-Number: 29661 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 07:27:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Set CPU boot up mode to turbo
by Lijian Zhao (Code Review) 01 Mar '19

01 Mar '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30446 Change subject: mb/google/sarien: Set CPU boot up mode to turbo ...................................................................... mb/google/sarien: Set CPU boot up mode to turbo Set CPU to be running at non-turbo maxium speed first and then switch to turbo maxium speed to accelerate boot performance. BUG=N/A TEST=Boot up with sarien platform, check with cbmem -t, boot time had been 110ms less. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I43bdb7ef82a5e6e147b3b506756c118dacdb0321 --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/30446/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 52840de..ce83d10 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -24,6 +24,7 @@ register "SkipExtGfxScan" = "1" register "VmxEnable" = "1" + register "bootfreq" = "2" register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 47abadc..98566f1 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -28,6 +28,7 @@ register "SkipExtGfxScan" = "1" register "VmxEnable" = "1" + register "bootfreq" = "2" register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/30446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43bdb7ef82a5e6e147b3b506756c118dacdb0321 Gerrit-Change-Number: 30446 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Add option for boot frquency
by Lijian Zhao (Code Review) 01 Mar '19

01 Mar '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30445 Change subject: soc/intel/cannonlake: Add option for boot frquency ...................................................................... soc/intel/cannonlake: Add option for boot frquency Cannonlake/Coffeelake FSP have options for CPU boot up frequency selection, expose that in coreboot side. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I6bd5849122c9035bb7f448acf08e258e8c207013 --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/30445/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 3a723d2..7e50a73 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -110,6 +110,11 @@ SaGv_Enabled, } SaGv; + /* Boot Frequency from reset vector. + * 0: Maximum battery performance, 1: Maximum non-turbo performance, 2: + * Maximum turbo performance @note If 2 is selected, system will start + * with non-turbo mode and then switch to turbo. */ + uint8_t bootfreq; /* Rank Margin Tool. 1:Enable, 0:Disable */ uint8_t RMT; diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index c3a2509..0514844 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -54,6 +54,8 @@ #if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE) m_cfg->SkipMpInit = !chip_get_fsp_mp_init(); #endif + m_cfg->BootFrequency = config->bootfreq; + /* If ISH is enabled, enable ISH elements */ if (!dev) m_cfg->PchIshEnable = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/30445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bd5849122c9035bb7f448acf08e258e8c207013 Gerrit-Change-Number: 30445 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/braswell: Add support for FSP MR2
by Frans Hendriks (Code Review) 01 Mar '19

01 Mar '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 ) Change subject: soc/intel/braswell: Add support for FSP MR2 ...................................................................... Patch Set 5: > Patch Set 5: > > > Why don't you use the 3rdparty/fsp repo instead, like done in https://review.coreboot.org/#/c/coreboot/+/30742/ ? > > IIRC, the original problem was that the current coreboot > source is incompatible with the upstream headers (because > UPDs were added that are unknown to Intel?). in drivers/intel/fsp1_1/fsp_util.c FSP_IMAGE_ID is checked against the ID in the FSP binary. There is a mismatch using MR2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Gerrit-Change-Number: 29661 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 07:18:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86/postcar: Configure MMU along with MTRRs
by Kyösti Mälkki (Code Review) 01 Mar '19

01 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30501 ) Change subject: arch/x86/postcar: Configure MMU along with MTRRs ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/30501/3/src/arch/x86/postcar_loader.c File src/arch/x86/postcar_loader.c: https://review.coreboot.org/#/c/30501/3/src/arch/x86/postcar_loader.c@93 PS3, Line 93: */ Ok.. I get the connection of PTE and MTRR now. I think you could just say that anything memory is WRBACK, from 0..TOLM and 4GiB..TOM. With MTRRs that cannot be easily done because of register alignment restrictions. Also the exact MTRR programming you see here gets discarded during ramstage. Anything WRBACK probably stays WRBACK, but some UC could (or should) be adjusted to WRCOMB after PCI enumeration. We might not currently make that WRCOMB setting, but any PCI MMIO with write-prefetch flag could gain some performance if we did. The UC tags from pagetables set here would void that. -- To view, visit https://review.coreboot.org/c/coreboot/+/30501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I235c70f05f63ed6d5146f093cf7f735879de4219 Gerrit-Change-Number: 30501 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 04:12:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86/mmu: Port armv8 MMU to x86_64
by Kyösti Mälkki (Code Review) 01 Mar '19

01 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30119 ) Change subject: arch/x86/mmu: Port armv8 MMU to x86_64 ...................................................................... Patch Set 9: Can you consolidate this with: src/cpu/x86/pae/pgtbl.c ? -- To view, visit https://review.coreboot.org/c/coreboot/+/30119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992 Gerrit-Change-Number: 30119 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 03:56:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/emulation/qemu-q35: Add x86_64 support
by Kyösti Mälkki (Code Review) 01 Mar '19

01 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29667 ) Change subject: mb/emulation/qemu-q35: Add x86_64 support ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/#/c/29667/15/src/mainboard/emulation/qemu-q35/r… File src/mainboard/emulation/qemu-q35/romstage.c: https://review.coreboot.org/#/c/29667/15/src/mainboard/emulation/qemu-q35/r… PS15, Line 48: * configure MTRRs here as on real hardware. I don't see the connection in requiring MTRRs to be setup to be able to use page-tables. -- To view, visit https://review.coreboot.org/c/coreboot/+/29667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 Gerrit-Change-Number: 29667 Gerrit-PatchSet: 15 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 03:50:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP]arch/x86/postcar: Add x86_64 support
by Kyösti Mälkki (Code Review) 01 Mar '19

01 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30500 ) Change subject: [WIP]arch/x86/postcar: Add x86_64 support ...................................................................... Patch Set 3: (10 comments) https://review.coreboot.org/#/c/30500/3/src/arch/x86/exit_car.S File src/arch/x86/exit_car.S: https://review.coreboot.org/#/c/30500/3/src/arch/x86/exit_car.S@27 PS3, Line 27: .quad 0 Is it u64 so just one quad? Or two long and no preprocessor here. https://review.coreboot.org/#/c/30500/3/src/arch/x86/exit_car.S@38 PS3, Line 38: #endif We are not consistent about this, perhaps .code without indent? https://review.coreboot.org/#/c/30500/3/src/arch/x86/exit_car.S@89 PS3, Line 89: and $(~0xf), %sp %rsp ? https://review.coreboot.org/#/c/30500/3/src/arch/x86/exit_car.S@110 PS3, Line 110: pop %rbx I don't know what our preference is about using GAS macros. Popping 64bit from stack to edx.eax would be good candidate here. I believe this entire change would reduce to having that macro defined differently (using that shr $32, %rax) on __x86_64__. https://review.coreboot.org/#/c/30500/3/src/arch/x86/exit_car.S@115 PS3, Line 115: mov $(MTRR_PHYS_BASE(0)), %rcx Why %rax instead of %eax here? Same for %ecx, %edx. https://review.coreboot.org/#/c/30500/3/src/arch/x86/exit_car.S@120 PS3, Line 120: inc %rcx %ecx ? https://review.coreboot.org/#/c/30500/3/src/arch/x86/exit_car.S@143 PS3, Line 143: dec %rbx %ecx %ebx https://review.coreboot.org/#/c/30500/3/src/arch/x86/exit_car.S@151 PS3, Line 151: or $(MTRR_DEF_TYPE_EN), %rax %eax and %ecx https://review.coreboot.org/#/c/30500/3/src/arch/x86/gdt_init.S File src/arch/x86/gdt_init.S: https://review.coreboot.org/#/c/30500/3/src/arch/x86/gdt_init.S@40 PS3, Line 40: .align 4 Is this enough for x86_64? https://review.coreboot.org/#/c/30500/3/src/arch/x86/gdt_init.S@42 PS3, Line 42: /* selgdt 0, unused */ Adding this is not x86_64 related change? -- To view, visit https://review.coreboot.org/c/coreboot/+/30500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Gerrit-Change-Number: 30500 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 03:46:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2019