Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 )
Change subject: soc/intel/braswell: Add support for FSP MR2
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Patch Set 5:
> Patch Set 5:
>
> > Why don't you use the 3rdparty/fsp repo instead, like done in https://review.coreboot.org/#/c/coreboot/+/30742/ ?
>
> IIRC, the original problem was that the current coreboot
> source is incompatible with the upstream headers (because
> UPDs were added that are unknown to Intel?).
in drivers/intel/fsp1_1/fsp_util.c FSP_IMAGE_ID is checked against the ID in the FSP binary. There is a mismatch using MR2
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30501 )
Change subject: arch/x86/postcar: Configure MMU along with MTRRs
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Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/30501/3/src/arch/x86/postcar_loader.c
File src/arch/x86/postcar_loader.c:
https://review.coreboot.org/#/c/30501/3/src/arch/x86/postcar_loader.c@93
PS3, Line 93: */
Ok.. I get the connection of PTE and MTRR now. I think you could just say that anything memory is WRBACK, from 0..TOLM and 4GiB..TOM. With MTRRs that cannot be easily done because of register alignment restrictions.
Also the exact MTRR programming you see here gets discarded during ramstage. Anything WRBACK probably stays WRBACK, but some UC could (or should) be adjusted to WRCOMB after PCI enumeration.
We might not currently make that WRCOMB setting, but any PCI MMIO with write-prefetch flag could gain some performance if we did. The UC tags from pagetables set here would void that.
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30119 )
Change subject: arch/x86/mmu: Port armv8 MMU to x86_64
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Patch Set 9:
Can you consolidate this with: src/cpu/x86/pae/pgtbl.c ?
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29667 )
Change subject: mb/emulation/qemu-q35: Add x86_64 support
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Patch Set 15:
(1 comment)
https://review.coreboot.org/#/c/29667/15/src/mainboard/emulation/qemu-q35/r…
File src/mainboard/emulation/qemu-q35/romstage.c:
https://review.coreboot.org/#/c/29667/15/src/mainboard/emulation/qemu-q35/r…
PS15, Line 48: * configure MTRRs here as on real hardware.
I don't see the connection in requiring MTRRs to be setup to be able to use page-tables.
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Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31665
Change subject: cpu/intel/model_1067x: Don't try to apply MCU a second time
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cpu/intel/model_1067x: Don't try to apply MCU a second time
Applying microcode updates a second time seems to be only necessary
on newer platforms (Nehalem+) for "uncore" updates.
Change-Id: Ia2ee9c70677190ffd1a08df1101d39a14fc2c384
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/cpu/intel/model_1067x/mp_init.c
1 file changed, 0 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/31665/1
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index b8b3159..4b67893 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -85,9 +85,6 @@
/* Relocate the SMM handler. */
smm_relocate();
-
- /* After SMM relocation a 2nd microcode load is required. */
- intel_microcode_load_unlocked(microcode_patch);
}
static void post_mp_init(void)
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