coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: soc/intel/braswell: Add support for FSP MR2
by Frans Hendriks (Code Review) 01 Mar '19

01 Mar '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 ) Change subject: soc/intel/braswell: Add support for FSP MR2 ...................................................................... Patch Set 5: > Patch Set 5: > > > Why don't you use the 3rdparty/fsp repo instead, like done in https://review.coreboot.org/#/c/coreboot/+/30742/ ? > > IIRC, the original problem was that the current coreboot > source is incompatible with the upstream headers (because > UPDs were added that are unknown to Intel?). in drivers/intel/fsp1_1/fsp_util.c FSP_IMAGE_ID is checked against the ID in the FSP binary. There is a mismatch using MR2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Gerrit-Change-Number: 29661 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 07:18:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86/postcar: Configure MMU along with MTRRs
by Kyösti Mälkki (Code Review) 01 Mar '19

01 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30501 ) Change subject: arch/x86/postcar: Configure MMU along with MTRRs ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/30501/3/src/arch/x86/postcar_loader.c File src/arch/x86/postcar_loader.c: https://review.coreboot.org/#/c/30501/3/src/arch/x86/postcar_loader.c@93 PS3, Line 93: */ Ok.. I get the connection of PTE and MTRR now. I think you could just say that anything memory is WRBACK, from 0..TOLM and 4GiB..TOM. With MTRRs that cannot be easily done because of register alignment restrictions. Also the exact MTRR programming you see here gets discarded during ramstage. Anything WRBACK probably stays WRBACK, but some UC could (or should) be adjusted to WRCOMB after PCI enumeration. We might not currently make that WRCOMB setting, but any PCI MMIO with write-prefetch flag could gain some performance if we did. The UC tags from pagetables set here would void that. -- To view, visit https://review.coreboot.org/c/coreboot/+/30501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I235c70f05f63ed6d5146f093cf7f735879de4219 Gerrit-Change-Number: 30501 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 04:12:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86/mmu: Port armv8 MMU to x86_64
by Kyösti Mälkki (Code Review) 01 Mar '19

01 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30119 ) Change subject: arch/x86/mmu: Port armv8 MMU to x86_64 ...................................................................... Patch Set 9: Can you consolidate this with: src/cpu/x86/pae/pgtbl.c ? -- To view, visit https://review.coreboot.org/c/coreboot/+/30119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992 Gerrit-Change-Number: 30119 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 03:56:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/emulation/qemu-q35: Add x86_64 support
by Kyösti Mälkki (Code Review) 01 Mar '19

01 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29667 ) Change subject: mb/emulation/qemu-q35: Add x86_64 support ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/#/c/29667/15/src/mainboard/emulation/qemu-q35/r… File src/mainboard/emulation/qemu-q35/romstage.c: https://review.coreboot.org/#/c/29667/15/src/mainboard/emulation/qemu-q35/r… PS15, Line 48: * configure MTRRs here as on real hardware. I don't see the connection in requiring MTRRs to be setup to be able to use page-tables. -- To view, visit https://review.coreboot.org/c/coreboot/+/29667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 Gerrit-Change-Number: 29667 Gerrit-PatchSet: 15 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 03:50:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP]arch/x86/postcar: Add x86_64 support
by Kyösti Mälkki (Code Review) 01 Mar '19

01 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30500 ) Change subject: [WIP]arch/x86/postcar: Add x86_64 support ...................................................................... Patch Set 3: (10 comments) https://review.coreboot.org/#/c/30500/3/src/arch/x86/exit_car.S File src/arch/x86/exit_car.S: https://review.coreboot.org/#/c/30500/3/src/arch/x86/exit_car.S@27 PS3, Line 27: .quad 0 Is it u64 so just one quad? Or two long and no preprocessor here. https://review.coreboot.org/#/c/30500/3/src/arch/x86/exit_car.S@38 PS3, Line 38: #endif We are not consistent about this, perhaps .code without indent? https://review.coreboot.org/#/c/30500/3/src/arch/x86/exit_car.S@89 PS3, Line 89: and $(~0xf), %sp %rsp ? https://review.coreboot.org/#/c/30500/3/src/arch/x86/exit_car.S@110 PS3, Line 110: pop %rbx I don't know what our preference is about using GAS macros. Popping 64bit from stack to edx.eax would be good candidate here. I believe this entire change would reduce to having that macro defined differently (using that shr $32, %rax) on __x86_64__. https://review.coreboot.org/#/c/30500/3/src/arch/x86/exit_car.S@115 PS3, Line 115: mov $(MTRR_PHYS_BASE(0)), %rcx Why %rax instead of %eax here? Same for %ecx, %edx. https://review.coreboot.org/#/c/30500/3/src/arch/x86/exit_car.S@120 PS3, Line 120: inc %rcx %ecx ? https://review.coreboot.org/#/c/30500/3/src/arch/x86/exit_car.S@143 PS3, Line 143: dec %rbx %ecx %ebx https://review.coreboot.org/#/c/30500/3/src/arch/x86/exit_car.S@151 PS3, Line 151: or $(MTRR_DEF_TYPE_EN), %rax %eax and %ecx https://review.coreboot.org/#/c/30500/3/src/arch/x86/gdt_init.S File src/arch/x86/gdt_init.S: https://review.coreboot.org/#/c/30500/3/src/arch/x86/gdt_init.S@40 PS3, Line 40: .align 4 Is this enough for x86_64? https://review.coreboot.org/#/c/30500/3/src/arch/x86/gdt_init.S@42 PS3, Line 42: /* selgdt 0, unused */ Adding this is not x86_64 related change? -- To view, visit https://review.coreboot.org/c/coreboot/+/30500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Gerrit-Change-Number: 30500 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 03:46:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel/model_1067x: Don't try to apply MCU a second time
by Nico Huber (Code Review) 01 Mar '19

01 Mar '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31665 Change subject: cpu/intel/model_1067x: Don't try to apply MCU a second time ...................................................................... cpu/intel/model_1067x: Don't try to apply MCU a second time Applying microcode updates a second time seems to be only necessary on newer platforms (Nehalem+) for "uncore" updates. Change-Id: Ia2ee9c70677190ffd1a08df1101d39a14fc2c384 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/cpu/intel/model_1067x/mp_init.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/31665/1 diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index b8b3159..4b67893 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -85,9 +85,6 @@ /* Relocate the SMM handler. */ smm_relocate(); - - /* After SMM relocation a 2nd microcode load is required. */ - intel_microcode_load_unlocked(microcode_patch); } static void post_mp_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/31665 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia2ee9c70677190ffd1a08df1101d39a14fc2c384 Gerrit-Change-Number: 31665 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: ALC3204 HDA verb table pin config change
by Joyce Toh (Code Review) 01 Mar '19

01 Mar '19

Joyce Toh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31624 Change subject: mb/google/sarien: ALC3204 HDA verb table pin config change ...................................................................... mb/google/sarien: ALC3204 HDA verb table pin config change On Sarien, change pin config of 0x19 (headset mic) and 0x21(headset headphone) to change jack location so that naming does not use "Front" in the name."Front Headphone" --> "Headphone" so it matches naming on Arcada. BUG=b:126334749 TEST= build coreboot with change and verify with 'evtest' command that jack name is "HDA Intel PCH Headphone" not "HDA Intel PCH Front Headphone". Change-Id: I36ccf0c0a3952ab363fe6ee313fac8f0cce4dd61 Signed-off-by: Joyce Toh <joyce.toh(a)intel.com> --- M src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/31624/1 diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h b/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h index 52ebb48..6eb6d14 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/hda_verb.h @@ -34,12 +34,12 @@ AZALIA_PIN_CFG(0x0, 0x13, 0x40000000), AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), - AZALIA_PIN_CFG(0x0, 0x19, 0x02a11030), + AZALIA_PIN_CFG(0x0, 0x19, 0x04a11030), AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), AZALIA_PIN_CFG(0x0, 0x1d, 0x40700001), AZALIA_PIN_CFG(0x0, 0x1e, 0x421212f2), - AZALIA_PIN_CFG(0x0, 0x21, 0x02211020), + AZALIA_PIN_CFG(0x0, 0x21, 0x04211020), /* ALC3204 default-1 */ 0x02050040, -- To view, visit https://review.coreboot.org/c/coreboot/+/31624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36ccf0c0a3952ab363fe6ee313fac8f0cce4dd61 Gerrit-Change-Number: 31624 Gerrit-PatchSet: 1 Gerrit-Owner: Joyce Toh <joyce.toh(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2019