coreboot-gerrit March 2019

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Change in ...coreboot[master]: src/arch/x86/acpi.c: Update ACPI table's revision numbers
by Patrick Georgi (Code Review) 01 Mar '19

01 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29579 ) Change subject: src/arch/x86/acpi.c: Update ACPI table's revision numbers ...................................................................... src/arch/x86/acpi.c: Update ACPI table's revision numbers Change-Id: I22020bd156536ee8f23a267d7c7b2d7af6c7cfeb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/29579 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/arch/x86/acpi.c 1 file changed, 9 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Richard Spiegel: Looks good to me, but someone else must approve diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 1872276..623a6df 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1394,7 +1394,7 @@ switch (table) { case FADT: return ACPI_FADT_REV_ACPI_3_0; - case MADT: /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */ + case MADT: /* ACPI 3.0: 2, ACPI 4.0/5.0: 3, ACPI 6.2b/6.3: 5 */ return 2; case MCFG: return 1; @@ -1402,29 +1402,29 @@ return 2; case TPM2: return 4; - case SSDT: /* ACPI 1.0/2.0: ?, ACPI 3.0/4.0: 2 */ + case SSDT: /* ACPI 3.0 upto 6.3: 2 */ return 2; - case SRAT: /* ACPI 1.0: N/A, 2.0: 1, 3.0: 2, 4.0: 3 */ + case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 upto 6.3: 3 */ return 1; /* TODO Should probably be upgraded to 2 */ case DMAR: return 1; - case SLIT: /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */ + case SLIT: /* ACPI 2.0 upto 6.3: 1 */ return 1; case HPET: /* Currently 1. Table added in ACPI 2.0. */ return 1; - case VFCT: /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */ + case VFCT: /* ACPI 2.0/3.0/4.0: 1 */ return 1; case IVRS: return IVRS_FORMAT_FIXED; case DBG2: return 0; - case FACS: /* ACPI 1.0: 0, ACPI 2.0/3.0: 1, ACPI 4.0: 2 */ + case FACS: /* ACPI 2.0/3.0: 1, ACPI 4.0 upto 6.3: 2 */ return 1; - case RSDT: /* ACPI 1.0/2.0/3.0/4.0: 1 */ + case RSDT: /* ACPI 1.0 upto 6.3: 1 */ return 1; - case XSDT: /* ACPI 1.0: N/A, 2.0/3.0/4.0: 1 */ + case XSDT: /* ACPI 2.0 upto 6.3: 1 */ return 1; - case RSDP: /* ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2. */ + case RSDP: /* ACPI 2.0 upto 6.3: 2 */ return 2; case HEST: return 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/29579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22020bd156536ee8f23a267d7c7b2d7af6c7cfeb Gerrit-Change-Number: 29579 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: ACPI: Rename FADT model and set it to zero
by Patrick Georgi (Code Review) 01 Mar '19

01 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29986 ) Change subject: ACPI: Rename FADT model and set it to zero ...................................................................... ACPI: Rename FADT model and set it to zero INT_MODEL defined in ACPI 1.0 and renamed to reserved since V 2.0. The value for this field is zero but 1 is allowed to maintain compatibility with ACPI 1.0. So set this value to zero as we are using greater version than ACPI 1.0. Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/29986 Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: David Guckian Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/include/arch/acpi.h M src/mainboard/aopen/dxplplusu/fadt.c M src/mainboard/emulation/qemu-q35/acpi_tables.c M src/mainboard/google/auron/fadt.c M src/mainboard/google/cyan/fadt.c M src/mainboard/google/jecht/fadt.c M src/mainboard/google/rambi/fadt.c M src/mainboard/intel/harcuvar/fadt.c M src/mainboard/intel/strago/fadt.c M src/mainboard/intel/wtm2/fadt.c M src/mainboard/lenovo/t400/fadt.c M src/mainboard/lenovo/x200/fadt.c M src/mainboard/purism/librem_bdw/fadt.c M src/mainboard/roda/rk9/fadt.c M src/mainboard/scaleway/tagada/fadt.c M src/soc/amd/stoneyridge/acpi.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/southbridge/amd/agesa/hudson/fadt.c M src/southbridge/amd/cimx/sb800/fadt.c M src/southbridge/amd/pi/hudson/fadt.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/fsp_rangeley/acpi.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c 26 files changed, 26 insertions(+), 26 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve David Guckian: Looks good to me, but someone else must approve diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index cc0f1a9..aced58a 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -484,7 +484,7 @@ struct acpi_table_header header; u32 firmware_ctrl; u32 dsdt; - u8 model; /* Eliminated in ACPI 2.0. Platforms should set + u8 reserved; /* Eliminated in ACPI 2.0. Platforms should set * this field to zero but field values of one * are also allowed to maintain compatibility * with ACPI 1.0. diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c index 299cac6..17f1a9d 100644 --- a/src/mainboard/aopen/dxplplusu/fadt.c +++ b/src/mainboard/aopen/dxplplusu/fadt.c @@ -46,7 +46,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = 0; /* PM_MOBILE; */ fadt->sci_int = 0x9; diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index b291936..e1eaa29 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -57,7 +57,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0x00; + fadt->reserved = 0x00; fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; fadt->smi_cmd = 0; diff --git a/src/mainboard/google/auron/fadt.c b/src/mainboard/google/auron/fadt.c index 038b79e..a24cf52 100644 --- a/src/mainboard/google/auron/fadt.c +++ b/src/mainboard/google/auron/fadt.c @@ -33,7 +33,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/google/cyan/fadt.c b/src/mainboard/google/cyan/fadt.c index 42568a4..2a54254 100644 --- a/src/mainboard/google/cyan/fadt.c +++ b/src/mainboard/google/cyan/fadt.c @@ -33,7 +33,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/google/jecht/fadt.c b/src/mainboard/google/jecht/fadt.c index 038b79e..a24cf52 100644 --- a/src/mainboard/google/jecht/fadt.c +++ b/src/mainboard/google/jecht/fadt.c @@ -33,7 +33,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/google/rambi/fadt.c b/src/mainboard/google/rambi/fadt.c index 7799c1e..9cccde6 100644 --- a/src/mainboard/google/rambi/fadt.c +++ b/src/mainboard/google/rambi/fadt.c @@ -32,7 +32,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/intel/harcuvar/fadt.c b/src/mainboard/intel/harcuvar/fadt.c index e33adde..d6c701a 100644 --- a/src/mainboard/intel/harcuvar/fadt.c +++ b/src/mainboard/intel/harcuvar/fadt.c @@ -23,6 +23,6 @@ void motherboard_fill_fadt(acpi_fadt_t *fadt) { - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; } diff --git a/src/mainboard/intel/strago/fadt.c b/src/mainboard/intel/strago/fadt.c index 6de2cfc..9814d1e 100644 --- a/src/mainboard/intel/strago/fadt.c +++ b/src/mainboard/intel/strago/fadt.c @@ -33,7 +33,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/intel/wtm2/fadt.c b/src/mainboard/intel/wtm2/fadt.c index 2dec7c7..a7c6536 100644 --- a/src/mainboard/intel/wtm2/fadt.c +++ b/src/mainboard/intel/wtm2/fadt.c @@ -32,7 +32,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (unsigned long)facs; diff --git a/src/mainboard/lenovo/t400/fadt.c b/src/mainboard/lenovo/t400/fadt.c index e361e8d..d22ffd9 100644 --- a/src/mainboard/lenovo/t400/fadt.c +++ b/src/mainboard/lenovo/t400/fadt.c @@ -36,7 +36,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0x00; + fadt->reserved = 0x00; fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; diff --git a/src/mainboard/lenovo/x200/fadt.c b/src/mainboard/lenovo/x200/fadt.c index e361e8d..d22ffd9 100644 --- a/src/mainboard/lenovo/x200/fadt.c +++ b/src/mainboard/lenovo/x200/fadt.c @@ -36,7 +36,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0x00; + fadt->reserved = 0x00; fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; diff --git a/src/mainboard/purism/librem_bdw/fadt.c b/src/mainboard/purism/librem_bdw/fadt.c index d4cf02e..5333701 100644 --- a/src/mainboard/purism/librem_bdw/fadt.c +++ b/src/mainboard/purism/librem_bdw/fadt.c @@ -32,7 +32,7 @@ fadt->firmware_ctrl = (u32)facs; fadt->dsdt = (u32)dsdt; - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_MOBILE; fadt->x_firmware_ctl_l = (u32)facs; diff --git a/src/mainboard/roda/rk9/fadt.c b/src/mainboard/roda/rk9/fadt.c index e361e8d..d22ffd9 100644 --- a/src/mainboard/roda/rk9/fadt.c +++ b/src/mainboard/roda/rk9/fadt.c @@ -36,7 +36,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0x00; + fadt->reserved = 0x00; fadt->preferred_pm_profile = PM_MOBILE; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; diff --git a/src/mainboard/scaleway/tagada/fadt.c b/src/mainboard/scaleway/tagada/fadt.c index 6259c2d..da25dec 100644 --- a/src/mainboard/scaleway/tagada/fadt.c +++ b/src/mainboard/scaleway/tagada/fadt.c @@ -24,6 +24,6 @@ void motherboard_fill_fadt(acpi_fadt_t *fadt) { - fadt->model = 1; + fadt->reserved = 0; fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; } diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index d6f9bb6..ccfd0fd 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -87,7 +87,7 @@ fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index ad32452..9d591fb 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -198,7 +198,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = config->fadt_pm_profile; /* unknown is default */ /* System Management */ diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index f7c572d..784e0cb 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -178,7 +178,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = 0; fadt->sci_int = acpi_sci_irq(); diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index 8a3f19f..230c89f 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -67,7 +67,7 @@ else fadt->dsdt = (uintptr_t)dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 5823813..5a5643f 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -71,7 +71,7 @@ else fadt->dsdt = (uintptr_t)dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON 1 - IRQ 09 - ACPI SCI */ fadt->smi_cmd = 0; /* disable system management mode */ diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 21c0930..075c577 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -59,7 +59,7 @@ fadt->firmware_ctrl = (u32) facs; fadt->dsdt = (u32) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = FADT_PM_PROFILE; fadt->sci_int = 9; /* HUDSON - IRQ 09 - ACPI SCI */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 4de4f16..de6b78c 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -745,7 +745,7 @@ u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; - fadt->model = 1; + fadt->reserved = 0; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c index 0aebb20..f88e999 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi.c +++ b/src/southbridge/intel/fsp_rangeley/acpi.c @@ -59,7 +59,7 @@ fadt->firmware_ctrl = (unsigned long) facs; fadt->dsdt = (unsigned long) dsdt; - fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ fadt->preferred_pm_profile = config->fadt_pm_profile; /* unknown is default */ /* System Management */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 7497c79..b71693a 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -572,7 +572,7 @@ fadt->mon_alrm = 0x00; fadt->century = 0x32; - fadt->model = 1; + fadt->reserved = 0; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index b06959a..6027d15 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -585,7 +585,7 @@ fadt->mon_alrm = 0x00; fadt->century = 0x32; - fadt->model = 1; + fadt->reserved = 0; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index a96b7ff..edbb57e 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -655,7 +655,7 @@ u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; - fadt->model = 1; + fadt->reserved = 0; fadt->sci_int = 0x9; fadt->smi_cmd = APM_CNT; -- To view, visit https://review.coreboot.org/c/coreboot/+/29986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a Gerrit-Change-Number: 29986 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: drivers/intel/fsp2_0: Add more EFI return status into FSP2.0 driver
by Patrick Georgi (Code Review) 01 Mar '19

01 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31647 ) Change subject: drivers/intel/fsp2_0: Add more EFI return status into FSP2.0 driver ...................................................................... drivers/intel/fsp2_0: Add more EFI return status into FSP2.0 driver This patch adds few more required EFI return status into FSP2.0 drivers so that coreboot code can make use of those. Change-Id: I9f040e7b9232b05dfc34971afa190cc3cbd7192a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/31647 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/drivers/intel/fsp2_0/include/fsp/api.h 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 5ed3801..b905b69 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -19,6 +19,11 @@ #include <soc/intel/common/mma.h> #define FSP_SUCCESS EFI_SUCCESS +#define FSP_INVALID_PARAMETER EFI_INVALID_PARAMETER +#define FSP_DEVICE_ERROR EFI_DEVICE_ERROR +#define FSP_NOT_FOUND EFI_NOT_FOUND +#define FSP_NOT_STARTED EFI_NOT_STARTED +#define FSP_UNSUPPORTED EFI_UNSUPPORTED enum fsp_boot_mode { FSP_BOOT_WITH_FULL_CONFIGURATION = 0x00, -- To view, visit https://review.coreboot.org/c/coreboot/+/31647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f040e7b9232b05dfc34971afa190cc3cbd7192a Gerrit-Change-Number: 31647 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/siemens/mc_bdx1: Enable TPM2 on LPC
by Werner Zeh (Code Review) 01 Mar '19

01 Mar '19

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31663 Change subject: mb/siemens/mc_bdx1: Enable TPM2 on LPC ...................................................................... mb/siemens/mc_bdx1: Enable TPM2 on LPC This mainboard has a TPM located on the LPC bus. Enable the driver for it so that it is initialized and the ACPI table entry is generated. Change-Id: I2eae63932658c2a9f752d28d7c08c27f48531360 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_bdx1/Kconfig M src/mainboard/siemens/mc_bdx1/devicetree.cb 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/31663/1 diff --git a/src/mainboard/siemens/mc_bdx1/Kconfig b/src/mainboard/siemens/mc_bdx1/Kconfig index 667a6ee..d99fea8 100644 --- a/src/mainboard/siemens/mc_bdx1/Kconfig +++ b/src/mainboard/siemens/mc_bdx1/Kconfig @@ -14,6 +14,8 @@ select DRIVER_SIEMENS_NC_FPGA select DRIVERS_I2C_RX6110SA select DRIVERS_I2C_PCA9538 + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_LPC_TPM config MAINBOARD_DIR string diff --git a/src/mainboard/siemens/mc_bdx1/devicetree.cb b/src/mainboard/siemens/mc_bdx1/devicetree.cb index 6b5c118..fd7d83f 100644 --- a/src/mainboard/siemens/mc_bdx1/devicetree.cb +++ b/src/mainboard/siemens/mc_bdx1/devicetree.cb @@ -7,7 +7,11 @@ device pci 14.0 on end # xHCI Controller device pci 19.0 on end # Gigabit LAN Controller device pci 1d.0 on end # EHCI Controller - device pci 1f.0 on end # LPC Bridge + device pci 1f.0 on # LPC Bridge + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 on # Enable external RTC chip -- To view, visit https://review.coreboot.org/c/coreboot/+/31663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2eae63932658c2a9f752d28d7c08c27f48531360 Gerrit-Change-Number: 31663 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: doc/util: Improve cbmem utility description
by Kyösti Mälkki (Code Review) 01 Mar '19

01 Mar '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31653 Change subject: doc/util: Improve cbmem utility description ...................................................................... doc/util: Improve cbmem utility description Change-Id: Ieddcf100d8db25f3ae9ac182cd374918e38d4f4c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M Documentation/util.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/31653/1 diff --git a/Documentation/util.md b/Documentation/util.md index f8fabc1..8f252c4 100644 --- a/Documentation/util.md +++ b/Documentation/util.md @@ -26,7 +26,7 @@ * _fmaptool_ - Converts plaintext fmd files into fmap blobs `C` * _rmodtool_ - Creates rmodules `C` * _ifwitool_ - For manipulating IFWI `C` -* __cbmem__ - Cbmem console log reader `C` +* __cbmem__ - CBMEM parser to read e.g. timestamps and console log `C` * __checklist__ - Board implementation checklist generator `Make` * __chromeos__ - These scripts can be used to extract System Agent reference code and other blobs (e.g. mrc.bin, refcode, VGA option roms) -- To view, visit https://review.coreboot.org/c/coreboot/+/31653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieddcf100d8db25f3ae9ac182cd374918e38d4f4c Gerrit-Change-Number: 31653 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/braswell: Add support for FSP MR2
by Nico Huber (Code Review) 01 Mar '19

01 Mar '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 ) Change subject: soc/intel/braswell: Add support for FSP MR2 ...................................................................... Patch Set 5: >> Usage of 'old non MR2 fields should be moved to 'Braswell' mainboards. > > but the current header is newer than MR2 (1.1.7.0 v 1.1.4.1). and since all existing boards compile with it, seems like MR2 should be the special case/exception requiring manual selection Um, how about always selecting the respective case: select SOC_INTEL_BRASWELL__BSWFSP_ or select SOC_INTEL_BRASWELL_BSWSBFSP I've also opened a ticket https://github.com/IntelFsp/FSP/issues/14 We should at least ask for an update, shouldn't we :) -- To view, visit https://review.coreboot.org/c/coreboot/+/29661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Gerrit-Change-Number: 29661 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 09:47:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86/postcar: Configure MMU along with MTRRs
by Kyösti Mälkki (Code Review) 01 Mar '19

01 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30501 ) Change subject: arch/x86/postcar: Configure MMU along with MTRRs ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/30501/3/src/arch/x86/postcar_loader.c File src/arch/x86/postcar_loader.c: https://review.coreboot.org/#/c/30501/3/src/arch/x86/postcar_loader.c@93 PS3, Line 93: */ > The main problem I was seeing is that I don't know TOLM or TOM in a platform independent manner. […] Sounds like it's time to invent common API for TOM and TOLM query then? The point was, I would rather see any MTRR code if at all possible, and sounds like compulsory pagetable enablement would do it. Better get some other opinions on this though. -- To view, visit https://review.coreboot.org/c/coreboot/+/30501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I235c70f05f63ed6d5146f093cf7f735879de4219 Gerrit-Change-Number: 30501 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 09:42:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/braswell: Add support for FSP MR2
by Frans Hendriks (Code Review) 01 Mar '19

01 Mar '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 ) Change subject: soc/intel/braswell: Add support for FSP MR2 ...................................................................... Patch Set 5: > Patch Set 5: > > > Usage of 'old non MR2 fields should be moved to 'Braswell' mainboards. > > but the current header is newer than MR2 (1.1.7.0 v 1.1.4.1). and since all existing boards compile with it, seems like MR2 should be the special case/exception requiring manual selection Are you sure existing boards use use 3rdparty FspUpdVpd.h? I tested with 3rdparty FspUpdVpd.h and this causes build errors on USB and I2C fields in braswell/chip.c. MR1 has version 1.1.7.0, MR2 1.1.4.1. -- To view, visit https://review.coreboot.org/c/coreboot/+/29661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Gerrit-Change-Number: 29661 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 09:40:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/braswell: Add support for FSP MR2
by Matt DeVillier (Code Review) 01 Mar '19

01 Mar '19

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 ) Change subject: soc/intel/braswell: Add support for FSP MR2 ...................................................................... Patch Set 5: > Usage of 'old non MR2 fields should be moved to 'Braswell' mainboards. but the current header is newer than MR2 (1.1.7.0 v 1.1.4.1). and since all existing boards compile with it, seems like MR2 should be the special case/exception requiring manual selection -- To view, visit https://review.coreboot.org/c/coreboot/+/29661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Gerrit-Change-Number: 29661 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 09:33:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP]arch/x86/postcar: Add x86_64 support
by Kyösti Mälkki (Code Review) 01 Mar '19

01 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30500 ) Change subject: [WIP]arch/x86/postcar: Add x86_64 support ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/30500/3/src/arch/x86/gdt_init.S File src/arch/x86/gdt_init.S: https://review.coreboot.org/#/c/30500/3/src/arch/x86/gdt_init.S@42 PS3, Line 42: /* selgdt 0, unused */ > It is, as gdt moved the struct at gdtptr can no longer be used as dummy. […] Well.. removal of the hack happens regardless of x86_64 and can be done separately. -- To view, visit https://review.coreboot.org/c/coreboot/+/30500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Gerrit-Change-Number: 30500 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 09:32:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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