Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 )
Change subject: soc/intel/braswell: Add support for FSP MR2
......................................................................
Patch Set 5:
> Different possibles to implement:
> 1. this patch, use CONFIG value to select MR1 or MR2.
> 2. Add MR2 ID and version ID. Modify find_fs() to support 2 FSP IDs.
> 3. Use 3rdparty include file. Usage of 'old non MR2 fields should be moved to 'Braswell' mainboards.
>
> Sounds like implementing solution 3?
I would prefer that too. A mainboard that needs the
additional fields would have to override the include
path, though, to compile in the default config.
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29394 )
Change subject: {src/include},{soc/intel): Configure HDA codecs
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Patch Set 13: Code-Review+2
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29394 )
Change subject: {src/include},{soc/intel): Configure HDA codecs
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Patch Set 13: Code-Review+1
This looks like a much cleaner solution than the earlier patchsets
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 )
Change subject: soc/intel/braswell: Add support for FSP MR2
......................................................................
Patch Set 5:
(1 comment)
> Patch Set 5:
>
> > why not use 3rdparty/fsp for all non chrome devices and just keep the files in vendorcode/intel for the use by google.
>
> that sounds like the ideal solution to me
Different possibles to implement:
1. this patch, use CONFIG value to select MR1 or MR2.
2. Add MR2 ID and version ID. Modify find_fs() to support 2 FSP IDs.
3. Use 3rdparty include file. Usage of 'old non MR2 fields should be moved to 'Braswell' mainboards.
Sounds like implementing solution 3?
https://review.coreboot.org/#/c/29661/5/src/vendorcode/intel/fsp/fsp1_1/bra…
File src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h:
https://review.coreboot.org/#/c/29661/5/src/vendorcode/intel/fsp/fsp1_1/bra…
PS5, Line 566: /** Offset 0x02FE
> this change is unguarded - is the currently listed offset incorrect for both MR2 and Google FSP?
Yes. Just correction of the comment.
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29683 )
Change subject: Revert "soc/intel/common/block: add VMX support"
......................................................................
Patch Set 4:
> I might have seen something on Gerrit that would collide with this.
CB:31442 maybe? but looks like it's going to be redone. Might as well give a gentle nudge by forcing a rebase ;-)
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 )
Change subject: soc/intel/braswell: Add support for FSP MR2
......................................................................
Patch Set 5:
> why not use 3rdparty/fsp for all non chrome devices and just keep the files in vendorcode/intel for the use by google.
that sounds like the ideal solution to me
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Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31666 )
Change subject: soc/intel/cannonlake: Fix DSDT compile remarks
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Set Ready For Review
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30500 )
Change subject: [WIP]arch/x86/postcar: Add x86_64 support
......................................................................
Patch Set 3:
(2 comments)
Do you think it's worth splitting x86_32 and x86_64 into separate files ?
https://review.coreboot.org/#/c/30500/3/src/arch/x86/gdt_init.S
File src/arch/x86/gdt_init.S:
https://review.coreboot.org/#/c/30500/3/src/arch/x86/gdt_init.S@40
PS3, Line 40: .align 4
> Is this enough for x86_64?
It's the same align as it was for x86_32.
https://review.coreboot.org/#/c/30500/3/src/arch/x86/gdt_init.S@42
PS3, Line 42: /* selgdt 0, unused */
> Adding this is not x86_64 related change?
It is, as gdt moved the struct at gdtptr can no longer be used as dummy. It was a hack to save some memory on x86.
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Change subject: rmodule: Don't emit reloc for R_X86_64_PC64
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Patch Set 2: Code-Review+2
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