coreboot-gerrit March 2019

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Change in ...coreboot[master]: soc/intel/braswell: Configure IO APIC
by Michał Żygowski (Code Review) 01 Mar '19

01 Mar '19

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29423 ) Change subject: soc/intel/braswell: Configure IO APIC ...................................................................... Patch Set 6: The change needs a rebase -- To view, visit https://review.coreboot.org/c/coreboot/+/29423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d Gerrit-Change-Number: 29423 Gerrit-PatchSet: 6 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 11:21:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/braswell/southcluster.c: Correct serial IRQ support
by Michał Żygowski (Code Review) 01 Mar '19

01 Mar '19

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29398 ) Change subject: src/soc/intel/braswell/southcluster.c: Correct serial IRQ support ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/29398/5/src/soc/intel/braswell/Kconfig File src/soc/intel/braswell/Kconfig: https://review.coreboot.org/#/c/29398/5/src/soc/intel/braswell/Kconfig@137 PS5, Line 137: : config ENABLE_SERIRQ : bool "Enable Serial IRQ" : default n : help : Enable Serial IRQ : : config SERIRQ_CONTINUOUS_MODE : bool "Serial IRQ continuous mode" : default n : depends on ENABLE_SERIRQ : help : Enable Serial IRQ continuous mode > In 'old' code base it was disabled, so to avoid causing problems when SERIRQ becomes enabled this fe […] I do not see any board which enables or sets SERIRQ mode in Kconfig menu. Probably it would be better to make these options hidden and be selected per mainboard in mainboard specific options. -- To view, visit https://review.coreboot.org/c/coreboot/+/29398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7844cad69dc0563fa6109d779d0afb7c2edd7245 Gerrit-Change-Number: 29398 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Fri, 01 Mar 2019 11:20:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Frans Hendriks <fhendriks(a)eltan.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/braswell/cpu.c: Set up local APIC
by Michał Żygowski (Code Review) 01 Mar '19

01 Mar '19

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29290 ) Change subject: src/soc/intel/braswell/cpu.c: Set up local APIC ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1da5b1bf235f34b957142e86c70a9dbfa3ded1d Gerrit-Change-Number: 29290 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 11:17:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Fix DSDT compile remarks
by Subrata Banik (Code Review) 01 Mar '19

01 Mar '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31666 ) Change subject: soc/intel/cannonlake: Fix DSDT compile remarks ...................................................................... Patch Set 2: > > Any idea, why these were added in the first place? > > If I'm not wrong, IASL detection of extraneous/redundant uses of > the Offset() was added in version 20180927 yes agree -- To view, visit https://review.coreboot.org/c/coreboot/+/31666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad660347b32d90ac1176654820375e30a21b5ffe Gerrit-Change-Number: 31666 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 10:47:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86/mmu: Port armv8 MMU to x86_64
by Paul Menzel (Code Review) 01 Mar '19

01 Mar '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30119 ) Change subject: arch/x86/mmu: Port armv8 MMU to x86_64 ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/#/c/30119/9//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/30119/9//COMMIT_MSG@9 PS9, Line 9: setup set up -- To view, visit https://review.coreboot.org/c/coreboot/+/30119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992 Gerrit-Change-Number: 30119 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 10:47:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: rmodule: Don't emit reloc for R_X86_64_PC64
by Paul Menzel (Code Review) 01 Mar '19

01 Mar '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31469 ) Change subject: rmodule: Don't emit reloc for R_X86_64_PC64 ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/31469/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/31469/2//COMMIT_MSG@9 PS2, Line 9: must not emitted must not be … -- To view, visit https://review.coreboot.org/c/coreboot/+/31469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife472a287ff15b1c04a516e25ff13221441fd122 Gerrit-Change-Number: 31469 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sol Boucher <solb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 10:46:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Fix DSDT compile remarks
by HAOUAS Elyes (Code Review) 01 Mar '19

01 Mar '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31666 ) Change subject: soc/intel/cannonlake: Fix DSDT compile remarks ...................................................................... Patch Set 2: > Any idea, why these were added in the first place? If I'm not wrong, IASL detection of extraneous/redundant uses of the Offset() was added in version 20180927 -- To view, visit https://review.coreboot.org/c/coreboot/+/31666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad660347b32d90ac1176654820375e30a21b5ffe Gerrit-Change-Number: 31666 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 10:46:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Fix DSDT compile remarks
by Paul Menzel (Code Review) 01 Mar '19

01 Mar '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31666 ) Change subject: soc/intel/cannonlake: Fix DSDT compile remarks ...................................................................... Patch Set 2: Any idea, why these were added in the first place? -- To view, visit https://review.coreboot.org/c/coreboot/+/31666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad660347b32d90ac1176654820375e30a21b5ffe Gerrit-Change-Number: 31666 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 01 Mar 2019 10:38:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/skylake: Unify serial IRQ options
by Nico Huber (Code Review) 01 Mar '19

01 Mar '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31596 Change subject: soc/intel/skylake: Unify serial IRQ options ...................................................................... soc/intel/skylake: Unify serial IRQ options We had two ways to configure the serial IRQ mode. One time in the devicetree for FSP and one time through Kconfig for coreboot. We'll use `enum serirq_mode` from soc/intel/common/ as a devicetree option instead. As the default is `quiet mode` here and that is the most common mode, this saves us a lot of lines. In two cases KBLRVP8 and 11, we had conflicting settings in devicetree and Kconfig. We'll maintain the devicetree state, although it might be that coreboot overrode this earlier. Note: A lot of Google boards have serial IRQ enabled, while the pin seems to be unconnected? Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/variants/asuka/devicetree.cb M src/mainboard/google/glados/variants/caroline/devicetree.cb M src/mainboard/google/glados/variants/cave/devicetree.cb M src/mainboard/google/glados/variants/chell/devicetree.cb M src/mainboard/google/glados/variants/glados/devicetree.cb M src/mainboard/google/glados/variants/lars/devicetree.cb M src/mainboard/google/glados/variants/sentry/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/Kconfig M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb M src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/lpc.c 29 files changed, 16 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/31596/1 diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 66c1c53..2f275ac 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -46,7 +46,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 07a453d..bfabe29 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -81,7 +81,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb index d365e8f..e0a792d 100644 --- a/src/mainboard/google/glados/variants/asuka/devicetree.cb +++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb @@ -38,7 +38,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "4" # 4s register "PmConfigSlpSusMinAssert" = "3" # 4s diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb index cffb6df..0f5a911 100644 --- a/src/mainboard/google/glados/variants/caroline/devicetree.cb +++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb @@ -48,7 +48,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb index e0c7fc7..a9b28a8 100644 --- a/src/mainboard/google/glados/variants/cave/devicetree.cb +++ b/src/mainboard/google/glados/variants/cave/devicetree.cb @@ -48,7 +48,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/glados/variants/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb index 1b87cca..07467b3 100644 --- a/src/mainboard/google/glados/variants/chell/devicetree.cb +++ b/src/mainboard/google/glados/variants/chell/devicetree.cb @@ -48,7 +48,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/glados/variants/glados/devicetree.cb b/src/mainboard/google/glados/variants/glados/devicetree.cb index f4e09a6..d4266cc 100644 --- a/src/mainboard/google/glados/variants/glados/devicetree.cb +++ b/src/mainboard/google/glados/variants/glados/devicetree.cb @@ -48,7 +48,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb index 56087ad..f3f5eab 100644 --- a/src/mainboard/google/glados/variants/lars/devicetree.cb +++ b/src/mainboard/google/glados/variants/lars/devicetree.cb @@ -36,7 +36,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "4" # 4s register "PmConfigSlpSusMinAssert" = "3" # 4s diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb index 0effbd7..5cce0f0 100644 --- a/src/mainboard/google/glados/variants/sentry/devicetree.cb +++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb @@ -38,7 +38,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "4" # 4s register "PmConfigSlpSusMinAssert" = "3" # 4s diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 5b49884..407c37d 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -54,7 +54,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 251cab8..7335c0a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -51,7 +51,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 5d9c096..59cca29 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -50,7 +50,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 75a01c2..fed85b6 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -51,7 +51,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 4d9403c..ac52208 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -56,7 +56,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index c8e4008..4f58f40 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -54,7 +54,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 4713a81..d813cc1 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -51,7 +51,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "1" # 500ms diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index 51399dc..fcd5aab 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -54,8 +54,6 @@ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s register "PmConfigSlpAMinAssert" = "0x03" - # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled - register "SerialIrqConfigSirqEnable" = "0x01" # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 119767f..436a4ed 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -11,7 +11,7 @@ register "Heci3Enabled" = "0" register "PmTimerDisabled" = "0" - register "SerialIrqConfigSirqMode" = "0x01" + register "serirq_mode" = "SERIRQ_CONTINUOUS" # Enable PCIE slot register "PcieRpEnable[5]" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 9753c64..8dbaf68 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -10,7 +10,8 @@ register "ScsSdCardEnabled" = "0" register "HeciEnabled" = "0" register "PmTimerDisabled" = "0" - register "SerialIrqConfigSirqMode" = "0x01" + + register "serirq_mode" = "SERIRQ_CONTINUOUS" # VR Settings Configuration for 5 Domains #+----------------+-------+-------+-------------+-------------+-------+ diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 4b720bf..ec1c11f 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -60,8 +60,6 @@ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s register "PmConfigSlpAMinAssert" = "0x03" - # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled - register "SerialIrqConfigSirqEnable" = "0x01" # VR Settings Configuration for 5 Domains #+----------------+-------+-------+-------------+-------------+-------+ diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index 197121e..524bcca 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -25,7 +25,6 @@ select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select INTEL_LPSS_UART_FOR_CONSOLE - select SERIRQ_CONTINUOUS_MODE select SKYLAKE_SOC_PCH_H select SOC_INTEL_SKYLAKE select SUPERIO_NUVOTON_NCT6776 diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 7036b28..8f78249 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -60,9 +60,7 @@ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s register "PmConfigSlpAMinAssert" = "0x03" - # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled - register "SerialIrqConfigSirqEnable" = "0x01" - register "SerialIrqConfigSirqMode" = "0x01" + register "serirq_mode" = "SERIRQ_CONTINUOUS" # VR Settings Configuration for 5 Domains #+----------------+-------+-------+-------------+-------------+-------+ diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index 399c643..a089712 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -61,7 +61,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "3" # 500ms diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index f9f7ef7..9bf0b98 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -61,7 +61,6 @@ register "Device4Enable" = "1" register "HeciEnabled" = "0" register "SaGv" = "3" - register "SerialIrqConfigSirqEnable" = "1" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s register "PmConfigSlpSusMinAssert" = "3" # 500ms diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 77d259b..53094b1 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -162,13 +162,6 @@ help This option allows you to select MMIO Base Address of sideband bus. -config SERIRQ_CONTINUOUS_MODE - bool - default n - help - If you set this option to y, the serial IRQ machine will be - operated in continuous mode. - config SMM_RESERVED_SIZE hex default 0x200000 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index cbbfaaa..1f32a3e 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -22,6 +22,7 @@ #include <fsp/util.h> #include <intelblocks/chip.h> #include <intelblocks/itss.h> +#include <intelblocks/lpc_lib.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <soc/acpi.h> @@ -190,8 +191,9 @@ params->PmConfigPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod; params->PmConfigPwrCycDur = config->PmConfigPwrCycDur; - params->SerialIrqConfigSirqEnable = config->SerialIrqConfigSirqEnable; - params->SerialIrqConfigSirqMode = config->SerialIrqConfigSirqMode; + params->SerialIrqConfigSirqEnable = config->serirq_mode != SERIRQ_OFF; + params->SerialIrqConfigSirqMode = + config->serirq_mode == SERIRQ_CONTINUOUS; params->SerialIrqConfigStartFramePulse = config->SerialIrqConfigStartFramePulse; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index f131a1a..a8ee064 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -24,6 +24,7 @@ #include <drivers/i2c/designware/dw_i2c.h> #include <intelblocks/chip.h> #include <intelblocks/gspi.h> +#include <intelblocks/lpc_lib.h> #include <stdint.h> #include <soc/gpe.h> #include <soc/gpio.h> @@ -428,13 +429,7 @@ RESET_POWER_CYCLE_4S = 4, } PmConfigPwrCycDur; - /* Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled.*/ - u8 SerialIrqConfigSirqEnable; - - enum { - SERIAL_IRQ_QUIET_MODE = 0, - SERIAL_IRQ_CONTINUOUS_MODE = 1, - } SerialIrqConfigSirqMode; + enum serirq_mode serirq_mode; enum { SERIAL_IRQ_FRAME_PULSE_4CLK = 0, diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index f4e17c6..c9afeb4 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -26,6 +26,7 @@ #include <fsp/util.h> #include <intelblocks/chip.h> #include <intelblocks/itss.h> +#include <intelblocks/lpc_lib.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <romstage_handoff.h> @@ -418,8 +419,8 @@ /* Indicate whether platform supports Voltage Margining */ params->PchPmSlpS0VmEnable = config->PchPmSlpS0VmEnable; - params->PchSirqEnable = config->SerialIrqConfigSirqEnable; - params->PchSirqMode = config->SerialIrqConfigSirqMode; + params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF; + params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS; params->CpuConfig.Bits.SkipMpInit = !chip_get_fsp_mp_init(); diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 8d97822..ae6c144 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -109,6 +109,8 @@ void lpc_soc_init(struct device *dev) { + const config_t *const config = dev->chip_info; + /* Legacy initialization */ isa_dma_init(); reg_script_run_on_dev(PCH_DEV_LPC, pch_misc_init_script); @@ -117,10 +119,7 @@ lpc_enable_pci_clk_cntl(); /* Set LPC Serial IRQ mode */ - if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) - lpc_set_serirq_mode(SERIRQ_CONTINUOUS); - else - lpc_set_serirq_mode(SERIRQ_QUIET); + lpc_set_serirq_mode(config->serirq_mode); /* Interrupt configuration */ pch_enable_ioapic(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/31596 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c Gerrit-Change-Number: 31596 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

6 11

Change in ...coreboot[master]: payloads/tianocore: Add option for custom bootsplash
by Matt DeVillier (Code Review) 01 Mar '19

01 Mar '19

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31561 Change subject: payloads/tianocore: Add option for custom bootsplash ...................................................................... payloads/tianocore: Add option for custom bootsplash Add Kconfig options to use custom bootsplash file, dependent on using MrChromebox's stable branch, with help info conveying required file format. Adjust Makefile to copy the custom bootsplash and overwrite the default Logo.bmp file, handling both absolute and relative paths, and restore the original logo file after building so as to keep the working directory clean. Test: build with and without custom bootsplash, ensure correct bootsplash displayed Change-Id: I164f46777169801cff56633fd920bc81b7c8129a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M payloads/external/Makefile.inc M payloads/external/tianocore/Kconfig M payloads/external/tianocore/Makefile 3 files changed, 32 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/31561/1 diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 4fda725..7249553 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -135,6 +135,7 @@ CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \ CONFIG_TIANOCORE_TARGET_IA32=$(CONFIG_TIANOCORE_TARGET_IA32) \ CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \ + CONFIG_TIANOCORE_BOOTSPLASH_FILE="$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" \ GCC_CC_x86_32=$(GCC_CC_x86_32) \ GCC_CC_x86_64=$(GCC_CC_x86_64) \ GCC_CC_arm=$(GCC_CC_arm) \ diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig index 79e09e6..12010ea 100644 --- a/payloads/external/tianocore/Kconfig +++ b/payloads/external/tianocore/Kconfig @@ -87,4 +87,24 @@ help Use 8254 Timer for legacy support. +config TIANOCORE_BOOTSPLASH_IMAGE + bool "Use a custom bootsplash image" + depends on TIANOCORE_STABLE + help + Select this option if you have a bootsplash image that you would + like to be used. If this option is not selected, the default + coreboot logo (European Brown Hare) will used. + +config TIANOCORE_BOOTSPLASH_FILE + string "Tianocore Bootsplash path and filename" + depends on TIANOCORE_BOOTSPLASH_IMAGE + default "bootsplash.bmp" + help + The path and filename of the file to use as graphical bootsplash + screen. The file format must be uncompressed BMP, and the file's + resolution must be less than the native resolution of the display. + + If an absolute path is not given, the path will assumed to be + relative to the coreboot root directory. + endif diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index e4f395f..989f723 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -87,6 +87,15 @@ build: $(project_dir)/.version_$(TAG-y) checktools unset CC; $(MAKE) -C $(project_dir)/BaseTools echo " build $(project_name) $(TAG-y)" + if [ -n "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" ]; then \ + echo " Copying custom bootsplash image"; \ + if [[ "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" = /* ]]; then \ + cp "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" "$(project_dir)/CorebootPayloadPkg/Logo/Logo.bmp"; \ + else \ + cp "$$(dirname "$$(dirname "$$(dirname "$(CURDIR)")")")/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" \ + "$(project_dir)/CorebootPayloadPkg/Logo/Logo.bmp"; \ + fi; \ + fi; \ cd $(project_dir); \ export EDK_TOOLS_PATH=$(project_dir)/BaseTools; \ export WORKSPACE=$(project_dir); \ @@ -96,7 +105,8 @@ cat ../tools_def.txt >> $(project_dir)/Conf/tools_def.txt; \ fi; \ build $(BUILD_STR); \ - mv $(project_dir)/Build/CorebootPayloadPkg*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd + mv $(project_dir)/Build/CorebootPayloadPkg*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \ + git checkout CorebootPayloadPkg/Logo/Logo.bmp > /dev/null 2>&1 clean: test -d $(project_dir) && (cd $(project_dir); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/31561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I164f46777169801cff56633fd920bc81b7c8129a Gerrit-Change-Number: 31561 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2019