Change in ...coreboot[master]: ec/lenovo/h8: Implement ACPI methods to set battery thresholds
by Evgeny Zinoviev (Code Review) 02 Mar '19
by Evgeny Zinoviev (Code Review) 02 Mar '19
02 Mar '19
Evgeny Zinoviev has uploaded a new patch set (#27) to the change originally created by Alexey Derlaft. ( https://review.coreboot.org/c/coreboot/+/23178 )
Change subject: ec/lenovo/h8: Implement ACPI methods to set battery thresholds
......................................................................
ec/lenovo/h8: Implement ACPI methods to set battery thresholds
There are two known reverse-engineered ways to manage battery
thresholds.
This patch implements them and adds a way to enable them for
different mainboards.
Tested on W530 with 4.18.3-gentoo kernel and X220 with 4.20.11.
Works fine with new Linux userspace API for controlling battery
thresholds, available since 4.17.
(/sys/class/power_supply/BAT0/charge_(start|stop)_threshold).
The new API is supported by TLP (you might need to set NATACPI_ENABLE=1
in /etc/tlp.conf).
tpacpi-bat works fine too.
Signed-off-by: Alexey Kharlamov <der(a)2-47.ru>
Signed-off-by: Evgeny Zinoviev <me(a)ch1p.com>
Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5
---
M src/ec/lenovo/h8/Kconfig
M src/ec/lenovo/h8/acpi/thinkpad.asl
A src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds.asl
A src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_24.asl
A src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl
M src/mainboard/lenovo/t400/Kconfig
M src/mainboard/lenovo/t400/acpi/ec.asl
M src/mainboard/lenovo/t420/Kconfig
M src/mainboard/lenovo/t420/acpi/ec.asl
M src/mainboard/lenovo/t420s/Kconfig
M src/mainboard/lenovo/t420s/acpi/ec.asl
M src/mainboard/lenovo/t430/Kconfig
M src/mainboard/lenovo/t430/acpi/ec.asl
M src/mainboard/lenovo/t430s/Kconfig
M src/mainboard/lenovo/t430s/acpi/ec.asl
M src/mainboard/lenovo/t520/Kconfig
M src/mainboard/lenovo/t520/acpi/ec.asl
M src/mainboard/lenovo/t530/Kconfig
M src/mainboard/lenovo/t530/acpi/ec.asl
M src/mainboard/lenovo/x1_carbon_gen1/Kconfig
M src/mainboard/lenovo/x1_carbon_gen1/acpi/ec.asl
M src/mainboard/lenovo/x200/Kconfig
M src/mainboard/lenovo/x200/acpi/ec.asl
M src/mainboard/lenovo/x201/Kconfig
M src/mainboard/lenovo/x201/acpi/ec.asl
M src/mainboard/lenovo/x220/Kconfig
M src/mainboard/lenovo/x220/acpi/ec.asl
M src/mainboard/lenovo/x230/Kconfig
M src/mainboard/lenovo/x230/acpi/ec.asl
29 files changed, 461 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/23178/27
--
To view, visit https://review.coreboot.org/c/coreboot/+/23178
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5
Gerrit-Change-Number: 23178
Gerrit-PatchSet: 27
Gerrit-Owner: Alexey Derlaft <derlafff(a)ya.ru>
Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu>
Gerrit-Reviewer: Alexey Derlaft <derlafff(a)ya.ru>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com>
Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: newpatchset
1
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Change in ...coreboot[master]: ec/lenovo/h8: Implement ACPI methods to set battery thresholds
by Evgeny Zinoviev (Code Review) 02 Mar '19
by Evgeny Zinoviev (Code Review) 02 Mar '19
02 Mar '19
Evgeny Zinoviev has uploaded a new patch set (#26) to the change originally created by Alexey Derlaft. ( https://review.coreboot.org/c/coreboot/+/23178 )
Change subject: ec/lenovo/h8: Implement ACPI methods to set battery thresholds
......................................................................
ec/lenovo/h8: Implement ACPI methods to set battery thresholds
There are two known (yet) different ways to manage battery thresholds.
This patch implements them and adds a way to enable them for
different mainboards.
Tested on W530 with 4.18.3-gentoo kernel. Works fine with new
Linux userspace API for controlling battery thresholds, available since
4.17.
(/sys/class/power_supply/BAT0/charge_(start|stop)_threshold).
The new API is supported by TLP (you might need to set NATACPI_ENABLE=1
in /etc/tlp.conf).
tpacpi-bat works fine too.
Signed-off-by: Alexey Kharlamov <der(a)2-47.ru>
Signed-off-by: Evgeny Zinoviev <me(a)ch1p.com>
Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5
---
M src/ec/lenovo/h8/Kconfig
M src/ec/lenovo/h8/acpi/thinkpad.asl
A src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds.asl
A src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_24.asl
A src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl
M src/mainboard/lenovo/t400/Kconfig
M src/mainboard/lenovo/t400/acpi/ec.asl
M src/mainboard/lenovo/t420/Kconfig
M src/mainboard/lenovo/t420/acpi/ec.asl
M src/mainboard/lenovo/t420s/Kconfig
M src/mainboard/lenovo/t420s/acpi/ec.asl
M src/mainboard/lenovo/t430/Kconfig
M src/mainboard/lenovo/t430/acpi/ec.asl
M src/mainboard/lenovo/t430s/Kconfig
M src/mainboard/lenovo/t430s/acpi/ec.asl
M src/mainboard/lenovo/t520/Kconfig
M src/mainboard/lenovo/t520/acpi/ec.asl
M src/mainboard/lenovo/t530/Kconfig
M src/mainboard/lenovo/t530/acpi/ec.asl
M src/mainboard/lenovo/x1_carbon_gen1/Kconfig
M src/mainboard/lenovo/x1_carbon_gen1/acpi/ec.asl
M src/mainboard/lenovo/x200/Kconfig
M src/mainboard/lenovo/x200/acpi/ec.asl
M src/mainboard/lenovo/x201/Kconfig
M src/mainboard/lenovo/x201/acpi/ec.asl
M src/mainboard/lenovo/x220/Kconfig
M src/mainboard/lenovo/x220/acpi/ec.asl
M src/mainboard/lenovo/x230/Kconfig
M src/mainboard/lenovo/x230/acpi/ec.asl
29 files changed, 461 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/23178/26
--
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Gerrit-Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5
Gerrit-Change-Number: 23178
Gerrit-PatchSet: 26
Gerrit-Owner: Alexey Derlaft <derlafff(a)ya.ru>
Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu>
Gerrit-Reviewer: Alexey Derlaft <derlafff(a)ya.ru>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com>
Gerrit-Reviewer: Marcello Sylvester Bauer <sylvblck(a)sylv.io>
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Change in ...coreboot[master]: Revert "mb/google/sarien: Update GPIOs for next build"
by Lijian Zhao (Code Review) 02 Mar '19
by Lijian Zhao (Code Review) 02 Mar '19
02 Mar '19
Hello Duncan Laurie, build bot (Jenkins), Patrick Georgi, Furquan Shaikh,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/30940
to review the following change.
Change subject: Revert "mb/google/sarien: Update GPIOs for next build"
......................................................................
Revert "mb/google/sarien: Update GPIOs for next build"
This reverts commit 025a03f6164b4f24e36aea39688b39abdec28fee.
Reason for revert: <INSERT REASONING HERE>
Change-Id: Ie0932da238dfacf61c507f042e72ad8452ab1bfe
---
M src/mainboard/google/sarien/variants/arcada/gpio.c
M src/mainboard/google/sarien/variants/sarien/gpio.c
2 files changed, 27 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/30940/1
diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c
index a29fd06..0ffd029 100644
--- a/src/mainboard/google/sarien/variants/arcada/gpio.c
+++ b/src/mainboard/google/sarien/variants/arcada/gpio.c
@@ -30,23 +30,18 @@
/* ESPI_CLK */
/* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE),
/* PME# */ PAD_NC(GPP_A11, NONE),
- /* ISH_LID_CL#_TAB */
-/* BM_BUSY# */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+/* BM_BUSY# */ PAD_NC(GPP_A12, NONE),
/* SUSWARN# */ PAD_NC(GPP_A13, NONE),
/* ESPI_RESET# */
/* SUSACK# */ PAD_NC(GPP_A15, NONE),
/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE),
/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE),
- /* ISH_ACC1_INT# */
-/* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
- /* ISH_ACC2_INT# */
-/* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
+/* ISH_GP0 */ PAD_NC(GPP_A18, NONE),
+/* ISH_GP1 */ PAD_NC(GPP_A19, NONE),
/* ISH_GP2 */ PAD_NC(GPP_A20, NONE),
/* ISH_GP3 */ PAD_NC(GPP_A21, NONE),
- /* ISH_NB_MODE */
-/* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
- /* ISH_LID_CL#_NB */
-/* ISH_GP5 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
+/* ISH_GP4 */ PAD_NC(GPP_A22, NONE),
+/* ISH_GP5 */ PAD_NC(GPP_A23, NONE),
/* CORE_VID0 */
/* CORE_VID1 */
@@ -54,17 +49,12 @@
/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */
/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */
- /* LAN_CLKREQ_CPU_N */
/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
- /* CARD_CLKREQ_CPU_N */
/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
- /* WLAN_CLKREQ_CPU_N */
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
- /* WWAN_CLKREQ_CPU_N */
/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
- /* SSD_CKLREQ_CPU_N */
/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
-/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */
+/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE),
/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */
/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
@@ -73,7 +63,7 @@
/* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */
/* GSPI0_MISO */ PAD_CFG_GPI(GPP_B17, NONE, DEEP), /* RTC_DET# */
/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),
-/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */
+/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE),
/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */
/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */
/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE),
@@ -122,10 +112,8 @@
/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE),
/* ISH_SPI_MISO */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */
/* ISH_SPI_MOSI */ PAD_NC(GPP_D12, NONE),
- /* ISH_CPU_UART0_RX */
-/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
- /* ISH_CPU_UART0_TX */
-/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+/* ISH_UART0_RXD */ PAD_NC(GPP_D13, NONE),
+/* ISH_UART0_TXD */ PAD_NC(GPP_D14, NONE),
/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */
/* ISH_UART0_CTS# */ PAD_NC(GPP_D16, NONE),
/* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */
@@ -156,10 +144,10 @@
/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */
/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */
/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */
-/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */
+/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE),
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
-/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */
-/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */
+/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE),
/* DDPC_CTRLDATA */ PAD_NC(GPP_E21, NONE),
/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE),
@@ -191,9 +179,9 @@
/* A4WP_PRESENT */ PAD_NC(GPP_F23, NONE),
/* SD_CMD */ PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */
-/* SD_DATA0 */ PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */
+/* SD_DATA0 */ PAD_NC(GPP_G1, NONE),
/* SD_DATA1 */ PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */
-/* SD_DATA2 */ PAD_NC(GPP_G3, NONE),
+/* SD_DATA2 */ PAD_NC(GPP_G3, NONE), /* T383 */
/* SD_DATA3 */ PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */
/* SD_CD# */ PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */
/* SD_CLK */ PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */
diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c
index 38d21c8..a41d940 100644
--- a/src/mainboard/google/sarien/variants/sarien/gpio.c
+++ b/src/mainboard/google/sarien/variants/sarien/gpio.c
@@ -49,11 +49,11 @@
/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST,
EDGE_SINGLE, INVERT), /* TOUCHPAD_INTR# */
/* CPU_GP3 */ PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */
-/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* CLKREQ_PCIE#0 */
-/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* CLKREQ_PCIE#1 */
-/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* CLKREQ_PCIE#2 */
-/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* CLKREQ_PCIE#3 */
-/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* CLKREQ_PCIE#4 */
+/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
+/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE),
/* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */
/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
@@ -63,7 +63,8 @@
/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE),
/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE),
/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),
-/* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */
+/* GSPI1_CS# */ PAD_CFG_GPI_APIC(GPP_B19, NONE, PLTRST,
+ EDGE_SINGLE, INVERT), /* HDD_FALL_INT */
/* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */
/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */
/* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE),
@@ -100,7 +101,7 @@
EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */
/* SPI1_CLK */ PAD_NC(GPP_D1, NONE),
/* SPI1_MISO */ PAD_NC(GPP_D2, NONE),
-/* SPI1_MOSI */ PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* RTC_DET# */
+/* SPI1_MOSI */ PAD_NC(GPP_D3, NONE),
/* FASHTRIG */ PAD_NC(GPP_D4, NONE),
/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE),
/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE),
@@ -134,7 +135,7 @@
/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */
/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */
/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */
-/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
+/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */
/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */
/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */
/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USB_OC2# */
@@ -142,7 +143,8 @@
/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* HDMI_DP1_HPD */
/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* CPU_DP2_HPD */
/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */
-/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */
+/* DDPE_HPD3 */ PAD_CFG_GPI_APIC(GPP_E16, NONE, PLTRST,
+ EDGE_SINGLE, INVERT), /* FFS_INT2 */
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
@@ -235,7 +237,7 @@
/* RESET# need to stay low before FULL_CARD_POWER_OFF assert */
/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */
/* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
-/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
+/* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */
/* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */
};
@@ -252,10 +254,7 @@
}
static const struct cros_gpio cros_gpios[] = {
- /*
- * TODO: re-enable recovery mode when boards are updated:
- * CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME),
- */
+ CROS_GPIO_REC_AH(GPP_E8, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME),
};
--
To view, visit https://review.coreboot.org/c/coreboot/+/30940
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie0932da238dfacf61c507f042e72ad8452ab1bfe
Gerrit-Change-Number: 30940
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
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Change in ...coreboot[master]: mb/google/sarien: Remove DRIVERS_PS2_KEYBOARD
by Duncan Laurie (Code Review) 02 Mar '19
by Duncan Laurie (Code Review) 02 Mar '19
02 Mar '19
Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31659
Change subject: mb/google/sarien: Remove DRIVERS_PS2_KEYBOARD
......................................................................
mb/google/sarien: Remove DRIVERS_PS2_KEYBOARD
In order to prevent keyboard keys pressed at boot from causing issues
in the payload remove the PS2 keyboard driver so it does not get
initialized until it is needed in libpayload.
BUG=b:126633269
TEST=boot on sarien while pressing keys and ensure libpayload and/or
the kernel does not have any issues initializing the keyboard.
Change-Id: I765e808f0d2589cf23c0349798a07e2706a2a7a4
Signed-off-by: Duncan Laurie <dlaurie(a)google.com>
---
M src/mainboard/google/sarien/Kconfig
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/31659/1
diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig
index a976d36..ce6b810 100644
--- a/src/mainboard/google/sarien/Kconfig
+++ b/src/mainboard/google/sarien/Kconfig
@@ -5,7 +5,6 @@
select DRIVERS_I2C_GENERIC
select DRIVERS_I2C_HID
select DRIVERS_SPI_ACPI
- select DRIVERS_PS2_KEYBOARD
select DRIVERS_USB_ACPI
select EC_GOOGLE_WILCO
select GENERIC_SPD_BIN
--
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Gerrit-Change-Id: I765e808f0d2589cf23c0349798a07e2706a2a7a4
Gerrit-Change-Number: 31659
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>
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9
Change in ...coreboot[master]: libpayload: i8042: Only test PS/2 AUX port when enabled
by Duncan Laurie (Code Review) 02 Mar '19
by Duncan Laurie (Code Review) 02 Mar '19
02 Mar '19
Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31658
Change subject: libpayload: i8042: Only test PS/2 AUX port when enabled
......................................................................
libpayload: i8042: Only test PS/2 AUX port when enabled
If a PS/2 AUX device is not present then the AUX test command
during i8042_probe() will time out and add ~500ms to the boot time.
In order to avoid this only test the PS/2 AUX port if
CONFIG_LP_PC_MOUSE is enabled.
BUG=b:126633269
TEST=boot on device without AUX port and check that this command
does not get executed, saving ~500ms at boot.
Change-Id: I2ebdecc66933bd33d320b17aa4608caf4aaf54aa
Signed-off-by: Duncan Laurie <dlaurie(a)google.com>
---
M payloads/libpayload/drivers/i8042/i8042.c
1 file changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/31658/1
diff --git a/payloads/libpayload/drivers/i8042/i8042.c b/payloads/libpayload/drivers/i8042/i8042.c
index 69740d9..4cdd0be 100644
--- a/payloads/libpayload/drivers/i8042/i8042.c
+++ b/payloads/libpayload/drivers/i8042/i8042.c
@@ -229,8 +229,10 @@
}
/* Test secondary port */
- if (i8042_cmd_with_response(I8042_CMD_AUX_TEST) == 0)
- aux_fifo = fifo_init(4 * 32);
+ if (IS_ENABLED(CONFIG_LP_PC_MOUSE)) {
+ if (i8042_cmd_with_response(I8042_CMD_AUX_TEST) == 0)
+ aux_fifo = fifo_init(4 * 32);
+ }
/* Test first PS/2 port */
if (i8042_cmd_with_response(I8042_CMD_KB_TEST) == 0)
--
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Gerrit-Change-Id: I2ebdecc66933bd33d320b17aa4608caf4aaf54aa
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Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>
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3
Change in ...coreboot[master]: libpayload: keyboard: Add option to ignore failures during init
by Duncan Laurie (Code Review) 02 Mar '19
by Duncan Laurie (Code Review) 02 Mar '19
02 Mar '19
Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31657
Change subject: libpayload: keyboard: Add option to ignore failures during init
......................................................................
libpayload: keyboard: Add option to ignore failures during init
If keys are pressed at boot some keyboard controllers will not
properly respond with an ACK to commands, which results in the
keyboard_init function aborting before it adds the keyboard to the
input device list.
This same keyboard controller will manage to properly return keyboard
data when keys are pressed later, so it is possible for it to be
functional in the payload even if it does not respond properly to
every command during initialization.
In order to allow payloads to use the keyboard when this happens a
new Kconfig option is added to ignore the keyboard ACK response and
always add the keyboard to the input device list. This option is
disabled by default and must be enabled by the specific boards that
need it.
BUG=b:126633269
TEST=boot on device with this controller and press keys during boot
and see that the keyboard is still functional in the payload.
Change-Id: Icc6053f99804f1b57d785cb04235b5c4b8d5426f
Signed-off-by: Duncan Laurie <dlaurie(a)google.com>
---
M payloads/libpayload/Kconfig
M payloads/libpayload/drivers/i8042/keyboard.c
2 files changed, 7 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/31657/1
diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig
index a79269f..6aa5b61 100644
--- a/payloads/libpayload/Kconfig
+++ b/payloads/libpayload/Kconfig
@@ -344,6 +344,10 @@
default y if ARCH_X86 # uses IO
default n
+config PC_KEYBOARD_IGNORE_FAILURE
+ bool "Ignore keyboard failures during init and always add input device"
+ default n
+
config PC_KEYBOARD_LAYOUT_US
bool "English (US) keyboard layout"
depends on PC_KEYBOARD
diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c
index 062aec2..918cafa 100644
--- a/payloads/libpayload/drivers/i8042/keyboard.c
+++ b/payloads/libpayload/drivers/i8042/keyboard.c
@@ -309,16 +309,16 @@
/* Set scancode set 1 */
ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE);
- if (!ret)
+ if (!ret && !IS_ENABLED(CONFIG_LP_PC_KEYBOARD_IGNORE_FAILURE))
return;
ret = keyboard_cmd(I8042_SCANCODE_SET_1);
- if (!ret)
+ if (!ret && !IS_ENABLED(CONFIG_LP_PC_KEYBOARD_IGNORE_FAILURE))
return;
/* Enable scanning */
ret = keyboard_cmd(I8042_KBCMD_EN);
- if (!ret)
+ if (!ret && !IS_ENABLED(CONFIG_LP_PC_KEYBOARD_IGNORE_FAILURE))
return;
console_add_input_driver(&cons);
--
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Gerrit-Change-Id: Icc6053f99804f1b57d785cb04235b5c4b8d5426f
Gerrit-Change-Number: 31657
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>
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8
Change in ...coreboot[master]: soc/intel/cannonlake: Fix DSDT compile remarks
by Bora Guvendik (Code Review) 02 Mar '19
by Bora Guvendik (Code Review) 02 Mar '19
02 Mar '19
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31666 )
Change subject: soc/intel/cannonlake: Fix DSDT compile remarks
......................................................................
Patch Set 2: Code-Review+2
--
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Gerrit-Change-Id: Iad660347b32d90ac1176654820375e30a21b5ffe
Gerrit-Change-Number: 31666
Gerrit-PatchSet: 2
Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com>
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Gerrit-Comment-Date: Fri, 01 Mar 2019 23:35:01 +0000
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0
Change in ...coreboot[master]: soc/intel/braswell: Configure IO APIC
by Nico Huber (Code Review) 01 Mar '19
by Nico Huber (Code Review) 01 Mar '19
01 Mar '19
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29423 )
Change subject: soc/intel/braswell: Configure IO APIC
......................................................................
Patch Set 7:
Are we sure FSP doesn't do this already? It seems unlikely
that all the in tree Braswell devices don't use the APIC.
Maybe we only have to reserve the resources?
--
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Gerrit-Change-Number: 29423
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Gerrit-Comment-Date: Fri, 01 Mar 2019 20:56:33 +0000
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Change in ...coreboot[master]: [WIP] device/pci: Fix PCI accessor headers
by Kyösti Mälkki (Code Review) 01 Mar '19
by Kyösti Mälkki (Code Review) 01 Mar '19
01 Mar '19
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31675
Change subject: [WIP] device/pci: Fix PCI accessor headers
......................................................................
[WIP] device/pci: Fix PCI accessor headers
PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.
Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/arch/x86/include/arch/io.h
M src/commonlib/storage/pci_sdhci.c
M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
M src/cpu/amd/family_10h-family_15h/monotonic_timer.c
M src/cpu/amd/family_10h-family_15h/powernow_acpi.c
M src/cpu/amd/family_10h-family_15h/ram_calc.c
M src/cpu/amd/quadcore/amd_sibling.c
M src/cpu/intel/fsp_model_406dx/bootblock.c
M src/device/cardbus_device.c
M src/device/hypertransport.c
M src/device/pci_class.c
M src/device/pci_device.c
M src/device/pcix_device.c
M src/drivers/dec/21143/21143.c
M src/drivers/generic/bayhub/bh720.c
M src/drivers/intel/gma/vbt.c
M src/drivers/intel/wifi/wifi.c
M src/drivers/net/atl1e.c
M src/drivers/ricoh/rce822/rce822.c
M src/drivers/uart/oxpcie.c
M src/drivers/uart/oxpcie_early.c
M src/drivers/usb/pci_ehci.c
M src/include/device/pci.h
M src/include/device/pci_ops.h
M src/lib/reg_script.c
M src/mainboard/adi/rcc-dff/romstage.c
M src/mainboard/advansus/a785e-i/romstage.c
M src/mainboard/amd/bimini_fam10/romstage.c
M src/mainboard/amd/mahogany_fam10/mainboard.c
M src/mainboard/amd/mahogany_fam10/mptable.c
M src/mainboard/amd/olivehill/romstage.c
M src/mainboard/amd/parmer/romstage.c
M src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
M src/mainboard/amd/thatcher/romstage.c
M src/mainboard/amd/tilapia_fam10/mainboard.c
M src/mainboard/amd/tilapia_fam10/mptable.c
M src/mainboard/aopen/dxplplusu/fadt.c
M src/mainboard/apple/macbook21/romstage.c
M src/mainboard/apple/macbookair4_2/romstage.c
M src/mainboard/asrock/b75pro3-m/romstage.c
M src/mainboard/asrock/g41c-gs/romstage.c
M src/mainboard/asrock/imb-a180/romstage.c
M src/mainboard/asus/am1i-a/romstage.c
M src/mainboard/asus/f2a85-m/romstage.c
M src/mainboard/asus/h61m-cs/romstage.c
M src/mainboard/asus/kcma-d8/acpi_tables.c
M src/mainboard/asus/kcma-d8/bootblock.c
M src/mainboard/asus/kcma-d8/mainboard.c
M src/mainboard/asus/kcma-d8/mptable.c
M src/mainboard/asus/kcma-d8/romstage.c
M src/mainboard/asus/kfsn4-dre/acpi_tables.c
M src/mainboard/asus/kfsn4-dre/get_bus_conf.c
M src/mainboard/asus/kfsn4-dre/mptable.c
M src/mainboard/asus/kfsn4-dre/romstage.c
M src/mainboard/asus/kgpe-d16/acpi_tables.c
M src/mainboard/asus/kgpe-d16/bootblock.c
M src/mainboard/asus/kgpe-d16/mainboard.c
M src/mainboard/asus/kgpe-d16/mptable.c
M src/mainboard/asus/kgpe-d16/romstage.c
M src/mainboard/asus/m4a78-em/mainboard.c
M src/mainboard/asus/m4a78-em/mptable.c
M src/mainboard/asus/m4a785-m/mainboard.c
M src/mainboard/asus/m4a785-m/mptable.c
M src/mainboard/asus/m5a88-v/romstage.c
M src/mainboard/asus/p5gc-mx/romstage.c
M src/mainboard/asus/p5qc/romstage.c
M src/mainboard/asus/p5qpl-am/romstage.c
M src/mainboard/asus/p8h61-m_pro/romstage.c
M src/mainboard/avalue/eax-785e/romstage.c
M src/mainboard/bap/ode_e20XX/romstage.c
M src/mainboard/biostar/a68n_5200/romstage.c
M src/mainboard/biostar/am1ml/romstage.c
M src/mainboard/compulab/intense_pc/romstage.c
M src/mainboard/emulation/qemu-i440fx/northbridge.c
M src/mainboard/emulation/qemu-q35/acpi_tables.c
M src/mainboard/emulation/qemu-q35/bootblock.c
M src/mainboard/foxconn/d41s/romstage.c
M src/mainboard/foxconn/g41s-k/romstage.c
M src/mainboard/getac/p470/mainboard.c
M src/mainboard/getac/p470/romstage.c
M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
M src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
M src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
M src/mainboard/gigabyte/ma785gm/mainboard.c
M src/mainboard/gigabyte/ma785gm/mptable.c
M src/mainboard/gigabyte/ma785gmt/mainboard.c
M src/mainboard/gigabyte/ma785gmt/mptable.c
M src/mainboard/gigabyte/ma78gm/mainboard.c
M src/mainboard/gigabyte/ma78gm/mptable.c
M src/mainboard/gizmosphere/gizmo2/romstage.c
M src/mainboard/google/auron/variants/buddy/variant.c
M src/mainboard/google/beltino/chromeos.c
M src/mainboard/google/beltino/lan.c
M src/mainboard/google/butterfly/chromeos.c
M src/mainboard/google/butterfly/romstage.c
M src/mainboard/google/cyan/com_init.c
M src/mainboard/google/jecht/chromeos.c
M src/mainboard/google/jecht/lan.c
M src/mainboard/google/kahlee/variants/baseboard/mainboard.c
M src/mainboard/google/link/romstage.c
M src/mainboard/google/parrot/chromeos.c
M src/mainboard/google/parrot/romstage.c
M src/mainboard/google/poppy/variants/nautilus/mainboard.c
M src/mainboard/google/rambi/variants/ninja/lan.c
M src/mainboard/google/rambi/variants/sumo/lan.c
M src/mainboard/google/stout/chromeos.c
M src/mainboard/google/stout/mainboard_smi.c
M src/mainboard/google/stout/romstage.c
M src/mainboard/hp/2570p/romstage.c
M src/mainboard/hp/2760p/romstage.c
M src/mainboard/hp/8460p/romstage.c
M src/mainboard/hp/8470p/romstage.c
M src/mainboard/hp/8770w/romstage.c
M src/mainboard/hp/abm/romstage.c
M src/mainboard/hp/compaq_8200_elite_sff/romstage.c
M src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
M src/mainboard/hp/dl165_g6_fam10/mptable.c
M src/mainboard/hp/dl165_g6_fam10/romstage.c
M src/mainboard/hp/folio_9470m/romstage.c
M src/mainboard/hp/revolve_810_g1/romstage.c
M src/mainboard/ibase/mb899/romstage.c
M src/mainboard/iei/kino-780am2-fam10/mptable.c
M src/mainboard/intel/baskingridge/chromeos.c
M src/mainboard/intel/d510mo/romstage.c
M src/mainboard/intel/d945gclf/romstage.c
M src/mainboard/intel/dcp847ske/early_southbridge.c
M src/mainboard/intel/dg41wv/romstage.c
M src/mainboard/intel/dg43gt/romstage.c
M src/mainboard/intel/emeraldlake2/chromeos.c
M src/mainboard/intel/emeraldlake2/romstage.c
M src/mainboard/intel/littleplains/romstage.c
M src/mainboard/intel/mohonpeak/romstage.c
M src/mainboard/intel/strago/com_init.c
M src/mainboard/jetway/pa78vm5/mainboard.c
M src/mainboard/jetway/pa78vm5/mptable.c
M src/mainboard/kontron/986lcd-m/romstage.c
M src/mainboard/kontron/ktqm77/romstage.c
M src/mainboard/lenovo/l520/romstage.c
M src/mainboard/lenovo/s230u/romstage.c
M src/mainboard/lenovo/t400/fadt.c
M src/mainboard/lenovo/t400/romstage.c
M src/mainboard/lenovo/t420/romstage.c
M src/mainboard/lenovo/t420s/romstage.c
M src/mainboard/lenovo/t420s/smihandler.c
M src/mainboard/lenovo/t430/romstage.c
M src/mainboard/lenovo/t430s/romstage.c
M src/mainboard/lenovo/t430s/smihandler.c
M src/mainboard/lenovo/t430s/variants/t430s/romstage.c
M src/mainboard/lenovo/t520/romstage.c
M src/mainboard/lenovo/t520/smihandler.c
M src/mainboard/lenovo/t530/romstage.c
M src/mainboard/lenovo/t530/smihandler.c
M src/mainboard/lenovo/t60/romstage.c
M src/mainboard/lenovo/t60/smihandler.c
M src/mainboard/lenovo/thinkcentre_a58/romstage.c
M src/mainboard/lenovo/x131e/romstage.c
M src/mainboard/lenovo/x1_carbon_gen1/romstage.c
M src/mainboard/lenovo/x200/dock.c
M src/mainboard/lenovo/x200/fadt.c
M src/mainboard/lenovo/x200/romstage.c
M src/mainboard/lenovo/x201/dock.c
M src/mainboard/lenovo/x201/mainboard.c
M src/mainboard/lenovo/x201/romstage.c
M src/mainboard/lenovo/x201/smihandler.c
M src/mainboard/lenovo/x220/romstage.c
M src/mainboard/lenovo/x220/smihandler.c
M src/mainboard/lenovo/x230/romstage.c
M src/mainboard/lenovo/x60/romstage.c
M src/mainboard/lenovo/x60/smihandler.c
M src/mainboard/lenovo/z61t/romstage.c
M src/mainboard/lenovo/z61t/smihandler.c
M src/mainboard/lippert/frontrunner-af/mainboard.c
M src/mainboard/lippert/toucan-af/mainboard.c
M src/mainboard/msi/ms7721/romstage.c
M src/mainboard/msi/ms9652_fam10/get_bus_conf.c
M src/mainboard/msi/ms9652_fam10/mptable.c
M src/mainboard/msi/ms9652_fam10/romstage.c
M src/mainboard/ocp/wedge100s/romstage.c
M src/mainboard/packardbell/ms2290/romstage.c
M src/mainboard/packardbell/ms2290/smihandler.c
M src/mainboard/pcengines/apu1/mainboard.c
M src/mainboard/pcengines/apu2/mainboard.c
M src/mainboard/pcengines/apu2/romstage.c
M src/mainboard/roda/rk886ex/romstage.c
M src/mainboard/roda/rk9/fadt.c
M src/mainboard/roda/rk9/romstage.c
M src/mainboard/roda/rk9/ti_pci7xx1.c
M src/mainboard/roda/rv11/variants/rv11/romstage.c
M src/mainboard/roda/rv11/variants/rw11/romstage.c
M src/mainboard/samsung/lumpy/chromeos.c
M src/mainboard/samsung/lumpy/romstage.c
M src/mainboard/samsung/stumpy/chromeos.c
M src/mainboard/samsung/stumpy/romstage.c
M src/mainboard/sapphire/pureplatinumh61/romstage.c
M src/mainboard/siemens/mc_apl1/mainboard.c
M src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
M src/mainboard/supermicro/h8dmr_fam10/mptable.c
M src/mainboard/supermicro/h8dmr_fam10/romstage.c
M src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
M src/mainboard/supermicro/h8qme_fam10/mptable.c
M src/mainboard/supermicro/h8qme_fam10/romstage.c
M src/mainboard/supermicro/h8scm_fam10/acpi_tables.c
M src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c
M src/mainboard/supermicro/h8scm_fam10/mptable.c
M src/mainboard/tyan/s2912_fam10/get_bus_conf.c
M src/mainboard/tyan/s2912_fam10/mptable.c
M src/mainboard/tyan/s2912_fam10/romstage.c
M src/northbridge/amd/agesa/family12/northbridge.c
M src/northbridge/amd/agesa/family14/northbridge.c
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/amdfam10/debug.c
M src/northbridge/amd/amdfam10/early_ht.c
M src/northbridge/amd/amdfam10/northbridge.c
M src/northbridge/amd/amdht/comlib.c
M src/northbridge/amd/amdht/h3finit.c
M src/northbridge/amd/amdk8/reset_test.c
M src/northbridge/amd/pi/00630F01/northbridge.c
M src/northbridge/amd/pi/00660F01/northbridge.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/amd/pi/ramtop.c
M src/northbridge/intel/e7505/debug.c
M src/northbridge/intel/e7505/memmap.c
M src/northbridge/intel/e7505/northbridge.c
M src/northbridge/intel/e7505/raminit.c
M src/northbridge/intel/fsp_rangeley/northbridge.c
M src/northbridge/intel/fsp_rangeley/port_access.c
M src/northbridge/intel/gm45/acpi.c
M src/northbridge/intel/gm45/bootblock.c
M src/northbridge/intel/gm45/early_init.c
M src/northbridge/intel/gm45/early_reset.c
M src/northbridge/intel/gm45/igd.c
M src/northbridge/intel/gm45/iommu.c
M src/northbridge/intel/gm45/northbridge.c
M src/northbridge/intel/gm45/pcie.c
M src/northbridge/intel/gm45/ram_calc.c
M src/northbridge/intel/gm45/raminit.c
M src/northbridge/intel/gm45/romstage.c
M src/northbridge/intel/haswell/acpi.c
M src/northbridge/intel/haswell/bootblock.c
M src/northbridge/intel/haswell/gma.c
M src/northbridge/intel/haswell/ram_calc.c
M src/northbridge/intel/haswell/report_platform.c
M src/northbridge/intel/i440bx/debug.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i440bx/ram_calc.c
M src/northbridge/intel/i440bx/raminit.c
M src/northbridge/intel/i945/acpi.c
M src/northbridge/intel/i945/bootblock.c
M src/northbridge/intel/i945/debug.c
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/i945/gma.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/i945/ram_calc.c
M src/northbridge/intel/i945/raminit.c
M src/northbridge/intel/nehalem/acpi.c
M src/northbridge/intel/nehalem/bootblock.c
M src/northbridge/intel/nehalem/early_init.c
M src/northbridge/intel/nehalem/northbridge.c
M src/northbridge/intel/nehalem/ram_calc.c
M src/northbridge/intel/nehalem/raminit.c
M src/northbridge/intel/nehalem/smi.c
M src/northbridge/intel/pineview/bootblock.c
M src/northbridge/intel/pineview/early_init.c
M src/northbridge/intel/pineview/northbridge.c
M src/northbridge/intel/pineview/ram_calc.c
M src/northbridge/intel/pineview/raminit.c
M src/northbridge/intel/pineview/romstage.c
M src/northbridge/intel/sandybridge/acpi.c
M src/northbridge/intel/sandybridge/bootblock.c
M src/northbridge/intel/sandybridge/early_init.c
M src/northbridge/intel/sandybridge/iommu.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/sandybridge/pcie.c
M src/northbridge/intel/sandybridge/ram_calc.c
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_common.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/northbridge/intel/sandybridge/romstage.c
M src/northbridge/intel/x4x/bootblock.c
M src/northbridge/intel/x4x/early_init.c
M src/northbridge/intel/x4x/northbridge.c
M src/northbridge/intel/x4x/ram_calc.c
M src/northbridge/intel/x4x/raminit.c
M src/northbridge/intel/x4x/raminit_ddr23.c
M src/northbridge/via/vx900/bootblock.c
M src/northbridge/via/vx900/chrome9hd.c
M src/northbridge/via/vx900/early_smbus.c
M src/northbridge/via/vx900/early_vx900.c
M src/northbridge/via/vx900/lpc.c
M src/northbridge/via/vx900/memmap.c
M src/northbridge/via/vx900/northbridge.c
M src/northbridge/via/vx900/pcie.c
M src/northbridge/via/vx900/raminit_ddr3.c
M src/northbridge/via/vx900/sata.c
M src/northbridge/via/vx900/traf_ctrl.c
M src/soc/amd/common/block/pci/amd_pci_util.c
M src/soc/amd/stoneyridge/acpi.c
M src/soc/amd/stoneyridge/enable_usbdebug.c
M src/soc/amd/stoneyridge/northbridge.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/apollolake/bootblock/bootblock.c
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/graphics.c
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/baytrail/bootblock/bootblock.c
M src/soc/intel/baytrail/chip.c
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/iosf.c
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/baytrail/pmutil.c
M src/soc/intel/baytrail/romstage/gfx.c
M src/soc/intel/baytrail/romstage/pmc.c
M src/soc/intel/baytrail/romstage/raminit.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/baytrail/romstage/uart.c
M src/soc/intel/baytrail/sata.c
M src/soc/intel/baytrail/sd.c
M src/soc/intel/baytrail/smihandler.c
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/baytrail/spi.c
M src/soc/intel/baytrail/xhci.c
M src/soc/intel/braswell/bootblock/bootblock.c
M src/soc/intel/braswell/chip.c
M src/soc/intel/braswell/iosf.c
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/braswell/pmutil.c
M src/soc/intel/braswell/romstage/romstage.c
M src/soc/intel/braswell/sd.c
M src/soc/intel/braswell/smihandler.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/spi.c
M src/soc/intel/broadwell/bootblock/pch.c
M src/soc/intel/broadwell/bootblock/systemagent.c
M src/soc/intel/broadwell/chip.c
M src/soc/intel/broadwell/ehci.c
M src/soc/intel/broadwell/igd.c
M src/soc/intel/broadwell/lpc.c
M src/soc/intel/broadwell/me.c
M src/soc/intel/broadwell/me_status.c
M src/soc/intel/broadwell/memmap.c
M src/soc/intel/broadwell/pch.c
M src/soc/intel/broadwell/pmutil.c
M src/soc/intel/broadwell/romstage/power_state.c
M src/soc/intel/broadwell/romstage/report_platform.c
M src/soc/intel/broadwell/romstage/systemagent.c
M src/soc/intel/broadwell/sata.c
M src/soc/intel/broadwell/serialio.c
M src/soc/intel/broadwell/smihandler.c
M src/soc/intel/broadwell/smmrelocate.c
M src/soc/intel/broadwell/spi.c
M src/soc/intel/broadwell/systemagent.c
M src/soc/intel/broadwell/xhci.c
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/bootblock/report_platform.c
M src/soc/intel/cannonlake/graphics.c
M src/soc/intel/cannonlake/lpc.c
M src/soc/intel/cannonlake/smmrelocate.c
M src/soc/intel/common/block/i2c/i2c.c
M src/soc/intel/common/block/lpc/lpc_lib.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/pmc/pmc.c
M src/soc/intel/common/block/sata/sata.c
M src/soc/intel/common/block/smbus/tco.c
M src/soc/intel/common/block/smm/smihandler.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/systemagent/systemagent_early.c
M src/soc/intel/denverton_ns/acpi.c
M src/soc/intel/denverton_ns/bootblock/uart.c
M src/soc/intel/denverton_ns/chip.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/pmc.c
M src/soc/intel/denverton_ns/romstage.c
M src/soc/intel/denverton_ns/sata.c
M src/soc/intel/denverton_ns/smihandler.c
M src/soc/intel/denverton_ns/soc_util.c
M src/soc/intel/denverton_ns/systemagent.c
M src/soc/intel/denverton_ns/uart_debug.c
M src/soc/intel/denverton_ns/xhci.c
M src/soc/intel/fsp_baytrail/acpi.c
M src/soc/intel/fsp_baytrail/bootblock/bootblock.c
M src/soc/intel/fsp_baytrail/chip.c
M src/soc/intel/fsp_baytrail/i2c.c
M src/soc/intel/fsp_baytrail/iosf.c
M src/soc/intel/fsp_baytrail/lpe.c
M src/soc/intel/fsp_baytrail/pmutil.c
M src/soc/intel/fsp_baytrail/romstage/report_platform.c
M src/soc/intel/fsp_baytrail/romstage/romstage.c
M src/soc/intel/fsp_baytrail/romstage/uart.c
M src/soc/intel/fsp_baytrail/smihandler.c
M src/soc/intel/fsp_baytrail/southcluster.c
M src/soc/intel/fsp_baytrail/spi.c
M src/soc/intel/fsp_broadwell_de/acpi.c
M src/soc/intel/fsp_broadwell_de/chip.c
M src/soc/intel/fsp_broadwell_de/romstage/romstage.c
M src/soc/intel/fsp_broadwell_de/smmrelocate.c
M src/soc/intel/fsp_broadwell_de/southcluster.c
M src/soc/intel/fsp_broadwell_de/vtd.c
M src/soc/intel/icelake/bootblock/report_platform.c
M src/soc/intel/icelake/graphics.c
M src/soc/intel/icelake/lpc.c
M src/soc/intel/icelake/smmrelocate.c
M src/soc/intel/quark/include/soc/ramstage.h
M src/soc/intel/quark/reg_access.c
M src/soc/intel/quark/romstage/report_platform.c
M src/soc/intel/quark/spi.c
M src/soc/intel/quark/storage_test.c
M src/soc/intel/skylake/bootblock/pch.c
M src/soc/intel/skylake/bootblock/report_platform.c
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/finalize.c
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/irq.c
M src/soc/intel/skylake/me.c
M src/soc/intel/skylake/pmutil.c
M src/soc/intel/skylake/smmrelocate.c
M src/soc/intel/skylake/thermal.c
M src/southbridge/amd/agesa/hudson/bootblock.c
M src/southbridge/amd/agesa/hudson/early_setup.c
M src/southbridge/amd/agesa/hudson/reset.c
M src/southbridge/amd/amd8111/amd8111.c
M src/southbridge/amd/amd8111/bootblock.c
M src/southbridge/amd/amd8111/reset.c
M src/southbridge/amd/cimx/sb800/bootblock.c
M src/southbridge/amd/cimx/sb800/fan.c
M src/southbridge/amd/cimx/sb800/late.c
M src/southbridge/amd/cimx/sb800/lpc.c
M src/southbridge/amd/cimx/sb800/reset.c
M src/southbridge/amd/cimx/sb900/bootblock.c
M src/southbridge/amd/cimx/sb900/lpc.c
M src/southbridge/amd/cimx/sb900/reset.c
M src/southbridge/amd/common/amd_pci_util.c
M src/southbridge/amd/pi/hudson/bootblock.c
M src/southbridge/amd/pi/hudson/early_setup.c
M src/southbridge/amd/pi/hudson/imc.c
M src/southbridge/amd/pi/hudson/reset.c
M src/southbridge/amd/rs780/early_setup.c
M src/southbridge/amd/sb700/bootblock.c
M src/southbridge/amd/sb700/early_setup.c
M src/southbridge/amd/sb700/reset.c
M src/southbridge/amd/sb700/sb700.h
M src/southbridge/amd/sb800/bootblock.c
M src/southbridge/amd/sr5650/cmn.h
M src/southbridge/amd/sr5650/early_setup.c
M src/southbridge/broadcom/bcm5785/bcm5785.c
M src/southbridge/broadcom/bcm5785/bootblock.c
M src/southbridge/intel/bd82x6x/bootblock.c
M src/southbridge/intel/bd82x6x/early_me.c
M src/southbridge/intel/bd82x6x/early_me_mrc.c
M src/southbridge/intel/bd82x6x/early_pch.c
M src/southbridge/intel/bd82x6x/early_smbus.c
M src/southbridge/intel/bd82x6x/early_thermal.c
M src/southbridge/intel/bd82x6x/early_usb.c
M src/southbridge/intel/bd82x6x/early_usb_mrc.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me_8.x.c
M src/southbridge/intel/bd82x6x/pch.c
M src/southbridge/intel/bd82x6x/pci.c
M src/southbridge/intel/bd82x6x/pcie.c
M src/southbridge/intel/bd82x6x/sata.c
M src/southbridge/intel/bd82x6x/smihandler.c
M src/southbridge/intel/bd82x6x/usb_ehci.c
M src/southbridge/intel/bd82x6x/usb_xhci.c
M src/southbridge/intel/bd82x6x/watchdog.c
M src/southbridge/intel/common/gpio.c
M src/southbridge/intel/common/pmbase.c
M src/southbridge/intel/common/smihandler.c
M src/southbridge/intel/common/spi.c
M src/southbridge/intel/common/usb_debug.c
M src/southbridge/intel/fsp_rangeley/acpi.c
M src/southbridge/intel/fsp_rangeley/early_init.c
M src/southbridge/intel/fsp_rangeley/early_smbus.c
M src/southbridge/intel/fsp_rangeley/early_usb.c
M src/southbridge/intel/fsp_rangeley/gpio.c
M src/southbridge/intel/fsp_rangeley/lpc.c
M src/southbridge/intel/fsp_rangeley/romstage.c
M src/southbridge/intel/fsp_rangeley/sata.c
M src/southbridge/intel/fsp_rangeley/soc.c
M src/southbridge/intel/fsp_rangeley/spi.c
M src/southbridge/intel/fsp_rangeley/watchdog.c
M src/southbridge/intel/i82371eb/bootblock.c
M src/southbridge/intel/i82371eb/early_pm.c
M src/southbridge/intel/i82371eb/early_smbus.c
M src/southbridge/intel/i82371eb/ide.c
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82371eb/smbus.c
M src/southbridge/intel/i82801dx/ac97.c
M src/southbridge/intel/i82801dx/bootblock.c
M src/southbridge/intel/i82801dx/early_smbus.c
M src/southbridge/intel/i82801dx/i82801dx.c
M src/southbridge/intel/i82801dx/smi.c
M src/southbridge/intel/i82801dx/smihandler.c
M src/southbridge/intel/i82801gx/ac97.c
M src/southbridge/intel/i82801gx/bootblock.c
M src/southbridge/intel/i82801gx/early_smbus.c
M src/southbridge/intel/i82801gx/i82801gx.c
M src/southbridge/intel/i82801gx/ide.c
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801gx/pci.c
M src/southbridge/intel/i82801gx/pcie.c
M src/southbridge/intel/i82801gx/sata.c
M src/southbridge/intel/i82801gx/usb.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801gx/watchdog.c
M src/southbridge/intel/i82801ix/bootblock.c
M src/southbridge/intel/i82801ix/early_init.c
M src/southbridge/intel/i82801ix/early_smbus.c
M src/southbridge/intel/i82801ix/i82801ix.c
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801ix/pci.c
M src/southbridge/intel/i82801ix/pcie.c
M src/southbridge/intel/i82801ix/sata.c
M src/southbridge/intel/i82801ix/smi.c
M src/southbridge/intel/i82801ix/thermal.c
M src/southbridge/intel/i82801ix/usb_ehci.c
M src/southbridge/intel/i82801jx/bootblock.c
M src/southbridge/intel/i82801jx/early_smbus.c
M src/southbridge/intel/i82801jx/i82801jx.c
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/i82801jx/pci.c
M src/southbridge/intel/i82801jx/pcie.c
M src/southbridge/intel/i82801jx/sata.c
M src/southbridge/intel/i82801jx/thermal.c
M src/southbridge/intel/i82801jx/usb_ehci.c
M src/southbridge/intel/ibexpeak/early_smbus.c
M src/southbridge/intel/ibexpeak/early_thermal.c
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/ibexpeak/me.c
M src/southbridge/intel/ibexpeak/sata.c
M src/southbridge/intel/ibexpeak/smi.c
M src/southbridge/intel/ibexpeak/smihandler.c
M src/southbridge/intel/ibexpeak/thermal.c
M src/southbridge/intel/ibexpeak/usb_ehci.c
M src/southbridge/intel/lynxpoint/bootblock.c
M src/southbridge/intel/lynxpoint/early_me.c
M src/southbridge/intel/lynxpoint/early_pch.c
M src/southbridge/intel/lynxpoint/early_smbus.c
M src/southbridge/intel/lynxpoint/early_usb.c
M src/southbridge/intel/lynxpoint/lp_gpio.c
M src/southbridge/intel/lynxpoint/me_9.x.c
M src/southbridge/intel/lynxpoint/pch.c
M src/southbridge/intel/lynxpoint/pci.c
M src/southbridge/intel/lynxpoint/sata.c
M src/southbridge/intel/lynxpoint/serialio.c
M src/southbridge/intel/lynxpoint/smihandler.c
M src/southbridge/intel/lynxpoint/usb_ehci.c
M src/southbridge/intel/lynxpoint/usb_xhci.c
M src/southbridge/intel/lynxpoint/watchdog.c
M src/southbridge/nvidia/ck804/bootblock.c
M src/southbridge/nvidia/ck804/early_smbus.c
M src/southbridge/nvidia/ck804/enable_usbdebug.c
M src/southbridge/nvidia/mcp55/bootblock.c
M src/southbridge/nvidia/mcp55/early_smbus.c
M src/southbridge/nvidia/mcp55/enable_usbdebug.c
558 files changed, 557 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/31675/1
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index 20338e0..aecf0b6 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -203,10 +203,6 @@
}
#endif
-/* FIXME: We should avoid this indirect include. Also this has to
- * appear here after all MMIO and IO read/write functions. */
-#include <arch/pci_ops.h>
-
#ifdef __SIMPLE_DEVICE__
#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c
index 9f7c521..2bba084 100644
--- a/src/commonlib/storage/pci_sdhci.c
+++ b/src/commonlib/storage/pci_sdhci.c
@@ -21,6 +21,7 @@
#include <assert.h>
#include <commonlib/sdhci.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include "sd_mmc.h"
#include <stdint.h>
#include "storage.h"
diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
index abf02a3..674ba78 100644
--- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
+++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
@@ -21,6 +21,7 @@
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <cpu/x86/smm.h>
#include <cpu/x86/pae.h>
diff --git a/src/cpu/amd/family_10h-family_15h/monotonic_timer.c b/src/cpu/amd/family_10h-family_15h/monotonic_timer.c
index ad83684..fe01345 100644
--- a/src/cpu/amd/family_10h-family_15h/monotonic_timer.c
+++ b/src/cpu/amd/family_10h-family_15h/monotonic_timer.c
@@ -19,6 +19,7 @@
#include <cpu/amd/msr.h>
#include <timer.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <northbridge/amd/amdht/AsPsDefs.h>
static struct monotonic_counter {
diff --git a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
index cf1646e..2ce4722 100644
--- a/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
+++ b/src/cpu/amd/family_10h-family_15h/powernow_acpi.c
@@ -23,6 +23,7 @@
#include <arch/acpigen.h>
#include <cpu/amd/powernow.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdfam10_sysconf.h>
#include <arch/cpu.h>
diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c
index 57bd2fc..0222bd0 100644
--- a/src/cpu/amd/family_10h-family_15h/ram_calc.c
+++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c
@@ -19,6 +19,7 @@
#include <cpu/amd/mtrr.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c
index f9259c2..000cb88 100644
--- a/src/cpu/amd/quadcore/amd_sibling.c
+++ b/src/cpu/amd/quadcore/amd_sibling.c
@@ -17,6 +17,7 @@
#include <cpu/x86/lapic.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
#include <smp/spinlock.h>
#include <cpu/x86/mtrr.h>
diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c
index 13c5d0f..2ffbd8b 100644
--- a/src/cpu/intel/fsp_model_406dx/bootblock.c
+++ b/src/cpu/intel/fsp_model_406dx/bootblock.c
@@ -20,6 +20,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <reset.h>
#include <southbridge/intel/fsp_rangeley/soc.h>
diff --git a/src/device/cardbus_device.c b/src/device/cardbus_device.c
index b572e85..adfc503 100644
--- a/src/device/cardbus_device.c
+++ b/src/device/cardbus_device.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <device/cardbus.h>
diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c
index ed6b2dd..ccad5ce 100644
--- a/src/device/hypertransport.c
+++ b/src/device/hypertransport.c
@@ -24,6 +24,7 @@
#include <device/device.h>
#include <device/path.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <device/hypertransport.h>
diff --git a/src/device/pci_class.c b/src/device/pci_class.c
index 1326b2c..aa28ce8 100644
--- a/src/device/pci_class.c
+++ b/src/device/pci_class.c
@@ -16,6 +16,7 @@
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
#include <stdlib.h>
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 82033a6..b275788 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -33,6 +33,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <bootmode.h>
#include <console/console.h>
#include <stdlib.h>
diff --git a/src/device/pcix_device.c b/src/device/pcix_device.c
index 1204660..e327b88 100644
--- a/src/device/pcix_device.c
+++ b/src/device/pcix_device.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pcix.h>
static void pcix_tune_dev(struct device *dev)
diff --git a/src/drivers/dec/21143/21143.c b/src/drivers/dec/21143/21143.c
index 36f86f1..3af334b 100644
--- a/src/drivers/dec/21143/21143.c
+++ b/src/drivers/dec/21143/21143.c
@@ -17,6 +17,7 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <console/console.h>
diff --git a/src/drivers/generic/bayhub/bh720.c b/src/drivers/generic/bayhub/bh720.c
index 2ac5387..09fa578 100644
--- a/src/drivers/generic/bayhub/bh720.c
+++ b/src/drivers/generic/bayhub/bh720.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/path.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "chip.h"
#include "bh720.h"
diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c
index f7dc99c..2cfe62b 100644
--- a/src/drivers/intel/gma/vbt.c
+++ b/src/drivers/intel/gma/vbt.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <delay.h>
#include <device/device.h>
#include <string.h>
diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c
index ade5087..bb617d5 100644
--- a/src/drivers/intel/wifi/wifi.c
+++ b/src/drivers/intel/wifi/wifi.c
@@ -20,6 +20,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <elog.h>
#include <sar.h>
diff --git a/src/drivers/net/atl1e.c b/src/drivers/net/atl1e.c
index 7e02e81..bbfe98a 100644
--- a/src/drivers/net/atl1e.c
+++ b/src/drivers/net/atl1e.c
@@ -25,6 +25,7 @@
#include <string.h>
#include <console/console.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#define REG_SPI_FLASH_CTRL 0x200
#define SPI_FLASH_CTRL_EN_VPD 0x2000
diff --git a/src/drivers/ricoh/rce822/rce822.c b/src/drivers/ricoh/rce822/rce822.c
index d576762..57f01dc 100644
--- a/src/drivers/ricoh/rce822/rce822.c
+++ b/src/drivers/ricoh/rce822/rce822.c
@@ -18,6 +18,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include "chip.h"
static void rce822_enable(struct device *dev)
diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c
index 7364a75..168ed6a 100644
--- a/src/drivers/uart/oxpcie.c
+++ b/src/drivers/uart/oxpcie.c
@@ -20,6 +20,7 @@
#include <console/console.h>
#include <console/uart.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
static void oxford_oxpcie_enable(struct device *dev)
{
diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c
index 2a01cb6..b81a7ff 100644
--- a/src/drivers/uart/oxpcie_early.c
+++ b/src/drivers/uart/oxpcie_early.c
@@ -18,6 +18,7 @@
#include <stdint.h>
#include <stddef.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/early_variables.h>
#include <boot/coreboot_tables.h>
#include <console/uart.h>
diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c
index c051291..4028d4b 100644
--- a/src/drivers/usb/pci_ehci.c
+++ b/src/drivers/usb/pci_ehci.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/pci_ehci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <string.h>
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index 71d6b20..814433d 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -23,7 +23,6 @@
#include <device/pci_def.h>
#include <device/resource.h>
#include <device/device.h>
-#include <device/pci_ops.h>
#include <device/pci_rom.h>
diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h
index 54284f5..1118df5 100644
--- a/src/include/device/pci_ops.h
+++ b/src/include/device/pci_ops.h
@@ -99,6 +99,8 @@
pci_write_config32(dev, reg, reg32);
}
+#if !defined(__ROMCC__)
const struct pci_bus_operations *pci_bus_default_ops(struct device *dev);
+#endif
#endif /* PCI_OPS_H */
diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c
index 926a659..ed709ee 100644
--- a/src/lib/reg_script.c
+++ b/src/lib/reg_script.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
diff --git a/src/mainboard/adi/rcc-dff/romstage.c b/src/mainboard/adi/rcc-dff/romstage.c
index 1925c78..3f97c82 100644
--- a/src/mainboard/adi/rcc-dff/romstage.c
+++ b/src/mainboard/adi/rcc-dff/romstage.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index 244dfad..bb830b2 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -19,6 +19,7 @@
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <timestamp.h>
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index a3de524..765bb24 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -19,6 +19,7 @@
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c
index e2bc54e..48f3f34 100644
--- a/src/mainboard/amd/mahogany_fam10/mainboard.c
+++ b/src/mainboard/amd/mahogany_fam10/mainboard.c
@@ -17,6 +17,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
diff --git a/src/mainboard/amd/mahogany_fam10/mptable.c b/src/mainboard/amd/mahogany_fam10/mptable.c
index 895b747..8c6ecf3 100644
--- a/src/mainboard/amd/mahogany_fam10/mptable.c
+++ b/src/mainboard/amd/mahogany_fam10/mptable.c
@@ -16,6 +16,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c
index 4316d4f..b82f0f8 100644
--- a/src/mainboard/amd/olivehill/romstage.c
+++ b/src/mainboard/amd/olivehill/romstage.c
@@ -17,6 +17,7 @@
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <commonlib/loglevel.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c
index 1eb9203..397f361 100644
--- a/src/mainboard/amd/parmer/romstage.c
+++ b/src/mainboard/amd/parmer/romstage.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
index 59d5673..33a81c6 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
@@ -15,6 +15,7 @@
#include <console/console.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/multicore.h>
diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c
index 11d6837..ed22ed1 100644
--- a/src/mainboard/amd/thatcher/romstage.c
+++ b/src/mainboard/amd/thatcher/romstage.c
@@ -18,6 +18,7 @@
#include <device/pci_def.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <commonlib/loglevel.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c
index ec0144a..63d3671 100644
--- a/src/mainboard/amd/tilapia_fam10/mainboard.c
+++ b/src/mainboard/amd/tilapia_fam10/mainboard.c
@@ -17,6 +17,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
diff --git a/src/mainboard/amd/tilapia_fam10/mptable.c b/src/mainboard/amd/tilapia_fam10/mptable.c
index 895b747..8c6ecf3 100644
--- a/src/mainboard/amd/tilapia_fam10/mptable.c
+++ b/src/mainboard/amd/tilapia_fam10/mptable.c
@@ -16,6 +16,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c
index 299cac6..9a376d4 100644
--- a/src/mainboard/aopen/dxplplusu/fadt.c
+++ b/src/mainboard/aopen/dxplplusu/fadt.c
@@ -15,6 +15,7 @@
#include <string.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <arch/acpi.h>
#include <version.h>
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index 291eabb..570360d 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -20,6 +20,7 @@
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/intel/romstage.h>
#include <cpu/x86/lapic.h>
diff --git a/src/mainboard/apple/macbookair4_2/romstage.c b/src/mainboard/apple/macbookair4_2/romstage.c
index 1a365b1..7ccbd6d 100644
--- a/src/mainboard/apple/macbookair4_2/romstage.c
+++ b/src/mainboard/apple/macbookair4_2/romstage.c
@@ -15,6 +15,7 @@
#include <string.h>
#include <arch/byteorder.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
diff --git a/src/mainboard/asrock/b75pro3-m/romstage.c b/src/mainboard/asrock/b75pro3-m/romstage.c
index 050d6c5..205c08c 100644
--- a/src/mainboard/asrock/b75pro3-m/romstage.c
+++ b/src/mainboard/asrock/b75pro3-m/romstage.c
@@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <superio/nuvoton/nct6776/nct6776.h>
#include <superio/nuvoton/common/nuvoton.h>
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c
index ab6b1d8..12f5cd4 100644
--- a/src/mainboard/asrock/g41c-gs/romstage.c
+++ b/src/mainboard/asrock/g41c-gs/romstage.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 0081c2f..83fc9a0 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -18,6 +18,7 @@
#include <device/pci_def.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <commonlib/loglevel.h>
#include <northbridge/amd/agesa/state_machine.h>
diff --git a/src/mainboard/asus/am1i-a/romstage.c b/src/mainboard/asus/am1i-a/romstage.c
index 76e2290..c42b86c 100644
--- a/src/mainboard/asus/am1i-a/romstage.c
+++ b/src/mainboard/asus/am1i-a/romstage.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <commonlib/loglevel.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/common/amd_defs.h>
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index d540bf0..db50765 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/common/amd_defs.h>
diff --git a/src/mainboard/asus/h61m-cs/romstage.c b/src/mainboard/asus/h61m-cs/romstage.c
index 0b62286..a0083fb 100644
--- a/src/mainboard/asus/h61m-cs/romstage.c
+++ b/src/mainboard/asus/h61m-cs/romstage.c
@@ -16,6 +16,7 @@
*/
#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <superio/nuvoton/common/nuvoton.h>
diff --git a/src/mainboard/asus/kcma-d8/acpi_tables.c b/src/mainboard/asus/kcma-d8/acpi_tables.c
index ef07460..52840ca 100644
--- a/src/mainboard/asus/kcma-d8/acpi_tables.c
+++ b/src/mainboard/asus/kcma-d8/acpi_tables.c
@@ -18,6 +18,7 @@
#include <arch/acpi.h>
#include <arch/ioapic.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <cpu/amd/amdfam10_sysconf.h>
unsigned long acpi_fill_madt(unsigned long current)
diff --git a/src/mainboard/asus/kcma-d8/bootblock.c b/src/mainboard/asus/kcma-d8/bootblock.c
index 4e8a790..01c99ba 100644
--- a/src/mainboard/asus/kcma-d8/bootblock.c
+++ b/src/mainboard/asus/kcma-d8/bootblock.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
void bootblock_mainboard_init(void)
diff --git a/src/mainboard/asus/kcma-d8/mainboard.c b/src/mainboard/asus/kcma-d8/mainboard.c
index 729ad35..dca89ef 100644
--- a/src/mainboard/asus/kcma-d8/mainboard.c
+++ b/src/mainboard/asus/kcma-d8/mainboard.c
@@ -18,6 +18,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
diff --git a/src/mainboard/asus/kcma-d8/mptable.c b/src/mainboard/asus/kcma-d8/mptable.c
index 22dbd1a..452c7a5 100644
--- a/src/mainboard/asus/kcma-d8/mptable.c
+++ b/src/mainboard/asus/kcma-d8/mptable.c
@@ -17,6 +17,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c
index 4493b25..028af4c 100644
--- a/src/mainboard/asus/kcma-d8/romstage.c
+++ b/src/mainboard/asus/kcma-d8/romstage.c
@@ -21,6 +21,7 @@
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
diff --git a/src/mainboard/asus/kfsn4-dre/acpi_tables.c b/src/mainboard/asus/kfsn4-dre/acpi_tables.c
index e5e2613..530521b 100644
--- a/src/mainboard/asus/kfsn4-dre/acpi_tables.c
+++ b/src/mainboard/asus/kfsn4-dre/acpi_tables.c
@@ -24,6 +24,7 @@
#include <assert.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c
index 806bad9..82172e8 100644
--- a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c
+++ b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c
@@ -20,6 +20,7 @@
#include <console/console.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
diff --git a/src/mainboard/asus/kfsn4-dre/mptable.c b/src/mainboard/asus/kfsn4-dre/mptable.c
index 69ea301..ad3f742 100644
--- a/src/mainboard/asus/kfsn4-dre/mptable.c
+++ b/src/mainboard/asus/kfsn4-dre/mptable.c
@@ -24,6 +24,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
index e25120e..66ebbdc 100644
--- a/src/mainboard/asus/kfsn4-dre/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre/romstage.c
@@ -22,6 +22,7 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
diff --git a/src/mainboard/asus/kgpe-d16/acpi_tables.c b/src/mainboard/asus/kgpe-d16/acpi_tables.c
index ef07460..52840ca 100644
--- a/src/mainboard/asus/kgpe-d16/acpi_tables.c
+++ b/src/mainboard/asus/kgpe-d16/acpi_tables.c
@@ -18,6 +18,7 @@
#include <arch/acpi.h>
#include <arch/ioapic.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <cpu/amd/amdfam10_sysconf.h>
unsigned long acpi_fill_madt(unsigned long current)
diff --git a/src/mainboard/asus/kgpe-d16/bootblock.c b/src/mainboard/asus/kgpe-d16/bootblock.c
index 4e8a790..01c99ba 100644
--- a/src/mainboard/asus/kgpe-d16/bootblock.c
+++ b/src/mainboard/asus/kgpe-d16/bootblock.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
void bootblock_mainboard_init(void)
diff --git a/src/mainboard/asus/kgpe-d16/mainboard.c b/src/mainboard/asus/kgpe-d16/mainboard.c
index d41a038..564826b 100644
--- a/src/mainboard/asus/kgpe-d16/mainboard.c
+++ b/src/mainboard/asus/kgpe-d16/mainboard.c
@@ -18,6 +18,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
diff --git a/src/mainboard/asus/kgpe-d16/mptable.c b/src/mainboard/asus/kgpe-d16/mptable.c
index e91a424..fa31fc5 100644
--- a/src/mainboard/asus/kgpe-d16/mptable.c
+++ b/src/mainboard/asus/kgpe-d16/mptable.c
@@ -17,6 +17,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index a14d944..5c4dbe8 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -21,6 +21,7 @@
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c
index fb01236..1607e7f 100644
--- a/src/mainboard/asus/m4a78-em/mainboard.c
+++ b/src/mainboard/asus/m4a78-em/mainboard.c
@@ -17,6 +17,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c
index 895b747..8c6ecf3 100644
--- a/src/mainboard/asus/m4a78-em/mptable.c
+++ b/src/mainboard/asus/m4a78-em/mptable.c
@@ -16,6 +16,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c
index 6d0f549..f5683f8 100644
--- a/src/mainboard/asus/m4a785-m/mainboard.c
+++ b/src/mainboard/asus/m4a785-m/mainboard.c
@@ -17,6 +17,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c
index 895b747..8c6ecf3 100644
--- a/src/mainboard/asus/m4a785-m/mptable.c
+++ b/src/mainboard/asus/m4a785-m/mptable.c
@@ -16,6 +16,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index d86db7a..0fe961f 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -21,6 +21,7 @@
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index 2a9a292..6493809 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -20,6 +20,7 @@
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c
index 5d585c8..fa8408d 100644
--- a/src/mainboard/asus/p5qc/romstage.c
+++ b/src/mainboard/asus/p5qc/romstage.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <southbridge/intel/i82801jx/i82801jx.h>
#include <southbridge/intel/common/gpio.h>
diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c
index 7f84b6a..c172ef8 100644
--- a/src/mainboard/asus/p5qpl-am/romstage.c
+++ b/src/mainboard/asus/p5qpl-am/romstage.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
#include <cpu/intel/speedstep.h>
diff --git a/src/mainboard/asus/p8h61-m_pro/romstage.c b/src/mainboard/asus/p8h61-m_pro/romstage.c
index a6785ed..63daa2e 100644
--- a/src/mainboard/asus/p8h61-m_pro/romstage.c
+++ b/src/mainboard/asus/p8h61-m_pro/romstage.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index d3794af..8e9fedb 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -19,6 +19,7 @@
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c
index 9921f36..ef7a7fb 100644
--- a/src/mainboard/bap/ode_e20XX/romstage.c
+++ b/src/mainboard/bap/ode_e20XX/romstage.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <northbridge/amd/agesa/state_machine.h>
diff --git a/src/mainboard/biostar/a68n_5200/romstage.c b/src/mainboard/biostar/a68n_5200/romstage.c
index f587257..15834fb 100644
--- a/src/mainboard/biostar/a68n_5200/romstage.c
+++ b/src/mainboard/biostar/a68n_5200/romstage.c
@@ -19,6 +19,7 @@
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <commonlib/loglevel.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c
index 94d2abe..9ac32a3 100644
--- a/src/mainboard/biostar/am1ml/romstage.c
+++ b/src/mainboard/biostar/am1ml/romstage.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <northbridge/amd/agesa/state_machine.h>
diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c
index a913f77..3cb7067 100644
--- a/src/mainboard/compulab/intense_pc/romstage.c
+++ b/src/mainboard/compulab/intense_pc/romstage.c
@@ -15,6 +15,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <superio/smsc/sio1007/chip.h>
diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c
index 0ff4c54..1493565 100644
--- a/src/mainboard/emulation/qemu-i440fx/northbridge.c
+++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c
@@ -15,6 +15,7 @@
#include <cpu/cpu.h>
#include <cpu/x86/lapic_def.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <stdint.h>
#include <device/device.h>
diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c
index b291936..e665073 100644
--- a/src/mainboard/emulation/qemu-q35/acpi_tables.c
+++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c
@@ -21,6 +21,7 @@
#include <arch/smp/mpspec.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <version.h>
#include "../qemu-i440fx/fw_cfg.h"
diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c
index 18a083d..5ee5fc9 100644
--- a/src/mainboard/emulation/qemu-q35/bootblock.c
+++ b/src/mainboard/emulation/qemu-q35/bootblock.c
@@ -12,6 +12,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <bootblock_common.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/romstage.c
index c88123b..fefc5f9 100644
--- a/src/mainboard/foxconn/d41s/romstage.c
+++ b/src/mainboard/foxconn/d41s/romstage.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#include <northbridge/intel/pineview/pineview.h>
#include <superio/ite/common/ite.h>
diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c
index 7c1402a..e6301df 100644
--- a/src/mainboard/foxconn/g41s-k/romstage.c
+++ b/src/mainboard/foxconn/g41s-k/romstage.c
@@ -18,6 +18,7 @@
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
+#include <device/pci_ops.h>
#include <northbridge/intel/x4x/iomap.h>
#include <northbridge/intel/x4x/x4x.h>
#include <southbridge/intel/common/gpio.h>
diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c
index 5d271fd..20e7230 100644
--- a/src/mainboard/getac/p470/mainboard.c
+++ b/src/mainboard/getac/p470/mainboard.c
@@ -17,6 +17,7 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <delay.h>
#include <drivers/intel/gma/int15.h>
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 3f80664..dcfd27f 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -17,6 +17,7 @@
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
index a9d3c25..8d714a0 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
@@ -19,6 +19,7 @@
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
index dbb015d..aa5f484 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
index 89f475e..035e20e 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index 2b9f4fb..c5d731c 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -17,6 +17,7 @@
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#include <southbridge/intel/common/gpio.h>
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
index f1cd176..7154cc9 100644
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c
@@ -13,6 +13,7 @@
* GNU General Public License for more details.
*/
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c
index d11deb0..ddf55b6 100644
--- a/src/mainboard/gigabyte/ma785gm/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gm/mainboard.c
@@ -17,6 +17,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
diff --git a/src/mainboard/gigabyte/ma785gm/mptable.c b/src/mainboard/gigabyte/ma785gm/mptable.c
index 895b747..8c6ecf3 100644
--- a/src/mainboard/gigabyte/ma785gm/mptable.c
+++ b/src/mainboard/gigabyte/ma785gm/mptable.c
@@ -16,6 +16,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c
index 3b4edee..22f71d0 100644
--- a/src/mainboard/gigabyte/ma785gmt/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c
@@ -17,6 +17,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
diff --git a/src/mainboard/gigabyte/ma785gmt/mptable.c b/src/mainboard/gigabyte/ma785gmt/mptable.c
index 895b747..8c6ecf3 100644
--- a/src/mainboard/gigabyte/ma785gmt/mptable.c
+++ b/src/mainboard/gigabyte/ma785gmt/mptable.c
@@ -16,6 +16,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c
index ff52b7b..1fe75df 100644
--- a/src/mainboard/gigabyte/ma78gm/mainboard.c
+++ b/src/mainboard/gigabyte/ma78gm/mainboard.c
@@ -18,6 +18,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
diff --git a/src/mainboard/gigabyte/ma78gm/mptable.c b/src/mainboard/gigabyte/ma78gm/mptable.c
index 895b747..8c6ecf3 100644
--- a/src/mainboard/gigabyte/ma78gm/mptable.c
+++ b/src/mainboard/gigabyte/ma78gm/mptable.c
@@ -16,6 +16,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c
index 283bea1..c656347 100644
--- a/src/mainboard/gizmosphere/gizmo2/romstage.c
+++ b/src/mainboard/gizmosphere/gizmo2/romstage.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
diff --git a/src/mainboard/google/auron/variants/buddy/variant.c b/src/mainboard/google/auron/variants/buddy/variant.c
index 23942fb..d072fd9 100644
--- a/src/mainboard/google/auron/variants/buddy/variant.c
+++ b/src/mainboard/google/auron/variants/buddy/variant.c
@@ -16,6 +16,7 @@
#include <types.h>
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c
index 0be19fa..0d7406d 100644
--- a/src/mainboard/google/beltino/chromeos.c
+++ b/src/mainboard/google/beltino/chromeos.c
@@ -15,6 +15,7 @@
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <bootmode.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/mainboard/google/beltino/lan.c b/src/mainboard/google/beltino/lan.c
index 140c814..1d0bc43 100644
--- a/src/mainboard/google/beltino/lan.c
+++ b/src/mainboard/google/beltino/lan.c
@@ -17,6 +17,7 @@
#include <string.h>
#include <types.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c
index da137b0..6aebaeb 100644
--- a/src/mainboard/google/butterfly/chromeos.c
+++ b/src/mainboard/google/butterfly/chromeos.c
@@ -17,6 +17,7 @@
#include <string.h>
#include <bootmode.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
index 0166997..cb3f139 100644
--- a/src/mainboard/google/butterfly/romstage.c
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -18,6 +18,7 @@
#include <string.h>
#include <timestamp.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
diff --git a/src/mainboard/google/cyan/com_init.c b/src/mainboard/google/cyan/com_init.c
index 3560a0f..e4fe6be 100644
--- a/src/mainboard/google/cyan/com_init.c
+++ b/src/mainboard/google/cyan/com_init.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <soc/gpio.h>
#include <soc/lpc.h>
#include <soc/pci_devs.h>
diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c
index d7e48a0..1e8ea94 100644
--- a/src/mainboard/google/jecht/chromeos.c
+++ b/src/mainboard/google/jecht/chromeos.c
@@ -15,6 +15,7 @@
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <vendorcode/google/chromeos/chromeos.h>
diff --git a/src/mainboard/google/jecht/lan.c b/src/mainboard/google/jecht/lan.c
index 59ed111..9735ca0 100644
--- a/src/mainboard/google/jecht/lan.c
+++ b/src/mainboard/google/jecht/lan.c
@@ -18,6 +18,7 @@
#include <types.h>
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c
index 71aca73..6600793 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c
@@ -20,6 +20,7 @@
#include <smbios.h>
#include <variant/gpio.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <drivers/generic/bayhub/bh720.h>
uint8_t variant_board_sku(void)
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 91f8297..d9755be 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -18,6 +18,7 @@
#include <string.h>
#include <timestamp.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c
index bc605aa..6efd57a 100644
--- a/src/mainboard/google/parrot/chromeos.c
+++ b/src/mainboard/google/parrot/chromeos.c
@@ -17,6 +17,7 @@
#include <string.h>
#include <bootmode.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index 186d16d..f6eb78a 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -18,6 +18,7 @@
#include <string.h>
#include <timestamp.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
diff --git a/src/mainboard/google/poppy/variants/nautilus/mainboard.c b/src/mainboard/google/poppy/variants/nautilus/mainboard.c
index bacf1a4..f11bde4 100644
--- a/src/mainboard/google/poppy/variants/nautilus/mainboard.c
+++ b/src/mainboard/google/poppy/variants/nautilus/mainboard.c
@@ -17,6 +17,7 @@
#include <chip.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <smbios.h>
#include <string.h>
#include <variant/sku.h>
diff --git a/src/mainboard/google/rambi/variants/ninja/lan.c b/src/mainboard/google/rambi/variants/ninja/lan.c
index 3d08ad7..87df672 100644
--- a/src/mainboard/google/rambi/variants/ninja/lan.c
+++ b/src/mainboard/google/rambi/variants/ninja/lan.c
@@ -17,6 +17,7 @@
#include <string.h>
#include <types.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/mainboard/google/rambi/variants/sumo/lan.c b/src/mainboard/google/rambi/variants/sumo/lan.c
index 07fe3d9..5dae431 100644
--- a/src/mainboard/google/rambi/variants/sumo/lan.c
+++ b/src/mainboard/google/rambi/variants/sumo/lan.c
@@ -17,6 +17,7 @@
#include <string.h>
#include <types.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c
index 5301d30..090cd6c 100644
--- a/src/mainboard/google/stout/chromeos.c
+++ b/src/mainboard/google/stout/chromeos.c
@@ -16,6 +16,7 @@
#include <string.h>
#include <bootmode.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c
index 6a51645..77d7a05 100644
--- a/src/mainboard/google/stout/mainboard_smi.c
+++ b/src/mainboard/google/stout/mainboard_smi.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <southbridge/intel/bd82x6x/nvs.h>
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index d212951..ab25b14 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -18,6 +18,7 @@
#include <string.h>
#include <timestamp.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
diff --git a/src/mainboard/hp/2570p/romstage.c b/src/mainboard/hp/2570p/romstage.c
index b2095b9..0d6e65c 100644
--- a/src/mainboard/hp/2570p/romstage.c
+++ b/src/mainboard/hp/2570p/romstage.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/hp/2760p/romstage.c b/src/mainboard/hp/2760p/romstage.c
index c6d9a7c..92a935a 100644
--- a/src/mainboard/hp/2760p/romstage.c
+++ b/src/mainboard/hp/2760p/romstage.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c
index b97d5e4..dd95def 100644
--- a/src/mainboard/hp/8460p/romstage.c
+++ b/src/mainboard/hp/8460p/romstage.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/hp/8470p/romstage.c b/src/mainboard/hp/8470p/romstage.c
index bb9298c..7e18fb2 100644
--- a/src/mainboard/hp/8470p/romstage.c
+++ b/src/mainboard/hp/8470p/romstage.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/hp/8770w/romstage.c b/src/mainboard/hp/8770w/romstage.c
index 75c2db0..6cce331 100644
--- a/src/mainboard/hp/8770w/romstage.c
+++ b/src/mainboard/hp/8770w/romstage.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 6b54103..2cc8d1b 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <southbridge/amd/agesa/hudson/hudson.h>
#include <superio/nuvoton/common/nuvoton.h>
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c
index 49bce1c..3ad60eb 100644
--- a/src/mainboard/hp/compaq_8200_elite_sff/romstage.c
+++ b/src/mainboard/hp/compaq_8200_elite_sff/romstage.c
@@ -19,6 +19,7 @@
#include <stdint.h>
#include <arch/byteorder.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <superio/nuvoton/npcd378/npcd378.h>
#include <superio/nuvoton/common/nuvoton.h>
diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
index 4a5c610..e217aa7 100644
--- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
+++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/multicore.h>
diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c
index 6c9a001..f6c72da 100644
--- a/src/mainboard/hp/dl165_g6_fam10/mptable.c
+++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c
@@ -26,6 +26,7 @@
#include <console/console.h>
#include <arch/smp/mpspec.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci.h>
#include <string.h>
#include <stdint.h>
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index 6d2eed4..7eaff57 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -25,6 +25,7 @@
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include "option_table.h"
diff --git a/src/mainboard/hp/folio_9470m/romstage.c b/src/mainboard/hp/folio_9470m/romstage.c
index 1994c4f..5230245 100644
--- a/src/mainboard/hp/folio_9470m/romstage.c
+++ b/src/mainboard/hp/folio_9470m/romstage.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/hp/revolve_810_g1/romstage.c b/src/mainboard/hp/revolve_810_g1/romstage.c
index c70660a..9925709 100644
--- a/src/mainboard/hp/revolve_810_g1/romstage.c
+++ b/src/mainboard/hp/revolve_810_g1/romstage.c
@@ -19,6 +19,7 @@
#include <cbfs.h>
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 9eaa8de..fd0db72 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -18,6 +18,7 @@
#include <stdint.h>
#include <halt.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/iei/kino-780am2-fam10/mptable.c b/src/mainboard/iei/kino-780am2-fam10/mptable.c
index 895b747..8c6ecf3 100644
--- a/src/mainboard/iei/kino-780am2-fam10/mptable.c
+++ b/src/mainboard/iei/kino-780am2-fam10/mptable.c
@@ -16,6 +16,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c
index 0e58959..69e1050 100644
--- a/src/mainboard/intel/baskingridge/chromeos.c
+++ b/src/mainboard/intel/baskingridge/chromeos.c
@@ -16,6 +16,7 @@
#include <string.h>
#include <bootmode.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index 550bac5..aadd833 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#include <northbridge/intel/pineview/pineview.h>
#include <superio/winbond/w83627thg/w83627thg.h>
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 426ee69..44f785f 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -18,6 +18,7 @@
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cpu/x86/lapic.h>
#include <superio/smsc/lpc47m15x/lpc47m15x.h>
#include <console/console.h>
diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c
index c4be4d50..233800a 100644
--- a/src/mainboard/intel/dcp847ske/early_southbridge.c
+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c
@@ -19,6 +19,7 @@
#include <stdint.h>
#include <halt.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <arch/acpi.h>
#include <console/console.h>
diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c
index 2caf5ec..64e8dd9 100644
--- a/src/mainboard/intel/dg41wv/romstage.c
+++ b/src/mainboard/intel/dg41wv/romstage.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
#include <cpu/x86/bist.h>
diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c
index c16160e..6a93cea 100644
--- a/src/mainboard/intel/dg43gt/romstage.c
+++ b/src/mainboard/intel/dg43gt/romstage.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <southbridge/intel/i82801jx/i82801jx.h>
#include <southbridge/intel/common/gpio.h>
diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c
index 8967a21..24f8875 100644
--- a/src/mainboard/intel/emeraldlake2/chromeos.c
+++ b/src/mainboard/intel/emeraldlake2/chromeos.c
@@ -16,6 +16,7 @@
#include <string.h>
#include <bootmode.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index b43a9b0..4074a30 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -18,6 +18,7 @@
#include <string.h>
#include <timestamp.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
diff --git a/src/mainboard/intel/littleplains/romstage.c b/src/mainboard/intel/littleplains/romstage.c
index 1925c78..3f97c82 100644
--- a/src/mainboard/intel/littleplains/romstage.c
+++ b/src/mainboard/intel/littleplains/romstage.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
diff --git a/src/mainboard/intel/mohonpeak/romstage.c b/src/mainboard/intel/mohonpeak/romstage.c
index 1925c78..3f97c82 100644
--- a/src/mainboard/intel/mohonpeak/romstage.c
+++ b/src/mainboard/intel/mohonpeak/romstage.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
diff --git a/src/mainboard/intel/strago/com_init.c b/src/mainboard/intel/strago/com_init.c
index 36cd1c1..e1e6476 100644
--- a/src/mainboard/intel/strago/com_init.c
+++ b/src/mainboard/intel/strago/com_init.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <soc/gpio.h>
#include <soc/lpc.h>
#include <soc/pci_devs.h>
diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c
index 444cd33..e2d39da 100644
--- a/src/mainboard/jetway/pa78vm5/mainboard.c
+++ b/src/mainboard/jetway/pa78vm5/mainboard.c
@@ -18,6 +18,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
diff --git a/src/mainboard/jetway/pa78vm5/mptable.c b/src/mainboard/jetway/pa78vm5/mptable.c
index db94b02..08df943 100644
--- a/src/mainboard/jetway/pa78vm5/mptable.c
+++ b/src/mainboard/jetway/pa78vm5/mptable.c
@@ -17,6 +17,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index fda8f97..0777412 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -22,6 +22,7 @@
#include <cpu/x86/bist.h>
#include <cpu/x86/lapic.h>
#include <device/pci_def.h>
+#include <device/pci_ops.h>
#include <device/pnp_def.h>
#include <pc80/mc146818rtc.h>
#include <northbridge/intel/i945/i945.h>
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index ea93e05..5333099 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -18,6 +18,7 @@
#include <string.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/msr.h>
#include <device/pci_def.h>
diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c
index d9e021b..c2539b1 100644
--- a/src/mainboard/lenovo/l520/romstage.c
+++ b/src/mainboard/lenovo/l520/romstage.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c
index beeb96d..ef3c835 100644
--- a/src/mainboard/lenovo/s230u/romstage.c
+++ b/src/mainboard/lenovo/s230u/romstage.c
@@ -18,6 +18,7 @@
#include <cbfs.h>
#include <arch/byteorder.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
diff --git a/src/mainboard/lenovo/t400/fadt.c b/src/mainboard/lenovo/t400/fadt.c
index e361e8d..2977492 100644
--- a/src/mainboard/lenovo/t400/fadt.c
+++ b/src/mainboard/lenovo/t400/fadt.c
@@ -16,6 +16,7 @@
#include <string.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <arch/acpi.h>
#include <cpu/x86/smm.h>
#include <version.h>
diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index 9f8993c..0be24eb 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -17,6 +17,7 @@
// __PRE_RAM__ means: use "unsigned" for device, not a struct.
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <southbridge/intel/common/gpio.h>
diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c
index aad8348..d497e0c 100644
--- a/src/mainboard/lenovo/t420/romstage.c
+++ b/src/mainboard/lenovo/t420/romstage.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c
index 5754a6d..1a7d341 100644
--- a/src/mainboard/lenovo/t420s/romstage.c
+++ b/src/mainboard/lenovo/t420s/romstage.c
@@ -17,6 +17,7 @@
#include <arch/byteorder.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c
index 0e8e6d0..be4228d 100644
--- a/src/mainboard/lenovo/t420s/smihandler.c
+++ b/src/mainboard/lenovo/t420s/smihandler.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <ec/acpi/ec.h>
diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c
index 90d0886..b5dc2bc 100644
--- a/src/mainboard/lenovo/t430/romstage.c
+++ b/src/mainboard/lenovo/t430/romstage.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c
index ab2bb0a..4edd5c6 100644
--- a/src/mainboard/lenovo/t430s/romstage.c
+++ b/src/mainboard/lenovo/t430s/romstage.c
@@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/lenovo/t430s/smihandler.c b/src/mainboard/lenovo/t430s/smihandler.c
index d69f6b6..876d81c 100644
--- a/src/mainboard/lenovo/t430s/smihandler.c
+++ b/src/mainboard/lenovo/t430s/smihandler.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <ec/acpi/ec.h>
diff --git a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c
index 1b1c4b2..33d65dd 100644
--- a/src/mainboard/lenovo/t430s/variants/t430s/romstage.c
+++ b/src/mainboard/lenovo/t430s/variants/t430s/romstage.c
@@ -18,6 +18,7 @@
#include <option.h>
#include <arch/byteorder.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c
index b7bdbbb..6f95250 100644
--- a/src/mainboard/lenovo/t520/romstage.c
+++ b/src/mainboard/lenovo/t520/romstage.c
@@ -18,6 +18,7 @@
#include <stdint.h>
#include <arch/byteorder.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c
index f8400dd..88ce504 100644
--- a/src/mainboard/lenovo/t520/smihandler.c
+++ b/src/mainboard/lenovo/t520/smihandler.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <ec/acpi/ec.h>
diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c
index 065cff6..d37f0d1 100644
--- a/src/mainboard/lenovo/t530/romstage.c
+++ b/src/mainboard/lenovo/t530/romstage.c
@@ -18,6 +18,7 @@
#include <stdint.h>
#include <arch/byteorder.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c
index 150232f..bf0f81f 100644
--- a/src/mainboard/lenovo/t530/smihandler.c
+++ b/src/mainboard/lenovo/t530/smihandler.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <ec/acpi/ec.h>
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 3017357..a8efa99 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -20,6 +20,7 @@
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c
index aa29984..51ced89 100644
--- a/src/mainboard/lenovo/t60/smihandler.c
+++ b/src/mainboard/lenovo/t60/smihandler.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <southbridge/intel/i82801gx/nvs.h>
diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
index cac09d1..f377c89 100644
--- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c
+++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c
@@ -21,6 +21,7 @@
#include <northbridge/intel/x4x/x4x.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
+#include <device/pci_ops.h>
#include <superio/smsc/smscsuperio/smscsuperio.h>
#include <northbridge/intel/x4x/iomap.h>
diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c
index 43e0bd7..c1a082f 100644
--- a/src/mainboard/lenovo/x131e/romstage.c
+++ b/src/mainboard/lenovo/x131e/romstage.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
index 7f6181b..fa7af40 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c
@@ -21,6 +21,7 @@
#include <timestamp.h>
#include <arch/byteorder.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
diff --git a/src/mainboard/lenovo/x200/dock.c b/src/mainboard/lenovo/x200/dock.c
index dc5eabf..6e87644 100644
--- a/src/mainboard/lenovo/x200/dock.c
+++ b/src/mainboard/lenovo/x200/dock.c
@@ -18,6 +18,7 @@
#define __SIMPLE_DEVICE__
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <delay.h>
diff --git a/src/mainboard/lenovo/x200/fadt.c b/src/mainboard/lenovo/x200/fadt.c
index e361e8d..2977492 100644
--- a/src/mainboard/lenovo/x200/fadt.c
+++ b/src/mainboard/lenovo/x200/fadt.c
@@ -16,6 +16,7 @@
#include <string.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <arch/acpi.h>
#include <cpu/x86/smm.h>
#include <version.h>
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index e8bbfb0..7e428e4 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -17,6 +17,7 @@
// __PRE_RAM__ means: use "unsigned" for device, not a struct.
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <northbridge/intel/gm45/gm45.h>
diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c
index a25fc70..04050f2 100644
--- a/src/mainboard/lenovo/x201/dock.c
+++ b/src/mainboard/lenovo/x201/dock.c
@@ -18,6 +18,7 @@
#define __SIMPLE_DEVICE__
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include "dock.h"
diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c
index eb686f4..5347429 100644
--- a/src/mainboard/lenovo/x201/mainboard.c
+++ b/src/mainboard/lenovo/x201/mainboard.c
@@ -19,6 +19,7 @@
#include <console/console.h>
#include <device/device.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <ec/acpi/ec.h>
#include <northbridge/intel/nehalem/nehalem.h>
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 601c4ae..caaeffc 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -21,6 +21,7 @@
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <lib.h>
diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c
index f1e2c3f..e733b3b 100644
--- a/src/mainboard/lenovo/x201/smihandler.c
+++ b/src/mainboard/lenovo/x201/smihandler.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <southbridge/intel/ibexpeak/nvs.h>
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index 2d6c2a7..a5b1b52 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -20,6 +20,7 @@
#include <timestamp.h>
#include <arch/byteorder.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c
index 150232f..bf0f81f 100644
--- a/src/mainboard/lenovo/x220/smihandler.c
+++ b/src/mainboard/lenovo/x220/smihandler.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <ec/acpi/ec.h>
diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c
index 6a47ac0..5014a76 100644
--- a/src/mainboard/lenovo/x230/romstage.c
+++ b/src/mainboard/lenovo/x230/romstage.c
@@ -20,6 +20,7 @@
#include <timestamp.h>
#include <arch/byteorder.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 6f66c88..4a9757d 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -20,6 +20,7 @@
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
diff --git a/src/mainboard/lenovo/x60/smihandler.c b/src/mainboard/lenovo/x60/smihandler.c
index 3c8565d..18e5046 100644
--- a/src/mainboard/lenovo/x60/smihandler.c
+++ b/src/mainboard/lenovo/x60/smihandler.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <southbridge/intel/i82801gx/nvs.h>
diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c
index 6eceaeb..33700fe 100644
--- a/src/mainboard/lenovo/z61t/romstage.c
+++ b/src/mainboard/lenovo/z61t/romstage.c
@@ -20,6 +20,7 @@
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
diff --git a/src/mainboard/lenovo/z61t/smihandler.c b/src/mainboard/lenovo/z61t/smihandler.c
index 4f62224..eacbd5e 100644
--- a/src/mainboard/lenovo/z61t/smihandler.c
+++ b/src/mainboard/lenovo/z61t/smihandler.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <southbridge/intel/i82801gx/nvs.h>
diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c
index 9660a73..cdd3f80 100644
--- a/src/mainboard/lippert/frontrunner-af/mainboard.c
+++ b/src/mainboard/lippert/frontrunner-af/mainboard.c
@@ -18,6 +18,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb800/sb800.h>
#include <arch/acpi.h>
diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c
index 5cb0916..ddea58d 100644
--- a/src/mainboard/lippert/toucan-af/mainboard.c
+++ b/src/mainboard/lippert/toucan-af/mainboard.c
@@ -18,6 +18,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb800/sb800.h>
#include <arch/acpi.h>
diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c
index ed1e7d4..1fa2fd8 100644
--- a/src/mainboard/msi/ms7721/romstage.c
+++ b/src/mainboard/msi/ms7721/romstage.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pnp.h>
#include <stdint.h>
diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
index a56242f..8c7f921 100644
--- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
+++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/multicore.h>
diff --git a/src/mainboard/msi/ms9652_fam10/mptable.c b/src/mainboard/msi/ms9652_fam10/mptable.c
index 63816dc..f3947e7 100644
--- a/src/mainboard/msi/ms9652_fam10/mptable.c
+++ b/src/mainboard/msi/ms9652_fam10/mptable.c
@@ -17,6 +17,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index b5acf36..2316a05 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -20,6 +20,7 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
diff --git a/src/mainboard/ocp/wedge100s/romstage.c b/src/mainboard/ocp/wedge100s/romstage.c
index e14a09f..b8da280 100644
--- a/src/mainboard/ocp/wedge100s/romstage.c
+++ b/src/mainboard/ocp/wedge100s/romstage.c
@@ -20,6 +20,7 @@
#include <cpu/x86/msr.h>
#include <cf9_reset.h>
#include <console/console.h>
+#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/lpc.h>
#include <superio/ite/common/ite.h>
diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c
index 992da7b..88589b0 100644
--- a/src/mainboard/packardbell/ms2290/romstage.c
+++ b/src/mainboard/packardbell/ms2290/romstage.c
@@ -21,6 +21,7 @@
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <lib.h>
diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c
index e0f16f3..e4c29b1d 100644
--- a/src/mainboard/packardbell/ms2290/smihandler.c
+++ b/src/mainboard/packardbell/ms2290/smihandler.c
@@ -16,6 +16,7 @@
#include <console/console.h>
#include <cpu/x86/smm.h>
+#include <device/pci_ops.h>
#include <southbridge/intel/ibexpeak/nvs.h>
#include <southbridge/intel/ibexpeak/pch.h>
#include <southbridge/intel/ibexpeak/me.h>
diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c
index a9ce66b..3b7d0f5 100644
--- a/src/mainboard/pcengines/apu1/mainboard.c
+++ b/src/mainboard/pcengines/apu1/mainboard.c
@@ -18,6 +18,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <southbridge/amd/common/amd_pci_util.h>
#include <southbridge/amd/cimx/cimx_util.h>
diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c
index b875437..e8b52dd 100644
--- a/src/mainboard/pcengines/apu2/mainboard.c
+++ b/src/mainboard/pcengines/apu2/mainboard.c
@@ -15,6 +15,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index 6c405b8..49281b9 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -17,6 +17,7 @@
#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pnp.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 3c42048..9492ca1 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -19,6 +19,7 @@
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
diff --git a/src/mainboard/roda/rk9/fadt.c b/src/mainboard/roda/rk9/fadt.c
index e361e8d..2977492 100644
--- a/src/mainboard/roda/rk9/fadt.c
+++ b/src/mainboard/roda/rk9/fadt.c
@@ -16,6 +16,7 @@
#include <string.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <arch/acpi.h>
#include <cpu/x86/smm.h>
#include <version.h>
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index 742e2ee..a6adb17 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -17,6 +17,7 @@
/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
#include <northbridge/intel/gm45/gm45.h>
diff --git a/src/mainboard/roda/rk9/ti_pci7xx1.c b/src/mainboard/roda/rk9/ti_pci7xx1.c
index 4f72f9d..9f8e53e 100644
--- a/src/mainboard/roda/rk9/ti_pci7xx1.c
+++ b/src/mainboard/roda/rk9/ti_pci7xx1.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/cardbus.h>
static void pci7xx1_enable(struct device *const dev)
diff --git a/src/mainboard/roda/rv11/variants/rv11/romstage.c b/src/mainboard/roda/rv11/variants/rv11/romstage.c
index c7de994..685e942 100644
--- a/src/mainboard/roda/rv11/variants/rv11/romstage.c
+++ b/src/mainboard/roda/rv11/variants/rv11/romstage.c
@@ -15,6 +15,7 @@
#include <stdint.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
diff --git a/src/mainboard/roda/rv11/variants/rw11/romstage.c b/src/mainboard/roda/rv11/variants/rw11/romstage.c
index ca705a4..e693f13 100644
--- a/src/mainboard/roda/rv11/variants/rw11/romstage.c
+++ b/src/mainboard/roda/rv11/variants/rw11/romstage.c
@@ -15,6 +15,7 @@
#include <stdint.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pnp.h>
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c
index bc660b6..cb709d1 100644
--- a/src/mainboard/samsung/lumpy/chromeos.c
+++ b/src/mainboard/samsung/lumpy/chromeos.c
@@ -16,6 +16,7 @@
#include <string.h>
#include <bootmode.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 9f6a6ba..244ce7c 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -18,6 +18,7 @@
#include <string.h>
#include <timestamp.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <cbfs.h>
diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c
index f543da2..d6ec147 100644
--- a/src/mainboard/samsung/stumpy/chromeos.c
+++ b/src/mainboard/samsung/stumpy/chromeos.c
@@ -16,6 +16,7 @@
#include <string.h>
#include <bootmode.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index e6ba28c..27759a6 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -18,6 +18,7 @@
#include <string.h>
#include <timestamp.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c
index e9e962e..1b74cbb 100644
--- a/src/mainboard/sapphire/pureplatinumh61/romstage.c
+++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c
@@ -18,6 +18,7 @@
#include <string.h>
#include <arch/byteorder.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c
index 4305a24..07d0fb1 100644
--- a/src/mainboard/siemens/mc_apl1/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/mainboard.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <hwilib.h>
#include <i210.h>
diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
index 5decd03..0a1e816 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/multicore.h>
diff --git a/src/mainboard/supermicro/h8dmr_fam10/mptable.c b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
index 9065965..8b96670 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/mptable.c
@@ -17,6 +17,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 18a4631b0..49fec53 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -20,6 +20,7 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
index a94c9e4e..4f1fa47 100644
--- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/multicore.h>
diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c
index 81c0c1a..5d4c1cb 100644
--- a/src/mainboard/supermicro/h8qme_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c
@@ -17,6 +17,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index e3dc87d..f61fa71 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -20,6 +20,7 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c
index 716a77f..530a913 100644
--- a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c
+++ b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c
@@ -17,6 +17,7 @@
#include <arch/acpi.h>
#include <arch/ioapic.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <cpu/amd/amdfam10_sysconf.h>
#include "mb_sysconf.h"
diff --git a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c
index f6ea933..3c0bf46 100644
--- a/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c
+++ b/src/mainboard/supermicro/h8scm_fam10/get_bus_conf.c
@@ -14,6 +14,7 @@
*/
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <stdlib.h>
diff --git a/src/mainboard/supermicro/h8scm_fam10/mptable.c b/src/mainboard/supermicro/h8scm_fam10/mptable.c
index e28f422..1a8d191 100644
--- a/src/mainboard/supermicro/h8scm_fam10/mptable.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mptable.c
@@ -16,6 +16,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
index 419b00b..1cefda9 100644
--- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
+++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/multicore.h>
diff --git a/src/mainboard/tyan/s2912_fam10/mptable.c b/src/mainboard/tyan/s2912_fam10/mptable.c
index 928feb3..f9062ca 100644
--- a/src/mainboard/tyan/s2912_fam10/mptable.c
+++ b/src/mainboard/tyan/s2912_fam10/mptable.c
@@ -17,6 +17,7 @@
#include <arch/smp/mpspec.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index babac6f..589e06d 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -20,6 +20,7 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index f50a643..243f5bb 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -17,6 +17,7 @@
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c
index 219970f..8e1c2ef 100644
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -15,6 +15,7 @@
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <stdint.h>
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index edc4585..0e10920 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -16,6 +16,7 @@
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <stdint.h>
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index b283094..d4c5c61 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -15,6 +15,7 @@
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <stdint.h>
diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c
index 55a00e1..405a700 100644
--- a/src/northbridge/amd/amdfam10/debug.c
+++ b/src/northbridge/amd/amdfam10/debug.c
@@ -16,6 +16,7 @@
#include "debug.h"
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <delay.h>
diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c
index c68b0c4..7ace6b7 100644
--- a/src/northbridge/amd/amdfam10/early_ht.c
+++ b/src/northbridge/amd/amdfam10/early_ht.c
@@ -16,6 +16,7 @@
#include "early_ht.h"
#include <inttypes.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
// For SB HT chain only
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index c0c6eeb..8bf6d9e 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c
index 7d9a547..3c2477c 100644
--- a/src/northbridge/amd/amdht/comlib.c
+++ b/src/northbridge/amd/amdht/comlib.c
@@ -18,6 +18,7 @@
#include "comlib.h"
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/amd/msr.h>
#include <device/pci_def.h>
diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c
index 436cb59..f919335 100644
--- a/src/northbridge/amd/amdht/h3finit.c
+++ b/src/northbridge/amd/amdht/h3finit.c
@@ -29,6 +29,7 @@
#include <arch/cpu.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/lapic_def.h>
#include <cpu/amd/msr.h>
diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c
index e58046d..a1df9b0 100644
--- a/src/northbridge/amd/amdk8/reset_test.c
+++ b/src/northbridge/amd/amdk8/reset_test.c
@@ -12,6 +12,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <stdint.h>
#include <cpu/x86/lapic.h>
#include "amdk8.h"
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c
index d606dc5..ebca9c6 100644
--- a/src/northbridge/amd/pi/00630F01/northbridge.c
+++ b/src/northbridge/amd/pi/00630F01/northbridge.c
@@ -15,6 +15,7 @@
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/acpi.h>
#include <stdint.h>
#include <device/device.h>
diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c
index 00558a5..ef8297e 100644
--- a/src/northbridge/amd/pi/00660F01/northbridge.c
+++ b/src/northbridge/amd/pi/00660F01/northbridge.c
@@ -15,6 +15,7 @@
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/acpi.h>
#include <stdint.h>
#include <device/device.h>
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 81517af..0c97e4b 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/acpi.h>
#include <stdint.h>
#include <device/device.h>
diff --git a/src/northbridge/amd/pi/ramtop.c b/src/northbridge/amd/pi/ramtop.c
index 8fa81c7..987d875 100644
--- a/src/northbridge/amd/pi/ramtop.c
+++ b/src/northbridge/amd/pi/ramtop.c
@@ -15,6 +15,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#define CBMEM_TOP_SCRATCHPAD 0x78
diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c
index c21e321..357a963 100644
--- a/src/northbridge/intel/e7505/debug.c
+++ b/src/northbridge/intel/e7505/debug.c
@@ -15,6 +15,7 @@
#include <console/console.h>
#include <stdlib.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <spd.h>
#include "raminit.h"
diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c
index 1b86012..afe11bb 100644
--- a/src/northbridge/intel/e7505/memmap.c
+++ b/src/northbridge/intel/e7505/memmap.c
@@ -15,6 +15,7 @@
#define __SIMPLE_DEVICE__
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <cbmem.h>
#include <console/console.h>
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
index 317f087..0032356 100644
--- a/src/northbridge/intel/e7505/northbridge.c
+++ b/src/northbridge/intel/e7505/northbridge.c
@@ -13,6 +13,7 @@
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 70a0d66..276307d 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -27,6 +27,7 @@
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <lib.h>
#include <stdlib.h>
#include <commonlib/helpers.h>
diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c
index 25560dd..ca439a0 100644
--- a/src/northbridge/intel/fsp_rangeley/northbridge.c
+++ b/src/northbridge/intel/fsp_rangeley/northbridge.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <stdint.h>
#include <delay.h>
#include <cpu/intel/fsp_model_406dx/model_406dx.h>
diff --git a/src/northbridge/intel/fsp_rangeley/port_access.c b/src/northbridge/intel/fsp_rangeley/port_access.c
index 91e0179..c93d3bd 100644
--- a/src/northbridge/intel/fsp_rangeley/port_access.c
+++ b/src/northbridge/intel/fsp_rangeley/port_access.c
@@ -18,6 +18,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include "northbridge.h"
diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c
index dc59372..301743c 100644
--- a/src/northbridge/intel/gm45/acpi.c
+++ b/src/northbridge/intel/gm45/acpi.c
@@ -21,6 +21,7 @@
#include <arch/acpigen.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include "gm45.h"
unsigned long acpi_fill_mcfg(unsigned long current)
diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c
index 8a61e1c..5b1c301 100644
--- a/src/northbridge/intel/gm45/bootblock.c
+++ b/src/northbridge/intel/gm45/bootblock.c
@@ -12,6 +12,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
/* Just re-define these instead of including gm45.h. It blows up romcc. */
#define D0F0_PCIEXBAR_LO 0x60
diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c
index c2e4aea..723a43f 100644
--- a/src/northbridge/intel/gm45/early_init.c
+++ b/src/northbridge/intel/gm45/early_init.c
@@ -15,6 +15,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include "gm45.h"
void gm45_early_init(void)
diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c
index c987cb3..9f919cf 100644
--- a/src/northbridge/intel/gm45/early_reset.c
+++ b/src/northbridge/intel/gm45/early_reset.c
@@ -16,6 +16,7 @@
#include <types.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <halt.h>
#include "gm45.h"
diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c
index 45144aa..b0e2ba9 100644
--- a/src/northbridge/intel/gm45/igd.c
+++ b/src/northbridge/intel/gm45/igd.c
@@ -17,6 +17,7 @@
#include <stdint.h>
#include <stddef.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <console/console.h>
#include <pc80/mc146818rtc.h>
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c
index f424564..642c877 100644
--- a/src/northbridge/intel/gm45/iommu.c
+++ b/src/northbridge/intel/gm45/iommu.c
@@ -18,6 +18,7 @@
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <arch/acpi.h>
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 791559b..fddb1fe 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -16,6 +16,7 @@
#include <cbmem.h>
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index 5d6c182..1a6e3de 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -18,6 +18,7 @@
#include <stddef.h>
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <console/console.h>
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index af1a46d..c1ef30e 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -20,6 +20,7 @@
#include <stdint.h>
#include <arch/cpu.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 176c16a..d4209dc 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -18,6 +18,7 @@
#include <stdlib.h>
#include <arch/cpu.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <device/device.h>
#include <spd.h>
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c
index 6d652bb..7335ac9 100644
--- a/src/northbridge/intel/gm45/romstage.c
+++ b/src/northbridge/intel/gm45/romstage.c
@@ -19,6 +19,7 @@
#include <romstage_handoff.h>
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/acpi.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/bist.h>
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index f655c3b..d92e858 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -20,6 +20,7 @@
#include <arch/acpi.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include "haswell.h"
#include <southbridge/intel/lynxpoint/pch.h>
diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c
index a25f363..d7f4e6e 100644
--- a/src/northbridge/intel/haswell/bootblock.c
+++ b/src/northbridge/intel/haswell/bootblock.c
@@ -12,6 +12,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
/* Just re-define this instead of including haswell.h. It blows up romcc. */
#define PCIEXBAR 0x60
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index be83894..a04b3f4 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <console/console.h>
#include <bootmode.h>
diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c
index d3e88f2..24fbb64 100644
--- a/src/northbridge/intel/haswell/ram_calc.c
+++ b/src/northbridge/intel/haswell/ram_calc.c
@@ -17,6 +17,7 @@
#define __SIMPLE_DEVICE__
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include "haswell.h"
diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c
index 1bc3110..376e63f 100644
--- a/src/northbridge/intel/haswell/report_platform.c
+++ b/src/northbridge/intel/haswell/report_platform.c
@@ -18,6 +18,7 @@
#include <string.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cpu/x86/msr.h>
#include "haswell.h"
diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c
index cff3ade..b4d92b0 100644
--- a/src/northbridge/intel/i440bx/debug.c
+++ b/src/northbridge/intel/i440bx/debug.c
@@ -13,6 +13,7 @@
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <spd.h>
#include "raminit.h"
diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c
index 4b1141c..ae89766 100644
--- a/src/northbridge/intel/i440bx/northbridge.c
+++ b/src/northbridge/intel/i440bx/northbridge.c
@@ -13,6 +13,7 @@
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c
index 962f3ba..3207688 100644
--- a/src/northbridge/intel/i440bx/ram_calc.c
+++ b/src/northbridge/intel/i440bx/ram_calc.c
@@ -16,6 +16,7 @@
#define __SIMPLE_DEVICE__
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <console/console.h>
#include <commonlib/helpers.h>
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 49994ed..0c9496b 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -20,6 +20,7 @@
#include <stdint.h>
#include <stdlib.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <console/console.h>
#include "i440bx.h"
diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c
index 053815b..f817cdf 100644
--- a/src/northbridge/intel/i945/acpi.c
+++ b/src/northbridge/intel/i945/acpi.c
@@ -20,6 +20,7 @@
#include <arch/acpigen.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include "i945.h"
unsigned long acpi_fill_mcfg(unsigned long current)
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index 5296d52..1c00e8b 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -12,6 +12,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
/* Just re-define this instead of including i945.h. It blows up romcc. */
#define PCIEXBAR 0x48
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index c52f2a6..370131f 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -16,6 +16,7 @@
#include <spd.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <console/console.h>
#include "i945.h"
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index b82812e..d9d88bb 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cbmem.h>
#include <halt.h>
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 7a2a489..3a01940 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -18,6 +18,7 @@
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <pc80/mc146818rtc.h>
#include <edid.h>
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 7c209dc..1dff3d1 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -16,6 +16,7 @@
#include <cbmem.h>
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index fd37aea..c797d42 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -17,6 +17,7 @@
#define __SIMPLE_DEVICE__
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <cbmem.h>
#include "i945.h"
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index dece9bf..c6a2e05 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <device/pci_def.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <lib.h>
#include <pc80/mc146818rtc.h>
diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c
index 08fc09c..462cdc0 100644
--- a/src/northbridge/intel/nehalem/acpi.c
+++ b/src/northbridge/intel/nehalem/acpi.c
@@ -21,6 +21,7 @@
#include <types.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include "nehalem.h"
unsigned long acpi_fill_mcfg(unsigned long current)
diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/nehalem/bootblock.c
index 807e919..c37aa3a 100644
--- a/src/northbridge/intel/nehalem/bootblock.c
+++ b/src/northbridge/intel/nehalem/bootblock.c
@@ -12,6 +12,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
static void bootblock_northbridge_init(void)
{
diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c
index ac0ed45..2c958a4 100644
--- a/src/northbridge/intel/nehalem/early_init.c
+++ b/src/northbridge/intel/nehalem/early_init.c
@@ -19,6 +19,7 @@
#include <stdlib.h>
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <elog.h>
#include <cpu/x86/msr.h>
diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index fbe6c11..43ec6ed 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <stdint.h>
#include <delay.h>
#include <cpu/intel/model_2065x/model_2065x.h>
diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c
index baf087e..3df6f81 100644
--- a/src/northbridge/intel/nehalem/ram_calc.c
+++ b/src/northbridge/intel/nehalem/ram_calc.c
@@ -18,6 +18,7 @@
#include <arch/cpu.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index c730b5e..9812e53 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cpu/x86/msr.h>
#include <cbmem.h>
#include <arch/cbfs.h>
diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/nehalem/smi.c
index a08ac1b..6aefc9b 100644
--- a/src/northbridge/intel/nehalem/smi.c
+++ b/src/northbridge/intel/nehalem/smi.c
@@ -17,6 +17,7 @@
#include <string.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include "nehalem.h"
#include <cpu/intel/smm/gen1/smi.h>
diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c
index 1fab845..f3eab49 100644
--- a/src/northbridge/intel/pineview/bootblock.c
+++ b/src/northbridge/intel/pineview/bootblock.c
@@ -12,6 +12,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#define PCIEXBAR 0x60
#define MMCONF_256_BUSSES 16
#define ENABLE 1
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
index 8974428..11dc203 100644
--- a/src/northbridge/intel/pineview/early_init.c
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -18,6 +18,7 @@
#include <stdlib.h>
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <device/pci.h>
#include <halt.h>
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index ec2c902..94aed89 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -17,6 +17,7 @@
#include <cbmem.h>
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c
index 21b926b..cf9db98 100644
--- a/src/northbridge/intel/pineview/ram_calc.c
+++ b/src/northbridge/intel/pineview/ram_calc.c
@@ -17,6 +17,7 @@
#define __SIMPLE_DEVICE__
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <console/console.h>
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index ed633fd..1b2ad8d 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <delay.h>
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c
index 10ac0f5..0d2cc36 100644
--- a/src/northbridge/intel/pineview/romstage.c
+++ b/src/northbridge/intel/pineview/romstage.c
@@ -20,6 +20,7 @@
#include <lib.h>
#include <timestamp.h>
#include <console/console.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <romstage_handoff.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c
index c274318..4afb546 100644
--- a/src/northbridge/intel/sandybridge/acpi.c
+++ b/src/northbridge/intel/sandybridge/acpi.c
@@ -21,6 +21,7 @@
#include <arch/acpi.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include "sandybridge.h"
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c
index 05b0c75..c35a49a 100644
--- a/src/northbridge/intel/sandybridge/bootblock.c
+++ b/src/northbridge/intel/sandybridge/bootblock.c
@@ -12,6 +12,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
/* Just re-define this instead of including sandybridge.h. It blows up romcc. */
#define PCIEXBAR 0x60
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index f8ecc1a..01787f1 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -18,6 +18,7 @@
#include <stdlib.h>
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/acpi.h>
#include <device/pci_def.h>
#include <elog.h>
diff --git a/src/northbridge/intel/sandybridge/iommu.c b/src/northbridge/intel/sandybridge/iommu.c
index 017c732..26bbdf9 100644
--- a/src/northbridge/intel/sandybridge/iommu.c
+++ b/src/northbridge/intel/sandybridge/iommu.c
@@ -17,6 +17,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci_def.h>
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 0d644ca..4d00d73 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <stdint.h>
#include <delay.h>
#include <cpu/intel/model_206ax/model_206ax.h>
diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c
index bb88c7a..53fb4d3 100644
--- a/src/northbridge/intel/sandybridge/pcie.c
+++ b/src/northbridge/intel/sandybridge/pcie.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
#include <assert.h>
diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c
index 00e3e78..0e5127d 100644
--- a/src/northbridge/intel/sandybridge/ram_calc.c
+++ b/src/northbridge/intel/sandybridge/ram_calc.c
@@ -17,6 +17,7 @@
#include <arch/cpu.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 5f7fd0a..115d515 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -21,6 +21,7 @@
#include <string.h>
#include <arch/cpu.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <halt.h>
#include <timestamp.h>
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 4897581..afdd908 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -19,6 +19,7 @@
#include <string.h>
#include <arch/cpu.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <northbridge/intel/sandybridge/chip.h>
#include <device/pci_def.h>
#include <delay.h>
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index af9b490..6142388 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -18,6 +18,7 @@
#include <bootmode.h>
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <arch/cbfs.h>
#include <cbfs.h>
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 26f4977..c979897 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -19,6 +19,7 @@
#include <string.h>
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cpu/x86/lapic.h>
#include <timestamp.h>
#include "sandybridge.h"
diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c
index 9629d88..b470e95 100644
--- a/src/northbridge/intel/x4x/bootblock.c
+++ b/src/northbridge/intel/x4x/bootblock.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include "iomap.h"
#include "x4x.h"
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index c6eb383..9cb3df3 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -16,6 +16,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include "iomap.h"
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)
#include <southbridge/intel/i82801gx/i82801gx.h> /* DEFAULT_PMBASE */
diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c
index 4b5a754..c168e38 100644
--- a/src/northbridge/intel/x4x/northbridge.c
+++ b/src/northbridge/intel/x4x/northbridge.c
@@ -17,6 +17,7 @@
#include <cbmem.h>
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index 6484326..ff3c31b 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -22,6 +22,7 @@
#include <stdint.h>
#include <arch/cpu.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 1fd6004..ea00f29 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index 5c5dafa..ffa861e 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -17,6 +17,7 @@
#include <assert.h>
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <commonlib/helpers.h>
#include <delay.h>
diff --git a/src/northbridge/via/vx900/bootblock.c b/src/northbridge/via/vx900/bootblock.c
index 11123b6..1051be4 100644
--- a/src/northbridge/via/vx900/bootblock.c
+++ b/src/northbridge/via/vx900/bootblock.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#if CONFIG_ROM_SIZE == 0x80000
# define ROM_DECODE_MAP 0x00
diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c
index abba4d3..69a0a6b 100644
--- a/src/northbridge/via/vx900/chrome9hd.c
+++ b/src/northbridge/via/vx900/chrome9hd.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci.h>
#include <device/pci_ids.h>
diff --git a/src/northbridge/via/vx900/early_smbus.c b/src/northbridge/via/vx900/early_smbus.c
index 0cf7427..5816926 100644
--- a/src/northbridge/via/vx900/early_smbus.c
+++ b/src/northbridge/via/vx900/early_smbus.c
@@ -19,6 +19,7 @@
#include <device/early_smbus.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
/**
diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c
index fe858b6..d5c702c 100644
--- a/src/northbridge/via/vx900/early_vx900.c
+++ b/src/northbridge/via/vx900/early_vx900.c
@@ -16,6 +16,7 @@
#include "early_vx900.h"
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
/**
diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c
index 40c4299..221fe8e 100644
--- a/src/northbridge/via/vx900/lpc.c
+++ b/src/northbridge/via/vx900/lpc.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/pirq_routing.h>
#include <console/console.h>
#include <device/pci.h>
diff --git a/src/northbridge/via/vx900/memmap.c b/src/northbridge/via/vx900/memmap.c
index 9940502..18d9635 100644
--- a/src/northbridge/via/vx900/memmap.c
+++ b/src/northbridge/via/vx900/memmap.c
@@ -20,6 +20,7 @@
#include "vx900.h"
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#define MCU PCI_DEV(0, 0, 3)
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c
index 41a1073..0544c17 100644
--- a/src/northbridge/via/vx900/northbridge.c
+++ b/src/northbridge/via/vx900/northbridge.c
@@ -20,6 +20,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <cpu/cpu.h>
#include <cf9_reset.h>
diff --git a/src/northbridge/via/vx900/pcie.c b/src/northbridge/via/vx900/pcie.c
index 1d3ecd9..b4d2723 100644
--- a/src/northbridge/via/vx900/pcie.c
+++ b/src/northbridge/via/vx900/pcie.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci.h>
#include <device/pciexp.h>
diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c
index 59d206c..e03470c 100644
--- a/src/northbridge/via/vx900/raminit_ddr3.c
+++ b/src/northbridge/via/vx900/raminit_ddr3.c
@@ -17,6 +17,7 @@
#include "early_vx900.h"
#include "raminit.h"
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci_ids.h>
#include <delay.h>
diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c
index d6f4c83..7911331 100644
--- a/src/northbridge/via/vx900/sata.c
+++ b/src/northbridge/via/vx900/sata.c
@@ -16,6 +16,7 @@
#include <console/console.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "vx900.h"
diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c
index 734defc..8f3f602 100644
--- a/src/northbridge/via/vx900/traf_ctrl.c
+++ b/src/northbridge/via/vx900/traf_ctrl.c
@@ -15,6 +15,7 @@
*/
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <console/console.h>
#include <drivers/generic/ioapic/chip.h>
diff --git a/src/soc/amd/common/block/pci/amd_pci_util.c b/src/soc/amd/common/block/pci/amd_pci_util.c
index 44a2e61..d06a8df 100644
--- a/src/soc/amd/common/block/pci/amd_pci_util.c
+++ b/src/soc/amd/common/block/pci/amd_pci_util.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <string.h>
#include <amdblocks/amd_pci_util.h>
#include <pc80/i8259.h>
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index d6f9bb6..152c299 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -23,6 +23,7 @@
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <cpu/x86/smm.h>
#include <cbmem.h>
diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c
index 27ac61f..ce84a47 100644
--- a/src/soc/amd/stoneyridge/enable_usbdebug.c
+++ b/src/soc/amd/stoneyridge/enable_usbdebug.c
@@ -18,6 +18,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_ehci.h>
#include <device/pci_def.h>
#include <soc/pci_devs.h>
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 4a856a9..9ccc2e9 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -15,6 +15,7 @@
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 9f8aed8..1489a57 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/cpu.h>
#include <arch/acpi.h>
#include <cpu/x86/msr.h>
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index cf3e839..bb5eff8 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -18,6 +18,7 @@
#include <bootblock_common.h>
#include <cpu/x86/pae.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/p2sb.h>
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 3634509..3eed45c 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -25,6 +25,7 @@
#include <cpu/x86/msr.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <intelblocks/acpi.h>
#include <intelblocks/chip.h>
#include <intelblocks/fast_spi.h>
diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c
index 37cdda4..9be598f 100644
--- a/src/soc/intel/apollolake/graphics.c
+++ b/src/soc/intel/apollolake/graphics.c
@@ -23,6 +23,7 @@
#include <fsp/util.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <intelblocks/graphics.h>
#include <drivers/intel/gma/opregion.h>
#include <drivers/intel/gma/libgfxinit.h>
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 9cc5166..a8a943d 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -19,6 +19,7 @@
#include <arch/cpu.h>
#include <arch/early_variables.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/symbols.h>
#include <assert.h>
#include <bootmode.h>
diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c
index ac61375..d51f281 100644
--- a/src/soc/intel/baytrail/bootblock/bootblock.c
+++ b/src/soc/intel/baytrail/bootblock/bootblock.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c
index 2c02689..2102637 100644
--- a/src/soc/intel/baytrail/chip.c
+++ b/src/soc/intel/baytrail/chip.c
@@ -15,6 +15,7 @@
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <arch/pci_ops.h>
#include <soc/pci_devs.h>
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c
index f8e78d2..5a36de5 100644
--- a/src/soc/intel/baytrail/gfx.c
+++ b/src/soc/intel/baytrail/gfx.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c
index 3c28ba5..5496b01 100644
--- a/src/soc/intel/baytrail/iosf.c
+++ b/src/soc/intel/baytrail/iosf.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <soc/iosf.h>
#if !defined(__PRE_RAM__)
diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c
index 2830f00..caa3710 100644
--- a/src/soc/intel/baytrail/lpe.c
+++ b/src/soc/intel/baytrail/lpe.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c
index 3e03ca5..2740f10 100644
--- a/src/soc/intel/baytrail/pcie.c
+++ b/src/soc/intel/baytrail/pcie.c
@@ -16,6 +16,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
#include <reg_script.h>
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index be870fc..5ef1f71 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -16,6 +16,7 @@
#include <stdint.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <console/console.h>
diff --git a/src/soc/intel/baytrail/romstage/gfx.c b/src/soc/intel/baytrail/romstage/gfx.c
index e1434ef..884bf87 100644
--- a/src/soc/intel/baytrail/romstage/gfx.c
+++ b/src/soc/intel/baytrail/romstage/gfx.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <soc/gfx.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c
index e77d00d..596ed11 100644
--- a/src/soc/intel/baytrail/romstage/pmc.c
+++ b/src/soc/intel/baytrail/romstage/pmc.c
@@ -15,6 +15,7 @@
#include <stddef.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci_def.h>
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index cc055c0..550f872 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -21,6 +21,7 @@
#include <cf9_reset.h>
#include <console/console.h>
#include <device/pci_def.h>
+#include <device/pci_ops.h>
#include <halt.h>
#include <mrc_cache.h>
#include <soc/gpio.h>
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index a4a05dc..3e0ba32 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -16,6 +16,7 @@
#include <stddef.h>
#include <arch/cpu.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <bootblock_common.h>
#include <console/console.h>
#include <cbmem.h>
diff --git a/src/soc/intel/baytrail/romstage/uart.c b/src/soc/intel/baytrail/romstage/uart.c
index f3c5029..41c879d 100644
--- a/src/soc/intel/baytrail/romstage/uart.c
+++ b/src/soc/intel/baytrail/romstage/uart.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c
index 4724d55..adf0f96 100644
--- a/src/soc/intel/baytrail/sata.c
+++ b/src/soc/intel/baytrail/sata.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <soc/sata.h>
diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c
index 0c03e56..872f6f9 100644
--- a/src/soc/intel/baytrail/sd.c
+++ b/src/soc/intel/baytrail/sd.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 3f8727d..c722f5c 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -16,6 +16,7 @@
#include <stdint.h>
#include <stdlib.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index d5e3400..89b6b31 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -17,6 +17,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/acpi.h>
#include <arch/cpu.h>
#include <bootstate.h>
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index f7472b9..7cbb082 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -19,6 +19,7 @@
#include <bootstate.h>
#include <delay.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <device/device.h>
diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c
index 6ad63ba..6408cd9 100644
--- a/src/soc/intel/baytrail/xhci.c
+++ b/src/soc/intel/baytrail/xhci.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <stdint.h>
#include <reg_script.h>
diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c
index 79d44e0..c544ff9 100644
--- a/src/soc/intel/braswell/bootblock/bootblock.c
+++ b/src/soc/intel/braswell/bootblock/bootblock.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index b7f6d4d..e8fd9d1 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <fsp/util.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
diff --git a/src/soc/intel/braswell/iosf.c b/src/soc/intel/braswell/iosf.c
index 990c2b5..aff1c3d 100644
--- a/src/soc/intel/braswell/iosf.c
+++ b/src/soc/intel/braswell/iosf.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <soc/iosf.h>
diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c
index 6338878..7b7eb9b 100644
--- a/src/soc/intel/braswell/lpe.c
+++ b/src/soc/intel/braswell/lpe.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c
index efd891a..8494974 100644
--- a/src/soc/intel/braswell/pcie.c
+++ b/src/soc/intel/braswell/pcie.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
#include <reg_script.h>
diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c
index be1b49e..fbaac2e 100644
--- a/src/soc/intel/braswell/pmutil.c
+++ b/src/soc/intel/braswell/pmutil.c
@@ -16,6 +16,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <console/console.h>
#include <soc/iomap.h>
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 9b9a0eb..38047ed 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -19,6 +19,7 @@
#include <stddef.h>
#include <arch/early_variables.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/cbfs.h>
#include <chip.h>
#include <cpu/x86/mtrr.h>
diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c
index 1775ce7..c0c827d 100644
--- a/src/soc/intel/braswell/sd.c
+++ b/src/soc/intel/braswell/sd.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index a4d2d88..1129e04 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -16,6 +16,7 @@
#include <arch/hlt.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index dc918eb..3cd2208 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -17,6 +17,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <bootstate.h>
diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c
index 14d1087..0937268 100644
--- a/src/soc/intel/braswell/spi.c
+++ b/src/soc/intel/braswell/spi.c
@@ -15,6 +15,7 @@
/* This file is derived from the flashrom project. */
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <bootstate.h>
#include <commonlib/helpers.h>
#include <console/console.h>
diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c
index 2643801..88c61d1 100644
--- a/src/soc/intel/broadwell/bootblock/pch.c
+++ b/src/soc/intel/broadwell/bootblock/pch.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/pci_devs.h>
diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c
index 1a09f8e..2f6b5b4 100644
--- a/src/soc/intel/broadwell/bootblock/systemagent.c
+++ b/src/soc/intel/broadwell/bootblock/systemagent.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/systemagent.h>
diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c
index 3b17745..aab8045 100644
--- a/src/soc/intel/broadwell/chip.c
+++ b/src/soc/intel/broadwell/chip.c
@@ -15,6 +15,7 @@
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <soc/acpi.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c
index 8972f56..7efdca0 100644
--- a/src/soc/intel/broadwell/ehci.c
+++ b/src/soc/intel/broadwell/ehci.c
@@ -20,6 +20,7 @@
#include <device/pci_ids.h>
#include <device/pci_ehci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <soc/ehci.h>
#include <soc/pch.h>
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index 23c650a..da6db7d 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -15,6 +15,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <bootmode.h>
#include <console/console.h>
#include <delay.h>
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 762198b1..63db9aa 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -24,6 +24,7 @@
#include <pc80/i8259.h>
#include <arch/cpu.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <arch/acpi.h>
#include <cpu/cpu.h>
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index f8b3be9..fc1406d 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -23,6 +23,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c
index 3748701..2249036 100644
--- a/src/soc/intel/broadwell/me_status.c
+++ b/src/soc/intel/broadwell/me_status.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci.h>
#include <stdlib.h>
diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c
index 175c20c..027c958 100644
--- a/src/soc/intel/broadwell/memmap.c
+++ b/src/soc/intel/broadwell/memmap.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <device/pci.h>
#include <soc/pci_devs.h>
diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c
index c5df1ad..cddc932 100644
--- a/src/soc/intel/broadwell/pch.c
+++ b/src/soc/intel/broadwell/pch.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <delay.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c
index e19025b..322e96f 100644
--- a/src/soc/intel/broadwell/pmutil.c
+++ b/src/soc/intel/broadwell/pmutil.c
@@ -20,6 +20,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c
index 2affb26..291d5eb 100644
--- a/src/soc/intel/broadwell/romstage/power_state.c
+++ b/src/soc/intel/broadwell/romstage/power_state.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/soc/intel/broadwell/romstage/report_platform.c
index db4b2eb..751e8d0 100644
--- a/src/soc/intel/broadwell/romstage/report_platform.c
+++ b/src/soc/intel/broadwell/romstage/report_platform.c
@@ -15,6 +15,7 @@
#include <arch/cpu.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci.h>
#include <string.h>
diff --git a/src/soc/intel/broadwell/romstage/systemagent.c b/src/soc/intel/broadwell/romstage/systemagent.c
index 153dfdf..9911ad1 100644
--- a/src/soc/intel/broadwell/romstage/systemagent.c
+++ b/src/soc/intel/broadwell/romstage/systemagent.c
@@ -16,6 +16,7 @@
#include <stdlib.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <reg_script.h>
#include <soc/iomap.h>
diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c
index f66eb0a..0853753 100644
--- a/src/soc/intel/broadwell/sata.c
+++ b/src/soc/intel/broadwell/sata.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c
index eb70112..9d751e5 100644
--- a/src/soc/intel/broadwell/serialio.c
+++ b/src/soc/intel/broadwell/serialio.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index 52725f2..6b2dfc2 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -17,6 +17,7 @@
#include <delay.h>
#include <types.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <device/pci_def.h>
diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c
index 49b8554..5dd076f 100644
--- a/src/soc/intel/broadwell/smmrelocate.c
+++ b/src/soc/intel/broadwell/smmrelocate.c
@@ -17,6 +17,7 @@
#include <string.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/mp.h>
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index 5280967..7770731 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -19,6 +19,7 @@
#include <commonlib/helpers.h>
#include <delay.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c
index 2ef8691..bfb8b06 100644
--- a/src/soc/intel/broadwell/systemagent.c
+++ b/src/soc/intel/broadwell/systemagent.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <stdint.h>
#include <delay.h>
#include <device/device.h>
diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c
index b5980df..bd11807 100644
--- a/src/soc/intel/broadwell/xhci.c
+++ b/src/soc/intel/broadwell/xhci.c
@@ -19,6 +19,7 @@
#include <device/pci_ids.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <soc/ramstage.h>
#include <soc/xhci.h>
#include <soc/cpu.h>
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index f45e177..5ca19e5 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -16,6 +16,7 @@
#include <console/console.h>
#include <device/device.h>
+#include <device/pci_ops.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/gspi.h>
#include <intelblocks/lpc_lib.h>
diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c
index 41cfad6..9a4dd4a 100644
--- a/src/soc/intel/cannonlake/bootblock/report_platform.c
+++ b/src/soc/intel/cannonlake/bootblock/report_platform.c
@@ -16,6 +16,7 @@
#include <arch/cpu.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <device/pci.h>
diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c
index 58f87f7..2b3c900 100644
--- a/src/soc/intel/cannonlake/graphics.c
+++ b/src/soc/intel/cannonlake/graphics.c
@@ -19,6 +19,7 @@
#include <fsp/util.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <drivers/intel/gma/i915_reg.h>
#include <drivers/intel/gma/opregion.h>
#include <intelblocks/graphics.h>
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index c06ce97..5dffb81 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -22,6 +22,7 @@
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <intelblocks/itss.h>
#include <intelblocks/lpc_lib.h>
diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c
index e688592..47efa18 100644
--- a/src/soc/intel/cannonlake/smmrelocate.c
+++ b/src/soc/intel/cannonlake/smmrelocate.c
@@ -18,6 +18,7 @@
#include <string.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/lapic.h>
diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c
index 70a4406..6358796 100644
--- a/src/soc/intel/common/block/i2c/i2c.c
+++ b/src/soc/intel/common/block/i2c/i2c.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/i2c_simple.h>
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index fb50b74..494a1b0 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -20,6 +20,7 @@
#include <assert.h>
#include <console/console.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <intelblocks/lpc_lib.h>
#include <lib.h>
#include "lpc_def.h"
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c
index 24f3a69..a0daeed 100644
--- a/src/soc/intel/common/block/p2sb/p2sb.c
+++ b/src/soc/intel/common/block/p2sb/p2sb.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c
index 7f6d249..1f25d75 100644
--- a/src/soc/intel/common/block/pmc/pmc.c
+++ b/src/soc/intel/common/block/pmc/pmc.c
@@ -15,6 +15,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <device/pci.h>
diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c
index a39ef52..129a359 100644
--- a/src/soc/intel/common/block/sata/sata.c
+++ b/src/soc/intel/common/block/sata/sata.c
@@ -15,6 +15,7 @@
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <soc/pci_devs.h>
diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c
index 1458945..f1a2ca0 100644
--- a/src/soc/intel/common/block/smbus/tco.c
+++ b/src/soc/intel/common/block/smbus/tco.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index 16f31b6..0c10d6b 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -16,6 +16,7 @@
#include <arch/hlt.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index 4b4e74c..55f19ae 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c
index c1cef5d..17df42d 100644
--- a/src/soc/intel/common/block/systemagent/systemagent_early.c
+++ b/src/soc/intel/common/block/systemagent/systemagent_early.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c
index fd89c79..7633637 100644
--- a/src/soc/intel/denverton_ns/acpi.c
+++ b/src/soc/intel/denverton_ns/acpi.c
@@ -24,6 +24,7 @@
#include <cpu/x86/smm.h>
#include <string.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <intelblocks/acpi.h>
diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c
index 8af6b39..c0aa25f 100644
--- a/src/soc/intel/denverton_ns/bootblock/uart.c
+++ b/src/soc/intel/denverton_ns/bootblock/uart.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <fsp/soc_binding.h>
#include <commonlib/helpers.h>
diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c
index 0f3c8a0..29bea2b 100644
--- a/src/soc/intel/denverton_ns/chip.c
+++ b/src/soc/intel/denverton_ns/chip.c
@@ -21,6 +21,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <fsp/api.h>
#include <fsp/util.h>
#include <intelblocks/fast_spi.h>
diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c
index dbc5ecc..5f16f04 100644
--- a/src/soc/intel/denverton_ns/lpc.c
+++ b/src/soc/intel/denverton_ns/lpc.c
@@ -19,6 +19,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <arch/acpi.h>
#include <cpu/x86/smm.h>
diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c
index fe1b705..193e41c 100644
--- a/src/soc/intel/denverton_ns/pmc.c
+++ b/src/soc/intel/denverton_ns/pmc.c
@@ -16,6 +16,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c
index 34fd7bb..5df8b71 100644
--- a/src/soc/intel/denverton_ns/romstage.c
+++ b/src/soc/intel/denverton_ns/romstage.c
@@ -18,6 +18,7 @@
#include <cf9_reset.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
+#include <device/pci_ops.h>
#include <soc/fiamux.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c
index 9d0bdfc..844a037 100644
--- a/src/soc/intel/denverton_ns/sata.c
+++ b/src/soc/intel/denverton_ns/sata.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c
index 85f99d7..9961778 100644
--- a/src/soc/intel/denverton_ns/smihandler.c
+++ b/src/soc/intel/denverton_ns/smihandler.c
@@ -19,6 +19,7 @@
#include <stdlib.h>
#include <arch/hlt.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c
index b56c839..fcfeaf7 100644
--- a/src/soc/intel/denverton_ns/soc_util.c
+++ b/src/soc/intel/denverton_ns/soc_util.c
@@ -16,6 +16,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/device.h>
diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c
index abce0ab..65cbbfb 100644
--- a/src/soc/intel/denverton_ns/systemagent.c
+++ b/src/soc/intel/denverton_ns/systemagent.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <stdint.h>
#include <delay.h>
#include <device/device.h>
diff --git a/src/soc/intel/denverton_ns/uart_debug.c b/src/soc/intel/denverton_ns/uart_debug.c
index f909d56..5911a45 100644
--- a/src/soc/intel/denverton_ns/uart_debug.c
+++ b/src/soc/intel/denverton_ns/uart_debug.c
@@ -16,8 +16,8 @@
#include <stdint.h>
#include <device/pci_def.h>
+#include <device/pci_ops.h>
#include <io.h>
-#include <arch/pci_io_cfg.h>
#include <soc/uart.h>
#define MY_PCI_DEV(SEGBUS, DEV, FN) \
diff --git a/src/soc/intel/denverton_ns/xhci.c b/src/soc/intel/denverton_ns/xhci.c
index 5f8482e..1395a07 100644
--- a/src/soc/intel/denverton_ns/xhci.c
+++ b/src/soc/intel/denverton_ns/xhci.c
@@ -19,6 +19,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c
index ad32452..1b1969f 100644
--- a/src/soc/intel/fsp_baytrail/acpi.c
+++ b/src/soc/intel/fsp_baytrail/acpi.c
@@ -38,6 +38,7 @@
#include <soc/irq.h>
#include <soc/iosf.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <soc/msr.h>
#include <soc/pattrs.h>
#include <cbmem.h>
diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
index 8ce0a1d..315c1a2 100644
--- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
+++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c
index a041b81..c74c847 100644
--- a/src/soc/intel/fsp_baytrail/chip.c
+++ b/src/soc/intel/fsp_baytrail/chip.c
@@ -16,6 +16,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c
index 22e565f..fbbbfe9 100644
--- a/src/soc/intel/fsp_baytrail/i2c.c
+++ b/src/soc/intel/fsp_baytrail/i2c.c
@@ -14,6 +14,7 @@
*/
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <soc/baytrail.h>
#include <soc/pci_devs.h>
#include <soc/iosf.h>
diff --git a/src/soc/intel/fsp_baytrail/iosf.c b/src/soc/intel/fsp_baytrail/iosf.c
index 3500025..252d69e 100644
--- a/src/soc/intel/fsp_baytrail/iosf.c
+++ b/src/soc/intel/fsp_baytrail/iosf.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <soc/iosf.h>
#if !defined(__PRE_RAM__)
diff --git a/src/soc/intel/fsp_baytrail/lpe.c b/src/soc/intel/fsp_baytrail/lpe.c
index 84a10fd..a5a18b7 100644
--- a/src/soc/intel/fsp_baytrail/lpe.c
+++ b/src/soc/intel/fsp_baytrail/lpe.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
diff --git a/src/soc/intel/fsp_baytrail/pmutil.c b/src/soc/intel/fsp_baytrail/pmutil.c
index 6e4a7c8..03d0e8f 100644
--- a/src/soc/intel/fsp_baytrail/pmutil.c
+++ b/src/soc/intel/fsp_baytrail/pmutil.c
@@ -15,6 +15,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <console/console.h>
diff --git a/src/soc/intel/fsp_baytrail/romstage/report_platform.c b/src/soc/intel/fsp_baytrail/romstage/report_platform.c
index 4c91b0a..ab5c582 100644
--- a/src/soc/intel/fsp_baytrail/romstage/report_platform.c
+++ b/src/soc/intel/fsp_baytrail/romstage/report_platform.c
@@ -16,6 +16,7 @@
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <soc/iosf.h>
#include <soc/romstage.h>
#include <cpu/x86/msr.h>
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index 19a0d44..83121fa 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -17,6 +17,7 @@
#include <stddef.h>
#include <lib.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/cbfs.h>
#include <arch/early_variables.h>
#include <console/console.h>
diff --git a/src/soc/intel/fsp_baytrail/romstage/uart.c b/src/soc/intel/fsp_baytrail/romstage/uart.c
index 10a00f8..d18f9d7 100644
--- a/src/soc/intel/fsp_baytrail/romstage/uart.c
+++ b/src/soc/intel/fsp_baytrail/romstage/uart.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
#include <soc/lpc.h>
diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c
index e8021ce..ee0929d 100644
--- a/src/soc/intel/fsp_baytrail/smihandler.c
+++ b/src/soc/intel/fsp_baytrail/smihandler.c
@@ -16,6 +16,7 @@
#include <stdint.h>
#include <stdlib.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c
index f0028f4..3c26808 100644
--- a/src/soc/intel/fsp_baytrail/southcluster.c
+++ b/src/soc/intel/fsp_baytrail/southcluster.c
@@ -18,6 +18,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <console/console.h>
#include <device/device.h>
diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c
index 275b038..0255888 100644
--- a/src/soc/intel/fsp_baytrail/spi.c
+++ b/src/soc/intel/fsp_baytrail/spi.c
@@ -21,6 +21,7 @@
#include <commonlib/helpers.h>
#include <delay.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c
index f7c572d..d4f34b1 100644
--- a/src/soc/intel/fsp_broadwell_de/acpi.c
+++ b/src/soc/intel/fsp_broadwell_de/acpi.c
@@ -21,6 +21,7 @@
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/smp/mpspec.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
diff --git a/src/soc/intel/fsp_broadwell_de/chip.c b/src/soc/intel/fsp_broadwell_de/chip.c
index 5cdedca..f6dd2a7 100644
--- a/src/soc/intel/fsp_broadwell_de/chip.c
+++ b/src/soc/intel/fsp_broadwell_de/chip.c
@@ -19,6 +19,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index 8ddca26..e46bcd0 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -18,6 +18,7 @@
#include <stddef.h>
#include <lib.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/cbfs.h>
#include <cbmem.h>
#include <console/console.h>
diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c
index a58744e..dae1712 100644
--- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c
+++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c
@@ -25,6 +25,7 @@
#include <cpu/x86/smm.h>
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <soc/lpc.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c
index da11f24..5c0cb7e 100644
--- a/src/soc/intel/fsp_broadwell_de/southcluster.c
+++ b/src/soc/intel/fsp_broadwell_de/southcluster.c
@@ -18,6 +18,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/soc/intel/fsp_broadwell_de/vtd.c b/src/soc/intel/fsp_broadwell_de/vtd.c
index 8f6b278..318927a 100644
--- a/src/soc/intel/fsp_broadwell_de/vtd.c
+++ b/src/soc/intel/fsp_broadwell_de/vtd.c
@@ -14,6 +14,7 @@
*/
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <soc/pci_devs.h>
#include <soc/acpi.h>
diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c
index 05ae25f..0b932a9 100644
--- a/src/soc/intel/icelake/bootblock/report_platform.c
+++ b/src/soc/intel/icelake/bootblock/report_platform.c
@@ -15,6 +15,7 @@
#include <arch/cpu.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <device/pci.h>
diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c
index 1c22f49..f0ad0e2 100644
--- a/src/soc/intel/icelake/graphics.c
+++ b/src/soc/intel/icelake/graphics.c
@@ -19,6 +19,7 @@
#include <fsp/util.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <drivers/intel/gma/i915_reg.h>
#include <drivers/intel/gma/opregion.h>
#include <intelblocks/graphics.h>
diff --git a/src/soc/intel/icelake/lpc.c b/src/soc/intel/icelake/lpc.c
index 422ba1e..e195865 100644
--- a/src/soc/intel/icelake/lpc.c
+++ b/src/soc/intel/icelake/lpc.c
@@ -21,6 +21,7 @@
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <intelblocks/itss.h>
#include <intelblocks/lpc_lib.h>
diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c
index 57a366a..05871e4 100644
--- a/src/soc/intel/icelake/smmrelocate.c
+++ b/src/soc/intel/icelake/smmrelocate.c
@@ -17,6 +17,7 @@
#include <string.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/lapic.h>
diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h
index da2eb61..67e37de 100644
--- a/src/soc/intel/quark/include/soc/ramstage.h
+++ b/src/soc/intel/quark/include/soc/ramstage.h
@@ -20,6 +20,7 @@
#include <arch/cpu.h>
#include <chip.h>
#include <device/device.h>
+#include <device/pci_ops.h>
#include <soc/QuarkNcSocId.h>
void mainboard_gpio_i2c_init(struct device *dev);
diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c
index 867a431..50a8ff0 100644
--- a/src/soc/intel/quark/reg_access.c
+++ b/src/soc/intel/quark/reg_access.c
@@ -18,6 +18,7 @@
#include <assert.h>
#include <cpu/x86/mtrr.h>
#include <console/console.h>
+#include <device/pci_ops.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <soc/reg_access.h>
diff --git a/src/soc/intel/quark/romstage/report_platform.c b/src/soc/intel/quark/romstage/report_platform.c
index 640f5b0..cbbf43f 100644
--- a/src/soc/intel/quark/romstage/report_platform.c
+++ b/src/soc/intel/quark/romstage/report_platform.c
@@ -17,6 +17,7 @@
#include <arch/cpu.h>
#include <console/console.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <soc/cpu.h>
#include <soc/pci_devs.h>
diff --git a/src/soc/intel/quark/spi.c b/src/soc/intel/quark/spi.c
index 4b011b7..d7b29e7 100644
--- a/src/soc/intel/quark/spi.c
+++ b/src/soc/intel/quark/spi.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <assert.h>
#include <bootstate.h>
#include <console/console.h>
diff --git a/src/soc/intel/quark/storage_test.c b/src/soc/intel/quark/storage_test.c
index d3cd1d3..0d0543e 100644
--- a/src/soc/intel/quark/storage_test.c
+++ b/src/soc/intel/quark/storage_test.c
@@ -15,6 +15,7 @@
#include <arch/early_variables.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <assert.h>
#include <cbmem.h>
#include <commonlib/cbmem_id.h>
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 6403ed3..f46345b 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <chip.h>
#include <device/device.h>
#include <device/pci_def.h>
diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c
index c245523..e6e4ba4 100644
--- a/src/soc/intel/skylake/bootblock/report_platform.c
+++ b/src/soc/intel/skylake/bootblock/report_platform.c
@@ -16,6 +16,7 @@
#include <arch/cpu.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <device/pci.h>
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index f4e17c6..1eea854 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -20,6 +20,7 @@
#include <fsp/api.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci_ids.h>
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 4c8a129..e337d8b 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <bootstate.h>
#include <chip.h>
#include <console/console.h>
diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c
index e67d82f..1bf6ba4 100644
--- a/src/soc/intel/skylake/graphics.c
+++ b/src/soc/intel/skylake/graphics.c
@@ -18,6 +18,7 @@
#include <cbmem.h>
#include <console/console.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <drivers/intel/gma/i915_reg.h>
#include <drivers/intel/gma/libgfxinit.h>
#include <intelblocks/graphics.h>
diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c
index 7b3e1bd..d10ca74 100644
--- a/src/soc/intel/skylake/irq.c
+++ b/src/soc/intel/skylake/irq.c
@@ -15,6 +15,7 @@
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/itss.h>
#include <soc/ramstage.h>
diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c
index f67086b..72d6655 100644
--- a/src/soc/intel/skylake/me.c
+++ b/src/soc/intel/skylake/me.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <bootstate.h>
#include <commonlib/helpers.h>
#include <console/console.h>
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index a79cf04..4007553 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -21,6 +21,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index cb4e23f..12ed26a 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -18,6 +18,7 @@
#include <string.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/mp.h>
diff --git a/src/soc/intel/skylake/thermal.c b/src/soc/intel/skylake/thermal.c
index c1b4ce3..eef42b2 100644
--- a/src/soc/intel/skylake/thermal.c
+++ b/src/soc/intel/skylake/thermal.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <chip.h>
#include <console/console.h>
#include <device/device.h>
diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c
index bb6a54b..a100687 100644
--- a/src/southbridge/amd/agesa/hudson/bootblock.c
+++ b/src/southbridge/amd/agesa/hudson/bootblock.c
@@ -15,6 +15,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
/*
* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c
index af0cb58..6229315 100644
--- a/src/southbridge/amd/agesa/hudson/early_setup.c
+++ b/src/southbridge/amd/agesa/hudson/early_setup.c
@@ -18,6 +18,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/acpi.h>
#include <console/console.h>
#include <reset.h>
diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c
index 83eaa46..64f947e 100644
--- a/src/southbridge/amd/agesa/hudson/reset.c
+++ b/src/southbridge/amd/agesa/hudson/reset.c
@@ -17,6 +17,7 @@
#define __SIMPLE_DEVICE__
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cf9_reset.h>
#include <reset.h>
diff --git a/src/southbridge/amd/amd8111/amd8111.c b/src/southbridge/amd/amd8111/amd8111.c
index fae22ad..cbf0d3085 100644
--- a/src/southbridge/amd/amd8111/amd8111.c
+++ b/src/southbridge/amd/amd8111/amd8111.c
@@ -13,6 +13,7 @@
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "amd8111.h"
diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c
index 0abd999..90ba000 100644
--- a/src/southbridge/amd/amd8111/bootblock.c
+++ b/src/southbridge/amd/amd8111/bootblock.c
@@ -16,6 +16,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <device/pci_type.h>
diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c
index 62ae99e..e1ac8a9 100644
--- a/src/southbridge/amd/amd8111/reset.c
+++ b/src/southbridge/amd/amd8111/reset.c
@@ -15,6 +15,7 @@
#define __SIMPLE_DEVICE__
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <reset.h>
#include <device/pci.h>
#include <device/pci_ids.h>
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index 585d5a8..dae8df8 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
static void enable_rom(void)
{
diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c
index db87b6a..a8dfa31 100644
--- a/src/southbridge/amd/cimx/sb800/fan.c
+++ b/src/southbridge/amd/cimx/sb800/fan.c
@@ -16,6 +16,7 @@
#include <southbridge/amd/cimx/cimx_util.h>
#include <device/device.h>
#include <device/pci.h> /* device_operations */
+#include <device/pci_ops.h>
#include "SBPLATFORM.h"
#include "sb_cimx.h"
#include "chip.h" /* struct southbridge_amd_cimx_sb800_config */
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index c66206f..872e045 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -17,6 +17,7 @@
#include <device/device.h>
#include <device/pci.h> /* device_operations */
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <bootstate.h>
#include <arch/ioapic.h>
diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c
index 2759af6..8573f6f 100644
--- a/src/southbridge/amd/cimx/sb800/lpc.c
+++ b/src/southbridge/amd/cimx/sb800/lpc.c
@@ -20,6 +20,7 @@
#include <arch/ioapic.h>
#include "lpc.h"
#include <arch/io.h>
+#include <device/pci_ops.h>
void lpc_read_resources(struct device *dev)
{
diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c
index db0aebb..4b96d3c 100644
--- a/src/southbridge/amd/cimx/sb800/reset.c
+++ b/src/southbridge/amd/cimx/sb800/reset.c
@@ -17,6 +17,7 @@
#define __SIMPLE_DEVICE__
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cf9_reset.h>
#include <reset.h>
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
index a069463..734cc7a 100644
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
static void sb900_enable_rom(void)
{
diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c
index 64b6aa5..b04ecfa 100644
--- a/src/southbridge/amd/cimx/sb900/lpc.c
+++ b/src/southbridge/amd/cimx/sb900/lpc.c
@@ -14,6 +14,7 @@
*/
#include <device/pci.h>
+#include <device/pci_ops.h>
#include "lpc.h"
#include <console/console.h> /* printk */
#include <arch/ioapic.h>
diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c
index db0aebb..4b96d3c 100644
--- a/src/southbridge/amd/cimx/sb900/reset.c
+++ b/src/southbridge/amd/cimx/sb900/reset.c
@@ -17,6 +17,7 @@
#define __SIMPLE_DEVICE__
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cf9_reset.h>
#include <reset.h>
diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c
index ca76809..8bb2e0e 100644
--- a/src/southbridge/amd/common/amd_pci_util.c
+++ b/src/southbridge/amd/common/amd_pci_util.c
@@ -16,6 +16,7 @@
#include <console/console.h>
#include <device/pci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <string.h>
#include "amd_pci_util.h"
#include <pc80/i8259.h>
diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c
index 32b1298..0f5bdb1 100644
--- a/src/southbridge/amd/pi/hudson/bootblock.c
+++ b/src/southbridge/amd/pi/hudson/bootblock.c
@@ -15,6 +15,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
/*
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 3b91f9b..0bed6ad 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -19,6 +19,7 @@
#include <assert.h>
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/acpi.h>
#include <console/console.h>
#include <reset.h>
diff --git a/src/southbridge/amd/pi/hudson/imc.c b/src/southbridge/amd/pi/hudson/imc.c
index bb63014..4b41ab5 100644
--- a/src/southbridge/amd/pi/hudson/imc.c
+++ b/src/southbridge/amd/pi/hudson/imc.c
@@ -17,6 +17,7 @@
#include "imc.h"
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <delay.h>
#include <Porting.h>
diff --git a/src/southbridge/amd/pi/hudson/reset.c b/src/southbridge/amd/pi/hudson/reset.c
index 83eaa46..64f947e 100644
--- a/src/southbridge/amd/pi/hudson/reset.c
+++ b/src/southbridge/amd/pi/hudson/reset.c
@@ -17,6 +17,7 @@
#define __SIMPLE_DEVICE__
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cf9_reset.h>
#include <reset.h>
diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c
index 017c764..0332f2f 100644
--- a/src/southbridge/amd/rs780/early_setup.c
+++ b/src/southbridge/amd/rs780/early_setup.c
@@ -15,6 +15,7 @@
#include <types.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <northbridge/amd/amdmct/mct/mct_d.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index 364fa01..ed6f256 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -16,6 +16,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#define IO_MEM_PORT_DECODE_ENABLE_5 0x48
#define IO_MEM_PORT_DECODE_ENABLE_6 0x4a
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 167986f..af2b6c1 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -20,6 +20,7 @@
#include <stdint.h>
#include <option.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <device/pci.h>
diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c
index 4c9b0f4..9a04459 100644
--- a/src/southbridge/amd/sb700/reset.c
+++ b/src/southbridge/amd/sb700/reset.c
@@ -17,6 +17,7 @@
#define __SIMPLE_DEVICE__
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <reset.h>
#include <southbridge/amd/common/reset.h>
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index 0b638f6..156522e 100644
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -73,6 +73,7 @@
uint16_t sb7xx_51xx_decode_last_reset(void);
#else
#include <device/pci.h>
+#include <device/pci_ops.h>
/* allow override in mainboard.c */
void sb7xx_51xx_setup_sata_phys(struct device *dev);
void sb7xx_51xx_setup_sata_port_indication(void *sata_bar5);
diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c
index b08d477..9062118 100644
--- a/src/southbridge/amd/sb800/bootblock.c
+++ b/src/southbridge/amd/sb800/bootblock.c
@@ -15,6 +15,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
/*
* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h
index 126b786..30aeed2 100644
--- a/src/southbridge/amd/sr5650/cmn.h
+++ b/src/southbridge/amd/sr5650/cmn.h
@@ -18,6 +18,7 @@
#define __SR5650_CMN_H__
#include <arch/io.h>
+#include <device/pci_ops.h>
#define NBMISC_INDEX 0x60
#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
index 8b6f22a..8671882 100644
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -18,6 +18,7 @@
#include <stdint.h>
#include <arch/cpu.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c
index 53ee8d4..beaa94a 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785.c
@@ -16,6 +16,7 @@
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "bcm5785.h"
diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c
index 62b20a3..3f74436 100644
--- a/src/southbridge/broadcom/bcm5785/bootblock.c
+++ b/src/southbridge/broadcom/bcm5785/bootblock.c
@@ -16,6 +16,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <device/pci_type.h>
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
index 673f0c7..b0b8afa 100644
--- a/src/southbridge/intel/bd82x6x/bootblock.c
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include "pch.h"
/*
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c
index ee149d0..edb514b 100644
--- a/src/southbridge/intel/bd82x6x/early_me.c
+++ b/src/southbridge/intel/bd82x6x/early_me.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <delay.h>
#include <device/pci_def.h>
diff --git a/src/southbridge/intel/bd82x6x/early_me_mrc.c b/src/southbridge/intel/bd82x6x/early_me_mrc.c
index ed27573..f6b26bf 100644
--- a/src/southbridge/intel/bd82x6x/early_me_mrc.c
+++ b/src/southbridge/intel/bd82x6x/early_me_mrc.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <delay.h>
#include <device/pci_def.h>
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c
index 167311f..2e1c5fc 100644
--- a/src/southbridge/intel/bd82x6x/early_pch.c
+++ b/src/southbridge/intel/bd82x6x/early_pch.c
@@ -15,6 +15,7 @@
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/cbfs.h>
#include <ip_checksum.h>
#include <device/pci_def.h>
diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c
index 3cd98ac..d3847a5 100644
--- a/src/southbridge/intel/bd82x6x/early_smbus.c
+++ b/src/southbridge/intel/bd82x6x/early_smbus.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci_def.h>
#include <southbridge/intel/common/smbus.h>
diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c
index a5c63b6..f29ba5d 100644
--- a/src/southbridge/intel/bd82x6x/early_thermal.c
+++ b/src/southbridge/intel/bd82x6x/early_thermal.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include "pch.h"
#include "cpu/intel/model_206ax/model_206ax.h"
#include <cpu/x86/msr.h>
diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c
index c34b3ec..a7321c9 100644
--- a/src/southbridge/intel/bd82x6x/early_usb.c
+++ b/src/southbridge/intel/bd82x6x/early_usb.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include "pch.h"
diff --git a/src/southbridge/intel/bd82x6x/early_usb_mrc.c b/src/southbridge/intel/bd82x6x/early_usb_mrc.c
index e4fadad..a19794e 100644
--- a/src/southbridge/intel/bd82x6x/early_usb_mrc.c
+++ b/src/southbridge/intel/bd82x6x/early_usb_mrc.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include "pch.h"
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 1bbce06..f5516e3 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -24,6 +24,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci_ids.h>
#include <device/pci_def.h>
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index dc78e71..951c8ab 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -24,6 +24,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci_ids.h>
#include <device/pci_def.h>
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 1a646b1..6d0a478 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -19,6 +19,7 @@
#include <delay.h>
#ifdef __SMM__
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#else /* !__SMM__ */
#include <device/device.h>
diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c
index f86d8a01e..4a62eb8 100644
--- a/src/southbridge/intel/bd82x6x/pci.c
+++ b/src/southbridge/intel/bd82x6x/pci.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "pch.h"
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 5605841..39c53e8 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
#include <southbridge/intel/common/pciehp.h>
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 00a65c8..02d478c 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 69df2bf..c7f668b 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -16,6 +16,7 @@
#include <types.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <device/pci_def.h>
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index 996c89c..b4060e5 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -21,6 +21,7 @@
#include "pch.h"
#include <device/pci_ehci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
static void usb_ehci_init(struct device *dev)
{
diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c
index 1b2755b..d7b25c9 100644
--- a/src/southbridge/intel/bd82x6x/usb_xhci.c
+++ b/src/southbridge/intel/bd82x6x/usb_xhci.c
@@ -21,6 +21,7 @@
#include "pch.h"
#include <device/pci_ehci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
static void usb_xhci_init(struct device *dev)
{
diff --git a/src/southbridge/intel/bd82x6x/watchdog.c b/src/southbridge/intel/bd82x6x/watchdog.c
index c186f35..4e40dd4 100644
--- a/src/southbridge/intel/bd82x6x/watchdog.c
+++ b/src/southbridge/intel/bd82x6x/watchdog.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c
index 8a511c3..1186058 100644
--- a/src/southbridge/intel/common/gpio.c
+++ b/src/southbridge/intel/common/gpio.c
@@ -16,6 +16,7 @@
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c
index 563856c..ae13272 100644
--- a/src/southbridge/intel/common/pmbase.c
+++ b/src/southbridge/intel/common/pmbase.c
@@ -16,6 +16,7 @@
#include <stdint.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <assert.h>
diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c
index 4525934..05b73f2 100644
--- a/src/southbridge/intel/common/smihandler.c
+++ b/src/southbridge/intel/common/smihandler.c
@@ -16,6 +16,7 @@
#include <types.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/acpi.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 1d871d2..429de8d 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -23,6 +23,7 @@
#include <commonlib/helpers.h>
#include <delay.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c
index 31f8497..83e4078 100644
--- a/src/southbridge/intel/common/usb_debug.c
+++ b/src/southbridge/intel/common/usb_debug.c
@@ -18,6 +18,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_ehci.h>
#include <device/pci_def.h>
diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c
index 0aebb20..b1ee9a1 100644
--- a/src/southbridge/intel/fsp_rangeley/acpi.c
+++ b/src/southbridge/intel/fsp_rangeley/acpi.c
@@ -20,6 +20,7 @@
#include <arch/acpi.h>
#include <southbridge/intel/fsp_rangeley/soc.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <version.h>
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c
index 1ef8cb2..05e2812 100644
--- a/src/southbridge/intel/fsp_rangeley/early_init.c
+++ b/src/southbridge/intel/fsp_rangeley/early_init.c
@@ -19,6 +19,7 @@
#include <stdlib.h>
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <pc80/mc146818rtc.h>
#include <version.h>
diff --git a/src/southbridge/intel/fsp_rangeley/early_smbus.c b/src/southbridge/intel/fsp_rangeley/early_smbus.c
index 9b47837..48b7769 100644
--- a/src/southbridge/intel/fsp_rangeley/early_smbus.c
+++ b/src/southbridge/intel/fsp_rangeley/early_smbus.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci_def.h>
#include <southbridge/intel/common/smbus.h>
diff --git a/src/southbridge/intel/fsp_rangeley/early_usb.c b/src/southbridge/intel/fsp_rangeley/early_usb.c
index 0bcd09d..896ef64 100644
--- a/src/southbridge/intel/fsp_rangeley/early_usb.c
+++ b/src/southbridge/intel/fsp_rangeley/early_usb.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include "soc.h"
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c
index 0a287c4..740587a 100644
--- a/src/southbridge/intel/fsp_rangeley/gpio.c
+++ b/src/southbridge/intel/fsp_rangeley/gpio.c
@@ -17,6 +17,7 @@
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include "soc.h"
#include "gpio.h"
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c
index 3e7c17a..4dee636 100644
--- a/src/southbridge/intel/fsp_rangeley/lpc.c
+++ b/src/southbridge/intel/fsp_rangeley/lpc.c
@@ -23,6 +23,7 @@
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <arch/acpi.h>
#include <arch/cpu.h>
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index ec60920..39d4362 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -19,6 +19,7 @@
#include <lib.h>
#include <timestamp.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <cbmem.h>
diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c
index c1d5749..c4d6fda 100644
--- a/src/southbridge/intel/fsp_rangeley/sata.c
+++ b/src/southbridge/intel/fsp_rangeley/sata.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/southbridge/intel/fsp_rangeley/soc.c b/src/southbridge/intel/fsp_rangeley/soc.c
index fd83342..ec5cd07 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.c
+++ b/src/southbridge/intel/fsp_rangeley/soc.c
@@ -20,6 +20,7 @@
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include "soc.h"
static int soc_revision_id = -1;
diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c
index 227422b..34d0fa2 100644
--- a/src/southbridge/intel/fsp_rangeley/spi.c
+++ b/src/southbridge/intel/fsp_rangeley/spi.c
@@ -20,6 +20,7 @@
#include <commonlib/helpers.h>
#include <delay.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/southbridge/intel/fsp_rangeley/watchdog.c b/src/southbridge/intel/fsp_rangeley/watchdog.c
index d7d3141..f18af89 100644
--- a/src/southbridge/intel/fsp_rangeley/watchdog.c
+++ b/src/southbridge/intel/fsp_rangeley/watchdog.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <watchdog.h>
diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c
index 38b797d..ea167b5 100644
--- a/src/southbridge/intel/i82371eb/bootblock.c
+++ b/src/southbridge/intel/i82371eb/bootblock.c
@@ -16,6 +16,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <device/pci_type.h>
#include "i82371eb.h"
diff --git a/src/southbridge/intel/i82371eb/early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c
index 720cb0d..2233be0 100644
--- a/src/southbridge/intel/i82371eb/early_pm.c
+++ b/src/southbridge/intel/i82371eb/early_pm.c
@@ -16,6 +16,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c
index 4e91c0a..b8b6dba 100644
--- a/src/southbridge/intel/i82371eb/early_smbus.c
+++ b/src/southbridge/intel/i82371eb/early_smbus.c
@@ -16,6 +16,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_def.h>
diff --git a/src/southbridge/intel/i82371eb/ide.c b/src/southbridge/intel/i82371eb/ide.c
index e3ed178..33f7ac7 100644
--- a/src/southbridge/intel/i82371eb/ide.c
+++ b/src/southbridge/intel/i82371eb/ide.c
@@ -20,6 +20,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "i82371eb.h"
diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index 8030a75..b4041ef 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <pc80/isa-dma.h>
#include <pc80/mc146818rtc.h>
diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c
index 5b95c57..afc4d6a 100644
--- a/src/southbridge/intel/i82371eb/smbus.c
+++ b/src/southbridge/intel/i82371eb/smbus.c
@@ -18,6 +18,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <stdint.h>
#include <device/device.h>
diff --git a/src/southbridge/intel/i82801dx/ac97.c b/src/southbridge/intel/i82801dx/ac97.c
index f9a7904..cbbc370 100644
--- a/src/southbridge/intel/i82801dx/ac97.c
+++ b/src/southbridge/intel/i82801dx/ac97.c
@@ -19,6 +19,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <delay.h>
#include "i82801dx.h"
diff --git a/src/southbridge/intel/i82801dx/bootblock.c b/src/southbridge/intel/i82801dx/bootblock.c
index a5e48e5..1601b55 100644
--- a/src/southbridge/intel/i82801dx/bootblock.c
+++ b/src/southbridge/intel/i82801dx/bootblock.c
@@ -13,6 +13,7 @@
#include <cpu/intel/car/bootblock.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
void bootblock_early_southbridge_init(void)
{
diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c
index fabb58b..83fd9a1 100644
--- a/src/southbridge/intel/i82801dx/early_smbus.c
+++ b/src/southbridge/intel/i82801dx/early_smbus.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <console/console.h>
#include <southbridge/intel/common/smbus.h>
diff --git a/src/southbridge/intel/i82801dx/i82801dx.c b/src/southbridge/intel/i82801dx/i82801dx.c
index f233eed..765bcb2 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.c
+++ b/src/southbridge/intel/i82801dx/i82801dx.c
@@ -16,6 +16,7 @@
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include "i82801dx.h"
void i82801dx_enable(struct device *dev)
diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c
index bdea66f..b977e32 100644
--- a/src/southbridge/intel/i82801dx/smi.c
+++ b/src/southbridge/intel/i82801dx/smi.c
@@ -20,6 +20,7 @@
#include <console/console.h>
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
#include <string.h>
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index e7a9589..17bedab 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -16,6 +16,7 @@
#include <types.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
diff --git a/src/southbridge/intel/i82801gx/ac97.c b/src/southbridge/intel/i82801gx/ac97.c
index 9bf9456..582c962 100644
--- a/src/southbridge/intel/i82801gx/ac97.c
+++ b/src/southbridge/intel/i82801gx/ac97.c
@@ -19,6 +19,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <delay.h>
#include "i82801gx.h"
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c
index 6d65df3..991f1bd 100644
--- a/src/southbridge/intel/i82801gx/bootblock.c
+++ b/src/southbridge/intel/i82801gx/bootblock.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include "i82801gx.h"
static void enable_spi_prefetch(void)
diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c
index 9dddcec..e970937 100644
--- a/src/southbridge/intel/i82801gx/early_smbus.c
+++ b/src/southbridge/intel/i82801gx/early_smbus.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci_def.h>
#include <southbridge/intel/common/smbus.h>
diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c
index a93d913..6aab741 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.c
+++ b/src/southbridge/intel/i82801gx/i82801gx.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include "i82801gx.h"
#include "sata.h"
diff --git a/src/southbridge/intel/i82801gx/ide.c b/src/southbridge/intel/i82801gx/ide.c
index 9709272..e25eaae 100644
--- a/src/southbridge/intel/i82801gx/ide.c
+++ b/src/southbridge/intel/i82801gx/ide.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "i82801gx.h"
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 7497c79..ba6e082 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -22,6 +22,7 @@
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <arch/acpi.h>
#include "i82801gx.h"
diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c
index 97ae98a..514db3c 100644
--- a/src/southbridge/intel/i82801gx/pci.c
+++ b/src/southbridge/intel/i82801gx/pci.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "i82801gx.h"
diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c
index c0f9c12..4679ee5 100644
--- a/src/southbridge/intel/i82801gx/pcie.c
+++ b/src/southbridge/intel/i82801gx/pcie.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "i82801gx.h"
diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c
index 567c1e5..bf473f6 100644
--- a/src/southbridge/intel/i82801gx/sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "i82801gx.h"
#include "sata.h"
diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c
index eaa2cf1..307b5ac 100644
--- a/src/southbridge/intel/i82801gx/usb.c
+++ b/src/southbridge/intel/i82801gx/usb.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "i82801gx.h"
diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c
index b40c83d..9b79aff 100644
--- a/src/southbridge/intel/i82801gx/usb_ehci.c
+++ b/src/southbridge/intel/i82801gx/usb_ehci.c
@@ -21,6 +21,7 @@
#include "i82801gx.h"
#include <device/pci_ehci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
static void usb_ehci_init(struct device *dev)
{
diff --git a/src/southbridge/intel/i82801gx/watchdog.c b/src/southbridge/intel/i82801gx/watchdog.c
index ff4da64..12284b4 100644
--- a/src/southbridge/intel/i82801gx/watchdog.c
+++ b/src/southbridge/intel/i82801gx/watchdog.c
@@ -16,6 +16,7 @@
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <watchdog.h>
diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c
index 6252712..8174623 100644
--- a/src/southbridge/intel/i82801ix/bootblock.c
+++ b/src/southbridge/intel/i82801ix/bootblock.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
static void enable_spi_prefetch(void)
{
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c
index f7e2fd2..da124ff 100644
--- a/src/southbridge/intel/i82801ix/early_init.c
+++ b/src/southbridge/intel/i82801ix/early_init.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include "i82801ix.h"
void i82801ix_early_init(void)
diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c
index 0dda0c8..6949a30 100644
--- a/src/southbridge/intel/i82801ix/early_smbus.c
+++ b/src/southbridge/intel/i82801ix/early_smbus.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci_def.h>
#include <southbridge/intel/common/smbus.h>
diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c
index f3027bf..991ae82 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.c
+++ b/src/southbridge/intel/i82801ix/i82801ix.c
@@ -18,6 +18,7 @@
#include <stdlib.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <console/console.h>
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index f9e1114..db5d3a6 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -23,6 +23,7 @@
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <arch/acpi.h>
#include <cpu/x86/smm.h>
diff --git a/src/southbridge/intel/i82801ix/pci.c b/src/southbridge/intel/i82801ix/pci.c
index 13f92f0..4003e74 100644
--- a/src/southbridge/intel/i82801ix/pci.c
+++ b/src/southbridge/intel/i82801ix/pci.c
@@ -16,6 +16,7 @@
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "i82801ix.h"
diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c
index 04eb9b9..a36fdc6 100644
--- a/src/southbridge/intel/i82801ix/pcie.c
+++ b/src/southbridge/intel/i82801ix/pcie.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
#include <southbridge/intel/common/pciehp.h>
diff --git a/src/southbridge/intel/i82801ix/sata.c b/src/southbridge/intel/i82801ix/sata.c
index e3b7e14..65422c8 100644
--- a/src/southbridge/intel/i82801ix/sata.c
+++ b/src/southbridge/intel/i82801ix/sata.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c
index 74fa495..a9d5e7d 100644
--- a/src/southbridge/intel/i82801ix/smi.c
+++ b/src/southbridge/intel/i82801ix/smi.c
@@ -20,6 +20,7 @@
#include <device/pci.h>
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/acpi.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
diff --git a/src/southbridge/intel/i82801ix/thermal.c b/src/southbridge/intel/i82801ix/thermal.c
index 9311982..325eb08 100644
--- a/src/southbridge/intel/i82801ix/thermal.c
+++ b/src/southbridge/intel/i82801ix/thermal.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c
index e386f82..8768e3e 100644
--- a/src/southbridge/intel/i82801ix/usb_ehci.c
+++ b/src/southbridge/intel/i82801ix/usb_ehci.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "i82801ix.h"
#include <device/pci_ehci.h>
diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c
index 911361a..011c15c 100644
--- a/src/southbridge/intel/i82801jx/bootblock.c
+++ b/src/southbridge/intel/i82801jx/bootblock.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include "i82801jx.h"
static void enable_spi_prefetch(void)
diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c
index 8c87045..d2b87d1 100644
--- a/src/southbridge/intel/i82801jx/early_smbus.c
+++ b/src/southbridge/intel/i82801jx/early_smbus.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci_def.h>
#include <southbridge/intel/common/smbus.h>
diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c
index 64859f8..d15f0e3 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.c
+++ b/src/southbridge/intel/i82801jx/i82801jx.c
@@ -18,6 +18,7 @@
#include <stdlib.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <console/console.h>
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c
index b06959a..64a5590 100644
--- a/src/southbridge/intel/i82801jx/lpc.c
+++ b/src/southbridge/intel/i82801jx/lpc.c
@@ -23,6 +23,7 @@
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <arch/acpi.h>
#include <cpu/x86/smm.h>
diff --git a/src/southbridge/intel/i82801jx/pci.c b/src/southbridge/intel/i82801jx/pci.c
index cfafda0..a32d4a9 100644
--- a/src/southbridge/intel/i82801jx/pci.c
+++ b/src/southbridge/intel/i82801jx/pci.c
@@ -16,6 +16,7 @@
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "i82801jx.h"
diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c
index f5eaca5..fb90cd9 100644
--- a/src/southbridge/intel/i82801jx/pcie.c
+++ b/src/southbridge/intel/i82801jx/pcie.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
#include <southbridge/intel/common/pciehp.h>
diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c
index 5978294..bb175e6 100644
--- a/src/southbridge/intel/i82801jx/sata.c
+++ b/src/southbridge/intel/i82801jx/sata.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/southbridge/intel/i82801jx/thermal.c b/src/southbridge/intel/i82801jx/thermal.c
index 4a8ba29..d3f0122 100644
--- a/src/southbridge/intel/i82801jx/thermal.c
+++ b/src/southbridge/intel/i82801jx/thermal.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c
index 0aad672..543ac57 100644
--- a/src/southbridge/intel/i82801jx/usb_ehci.c
+++ b/src/southbridge/intel/i82801jx/usb_ehci.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "i82801jx.h"
#include <device/pci_ehci.h>
diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c
index 8760a82..241584b 100644
--- a/src/southbridge/intel/ibexpeak/early_smbus.c
+++ b/src/southbridge/intel/ibexpeak/early_smbus.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci_def.h>
#include <southbridge/intel/common/smbus.h>
diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c
index 4e4860c..6c9f794 100644
--- a/src/southbridge/intel/ibexpeak/early_thermal.c
+++ b/src/southbridge/intel/ibexpeak/early_thermal.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include "pch.h"
#include "cpu/intel/model_2065x/model_2065x.h"
#include <cpu/x86/msr.h>
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index a96b7ff..6ea3971 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -23,6 +23,7 @@
#include <pc80/isa-dma.h>
#include <pc80/i8259.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <arch/acpi.h>
#include <arch/cpu.h>
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index b1ff815..8eafd35 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -24,6 +24,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci_ids.h>
#include <device/pci_def.h>
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index 3833e12..ea66666 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -16,6 +16,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c
index 3173662..d9d0215 100644
--- a/src/southbridge/intel/ibexpeak/smi.c
+++ b/src/southbridge/intel/ibexpeak/smi.c
@@ -20,6 +20,7 @@
#include <device/pci.h>
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
#include <string.h>
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index d305635..e6e4682 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -16,6 +16,7 @@
#include <types.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <device/pci_def.h>
diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c
index 374cbf1..bafc83b 100644
--- a/src/southbridge/intel/ibexpeak/thermal.c
+++ b/src/southbridge/intel/ibexpeak/thermal.c
@@ -20,6 +20,7 @@
#include <device/pci_ids.h>
#include "pch.h"
#include <arch/io.h>
+#include <device/pci_ops.h>
static void thermal_init(struct device *dev)
{
diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c
index 13670b8..b67a96a 100644
--- a/src/southbridge/intel/ibexpeak/usb_ehci.c
+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c
@@ -22,6 +22,7 @@
#include "pch.h"
#include <device/pci_ehci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
static void usb_ehci_init(struct device *dev)
{
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c
index cb595cd..82fe07e 100644
--- a/src/southbridge/intel/lynxpoint/bootblock.c
+++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -14,6 +14,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include "pch.h"
/*
diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c
index e02a16c..b02f195 100644
--- a/src/southbridge/intel/lynxpoint/early_me.c
+++ b/src/southbridge/intel/lynxpoint/early_me.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <delay.h>
#include <halt.h>
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 912df8e..a5c69e0 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -16,6 +16,7 @@
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <elog.h>
diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c
index 3cd98ac..d3847a5 100644
--- a/src/southbridge/intel/lynxpoint/early_smbus.c
+++ b/src/southbridge/intel/lynxpoint/early_smbus.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci_def.h>
#include <southbridge/intel/common/smbus.h>
diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c
index 4b44716..c0186db 100644
--- a/src/southbridge/intel/lynxpoint/early_usb.c
+++ b/src/southbridge/intel/lynxpoint/early_usb.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_def.h>
#include "pch.h"
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c
index b6edc8d..48e0be3 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.c
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.c
@@ -16,6 +16,7 @@
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index 1a0a68c..08085af 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -24,6 +24,7 @@
#include <arch/acpi.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index b197bbc..74943c6 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -18,6 +18,7 @@
#include <console/console.h>
#include <delay.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
diff --git a/src/southbridge/intel/lynxpoint/pci.c b/src/southbridge/intel/lynxpoint/pci.c
index 3c43210..6c26bb8 100644
--- a/src/southbridge/intel/lynxpoint/pci.c
+++ b/src/southbridge/intel/lynxpoint/pci.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
+#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "pch.h"
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 30e8aa8..aa18f4a 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c
index 92fa950..44c9a07 100644
--- a/src/southbridge/intel/lynxpoint/serialio.c
+++ b/src/southbridge/intel/lynxpoint/serialio.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index fd1ba22..8c46ab0 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -18,6 +18,7 @@
#include <delay.h>
#include <types.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <device/pci_def.h>
diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c
index 7f300d6..977dcfac 100644
--- a/src/southbridge/intel/lynxpoint/usb_ehci.c
+++ b/src/southbridge/intel/lynxpoint/usb_ehci.c
@@ -21,6 +21,7 @@
#include <device/pci_ids.h>
#include <device/pci_ehci.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include "pch.h"
#ifdef __SMM__
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index 03341da..490740e 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -19,6 +19,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include "pch.h"
typedef struct southbridge_intel_lynxpoint_config config_t;
diff --git a/src/southbridge/intel/lynxpoint/watchdog.c b/src/southbridge/intel/lynxpoint/watchdog.c
index ec7cb5d..545d3d5 100644
--- a/src/southbridge/intel/lynxpoint/watchdog.c
+++ b/src/southbridge/intel/lynxpoint/watchdog.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>
#include <watchdog.h>
diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c
index 24ca0a8..4275472 100644
--- a/src/southbridge/nvidia/ck804/bootblock.c
+++ b/src/southbridge/nvidia/ck804/bootblock.c
@@ -15,6 +15,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include "ck804.h"
static void ck804_enable_rom(void)
diff --git a/src/southbridge/nvidia/ck804/early_smbus.c b/src/southbridge/nvidia/ck804/early_smbus.c
index f7bddbf..a310422 100644
--- a/src/southbridge/nvidia/ck804/early_smbus.c
+++ b/src/southbridge/nvidia/ck804/early_smbus.c
@@ -16,6 +16,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci.h>
#include <device/pci_def.h>
diff --git a/src/southbridge/nvidia/ck804/enable_usbdebug.c b/src/southbridge/nvidia/ck804/enable_usbdebug.c
index 7296e05..c866138 100644
--- a/src/southbridge/nvidia/ck804/enable_usbdebug.c
+++ b/src/southbridge/nvidia/ck804/enable_usbdebug.c
@@ -22,6 +22,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_ehci.h>
#include <device/pci_def.h>
#include "ck804.h"
diff --git a/src/southbridge/nvidia/mcp55/bootblock.c b/src/southbridge/nvidia/mcp55/bootblock.c
index 6d24f56..9a04a87 100644
--- a/src/southbridge/nvidia/mcp55/bootblock.c
+++ b/src/southbridge/nvidia/mcp55/bootblock.c
@@ -19,6 +19,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include "mcp55.h"
static void mcp55_enable_rom(void)
diff --git a/src/southbridge/nvidia/mcp55/early_smbus.c b/src/southbridge/nvidia/mcp55/early_smbus.c
index f52d079..fe9ccdd 100644
--- a/src/southbridge/nvidia/mcp55/early_smbus.c
+++ b/src/southbridge/nvidia/mcp55/early_smbus.c
@@ -18,6 +18,7 @@
*/
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <console/console.h>
#include <device/pci.h>
#include "smbus.h"
diff --git a/src/southbridge/nvidia/mcp55/enable_usbdebug.c b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
index 69e0859..b4b4286 100644
--- a/src/southbridge/nvidia/mcp55/enable_usbdebug.c
+++ b/src/southbridge/nvidia/mcp55/enable_usbdebug.c
@@ -22,6 +22,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <device/pci_ops.h>
#include <device/pci_ehci.h>
#include <device/pci_def.h>
#include "mcp55.h"
--
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Gerrit-Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Gerrit-Change-Number: 31675
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
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6
01 Mar '19
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31680 )
Change subject: device/pci: Organize Makefile
......................................................................
Patch Set 2: Code-Review+1
haven't verified that the other options also depend on CONFIG_PCI, but I assume that they do, so I only +1 this patch from me
--
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Gerrit-Change-Number: 31680
Gerrit-PatchSet: 2
Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
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