coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

1 participants
1542 discussions

Change in ...coreboot[master]: device/pci_ops: Drop parameter from pci_bus_default_ops()
by Kyösti Mälkki (Code Review) 03 Mar '19

03 Mar '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31679 ) Change subject: device/pci_ops: Drop parameter from pci_bus_default_ops() ...................................................................... device/pci_ops: Drop parameter from pci_bus_default_ops() A default is a build-time static value, fallback. Return value does not depend of input parameter. Change-Id: I43ae28f465fb46391519ec97a2a50891d458c46d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/31679 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/pci_ops.c M src/device/pci_ops.c M src/device/pci_ops_mmconf.c M src/include/device/pci_ops.h 4 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Felix Held: Looks good to me, approved diff --git a/src/arch/x86/pci_ops.c b/src/arch/x86/pci_ops.c index 82f9fd2..f30bffe 100644 --- a/src/arch/x86/pci_ops.c +++ b/src/arch/x86/pci_ops.c @@ -16,7 +16,7 @@ #include <device/device.h> #include <device/pci_ops.h> -const struct pci_bus_operations *pci_bus_default_ops(struct device *dev) +const struct pci_bus_operations *pci_bus_default_ops(void) { return &pci_cf8_conf1; } diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index de0bf63..b7c8942 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -27,7 +27,7 @@ bops = bus->dev->ops->ops_pci_bus(dev); } if (!bops) - bops = pci_bus_default_ops(dev); + bops = pci_bus_default_ops(); return bops; } diff --git a/src/device/pci_ops_mmconf.c b/src/device/pci_ops_mmconf.c index 8b7b574..0af8f8e 100644 --- a/src/device/pci_ops_mmconf.c +++ b/src/device/pci_ops_mmconf.c @@ -71,7 +71,7 @@ .write32 = pci_mmconf_write_config32, }; -const struct pci_bus_operations *pci_bus_default_ops(struct device *dev) +const struct pci_bus_operations *pci_bus_default_ops(void) { return &pci_ops_mmconf; } diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 6bcb3e9..6971ce4 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -24,7 +24,7 @@ void pci_write_config8(struct device *dev, unsigned int where, u8 val); void pci_write_config16(struct device *dev, unsigned int where, u16 val); void pci_write_config32(struct device *dev, unsigned int where, u32 val); -const struct pci_bus_operations *pci_bus_default_ops(struct device *dev); +const struct pci_bus_operations *pci_bus_default_ops(void); #endif #ifdef __SIMPLE_DEVICE__ -- To view, visit https://review.coreboot.org/c/coreboot/+/31679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43ae28f465fb46391519ec97a2a50891d458c46d Gerrit-Change-Number: 31679 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: device/pci_ops: Drop unused parameter
by Kyösti Mälkki (Code Review) 03 Mar '19

03 Mar '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31678 ) Change subject: device/pci_ops: Drop unused parameter ...................................................................... device/pci_ops: Drop unused parameter Drop the bus parameter, we do not use it. It would still be possible to do per-bus selection by evaluating the bus number, but currently we do not have need for that either. Change-Id: I09e928b4677d9db2eee12730ba7b3fdd8837805c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/31678 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/arch/x86/pci_ops_conf1.c M src/device/pci_ops.c M src/device/pci_ops_mmconf.c M src/include/device/pci.h M src/southbridge/amd/rs780/rs780.c M src/southbridge/amd/sr5650/pcie.c 6 files changed, 54 insertions(+), 65 deletions(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Felix Held: Looks good to me, approved diff --git a/src/arch/x86/pci_ops_conf1.c b/src/arch/x86/pci_ops_conf1.c index e088463..1180a82 100644 --- a/src/arch/x86/pci_ops_conf1.c +++ b/src/arch/x86/pci_ops_conf1.c @@ -27,43 +27,40 @@ ((where & 0xf00)<<16)) #endif -static uint8_t pci_conf1_read_config8(struct bus *pbus, int bus, int devfn, - int where) +static uint8_t pci_conf1_read_config8(int bus, int devfn, int where) { outl(CONF_CMD(bus, devfn, where), 0xCF8); return inb(0xCFC + (where & 3)); } -static uint16_t pci_conf1_read_config16(struct bus *pbus, int bus, int devfn, - int where) +static uint16_t pci_conf1_read_config16(int bus, int devfn, int where) { outl(CONF_CMD(bus, devfn, where), 0xCF8); return inw(0xCFC + (where & 2)); } -static uint32_t pci_conf1_read_config32(struct bus *pbus, int bus, int devfn, - int where) +static uint32_t pci_conf1_read_config32(int bus, int devfn, int where) { outl(CONF_CMD(bus, devfn, where), 0xCF8); return inl(0xCFC); } -static void pci_conf1_write_config8(struct bus *pbus, int bus, int devfn, - int where, uint8_t value) +static void pci_conf1_write_config8(int bus, int devfn, int where, + uint8_t value) { outl(CONF_CMD(bus, devfn, where), 0xCF8); outb(value, 0xCFC + (where & 3)); } -static void pci_conf1_write_config16(struct bus *pbus, int bus, int devfn, - int where, uint16_t value) +static void pci_conf1_write_config16(int bus, int devfn, int where, + uint16_t value) { outl(CONF_CMD(bus, devfn, where), 0xCF8); outw(value, 0xCFC + (where & 2)); } -static void pci_conf1_write_config32(struct bus *pbus, int bus, int devfn, - int where, uint32_t value) +static void pci_conf1_write_config32(int bus, int devfn, int where, + uint32_t value) { outl(CONF_CMD(bus, devfn, where), 0xCF8); outl(value, 0xCFC); diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 82c22a7..de0bf63 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -70,41 +70,41 @@ u8 pci_read_config8(struct device *dev, unsigned int where) { struct bus *pbus = get_pbus(dev); - return pci_bus_ops(pbus, dev)->read8(pbus, dev->bus->secondary, + return pci_bus_ops(pbus, dev)->read8(dev->bus->secondary, dev->path.pci.devfn, where); } u16 pci_read_config16(struct device *dev, unsigned int where) { struct bus *pbus = get_pbus(dev); - return pci_bus_ops(pbus, dev)->read16(pbus, dev->bus->secondary, + return pci_bus_ops(pbus, dev)->read16(dev->bus->secondary, dev->path.pci.devfn, where); } u32 pci_read_config32(struct device *dev, unsigned int where) { struct bus *pbus = get_pbus(dev); - return pci_bus_ops(pbus, dev)->read32(pbus, dev->bus->secondary, + return pci_bus_ops(pbus, dev)->read32(dev->bus->secondary, dev->path.pci.devfn, where); } void pci_write_config8(struct device *dev, unsigned int where, u8 val) { struct bus *pbus = get_pbus(dev); - pci_bus_ops(pbus, dev)->write8(pbus, dev->bus->secondary, + pci_bus_ops(pbus, dev)->write8(dev->bus->secondary, dev->path.pci.devfn, where, val); } void pci_write_config16(struct device *dev, unsigned int where, u16 val) { struct bus *pbus = get_pbus(dev); - pci_bus_ops(pbus, dev)->write16(pbus, dev->bus->secondary, + pci_bus_ops(pbus, dev)->write16(dev->bus->secondary, dev->path.pci.devfn, where, val); } void pci_write_config32(struct device *dev, unsigned int where, u32 val) { struct bus *pbus = get_pbus(dev); - pci_bus_ops(pbus, dev)->write32(pbus, dev->bus->secondary, + pci_bus_ops(pbus, dev)->write32(dev->bus->secondary, dev->path.pci.devfn, where, val); } diff --git a/src/device/pci_ops_mmconf.c b/src/device/pci_ops_mmconf.c index f321347..8b7b574 100644 --- a/src/device/pci_ops_mmconf.c +++ b/src/device/pci_ops_mmconf.c @@ -29,38 +29,35 @@ (((DEVFN) & 0xFF) << 12) |\ ((WHERE) & 0xFFF)) & ~MASK)) -static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn, - int where) +static uint8_t pci_mmconf_read_config8(int bus, int devfn, int where) { return read8(PCI_MMIO_ADDR(bus, devfn, where, 0)); } -static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn, - int where) +static uint16_t pci_mmconf_read_config16(int bus, int devfn, int where) { return read16(PCI_MMIO_ADDR(bus, devfn, where, 1)); } -static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn, - int where) +static uint32_t pci_mmconf_read_config32(int bus, int devfn, int where) { return read32(PCI_MMIO_ADDR(bus, devfn, where, 3)); } -static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn, - int where, uint8_t value) +static void pci_mmconf_write_config8(int bus, int devfn, int where, + uint8_t value) { write8(PCI_MMIO_ADDR(bus, devfn, where, 0), value); } -static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn, - int where, uint16_t value) +static void pci_mmconf_write_config16(int bus, int devfn, int where, + uint16_t value) { write16(PCI_MMIO_ADDR(bus, devfn, where, 1), value); } -static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn, - int where, uint32_t value) +static void pci_mmconf_write_config32(int bus, int devfn, int where, + uint32_t value) { write32(PCI_MMIO_ADDR(bus, devfn, where, 3), value); } diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 814433d..0ead578 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -36,15 +36,12 @@ /* Common pci bus operations */ struct pci_bus_operations { - uint8_t (*read8)(struct bus *pbus, int bus, int devfn, int where); - uint16_t (*read16)(struct bus *pbus, int bus, int devfn, int where); - uint32_t (*read32)(struct bus *pbus, int bus, int devfn, int where); - void (*write8)(struct bus *pbus, int bus, int devfn, int where, - uint8_t val); - void (*write16)(struct bus *pbus, int bus, int devfn, int where, - uint16_t val); - void (*write32)(struct bus *pbus, int bus, int devfn, int where, - uint32_t val); + uint8_t (*read8)(int bus, int devfn, int where); + uint16_t (*read16)(int bus, int devfn, int where); + uint32_t (*read32)(int bus, int devfn, int where); + void (*write8)(int bus, int devfn, int where, uint8_t val); + void (*write16)(int bus, int devfn, int where, uint16_t val); + void (*write32)(int bus, int devfn, int where, uint32_t val); }; struct pci_driver { diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index c5e38c1..28e337f 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -31,33 +31,32 @@ u32 reg; u16 word; u8 byte; - struct bus pbus; /* fake bus for dev0 fun1 */ reg = pci_read_config32(nb_dev, 0x4c); reg |= 1 << 0; pci_write_config32(nb_dev, 0x4c, reg); - word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8); + word = pci_cf8_conf1.read16(0, 1, 0xf8); word &= 0xf00; - pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word); + pci_cf8_conf1.write16(0, 1, 0xf8, word); - word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xe8); + word = pci_cf8_conf1.read16(0, 1, 0xe8); word &= ~((1 << 12) | (1 << 13) | (1 << 14)); word |= 1 << 13; - pci_cf8_conf1.write16(&pbus, 0, 1, 0xe8, word); + pci_cf8_conf1.write16(0, 1, 0xe8, word); - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94); + reg = pci_cf8_conf1.read32(0, 1, 0x94); reg &= ~((1 << 16) | (1 << 24) | (1 << 28)); - pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg); + pci_cf8_conf1.write32(0, 1, 0x94, reg); - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c); + reg = pci_cf8_conf1.read32(0, 1, 0x8c); reg &= ~((1 << 13) | (1 << 14) | (1 << 24) | (1 << 25)); reg |= 1 << 13; - pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg); + pci_cf8_conf1.write32(0, 1, 0x8c, reg); - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc); + reg = pci_cf8_conf1.read32(0, 1, 0xcc); reg |= 1 << 24; - pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg); + pci_cf8_conf1.write32(0, 1, 0xcc, reg); reg = nbmc_read_index(nb_dev, 0x7a); reg &= ~0x3f; @@ -66,31 +65,31 @@ set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11); nbmc_write_index(nb_dev, 0x7a, reg); /* Powering Down efuse and strap block clocks after boot-up. GFX Mode. */ - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc); + reg = pci_cf8_conf1.read32(0, 1, 0xcc); reg &= ~(1 << 23); reg |= 1 << 24; - pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg); + pci_cf8_conf1.write32(0, 1, 0xcc, reg); /* Programming NB CLK table. */ - byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe0); + byte = pci_cf8_conf1.read8(0, 1, 0xe0); byte |= 0x01; - pci_cf8_conf1.write8(&pbus, 0, 1, 0xe0, byte); + pci_cf8_conf1.write8(0, 1, 0xe0, byte); #if 0 /* Powerdown reference clock to graphics core PLL in northbridge only mode */ - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c); + reg = pci_cf8_conf1.read32(0, 1, 0x8c); reg |= 1 << 21; - pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg); + pci_cf8_conf1.write32(0, 1, 0x8c, reg); /* Powering Down efuse and strap block clocks after boot-up. NB Only Mode. */ - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc); + reg = pci_cf8_conf1.read32(0, 1, 0xcc); reg |= (1 << 23) | (1 << 24); - pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg); + pci_cf8_conf1.write32(0, 1, 0xcc, reg); /* Powerdown clock to memory controller in northbridge only mode */ - byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe4); + byte = pci_cf8_conf1.read8(0, 1, 0xe4); byte |= 1 << 0; - pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg); + pci_cf8_conf1.write8(0, 1, 0xe4, reg); /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ /* TODO: */ diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 9d4c689..763dd01 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -888,7 +888,6 @@ void pcie_config_misc_clk(struct device *nb_dev) { u32 reg; - //struct bus pbus; /* fake bus for dev0 fun1 */ reg = pci_read_config32(nb_dev, 0x4c); reg |= 1 << 0; @@ -902,9 +901,9 @@ set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6); /* LCLK Clock Gating */ - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94); + reg = pci_cf8_conf1.read32(0, 1, 0x94); reg &= ~(1 << 16); - pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg); + pci_cf8_conf1.write32(0, 1, 0x94, reg); } if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) { @@ -914,9 +913,9 @@ set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_SB, (3 << 6) | (~0xf), 3 << 6); /* LCLK Clock Gating */ - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94); + reg = pci_cf8_conf1.read32(0, 1, 0x94); reg &= ~(1 << 24); - pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg); + pci_cf8_conf1.write32(0, 1, 0x94, reg); } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31678 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09e928b4677d9db2eee12730ba7b3fdd8837805c Gerrit-Change-Number: 31678 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: device/pci_ops: Avoid name collisions
by Kyösti Mälkki (Code Review) 03 Mar '19

03 Mar '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31677 ) Change subject: device/pci_ops: Avoid name collisions ...................................................................... device/pci_ops: Avoid name collisions Having different signatures for the PCI config accessors prevents them from having the same name in different stages. For now, work around this using __SIMPLE_DEVICE__. Change-Id: I20f56cfe3ac7dc4421e62a99ca91f39a857c0ccf Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/31677 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/arch/x86/include/arch/pci_io_cfg.h M src/include/device/pci_mmio_cfg.h M src/include/device/pci_ops.h 3 files changed, 37 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Felix Held: Looks good to me, approved diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index d02e640..3e2129f 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -78,43 +78,48 @@ } #if !IS_ENABLED(CONFIG_MMCONF_SUPPORT) -#ifdef __SIMPLE_DEVICE__ + +/* Avoid name collisions as different stages have different signature + * for these functions. The _s_ stands for simple, fundamental IO or + * MMIO variant. + */ + static __always_inline -uint8_t pci_read_config8(pci_devfn_t dev, unsigned int where) +uint8_t pci_s_read_config8(pci_devfn_t dev, unsigned int where) { return pci_io_read_config8(dev, where); } static __always_inline -uint16_t pci_read_config16(pci_devfn_t dev, unsigned int where) +uint16_t pci_s_read_config16(pci_devfn_t dev, unsigned int where) { return pci_io_read_config16(dev, where); } static __always_inline -uint32_t pci_read_config32(pci_devfn_t dev, unsigned int where) +uint32_t pci_s_read_config32(pci_devfn_t dev, unsigned int where) { return pci_io_read_config32(dev, where); } static __always_inline -void pci_write_config8(pci_devfn_t dev, unsigned int where, uint8_t value) +void pci_s_write_config8(pci_devfn_t dev, unsigned int where, uint8_t value) { pci_io_write_config8(dev, where, value); } static __always_inline -void pci_write_config16(pci_devfn_t dev, unsigned int where, uint16_t value) +void pci_s_write_config16(pci_devfn_t dev, unsigned int where, uint16_t value) { pci_io_write_config16(dev, where, value); } static __always_inline -void pci_write_config32(pci_devfn_t dev, unsigned int where, uint32_t value) +void pci_s_write_config32(pci_devfn_t dev, unsigned int where, uint32_t value) { pci_io_write_config32(dev, where, value); } -#endif /* __SIMPLE_DEVICE__ */ + #endif #endif /* _PCI_IO_CFG_H */ diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index 0545001..d7ada4d 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -72,43 +72,46 @@ #if IS_ENABLED(CONFIG_MMCONF_SUPPORT) -#ifdef __SIMPLE_DEVICE__ +/* Avoid name collisions as different stages have different signature + * for these functions. The _s_ stands for simple, fundamental IO or + * MMIO variant. + */ + static __always_inline -uint8_t pci_read_config8(pci_devfn_t dev, unsigned int where) +uint8_t pci_s_read_config8(pci_devfn_t dev, unsigned int where) { return pci_mmio_read_config8(dev, where); } static __always_inline -uint16_t pci_read_config16(pci_devfn_t dev, unsigned int where) +uint16_t pci_s_read_config16(pci_devfn_t dev, unsigned int where) { return pci_mmio_read_config16(dev, where); } static __always_inline -uint32_t pci_read_config32(pci_devfn_t dev, unsigned int where) +uint32_t pci_s_read_config32(pci_devfn_t dev, unsigned int where) { return pci_mmio_read_config32(dev, where); } static __always_inline -void pci_write_config8(pci_devfn_t dev, unsigned int where, uint8_t value) +void pci_s_write_config8(pci_devfn_t dev, unsigned int where, uint8_t value) { pci_mmio_write_config8(dev, where, value); } static __always_inline -void pci_write_config16(pci_devfn_t dev, unsigned int where, uint16_t value) +void pci_s_write_config16(pci_devfn_t dev, unsigned int where, uint16_t value) { pci_mmio_write_config16(dev, where, value); } static __always_inline -void pci_write_config32(pci_devfn_t dev, unsigned int where, uint32_t value) +void pci_s_write_config32(pci_devfn_t dev, unsigned int where, uint32_t value) { pci_mmio_write_config32(dev, where, value); } -#endif /* __SIMPLE_DEVICE__ */ #endif diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 1cf5b77..6bcb3e9 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -5,7 +5,19 @@ #include <device/device.h> #include <arch/pci_ops.h> -#ifndef __SIMPLE_DEVICE__ +#ifdef __SIMPLE_DEVICE__ + +/* Avoid name collisions as different stages have different signature + * for these functions. The _s_ stands for simple, fundamental IO or + * MMIO variant. + */ +#define pci_read_config8 pci_s_read_config8 +#define pci_read_config16 pci_s_read_config16 +#define pci_read_config32 pci_s_read_config32 +#define pci_write_config8 pci_s_write_config8 +#define pci_write_config16 pci_s_write_config16 +#define pci_write_config32 pci_s_write_config32 +#else u8 pci_read_config8(struct device *dev, unsigned int where); u16 pci_read_config16(struct device *dev, unsigned int where); u32 pci_read_config32(struct device *dev, unsigned int where); -- To view, visit https://review.coreboot.org/c/coreboot/+/31677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20f56cfe3ac7dc4421e62a99ca91f39a857c0ccf Gerrit-Change-Number: 31677 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: Fix <io.h> includes
by Felix Held (Code Review) 03 Mar '19

03 Mar '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31693 ) Change subject: Fix <io.h> includes ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aa0bdf34cd1d53e20b4494c7986f0878f4fd840 Gerrit-Change-Number: 31693 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 03 Mar 2019 13:29:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: arch/io.h: Fix PCI and PNP simple typedefs
by Felix Held (Code Review) 03 Mar '19

03 Mar '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31690 ) Change subject: arch/io.h: Fix PCI and PNP simple typedefs ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85db254d50f18ea34a5e95bc517eac4085a5fafa Gerrit-Change-Number: 31690 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 03 Mar 2019 13:24:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: cpu/intel/model_1067x: Implement microcode loading
by Nico Huber (Code Review) 03 Mar '19

03 Mar '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31664 Change subject: cpu/intel/model_1067x: Implement microcode loading ...................................................................... cpu/intel/model_1067x: Implement microcode loading We load it once for the BSP in advance and let the MP init handle it for the APs. The BSP load could also be done earlier, e.g. before CAR setup, to align with other platforms. TEST=Booted ThinkPad X200s and checked log: Microcode is loaded correctly on the BSP before SMM setup, and reported to be up to date on all cores after. Change-Id: I85adb22a608ca3e7355bd486ebba52ec8fdd396c Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/cpu/intel/model_1067x/mp_init.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/31664/1 diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index acd56c8..b8b3159 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -42,6 +42,12 @@ return cores; } +static void get_microcode_info(const void **microcode, int *parallel) +{ + *microcode = microcode_patch; + *parallel = 1; +} + /* the SMRR enable and lock bit need to be set in IA32_FEATURE_CONTROL to enable SMRR so configure IA32_FEATURE_CONTROL early on */ static void pre_mp_smm_init(void) @@ -98,6 +104,7 @@ .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = smm_info, + .get_microcode_info = get_microcode_info, .pre_mp_smm_init = pre_mp_smm_init, .per_cpu_smm_trigger = per_cpu_smm_trigger, .relocation_handler = smm_relocation_handler, @@ -106,6 +113,9 @@ void bsp_init_and_start_aps(struct bus *cpu_bus) { + microcode_patch = intel_microcode_find(); + intel_microcode_load_unlocked(microcode_patch); + if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/31664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85adb22a608ca3e7355bd486ebba52ec8fdd396c Gerrit-Change-Number: 31664 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

5 6

Change in ...coreboot[master]: device/mmio.h: Add include file for MMIO ops
by Kyösti Mälkki (Code Review) 03 Mar '19

03 Mar '19

Hello Aaron Durbin, Patrick Rudolph, Piotr Król, Julius Werner, build bot (Jenkins), Philipp Hug, Werner Zeh, ron minnich, Felix Held, Vanessa Eusebio, Huang Jin, York Yang, Jonathan Neuschäfer, Philipp Deppenwiese, Nico Huber, Damien Zammit, David Guckian, Michał Żygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31691 to look at the new patch set (#4). Change subject: device/mmio.h: Add include file for MMIO ops ...................................................................... device/mmio.h: Add include file for MMIO ops MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/riscv/arch_timer.c M src/arch/x86/ioapic.c M src/commonlib/storage/sdhci.h M src/cpu/allwinner/a10/clock.c M src/cpu/allwinner/a10/gpio.c M src/cpu/allwinner/a10/pinmux.c M src/cpu/allwinner/a10/raminit.c M src/cpu/allwinner/a10/timer.c M src/cpu/allwinner/a10/twi.c M src/cpu/allwinner/a10/uart.c M src/cpu/amd/microcode/microcode.c M src/cpu/ti/am335x/gpio.c M src/cpu/ti/am335x/pinmux.c M src/cpu/ti/am335x/uart.c M src/device/azalia_device.c M src/device/oprom/realmode/x86.c M src/device/pci_ops_mmconf.c M src/drivers/aspeed/common/aspeed_coreboot.h M src/drivers/gic/gic.c M src/drivers/i2c/designware/dw_i2c.c M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/util.c M src/drivers/intel/gma/edid.c M src/drivers/maxim/max77686/max77686.c M src/drivers/net/atl1e.c M src/drivers/pc80/tpm/tis.c M src/drivers/siemens/nc_fpga/nc_fpga.c M src/drivers/uart/oxpcie.c M src/drivers/uart/pl011.c M src/drivers/uart/sifive.c M src/drivers/uart/uart8250mem.c M src/drivers/usb/ehci_debug.c M src/drivers/usb/pci_ehci.c M src/drivers/xgi/common/xgi_coreboot.h M src/include/device/azalia_device.h A src/include/device/mmio.h M src/include/device/pci.h M src/include/device/pci_mmio_cfg.h M src/lib/reg_script.c M src/mainboard/adi/rcc-dff/romstage.c M src/mainboard/amd/bettong/boardid.c M src/mainboard/amd/persimmon/mainboard.c M src/mainboard/amd/torpedo/mptable.c M src/mainboard/asrock/e350m1/mainboard.c M src/mainboard/asus/kcma-d8/mainboard.c M src/mainboard/asus/kgpe-d16/mainboard.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/cubietech/cubieboard/bootblock.c M src/mainboard/elmex/pcm205400/mainboard.c M src/mainboard/emulation/qemu-armv7/cbmem.c M src/mainboard/emulation/qemu-armv7/mainboard.c M src/mainboard/gizmosphere/gizmo/mainboard.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/cyan/com_init.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/foster/bootblock.c M src/mainboard/google/gale/reset.c M src/mainboard/google/gru/bootblock.c M src/mainboard/google/gru/mainboard.c M src/mainboard/google/gru/pwm_regulator.c M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kahlee/variants/baseboard/mainboard.c M src/mainboard/google/nyan/bootblock.c M src/mainboard/google/nyan/mainboard.c M src/mainboard/google/nyan_big/bootblock.c M src/mainboard/google/nyan_big/mainboard.c M src/mainboard/google/nyan_blaze/bootblock.c M src/mainboard/google/nyan_blaze/mainboard.c M src/mainboard/google/oak/bootblock.c M src/mainboard/google/peach_pit/mainboard.c M src/mainboard/google/smaug/bootblock.c M src/mainboard/google/smaug/mainboard.c M src/mainboard/google/storm/cdp.c M src/mainboard/google/storm/reset.c M src/mainboard/google/urara/bootblock.c M src/mainboard/google/veyron/bootblock.c M src/mainboard/google/veyron/mainboard.c M src/mainboard/google/veyron/romstage.c M src/mainboard/google/veyron_mickey/bootblock.c M src/mainboard/google/veyron_mickey/mainboard.c M src/mainboard/google/veyron_mickey/romstage.c M src/mainboard/google/veyron_rialto/bootblock.c M src/mainboard/google/veyron_rialto/mainboard.c M src/mainboard/google/veyron_rialto/romstage.c M src/mainboard/intel/littleplains/romstage.c M src/mainboard/intel/mohonpeak/romstage.c M src/mainboard/intel/strago/com_init.c M src/mainboard/jetway/nf81-t56n-lf/mainboard.c M src/mainboard/lippert/frontrunner-af/mainboard.c M src/mainboard/lippert/toucan-af/mainboard.c M src/mainboard/pcengines/apu1/mainboard.c M src/mainboard/pcengines/apu2/gpio_ftns.c M src/mainboard/pcengines/apu2/mainboard.c M src/mainboard/siemens/mc_apl1/mainboard.c M src/mainboard/siemens/mc_bdx1/mainboard.c M src/mainboard/ti/beaglebone/bootblock.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/gm45/raminit_read_write_training.c M src/northbridge/intel/gm45/raminit_receive_enable_calibration.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/i945/rcven.c M src/northbridge/intel/nehalem/gma.c M src/northbridge/intel/nehalem/raminit.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/iommu.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/rcven.c M src/soc/amd/common/block/psp/psp.c M src/soc/amd/common/block/s3/s3_resume.c M src/soc/amd/stoneyridge/gpio.c M src/soc/amd/stoneyridge/sb_util.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/amd/stoneyridge/spi.c M src/soc/cavium/cn81xx/clock.c M src/soc/cavium/cn81xx/cpu.c M src/soc/cavium/cn81xx/ecam0.c M src/soc/cavium/cn81xx/gpio.c M src/soc/cavium/cn81xx/sdram.c M src/soc/cavium/cn81xx/spi.c M src/soc/cavium/cn81xx/timer.c M src/soc/cavium/cn81xx/twsi.c M src/soc/cavium/cn81xx/uart.c M src/soc/imgtec/pistachio/clocks.c M src/soc/imgtec/pistachio/ddr2_init.c M src/soc/imgtec/pistachio/ddr3_init.c M src/soc/imgtec/pistachio/include/soc/cpu.h M src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h M src/soc/imgtec/pistachio/monotonic_timer.c M src/soc/imgtec/pistachio/reset.c M src/soc/imgtec/pistachio/spi.c M src/soc/imgtec/pistachio/uart.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cse.c M src/soc/intel/apollolake/pmc.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/apollolake/xdci.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/gfx.c M src/soc/intel/baytrail/gpio.c M src/soc/intel/baytrail/include/soc/gpio.h M src/soc/intel/baytrail/iosf.c M src/soc/intel/baytrail/lpe.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/baytrail/sata.c M src/soc/intel/baytrail/smm.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/baytrail/spi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/gpio.c M src/soc/intel/braswell/gpio_support.c M src/soc/intel/braswell/include/soc/gpio.h M src/soc/intel/braswell/iosf.c M src/soc/intel/braswell/lpc_init.c M src/soc/intel/braswell/lpe.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/braswell/smm.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/braswell/spi.c M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/hda.c M src/soc/intel/broadwell/igd.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/romstage/systemagent.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/broadwell/spi.c M src/soc/intel/broadwell/xhci.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/lockdown.c M src/soc/intel/cannonlake/pmc.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/romstage/power_state.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/lpss/lpss.c M src/soc/intel/common/block/pcr/pcr.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/common/hda_verb.c M src/soc/intel/denverton_ns/bootblock/uart.c M src/soc/intel/denverton_ns/gpio_dnv.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/denverton_ns/sata.c M src/soc/intel/denverton_ns/soc_util.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/bootblock/bootblock.c M src/soc/intel/fsp_baytrail/gpio.c M src/soc/intel/fsp_baytrail/i2c.c M src/soc/intel/fsp_baytrail/include/soc/gpio.h M src/soc/intel/fsp_baytrail/iosf.c M src/soc/intel/fsp_baytrail/lpe.c M src/soc/intel/fsp_baytrail/pmutil.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_baytrail/smm.c M src/soc/intel/fsp_baytrail/southcluster.c M src/soc/intel/fsp_baytrail/spi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/finalize.c M src/soc/intel/icelake/lockdown.c M src/soc/intel/icelake/pmc.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/icelake/romstage/power_state.c M src/soc/intel/quark/spi.c M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/lockdown.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/thermal.c M src/soc/mediatek/common/gpio.c M src/soc/mediatek/common/mtcmos.c M src/soc/mediatek/common/pll.c M src/soc/mediatek/common/pmic_wrap.c M src/soc/mediatek/common/reset.c M src/soc/mediatek/common/spi.c M src/soc/mediatek/common/timer.c M src/soc/mediatek/common/uart.c M src/soc/mediatek/common/usb.c M src/soc/mediatek/common/wdt.c M src/soc/mediatek/mt8173/ddp.c M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/dsi.c M src/soc/mediatek/mt8173/emi.c M src/soc/mediatek/mt8173/flash_controller.c M src/soc/mediatek/mt8173/gpio.c M src/soc/mediatek/mt8173/gpio_init.c M src/soc/mediatek/mt8173/i2c.c M src/soc/mediatek/mt8173/mmu_operations.c M src/soc/mediatek/mt8173/pll.c M src/soc/mediatek/mt8173/pmic_wrap.c M src/soc/mediatek/mt8173/spi.c M src/soc/mediatek/mt8173/timer.c M src/soc/mediatek/mt8183/auxadc.c M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/gpio.c M src/soc/mediatek/mt8183/mmu_operations.c M src/soc/mediatek/mt8183/mtcmos.c M src/soc/mediatek/mt8183/pll.c M src/soc/mediatek/mt8183/pmic_wrap.c M src/soc/mediatek/mt8183/spi.c M src/soc/nvidia/tegra/apbmisc.c M src/soc/nvidia/tegra/gpio.c M src/soc/nvidia/tegra/i2c.c M src/soc/nvidia/tegra/pingroup.c M src/soc/nvidia/tegra/pinmux.c M src/soc/nvidia/tegra/usb.c M src/soc/nvidia/tegra124/clock.c M src/soc/nvidia/tegra124/display.c M src/soc/nvidia/tegra124/dma.c M src/soc/nvidia/tegra124/include/soc/clock.h M src/soc/nvidia/tegra124/monotonic_timer.c M src/soc/nvidia/tegra124/power.c M src/soc/nvidia/tegra124/sdram.c M src/soc/nvidia/tegra124/spi.c M src/soc/nvidia/tegra124/uart.c M src/soc/nvidia/tegra210/addressmap.c M src/soc/nvidia/tegra210/bootblock.c M src/soc/nvidia/tegra210/ccplex.c M src/soc/nvidia/tegra210/clock.c M src/soc/nvidia/tegra210/cpu.c M src/soc/nvidia/tegra210/dc.c M src/soc/nvidia/tegra210/dma.c M src/soc/nvidia/tegra210/dsi.c M src/soc/nvidia/tegra210/flow_ctrl.c M src/soc/nvidia/tegra210/i2c6.c M src/soc/nvidia/tegra210/include/soc/clock.h M src/soc/nvidia/tegra210/include/soc/id.h M src/soc/nvidia/tegra210/include/soc/tegra_dsi.h M src/soc/nvidia/tegra210/mipi.c M src/soc/nvidia/tegra210/monotonic_timer.c M src/soc/nvidia/tegra210/padconfig.c M src/soc/nvidia/tegra210/power.c M src/soc/nvidia/tegra210/ram_code.c M src/soc/nvidia/tegra210/ramstage.c M src/soc/nvidia/tegra210/sdram.c M src/soc/nvidia/tegra210/spi.c M src/soc/nvidia/tegra210/uart.c M src/soc/qualcomm/ipq40xx/blobs_init.c M src/soc/qualcomm/ipq40xx/blsp.c M src/soc/qualcomm/ipq40xx/clock.c M src/soc/qualcomm/ipq40xx/gpio.c M src/soc/qualcomm/ipq40xx/include/soc/iomap.h M src/soc/qualcomm/ipq40xx/lcc.c M src/soc/qualcomm/ipq40xx/qup.c M src/soc/qualcomm/ipq40xx/spi.c M src/soc/qualcomm/ipq40xx/timer.c M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/ipq40xx/usb.c M src/soc/qualcomm/ipq806x/blobs_init.c M src/soc/qualcomm/ipq806x/clock.c M src/soc/qualcomm/ipq806x/gpio.c M src/soc/qualcomm/ipq806x/gsbi.c M src/soc/qualcomm/ipq806x/include/soc/iomap.h M src/soc/qualcomm/ipq806x/lcc.c M src/soc/qualcomm/ipq806x/qup.c M src/soc/qualcomm/ipq806x/spi.c M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/ipq806x/usb.c M src/soc/qualcomm/sdm845/clock.c M src/soc/qualcomm/sdm845/gpio.c M src/soc/qualcomm/sdm845/qspi.c M src/soc/rockchip/common/edp.c M src/soc/rockchip/common/gpio.c M src/soc/rockchip/common/i2c.c M src/soc/rockchip/common/include/soc/soc.h M src/soc/rockchip/common/pwm.c M src/soc/rockchip/common/spi.c M src/soc/rockchip/common/vop.c M src/soc/rockchip/rk3288/clock.c M src/soc/rockchip/rk3288/crypto.c M src/soc/rockchip/rk3288/display.c M src/soc/rockchip/rk3288/hdmi.c M src/soc/rockchip/rk3288/sdram.c M src/soc/rockchip/rk3288/software_i2c.c M src/soc/rockchip/rk3288/timer.c M src/soc/rockchip/rk3288/tsadc.c M src/soc/rockchip/rk3399/bootblock.c M src/soc/rockchip/rk3399/clock.c M src/soc/rockchip/rk3399/display.c M src/soc/rockchip/rk3399/mipi.c M src/soc/rockchip/rk3399/saradc.c M src/soc/rockchip/rk3399/sdram.c M src/soc/rockchip/rk3399/timer.c M src/soc/rockchip/rk3399/tsadc.c M src/soc/rockchip/rk3399/usb.c M src/soc/samsung/exynos5250/clock.c M src/soc/samsung/exynos5250/clock_init.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5250/dmc_common.c M src/soc/samsung/exynos5250/dmc_init_ddr3.c M src/soc/samsung/exynos5250/dp-reg.c M src/soc/samsung/exynos5250/fb.c M src/soc/samsung/exynos5250/gpio.c M src/soc/samsung/exynos5250/i2c.c M src/soc/samsung/exynos5250/include/soc/cpu.h M src/soc/samsung/exynos5250/power.c M src/soc/samsung/exynos5250/spi.c M src/soc/samsung/exynos5250/timer.c M src/soc/samsung/exynos5250/tmu.c M src/soc/samsung/exynos5250/trustzone.c M src/soc/samsung/exynos5250/uart.c M src/soc/samsung/exynos5250/usb.c M src/soc/samsung/exynos5420/clock.c M src/soc/samsung/exynos5420/clock_init.c M src/soc/samsung/exynos5420/cpu.c M src/soc/samsung/exynos5420/dmc_common.c M src/soc/samsung/exynos5420/dmc_init_ddr3.c M src/soc/samsung/exynos5420/dp_lowlevel.c M src/soc/samsung/exynos5420/fimd.c M src/soc/samsung/exynos5420/gpio.c M src/soc/samsung/exynos5420/i2c.c M src/soc/samsung/exynos5420/include/soc/cpu.h M src/soc/samsung/exynos5420/power.c M src/soc/samsung/exynos5420/smp.c M src/soc/samsung/exynos5420/spi.c M src/soc/samsung/exynos5420/timer.c M src/soc/samsung/exynos5420/tmu.c M src/soc/samsung/exynos5420/trustzone.c M src/soc/samsung/exynos5420/uart.c M src/soc/samsung/exynos5420/usb.c M src/soc/sifive/fu540/bootblock.c M src/soc/sifive/fu540/clint.c M src/soc/sifive/fu540/clock.c M src/soc/sifive/fu540/otp.c M src/southbridge/amd/agesa/hudson/enable_usbdebug.c M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/agesa/hudson/imc.c M src/southbridge/amd/agesa/hudson/smi.h M src/southbridge/amd/agesa/hudson/spi.c M src/southbridge/amd/amd8111/nic.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/cimx/sb800/spi.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/enable_usbdebug.c M src/southbridge/amd/pi/hudson/gpio.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/pi/hudson/imc.c M src/southbridge/amd/pi/hudson/smi.h M src/southbridge/amd/sb700/enable_usbdebug.c M src/southbridge/amd/sb700/hda.c M src/southbridge/amd/sb700/sata.c M src/southbridge/amd/sb700/spi.c M src/southbridge/amd/sb700/usb.c M src/southbridge/amd/sb800/enable_usbdebug.c M src/southbridge/amd/sb800/hda.c M src/southbridge/amd/sb800/sata.c M src/southbridge/amd/sb800/usb.c M src/southbridge/amd/sr5650/sr5650.c M src/southbridge/broadcom/bcm5785/sata.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/early_thermal.c M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/usb_ehci.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/fsp_rangeley/early_init.c M src/southbridge/intel/fsp_rangeley/gpio.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/fsp_rangeley/sata.c M src/southbridge/intel/fsp_rangeley/spi.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/usb_ehci.c M src/southbridge/intel/i82801ix/hdaudio.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801ix/thermal.c M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/i82801jx/thermal.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/early_thermal.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/ibexpeak/thermal.c M src/southbridge/intel/ibexpeak/usb_ehci.c M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/hda_verb.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c M src/southbridge/nvidia/ck804/nic.c M src/southbridge/nvidia/mcp55/azalia.c M src/southbridge/nvidia/mcp55/nic.c M src/vendorcode/cavium/include/bdk/bdk-coreboot.h M src/vendorcode/google/chromeos/watchdog.c M src/vendorcode/siemens/hwilib/hwilib.c 465 files changed, 489 insertions(+), 358 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/31691/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/31691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Gerrit-Change-Number: 31691 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: arch/io.h: Fix PCI and PNP simple typedefs
by Kyösti Mälkki (Code Review) 03 Mar '19

03 Mar '19

Hello Aaron Durbin, Felix Held, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31690 to look at the new patch set (#4). Change subject: arch/io.h: Fix PCI and PNP simple typedefs ...................................................................... arch/io.h: Fix PCI and PNP simple typedefs Provide clean separation for PCI and PNP headers, followup will also move PNP outside <arch/io.h>. Change-Id: I85db254d50f18ea34a5e95bc517eac4085a5fafa Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/include/arch/io.h M src/include/device/pci_ehci.h M src/include/device/pci_ops.h M src/include/device/pci_type.h M src/include/reg_script.h M src/northbridge/amd/amdfam10/pci.h 6 files changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/31690/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/31690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85db254d50f18ea34a5e95bc517eac4085a5fafa Gerrit-Change-Number: 31690 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: include/efi/efi_datatype: Convert EFI datatypes as per coreboot speci...
by Subrata Banik (Code Review) 03 Mar '19

03 Mar '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31648 ) Change subject: include/efi/efi_datatype: Convert EFI datatypes as per coreboot specification ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/31648/3/src/include/efi/efi_datatype.h File src/include/efi/efi_datatype.h: https://review.coreboot.org/#/c/31648/3/src/include/efi/efi_datatype.h@16 PS3, Line 16: /* Create coreboot equivalent datatype for EFI based on UDK2018 */ > Can we just say TianoCore. […] Philipp, i think Tianocore might not applicable here, can i update as UEFI ? https://www.tianocore.org/ -- To view, visit https://review.coreboot.org/c/coreboot/+/31648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79cdaaa1dd63d248692989d943a15ad178c46369 Gerrit-Change-Number: 31648 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Comment-Date: Sun, 03 Mar 2019 02:20:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: Fix <io.h> includes
by Arthur Heymans (Code Review) 03 Mar '19

03 Mar '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31693 ) Change subject: Fix <io.h> includes ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aa0bdf34cd1d53e20b4494c7986f0878f4fd840 Gerrit-Change-Number: 31693 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 03 Mar 2019 02:06:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2019