coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: device/mmio.h: Add include file for MMIO ops
by Kyösti Mälkki (Code Review) 02 Mar '19

02 Mar '19

Hello Aaron Durbin, Patrick Rudolph, Piotr Król, Julius Werner, build bot (Jenkins), Philipp Hug, Werner Zeh, Felix Held, Vanessa Eusebio, Huang Jin, Jonathan Neuschäfer, Philipp Deppenwiese, Nico Huber, David Guckian, Michał Żygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31691 to look at the new patch set (#3). Change subject: device/mmio.h: Add include file for MMIO ops ...................................................................... device/mmio.h: Add include file for MMIO ops MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/riscv/arch_timer.c M src/arch/x86/ioapic.c M src/commonlib/storage/sdhci.h M src/cpu/allwinner/a10/clock.c M src/cpu/allwinner/a10/gpio.c M src/cpu/allwinner/a10/pinmux.c M src/cpu/allwinner/a10/raminit.c M src/cpu/allwinner/a10/timer.c M src/cpu/allwinner/a10/twi.c M src/cpu/allwinner/a10/uart.c M src/cpu/amd/microcode/microcode.c M src/cpu/ti/am335x/gpio.c M src/cpu/ti/am335x/pinmux.c M src/cpu/ti/am335x/uart.c M src/device/azalia_device.c M src/device/oprom/realmode/x86.c M src/device/pci_ops_mmconf.c M src/drivers/aspeed/common/aspeed_coreboot.h M src/drivers/gic/gic.c M src/drivers/i2c/designware/dw_i2c.c M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/util.c M src/drivers/intel/gma/edid.c M src/drivers/net/atl1e.c M src/drivers/pc80/tpm/tis.c M src/drivers/siemens/nc_fpga/nc_fpga.c M src/drivers/uart/oxpcie.c M src/drivers/uart/pl011.c M src/drivers/uart/sifive.c M src/drivers/uart/uart8250mem.c M src/drivers/usb/ehci_debug.c M src/drivers/usb/pci_ehci.c M src/drivers/xgi/common/xgi_coreboot.h A src/include/device/mmio.h M src/include/device/pci.h M src/include/device/pci_mmio_cfg.h M src/lib/reg_script.c M src/mainboard/adi/rcc-dff/romstage.c M src/mainboard/amd/bettong/boardid.c M src/mainboard/amd/persimmon/mainboard.c M src/mainboard/amd/torpedo/mptable.c M src/mainboard/asrock/e350m1/mainboard.c M src/mainboard/asus/kcma-d8/mainboard.c M src/mainboard/asus/kgpe-d16/mainboard.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/cubietech/cubieboard/bootblock.c M src/mainboard/elmex/pcm205400/mainboard.c M src/mainboard/emulation/qemu-armv7/cbmem.c M src/mainboard/emulation/qemu-armv7/mainboard.c M src/mainboard/gizmosphere/gizmo/mainboard.c M src/mainboard/google/cyan/chromeos.c M src/mainboard/google/cyan/com_init.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/foster/bootblock.c M src/mainboard/google/gale/reset.c M src/mainboard/google/gru/bootblock.c M src/mainboard/google/gru/mainboard.c M src/mainboard/google/gru/pwm_regulator.c M src/mainboard/google/kahlee/variants/baseboard/mainboard.c M src/mainboard/google/nyan/bootblock.c M src/mainboard/google/nyan/mainboard.c M src/mainboard/google/nyan_big/bootblock.c M src/mainboard/google/nyan_big/mainboard.c M src/mainboard/google/nyan_blaze/bootblock.c M src/mainboard/google/nyan_blaze/mainboard.c M src/mainboard/google/peach_pit/mainboard.c M src/mainboard/google/smaug/bootblock.c M src/mainboard/google/smaug/mainboard.c M src/mainboard/google/storm/reset.c M src/mainboard/google/urara/bootblock.c M src/mainboard/google/veyron/bootblock.c M src/mainboard/google/veyron/mainboard.c M src/mainboard/google/veyron/romstage.c M src/mainboard/google/veyron_mickey/bootblock.c M src/mainboard/google/veyron_mickey/mainboard.c M src/mainboard/google/veyron_mickey/romstage.c M src/mainboard/google/veyron_rialto/bootblock.c M src/mainboard/google/veyron_rialto/mainboard.c M src/mainboard/google/veyron_rialto/romstage.c M src/mainboard/intel/littleplains/romstage.c M src/mainboard/intel/mohonpeak/romstage.c M src/mainboard/intel/strago/com_init.c M src/mainboard/jetway/nf81-t56n-lf/mainboard.c M src/mainboard/lippert/frontrunner-af/mainboard.c M src/mainboard/lippert/toucan-af/mainboard.c M src/mainboard/pcengines/apu1/mainboard.c M src/mainboard/pcengines/apu2/gpio_ftns.c M src/mainboard/pcengines/apu2/mainboard.c M src/mainboard/siemens/mc_apl1/mainboard.c M src/mainboard/siemens/mc_bdx1/mainboard.c M src/mainboard/ti/beaglebone/bootblock.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/gm45/raminit.c M src/northbridge/intel/gm45/raminit_read_write_training.c M src/northbridge/intel/gm45/raminit_receive_enable_calibration.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/i945/gma.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/i945/rcven.c M src/northbridge/intel/nehalem/gma.c M src/northbridge/intel/nehalem/raminit.c M src/northbridge/intel/pineview/gma.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/iommu.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/rcven.c M src/soc/amd/common/block/psp/psp.c M src/soc/amd/common/block/s3/s3_resume.c M src/soc/amd/stoneyridge/gpio.c M src/soc/amd/stoneyridge/sb_util.c M src/soc/amd/stoneyridge/southbridge.c M src/soc/amd/stoneyridge/spi.c M src/soc/cavium/cn81xx/clock.c M src/soc/cavium/cn81xx/cpu.c M src/soc/cavium/cn81xx/ecam0.c M src/soc/cavium/cn81xx/gpio.c M src/soc/cavium/cn81xx/sdram.c M src/soc/cavium/cn81xx/spi.c M src/soc/cavium/cn81xx/timer.c M src/soc/cavium/cn81xx/twsi.c M src/soc/cavium/cn81xx/uart.c M src/soc/imgtec/pistachio/clocks.c M src/soc/imgtec/pistachio/ddr2_init.c M src/soc/imgtec/pistachio/ddr3_init.c M src/soc/imgtec/pistachio/include/soc/cpu.h M src/soc/imgtec/pistachio/include/soc/ddr_private_reg.h M src/soc/imgtec/pistachio/monotonic_timer.c M src/soc/imgtec/pistachio/reset.c M src/soc/imgtec/pistachio/spi.c M src/soc/imgtec/pistachio/uart.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cse.c M src/soc/intel/apollolake/pmc.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/apollolake/xdci.c M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/gfx.c M src/soc/intel/baytrail/gpio.c M src/soc/intel/baytrail/include/soc/gpio.h M src/soc/intel/baytrail/iosf.c M src/soc/intel/baytrail/lpe.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/baytrail/sata.c M src/soc/intel/baytrail/smm.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/baytrail/spi.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/gpio.c M src/soc/intel/braswell/gpio_support.c M src/soc/intel/braswell/iosf.c M src/soc/intel/braswell/lpc_init.c M src/soc/intel/braswell/lpe.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/braswell/smm.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/braswell/spi.c M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/hda.c M src/soc/intel/broadwell/igd.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/romstage/systemagent.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/broadwell/spi.c M src/soc/intel/broadwell/xhci.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/lockdown.c M src/soc/intel/cannonlake/pmc.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/romstage/power_state.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/lpss/lpss.c M src/soc/intel/common/block/pcr/pcr.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/common/hda_verb.c M src/soc/intel/denverton_ns/bootblock/uart.c M src/soc/intel/denverton_ns/gpio_dnv.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/denverton_ns/sata.c M src/soc/intel/denverton_ns/soc_util.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/bootblock/bootblock.c M src/soc/intel/fsp_baytrail/gpio.c M src/soc/intel/fsp_baytrail/i2c.c M src/soc/intel/fsp_baytrail/include/soc/gpio.h M src/soc/intel/fsp_baytrail/iosf.c M src/soc/intel/fsp_baytrail/lpe.c M src/soc/intel/fsp_baytrail/pmutil.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_baytrail/smm.c M src/soc/intel/fsp_baytrail/southcluster.c M src/soc/intel/fsp_baytrail/spi.c M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/finalize.c M src/soc/intel/icelake/lockdown.c M src/soc/intel/icelake/pmc.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/icelake/romstage/power_state.c M src/soc/intel/quark/spi.c M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/lockdown.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/thermal.c M src/soc/mediatek/common/gpio.c M src/soc/mediatek/common/mtcmos.c M src/soc/mediatek/common/pll.c M src/soc/mediatek/common/pmic_wrap.c M src/soc/mediatek/common/reset.c M src/soc/mediatek/common/spi.c M src/soc/mediatek/common/timer.c M src/soc/mediatek/common/uart.c M src/soc/mediatek/common/usb.c M src/soc/mediatek/common/wdt.c M src/soc/mediatek/mt8173/ddp.c M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/dsi.c M src/soc/mediatek/mt8173/emi.c M src/soc/mediatek/mt8173/flash_controller.c M src/soc/mediatek/mt8173/gpio.c M src/soc/mediatek/mt8173/gpio_init.c M src/soc/mediatek/mt8173/i2c.c M src/soc/mediatek/mt8173/mmu_operations.c M src/soc/mediatek/mt8173/pll.c M src/soc/mediatek/mt8173/pmic_wrap.c M src/soc/mediatek/mt8173/spi.c M src/soc/mediatek/mt8173/timer.c M src/soc/mediatek/mt8183/auxadc.c M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/mmu_operations.c M src/soc/mediatek/mt8183/mtcmos.c M src/soc/mediatek/mt8183/pll.c M src/soc/mediatek/mt8183/pmic_wrap.c M src/soc/mediatek/mt8183/spi.c M src/soc/nvidia/tegra/apbmisc.c M src/soc/nvidia/tegra/gpio.c M src/soc/nvidia/tegra/i2c.c M src/soc/nvidia/tegra/pingroup.c M src/soc/nvidia/tegra/pinmux.c M src/soc/nvidia/tegra/usb.c M src/soc/nvidia/tegra124/clock.c M src/soc/nvidia/tegra124/display.c M src/soc/nvidia/tegra124/dma.c M src/soc/nvidia/tegra124/monotonic_timer.c M src/soc/nvidia/tegra124/power.c M src/soc/nvidia/tegra124/sdram.c M src/soc/nvidia/tegra124/spi.c M src/soc/nvidia/tegra124/uart.c M src/soc/nvidia/tegra210/addressmap.c M src/soc/nvidia/tegra210/bootblock.c M src/soc/nvidia/tegra210/ccplex.c M src/soc/nvidia/tegra210/clock.c M src/soc/nvidia/tegra210/cpu.c M src/soc/nvidia/tegra210/dc.c M src/soc/nvidia/tegra210/dma.c M src/soc/nvidia/tegra210/dsi.c M src/soc/nvidia/tegra210/flow_ctrl.c M src/soc/nvidia/tegra210/i2c6.c M src/soc/nvidia/tegra210/include/soc/id.h M src/soc/nvidia/tegra210/include/soc/tegra_dsi.h M src/soc/nvidia/tegra210/mipi.c M src/soc/nvidia/tegra210/monotonic_timer.c M src/soc/nvidia/tegra210/padconfig.c M src/soc/nvidia/tegra210/power.c M src/soc/nvidia/tegra210/ram_code.c M src/soc/nvidia/tegra210/ramstage.c M src/soc/nvidia/tegra210/sdram.c M src/soc/nvidia/tegra210/spi.c M src/soc/nvidia/tegra210/uart.c M src/soc/qualcomm/ipq40xx/blobs_init.c M src/soc/qualcomm/ipq40xx/clock.c M src/soc/qualcomm/ipq40xx/gpio.c M src/soc/qualcomm/ipq40xx/include/soc/iomap.h M src/soc/qualcomm/ipq40xx/lcc.c M src/soc/qualcomm/ipq40xx/qup.c M src/soc/qualcomm/ipq40xx/spi.c M src/soc/qualcomm/ipq40xx/timer.c M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/ipq40xx/usb.c M src/soc/qualcomm/ipq806x/blobs_init.c M src/soc/qualcomm/ipq806x/clock.c M src/soc/qualcomm/ipq806x/gpio.c M src/soc/qualcomm/ipq806x/gsbi.c M src/soc/qualcomm/ipq806x/include/soc/iomap.h M src/soc/qualcomm/ipq806x/lcc.c M src/soc/qualcomm/ipq806x/qup.c M src/soc/qualcomm/ipq806x/spi.c M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/ipq806x/usb.c M src/soc/qualcomm/sdm845/clock.c M src/soc/qualcomm/sdm845/gpio.c M src/soc/qualcomm/sdm845/qspi.c M src/soc/rockchip/common/edp.c M src/soc/rockchip/common/gpio.c M src/soc/rockchip/common/i2c.c M src/soc/rockchip/common/pwm.c M src/soc/rockchip/common/spi.c M src/soc/rockchip/common/vop.c M src/soc/rockchip/rk3288/clock.c M src/soc/rockchip/rk3288/crypto.c M src/soc/rockchip/rk3288/display.c M src/soc/rockchip/rk3288/hdmi.c M src/soc/rockchip/rk3288/sdram.c M src/soc/rockchip/rk3288/software_i2c.c M src/soc/rockchip/rk3288/timer.c M src/soc/rockchip/rk3288/tsadc.c M src/soc/rockchip/rk3399/bootblock.c M src/soc/rockchip/rk3399/clock.c M src/soc/rockchip/rk3399/display.c M src/soc/rockchip/rk3399/mipi.c M src/soc/rockchip/rk3399/saradc.c M src/soc/rockchip/rk3399/sdram.c M src/soc/rockchip/rk3399/timer.c M src/soc/rockchip/rk3399/tsadc.c M src/soc/rockchip/rk3399/usb.c M src/soc/samsung/exynos5250/clock.c M src/soc/samsung/exynos5250/clock_init.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5250/dmc_common.c M src/soc/samsung/exynos5250/dmc_init_ddr3.c M src/soc/samsung/exynos5250/dp-reg.c M src/soc/samsung/exynos5250/fb.c M src/soc/samsung/exynos5250/gpio.c M src/soc/samsung/exynos5250/i2c.c M src/soc/samsung/exynos5250/power.c M src/soc/samsung/exynos5250/spi.c M src/soc/samsung/exynos5250/timer.c M src/soc/samsung/exynos5250/tmu.c M src/soc/samsung/exynos5250/trustzone.c M src/soc/samsung/exynos5250/uart.c M src/soc/samsung/exynos5250/usb.c M src/soc/samsung/exynos5420/clock.c M src/soc/samsung/exynos5420/clock_init.c M src/soc/samsung/exynos5420/cpu.c M src/soc/samsung/exynos5420/dmc_common.c M src/soc/samsung/exynos5420/dmc_init_ddr3.c M src/soc/samsung/exynos5420/dp_lowlevel.c M src/soc/samsung/exynos5420/fimd.c M src/soc/samsung/exynos5420/gpio.c M src/soc/samsung/exynos5420/i2c.c M src/soc/samsung/exynos5420/power.c M src/soc/samsung/exynos5420/smp.c M src/soc/samsung/exynos5420/spi.c M src/soc/samsung/exynos5420/timer.c M src/soc/samsung/exynos5420/tmu.c M src/soc/samsung/exynos5420/trustzone.c M src/soc/samsung/exynos5420/uart.c M src/soc/samsung/exynos5420/usb.c M src/soc/sifive/fu540/bootblock.c M src/soc/sifive/fu540/clint.c M src/soc/sifive/fu540/clock.c M src/soc/sifive/fu540/otp.c M src/southbridge/amd/agesa/hudson/enable_usbdebug.c M src/southbridge/amd/agesa/hudson/hudson.c M src/southbridge/amd/agesa/hudson/imc.c M src/southbridge/amd/agesa/hudson/smi.h M src/southbridge/amd/agesa/hudson/spi.c M src/southbridge/amd/amd8111/nic.c M src/southbridge/amd/cimx/sb800/late.c M src/southbridge/amd/cimx/sb800/spi.c M src/southbridge/amd/pi/hudson/early_setup.c M src/southbridge/amd/pi/hudson/enable_usbdebug.c M src/southbridge/amd/pi/hudson/gpio.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/pi/hudson/imc.c M src/southbridge/amd/pi/hudson/smi.h M src/southbridge/amd/sb700/enable_usbdebug.c M src/southbridge/amd/sb700/hda.c M src/southbridge/amd/sb700/sata.c M src/southbridge/amd/sb700/spi.c M src/southbridge/amd/sb700/usb.c M src/southbridge/amd/sb800/enable_usbdebug.c M src/southbridge/amd/sb800/hda.c M src/southbridge/amd/sb800/sata.c M src/southbridge/amd/sb800/usb.c M src/southbridge/amd/sr5650/sr5650.c M src/southbridge/broadcom/bcm5785/sata.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/early_thermal.c M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/usb_ehci.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/fsp_rangeley/early_init.c M src/southbridge/intel/fsp_rangeley/gpio.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/fsp_rangeley/sata.c M src/southbridge/intel/fsp_rangeley/spi.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801gx/usb_ehci.c M src/southbridge/intel/i82801ix/hdaudio.c M src/southbridge/intel/i82801ix/sata.c M src/southbridge/intel/i82801ix/thermal.c M src/southbridge/intel/i82801jx/hdaudio.c M src/southbridge/intel/i82801jx/sata.c M src/southbridge/intel/i82801jx/thermal.c M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/early_thermal.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/ibexpeak/thermal.c M src/southbridge/intel/ibexpeak/usb_ehci.c M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/hda_verb.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c M src/southbridge/nvidia/ck804/nic.c M src/southbridge/nvidia/mcp55/azalia.c M src/southbridge/nvidia/mcp55/nic.c M src/vendorcode/cavium/include/bdk/bdk-coreboot.h M src/vendorcode/google/chromeos/watchdog.c M src/vendorcode/siemens/hwilib/hwilib.c 452 files changed, 480 insertions(+), 346 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/31691/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/31691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Gerrit-Change-Number: 31691 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: arch/io.h: Fix PCI and PNP simple typedefs
by Kyösti Mälkki (Code Review) 02 Mar '19

02 Mar '19

Hello Aaron Durbin, Felix Held, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31690 to look at the new patch set (#3). Change subject: arch/io.h: Fix PCI and PNP simple typedefs ...................................................................... arch/io.h: Fix PCI and PNP simple typedefs Provide clean separation for PCI and PNP headers, followup will also move PNP outside <arch/io.h>. Change-Id: I85db254d50f18ea34a5e95bc517eac4085a5fafa Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/include/arch/io.h M src/include/device/pci_ops.h M src/include/device/pci_type.h M src/northbridge/amd/amdfam10/pci.h 4 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/31690/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/31690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85db254d50f18ea34a5e95bc517eac4085a5fafa Gerrit-Change-Number: 31690 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: include/efi/efi_datatype: Convert EFI datatypes as per coreboot speci...
by Philipp Deppenwiese (Code Review) 02 Mar '19

02 Mar '19

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31648 ) Change subject: include/efi/efi_datatype: Convert EFI datatypes as per coreboot specification ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/31648/3/src/include/efi/efi_datatype.h File src/include/efi/efi_datatype.h: https://review.coreboot.org/#/c/31648/3/src/include/efi/efi_datatype.h@16 PS3, Line 16: /* Create coreboot equivalent datatype for EFI based on UDK2018 */ Can we just say TianoCore. Whatever branch we use here shouldn't matter -- To view, visit https://review.coreboot.org/c/coreboot/+/31648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79cdaaa1dd63d248692989d943a15ad178c46369 Gerrit-Change-Number: 31648 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Comment-Date: Sat, 02 Mar 2019 21:32:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: device/mmio.h: Add include file for MMIO ops
by Nico Huber (Code Review) 02 Mar '19

02 Mar '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31691 ) Change subject: device/mmio.h: Add include file for MMIO ops ...................................................................... Patch Set 2: >> I'm confused, when exactly should the include path be >> `arch/`? I thought it makes sense when the interface is >> common but the implementation is not. Which might be >> the case for MMIO, or isn't it? > > I am not sure either; MMIO ops fall into this category of common interface, different implementation. If we want to extend them to read-modify-write cases, those might be a common implementation and <device/mmio.h> would have room for that. Ack, we'd spare us to include two files then. As long as we agree that this is how we define "device/mmio.h", I'm ok with it. > Aaron made comment earlier that only inb/outb etc should remain in io.h. But I guess your question was whether to use <arch/mmio.h> or <device/mmio.h> ? Yep. -- To view, visit https://review.coreboot.org/c/coreboot/+/31691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Gerrit-Change-Number: 31691 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Mar 2019 20:00:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: device/mmio.h: Add include file for MMIO ops
by Kyösti Mälkki (Code Review) 02 Mar '19

02 Mar '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31691 ) Change subject: device/mmio.h: Add include file for MMIO ops ...................................................................... Patch Set 2: > Patch Set 2: > > I'm confused, when exactly should the include path be > `arch/`? I thought it makes sense when the interface is > common but the implementation is not. Which might be > the case for MMIO, or isn't it? I am not sure either; MMIO ops fall into this category of common interface, different implementation. If we want to extend them to read-modify-write cases, those might be a common implementation and <device/mmio.h> would have room for that. Aaron made comment earlier that only inb/outb etc should remain in io.h. But I guess your question was whether to use <arch/mmio.h> or <device/mmio.h> ? -- To view, visit https://review.coreboot.org/c/coreboot/+/31691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Gerrit-Change-Number: 31691 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Mar 2019 19:53:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: device/mmio.h: Add include file for MMIO ops
by Nico Huber (Code Review) 02 Mar '19

02 Mar '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31691 ) Change subject: device/mmio.h: Add include file for MMIO ops ...................................................................... Patch Set 2: I'm confused, when exactly should the include path be `arch/`? I thought it makes sense when the interface is common but the implementation is not. Which might be the case for MMIO, or isn't it? -- To view, visit https://review.coreboot.org/c/coreboot/+/31691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Gerrit-Change-Number: 31691 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Mar 2019 19:44:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86/include/arch/acpi.h: Clean-up
by HAOUAS Elyes (Code Review) 02 Mar '19

02 Mar '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31689 Change subject: arch/x86/include/arch/acpi.h: Clean-up ...................................................................... arch/x86/include/arch/acpi.h: Clean-up As we are running ACPI v3.0, references to older than v3.0 are removed. Also clean comments. Change-Id: I0cce0035ed2b952d59cc1a4a9e6017dae67ef6db Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/include/arch/acpi.h 1 file changed, 13 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/31689/1 diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index aced58a..225b8e2 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -90,7 +90,7 @@ char signature[8]; /* RSDP signature */ u8 checksum; /* Checksum of the first 20 bytes */ char oem_id[6]; /* OEM ID */ - u8 revision; /* 0 for ACPI 1.0, 2 for ACPI 2.0/3.0/4.0/6.2a */ + u8 revision; /* RSDP revision */ u32 rsdt_address; /* Physical address of RSDT (32 bits) */ u32 length; /* Total RSDP length (incl. extended part) */ u64 xsdt_address; /* Physical address of XSDT (64 bits) */ @@ -104,12 +104,7 @@ u8 space_id; /* Address space ID */ u8 bit_width; /* Register size in bits */ u8 bit_offset; /* Register bit offset */ - union { - u8 resv; /* Reserved in ACPI 2.0 - 2.0b */ - u8 access_size; /* Access size in - * ACPI 2.0c/3.0/4.0/5.0/6.2a - */ - }; + u8 access_size; /* Access size */ u32 addrl; /* Register address, low 32 bits */ u32 addrh; /* Register address, high 32 bits */ } __packed acpi_addr_t; @@ -484,11 +479,7 @@ struct acpi_table_header header; u32 firmware_ctrl; u32 dsdt; - u8 reserved; /* Eliminated in ACPI 2.0. Platforms should set - * this field to zero but field values of one - * are also allowed to maintain compatibility - * with ACPI 1.0. - */ + u8 reserved; /* This value is 0 */ u8 preferred_pm_profile; u16 sci_int; u32 smi_cmd; @@ -578,7 +569,7 @@ /* Bits 20-31: reserved ACPI 3.0 & 4.0 */ #define ACPI_FADT_HW_REDUCED_ACPI (1 << 20) #define ACPI_FADT_LOW_PWR_IDLE_S0 (1 << 21) -/* bits 22-31: reserved ACPI 5.0/6.2a */ +/* bits 22-31: reserved ACPI 5.0/6.3 */ /* FADT Boot Architecture Flags */ #define ACPI_FADT_LEGACY_DEVICES (1 << 0) @@ -592,7 +583,7 @@ /* FADT ARM Boot Architecture Flags */ #define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0) #define ACPI_FADT_ARM_PSCI_USE_HVC (1 << 1) -/* bits 2-16: reserved ACPI 6.2a */ +/* bits 2-16: reserved ACPI 6.3 */ /* FADT Preferred Power Management Profile */ enum acpi_preferred_pm_profiles { @@ -604,7 +595,7 @@ PM_SOHO_SERVER = 5, PM_APPLIANCE_PC = 6, PM_PERFORMANCE_SERVER = 7, - PM_TABLET = 8, /* ACPI 5.0/6.2a */ + PM_TABLET = 8, /* ACPI 5.0 & greater */ }; /* FACS (Firmware ACPI Control Structure) */ @@ -617,10 +608,10 @@ u32 flags; /* FACS flags */ u32 x_firmware_waking_vector_l; /* X FW waking vector, low */ u32 x_firmware_waking_vector_h; /* X FW waking vector, high */ - u8 version; /* ACPI 6.2-A: 2 */ - u8 resv1[3]; /* ACPI 6.2-A: 0 */ + u8 version; /* FACS version */ + u8 resv1[3]; /* This value is 0 */ u32 ospm_flags; /* 64BIT_WAKE_F */ - u8 resv2[24]; /* ACPI 6.2-A: 0 */ + u8 resv2[24]; /* This value is 0 */ } __packed acpi_facs_t; /* FACS flags */ @@ -678,7 +669,7 @@ u64 error_region; } __packed acpi_bert_t; -/* Generic Error Data Entry (ACPI spec v6.2-A, table 382) */ +/* Generic Error Data Entry (ACPI spec v6.3, Table 18-392) */ typedef struct acpi_hest_generic_data { guid_t section_type; u32 error_severity; @@ -691,7 +682,7 @@ /* error data */ } __packed acpi_hest_generic_data_t; -/* Generic Error Data Entry (ACPI spec v6.2-A, table 382) */ +/* Generic Error Data Entry (ACPI spec v6.3, Table 18-392) */ typedef struct acpi_hest_generic_data_v300 { guid_t section_type; u32 error_severity; @@ -717,7 +708,7 @@ #define ACPI_GENERROR_VALID_FRUID_TEXT BIT(1) #define ACPI_GENERROR_VALID_TIMESTAMP BIT(2) -/* Generic Error Status Block (ACPI spec v6.2-A, table 381) */ +/* Generic Error Status Block (ACPI spec v6.3, Table 18-391) */ typedef struct acpi_generic_error_status { u32 block_status; u32 raw_data_offset; /* must follow any generic entries */ @@ -755,7 +746,7 @@ /* Port types for ACPI _UPC object */ enum acpi_upc_type { - /* These types are defined in ACPI 6.2 section 9.14 */ + /* These types are defined in ACPI 6.3 section 9.14 */ UPC_TYPE_A, UPC_TYPE_MINI_AB, UPC_TYPE_EXPRESSCARD, -- To view, visit https://review.coreboot.org/c/coreboot/+/31689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cce0035ed2b952d59cc1a4a9e6017dae67ef6db Gerrit-Change-Number: 31689 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: arch/io.h: Fix PCI and PNP simple typedefs
by Nico Huber (Code Review) 02 Mar '19

02 Mar '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31690 ) Change subject: arch/io.h: Fix PCI and PNP simple typedefs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85db254d50f18ea34a5e95bc517eac4085a5fafa Gerrit-Change-Number: 31690 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Mar 2019 19:40:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/io.h: Fix PCI and PNP simple typedefs
by Felix Held (Code Review) 02 Mar '19

02 Mar '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31690 ) Change subject: arch/io.h: Fix PCI and PNP simple typedefs ...................................................................... Patch Set 2: Code-Review+1 the patch looks good to me; the commit message is however a bit lacking. would be good to mention that this untangles the pci and pnp devfn definitions; at least that's what i saw the patch does -- To view, visit https://review.coreboot.org/c/coreboot/+/31690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85db254d50f18ea34a5e95bc517eac4085a5fafa Gerrit-Change-Number: 31690 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 02 Mar 2019 19:40:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: superio/ite/common: add option for enabling 5 FANs
by Krystian Hebel (Code Review) 02 Mar '19

02 Mar '19

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31616 Change subject: superio/ite/common: add option for enabling 5 FANs ...................................................................... superio/ite/common: add option for enabling 5 FANs Some ITEs have more than 3 independent FAN controller outputs. As the initial implementation assumed only 3 outputs some registers are not consequently numbered. This change adds macros for accessing those registers. Additionally some chips have SmartGuardian always enabled, without the option for turning it off. For these chips bits that were responsible for ON/OFF control are either reserved or have different meaning. Another Kconfig option was added to disable ON/OFF functionality on platforms that do not support it. Change-Id: Icd60a16b6b5583a3b981bdc220aac472c2a8f40f Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M src/superio/ite/common/Kconfig M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/env_ctrl.h M src/superio/ite/common/env_ctrl_chip.h 4 files changed, 132 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/31616/1 diff --git a/src/superio/ite/common/Kconfig b/src/superio/ite/common/Kconfig index 8e52cf4..a4b7ece 100644 --- a/src/superio/ite/common/Kconfig +++ b/src/superio/ite/common/Kconfig @@ -4,6 +4,7 @@ ## Copyright (C) 2009 Ronald G. Minnich ## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> ## Copyright (C) 2016 secunet Security Networks AG +## Copyright (C) 2019 Protectli ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -41,4 +42,13 @@ help The second FAN controller has a separate frequency setting. +config SUPERIO_ITE_ENV_CTRL_NO_ONOFF + bool + help + FAN controller always works in SmartGuardian mode + +config SUPERIO_ITE_ENV_CTRL_5FANS + bool + help + ITE FAN controller has 5 independent outputs endif diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 1dc5bb6..29a9b94 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -3,6 +3,7 @@ * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2019 Protectli * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -191,7 +192,9 @@ { u8 reg; - if (conf->mode == FAN_IGNORE) + if (conf->mode == FAN_IGNORE || + (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_NO_ONOFF) && + conf->mode <= FAN_MODE_OFF)) return; /* FAN_CTL2 might have its own frequency setting */ @@ -213,23 +216,36 @@ ite_ec_write(base, ITE_EC_FAN_CTL_MODE, reg); } - if (IS_ENABLED(SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) + if (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) && conf->mode >= FAN_MODE_ON) { reg = ite_ec_read(base, ITE_EC_FAN_TAC_COUNTER_ENABLE); reg |= ITE_EC_FAN_TAC_16BIT_ENABLE(fan); ite_ec_write(base, ITE_EC_FAN_TAC_COUNTER_ENABLE, reg); } - reg = ite_ec_read(base, ITE_EC_FAN_MAIN_CTL); - if (conf->mode >= FAN_MODE_ON) - reg |= ITE_EC_FAN_MAIN_CTL_TAC_EN(fan); - else - reg &= ~ITE_EC_FAN_MAIN_CTL_TAC_EN(fan); - if (conf->mode >= FAN_SMART_SOFTWARE) - reg |= ITE_EC_FAN_MAIN_CTL_SMART(fan); - else - reg &= ~ITE_EC_FAN_MAIN_CTL_SMART(fan); - ite_ec_write(base, ITE_EC_FAN_MAIN_CTL, reg); + if (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS) && fan > 3) { + reg = ite_ec_read(base, ITE_EC_FAN_SEC_CTL); + if (conf->mode >= FAN_MODE_ON) + reg |= ITE_EC_FAN_SEC_CTL_TAC_EN(fan); + else + reg &= ~ITE_EC_FAN_SEC_CTL_TAC_EN(fan); + ite_ec_write(base, ITE_EC_FAN_SEC_CTL, reg); + } else { + reg = ite_ec_read(base, ITE_EC_FAN_MAIN_CTL); + if (conf->mode >= FAN_MODE_ON) + reg |= ITE_EC_FAN_MAIN_CTL_TAC_EN(fan); + else + reg &= ~ITE_EC_FAN_MAIN_CTL_TAC_EN(fan); + + /* Some ITEs have SmartGuardian always enabled */ + if (!IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_NO_ONOFF)) { + if (conf->mode >= FAN_SMART_SOFTWARE) + reg |= ITE_EC_FAN_MAIN_CTL_SMART(fan); + else + reg &= ~ITE_EC_FAN_MAIN_CTL_SMART(fan); + } + ite_ec_write(base, ITE_EC_FAN_MAIN_CTL, reg); + } } static void enable_beeps(const u16 base, const struct ite_ec_config *const conf) diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h index 11316db..a265458 100644 --- a/src/superio/ite/common/env_ctrl.h +++ b/src/superio/ite/common/env_ctrl.h @@ -3,6 +3,7 @@ * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2019 Protectli * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -52,8 +53,26 @@ #define ITE_EC_FAN_TAC_COUNTER_ENABLE 0x0c #define ITE_EC_FAN_TAC_16BIT_ENABLE(x) (1 << ((x)-1)) + +#if IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS) +#define ITE_EC_FAN_SEC_CTL 0x0c +#define ITE_EC_FAN_SEC_CTL_TAC_EN(x) (1 << (x)) +#define ITE_EC_FAN_TAC_LIMIT(x) \ + ({ \ + (x > 3) \ + ? (0x84 + ((x)-4) * 2) \ + : (0x10 + ((x)-1)); \ + }) +#define ITE_EC_FAN_TAC_EXT_LIMIT(x) \ + ({ \ + (x > 3) \ + ? (0x85 + ((x)-4) * 2) \ + : (0x1b + ((x)-1)); \ + }) +#else #define ITE_EC_FAN_TAC_LIMIT(x) (0x10 + ((x)-1)) #define ITE_EC_FAN_TAC_EXT_LIMIT(x) (0x1b + ((x)-1)) +#endif #define ITE_EC_FAN_MAIN_CTL 0x13 #define ITE_EC_FAN_MAIN_CTL_TAC_EN(x) (1 << ((x)+3)) @@ -72,7 +91,22 @@ #define ITE_EC_FAN_PWM_CLOCK_51KHZ (7 << 4) #define ITE_EC_FAN_PWM_MIN_DUTY_20 (1 << 3) #define ITE_EC_FAN_CTL_ON(x) (1 << ((x)-1)) + +#if IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS) +#define ITE_EC_FAN_CTL_PWM_CONTROL(x) \ + ({ \ + (x > 3) \ + ? (0x1e + ((x)-4)) \ + : (0x15 + ((x)-1)); \ + }) +#define ITE_EC_FAN_CTL_TEMPIN_MASK (7 << 3) +#define ITE_EC_FAN_CTL_TEMPIN(x) ((((x)-1) & 7) << 3) +#else #define ITE_EC_FAN_CTL_PWM_CONTROL(x) (0x15 + ((x)-1)) +#define ITE_EC_FAN_CTL_TEMPIN_MASK (3 << 0) +#define ITE_EC_FAN_CTL_TEMPIN(x) (((x)-1) & 3) +#endif + #define ITE_EC_FAN_CTL_PWM_MODE_SOFTWARE (0 << 7) #define ITE_EC_FAN_CTL_PWM_MODE_AUTOMATIC (1 << 7) #define ITE_EC_FAN_CTL_PWM_DUTY_MASK (ITE_EC_FAN_MAX_PWM << 0) @@ -83,8 +117,6 @@ ? ITE_EC_FAN_MAX_PWM \ : (_p * ITE_EC_FAN_MAX_PWM) / 100; \ }) -#define ITE_EC_FAN_CTL_TEMPIN_MASK (3 << 0) -#define ITE_EC_FAN_CTL_TEMPIN(x) (((x)-1) & 3) #define ITE_EC_HIGH_TEMP_LIMIT(x) (0x40 + ((x-1) * 2)) #define ITE_EC_LOW_TEMP_LIMIT(x) (0x41 + ((x-1) * 2)) @@ -119,16 +151,64 @@ #define ITE_EC_BEEP_TONE_DIVISOR(x) (((x) & 0x0f) << 4) #define ITE_EC_BEEP_FREQ_DIVISOR(x) (((x) & 0x0f) << 0) +#if IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS) +#define ITE_EC_FAN_CTL_TEMP_LIMIT_OFF(x) \ + ({ \ + (x == 5) \ + ? (0xa0) \ + : (0x60 + ((x)-1) * 8); \ + }) +#define ITE_EC_FAN_CTL_TEMP_LIMIT_START(x) \ + ({ \ + (x == 5) \ + ? (0xa1) \ + : (0x61 + ((x)-1) * 8); \ + }) +#define ITE_EC_FAN_CTL_TEMP_LIMIT_FULL(x) \ + ({ \ + (x == 5) \ + ? (0xa2) \ + : (0x62 + ((x)-1) * 8); \ + }) +#define ITE_EC_FAN_CTL_PWM_START(x) \ + ({ \ + (x == 5) \ + ? (0xa3) \ + : (0x63 + ((x)-1) * 8); \ + }) +#define ITE_EC_FAN_CTL_PWM_AUTO(x) \ + ({ \ + (x == 5) \ + ? (0xa4) \ + : (0x64 + ((x)-1) * 8); \ + }) +#define ITE_EC_FAN_CTL_DELTA_TEMP(x) \ + ({ \ + (x == 5) \ + ? (0xa5) \ + : (0x65 + ((x)-1) * 8); \ + }) +#define ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(c) ((c) & 0x1f) + +#else + #define ITE_EC_FAN_CTL_TEMP_LIMIT_OFF(x) (0x60 + ((x)-1) * 8) #define ITE_EC_FAN_CTL_TEMP_LIMIT_START(x) (0x61 + ((x)-1) * 8) #define ITE_EC_FAN_CTL_TEMP_LIMIT_FULL(x) (0x62 + ((x)-1) * 8) #define ITE_EC_FAN_CTL_PWM_START(x) (0x63 + ((x)-1) * 8) +#define ITE_EC_FAN_CTL_PWM_AUTO(x) (0x64 + ((x)-1) * 8) +#define ITE_EC_FAN_CTL_DELTA_TEMP(x) (0x65 + ((x)-1) * 8) +#endif + +/* Common for ITE_EC_FAN_CTL_PWM_START */ #define ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(s) (((s) & 0x40) << 1) #define ITE_EC_FAN_CTL_PWM_START_DUTY(p) ITE_EC_FAN_CTL_PWM_DUTY(p) -#define ITE_EC_FAN_CTL_PWM_AUTO(x) (0x64 + ((x)-1) * 8) + +/* Common for ITE_EC_FAN_CTL_PWM_AUTO */ #define ITE_EC_FAN_CTL_AUTO_SMOOTHING_EN (1 << 7) #define ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(s) ((s) & 0x3f) -#define ITE_EC_FAN_CTL_DELTA_TEMP(x) (0x65 + ((x)-1) * 8) + +/* Common for ITE_EC_FAN_CTL_DELTA_TEMP */ #define ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(c) ((c) & 0x1f) #define ITE_EC_EXTEMP_STATUS 0x88 diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index f8f2e1e..5069b45 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -3,6 +3,7 @@ * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2019 Protectli * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,7 +20,12 @@ #define SUPERIO_ITE_ENV_CTRL_CHIP_H #define ITE_EC_TMPIN_CNT 3 + +#if IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS) +#define ITE_EC_FAN_CNT 5 +#else #define ITE_EC_FAN_CNT 3 +#endif /* Supported thermal mode on TMPINx */ enum ite_ec_thermal_mode { @@ -105,5 +111,9 @@ #define FAN1 ec.fan[0] #define FAN2 ec.fan[1] #define FAN3 ec.fan[2] +#if IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS) +#define FAN4 ec.fan[3] +#define FAN5 ec.fan[4] +#endif #endif /* SUPERIO_ITE_ENV_CTRL_CHIP_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd60a16b6b5583a3b981bdc220aac472c2a8f40f Gerrit-Change-Number: 31616 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2019