coreboot-gerrit March 2019

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Change in ...coreboot[master]: sb/intel/common: Fix SMBUs block commands
by Kyösti Mälkki (Code Review) 04 Mar '19

04 Mar '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31622 Change subject: sb/intel/common: Fix SMBUs block commands ...................................................................... sb/intel/common: Fix SMBUs block commands Fix regression after commit c38d543 sb/intel/common: SMBus complete_command() When evaluating HSTSTS register, BYTE_DONE bit must be excluded from transaction completion and error criteria. Change-Id: I49cc43d1fa58250988cc41b2ca747b9f1d7586d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/common/smbus.c 1 file changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/31622/1 diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index a842a61..9ae01ad 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -74,7 +74,10 @@ { if (status & SMBHSTSTS_HOST_BUSY) return 0; - status &= ~(SMBHSTSTS_SMBALERT_STS | SMBHSTSTS_INUSE_STS); + + /* These status bits do not imply completion of transaction. */ + status &= ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS | + SMBHSTSTS_SMBALERT_STS); return status != 0; } @@ -89,8 +92,9 @@ static int cb_err_from_stat(u8 status) { - /* Ignore the "In Use" status... */ - status &= ~(SMBHSTSTS_SMBALERT_STS | SMBHSTSTS_INUSE_STS); + /* These status bits do not imply errors. */ + status &= ~(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INUSE_STS | + SMBHSTSTS_SMBALERT_STS); if (status == SMBHSTSTS_INTR) return 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/31622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49cc43d1fa58250988cc41b2ca747b9f1d7586d6 Gerrit-Change-Number: 31622 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/fsp_broadwell_de: Use new memory clearing API
by Patrick Georgi (Code Review) 04 Mar '19

04 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31551 ) Change subject: soc/intel/fsp_broadwell_de: Use new memory clearing API ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/31551/5/src/soc/intel/fsp_broadwell_de/roms… File src/soc/intel/fsp_broadwell_de/romstage/romstage.c: https://review.coreboot.org/#/c/31551/5/src/soc/intel/fsp_broadwell_de/roms… PS5, Line 158: if (security_clear_dram_request()) : romstage_clear_mem(hob_list_ptr); isn't there a more generic piece of code where this could be put in? -- To view, visit https://review.coreboot.org/c/coreboot/+/31551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaac34a9058ee002be71e7089605d80a8b72a3d4 Gerrit-Change-Number: 31551 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Mar 2019 12:41:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/x86/pae/pgtbl: Add memset with PAE
by Patrick Georgi (Code Review) 04 Mar '19

04 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31549 ) Change subject: cpu/x86/pae/pgtbl: Add memset with PAE ...................................................................... Patch Set 5: (4 comments) https://review.coreboot.org/#/c/31549/5/Documentation/security/memory_clear… File Documentation/security/memory_clearing.md: https://review.coreboot.org/#/c/31549/5/Documentation/security/memory_clear… PS5, Line 40: ## Architecture specific implementations : : * [x86_32 architecture](../arch/x86/index.md) that doesn't look helpful to me as it points to generic x86 docs. https://review.coreboot.org/#/c/31549/5/src/cpu/x86/pae/pgtbl.c File src/cpu/x86/pae/pgtbl.c: https://review.coreboot.org/#/c/31549/5/src/cpu/x86/pae/pgtbl.c@114 PS5, Line 114: scratch2 vmem_addr? https://review.coreboot.org/#/c/31549/5/src/cpu/x86/pae/pgtbl.c@117 PS5, Line 117: scratch pgtbl_buf? also it's size should be stated somewhere. https://review.coreboot.org/#/c/31549/5/src/cpu/x86/pae/pgtbl.c@135 PS5, Line 135: assert(scratch); : assert(IS_ALIGNED((uintptr_t)scratch, 4096)); : assert(IS_ALIGNED((uintptr_t)scratch2, 2 * MiB)); : assert(((uintptr_t)dest > (uintptr_t)scratch2 + 2 * MiB) || : ((uintptr_t)dest < (uintptr_t)scratch2)); : assert(((uintptr_t)dest < (uintptr_t)scratch) || : ((uintptr_t)dest > (uintptr_t)scratch + sizeof(struct pg_table))); we don't always enforce asserts, so this may be unreliable. -- To view, visit https://review.coreboot.org/c/coreboot/+/31549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57 Gerrit-Change-Number: 31549 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Mon, 04 Mar 2019 12:38:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/fsp_broadwell_de: Use new memory clearing API
by Patrick Georgi (Code Review) 04 Mar '19

04 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31551 ) Change subject: soc/intel/fsp_broadwell_de: Use new memory clearing API ...................................................................... Patch Set 5: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/31551/5/src/soc/intel/fsp_broadwell_de/roms… File src/soc/intel/fsp_broadwell_de/romstage/romstage.c: https://review.coreboot.org/#/c/31551/5/src/soc/intel/fsp_broadwell_de/roms… PS5, Line 112: if (GetUsableHighMemTop(hob_list_ptr) > 4ULL * GiB) : highmem_size = GetUsableHighMemTop(hob_list_ptr) - 4ULL * GiB; : tolm = GetPhysicalLowMemTop(hob_list_ptr); totally wacky formatting -- To view, visit https://review.coreboot.org/c/coreboot/+/31551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaac34a9058ee002be71e7089605d80a8b72a3d4 Gerrit-Change-Number: 31551 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Mar 2019 12:34:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: security: Add memory subfolder
by Patrick Georgi (Code Review) 04 Mar '19

04 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31548 ) Change subject: security: Add memory subfolder ...................................................................... Patch Set 3: Code-Review+1 (3 comments) https://review.coreboot.org/#/c/31548/3/src/security/memory/Kconfig File src/security/memory/Kconfig: https://review.coreboot.org/#/c/31548/3/src/security/memory/Kconfig@16 PS3, Line 16: initilization typo https://review.coreboot.org/#/c/31548/3/src/security/memory/Kconfig@23 PS3, Line 23: (as part of FSP or coreboot). an x86 specific implementation detail (FSP) that doesn't belong here. https://review.coreboot.org/#/c/31548/3/src/security/memory/Kconfig@34 PS3, Line 34: endmenu #Memory initilization > 'initilization' may be misspelled - perhaps 'initialization'? typo -- To view, visit https://review.coreboot.org/c/coreboot/+/31548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110 Gerrit-Change-Number: 31548 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Mar 2019 12:32:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Remove unused variables
by HAOUAS Elyes (Code Review) 04 Mar '19

04 Mar '19

Hello Patrick Rudolph, Angel Pons, Huang Jin, Julius Werner, York Yang, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Damien Zammit, David Guckian, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#29). Change subject: src: Remove unused variables ...................................................................... src: Remove unused variables If we enable Wunused in the compiler, we'll have some 'unused variables'. This patch corrects some of them. Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/cpu/amd/quadcore/quadcore.c M src/device/dram/ddr3.c M src/drivers/spi/sst.c M src/lib/selfboot.c M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/via/vx900/raminit_ddr3.c M src/soc/cavium/common/bootblock.c M src/soc/intel/fsp_baytrail/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/i82371eb/fadt.c 18 files changed, 43 insertions(+), 80 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/29 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 29 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support
by Arthur Heymans (Code Review) 04 Mar '19

04 Mar '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 7: > Patch Set 7: > > > Patch Set 7: > > > > > Patch Set 7: > > > > > > > Patch Set 7: > > > > > > > > > Patch Set 7: Code-Review-2 > > > > > > > > > > (1 comment) > > > > > > > > > > select C_ENVIRONMENT_BOOTBLOCK is the braswell Kconfig and drop the romcc bootblock option and add console init in the bootblock. > > > > > Also drop things that get unused in drivers/intel/fsp1_1 > > > > > This patch is not even build tested... > > > > > > > > This patch is to support C_ENVIRONMENT_BOOTBLOCK for Braswell. To be backward compatible this support has made optional. > > > > > > Please don't make it optional and remove the 'backwards compatibility', there is really no reason to keep that around. > > > > > > > This patch has been build and tested. I will check if I made mistake by uploading. > > > > > > > > > > No gerrit has not build-tested it. > > > > > > > Can you clarify your comment? > > > > I concur with Arthur. C_ENVIRONMENT_BOOTBLOCK is becoming a standard in coreboot. No reason to keep backward compatibility. > > Removing backward compatibity in Braswell is no problem. Removing it from drivers/intel/fsp1_1 means also Intel Quark backward compatibility will be removed. I can verify that Intel Quark still build, but how to be sure tree is still working fine? The quark fsp1.1 option was dropped in master so no need to worry about that. -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 7 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 04 Mar 2019 09:27:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support
by Frans Hendriks (Code Review) 04 Mar '19

04 Mar '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 7: > Patch Set 7: > > > Patch Set 7: > > > > > Patch Set 7: > > > > > > > Patch Set 7: Code-Review-2 > > > > > > > > (1 comment) > > > > > > > > select C_ENVIRONMENT_BOOTBLOCK is the braswell Kconfig and drop the romcc bootblock option and add console init in the bootblock. > > > > Also drop things that get unused in drivers/intel/fsp1_1 > > > > This patch is not even build tested... > > > > > > This patch is to support C_ENVIRONMENT_BOOTBLOCK for Braswell. To be backward compatible this support has made optional. > > > > Please don't make it optional and remove the 'backwards compatibility', there is really no reason to keep that around. > > > > > This patch has been build and tested. I will check if I made mistake by uploading. > > > > > > > No gerrit has not build-tested it. > > > > > Can you clarify your comment? > > I concur with Arthur. C_ENVIRONMENT_BOOTBLOCK is becoming a standard in coreboot. No reason to keep backward compatibility. Removing backward compatibity in Braswell is no problem. Removing it from drivers/intel/fsp1_1 means also Intel Quark backward compatibility will be removed. I can verify that Intel Quark still build, but how to be sure tree is still working fine? -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 7 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 04 Mar 2019 08:50:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/braswell: Configure IO APIC
by Frans Hendriks (Code Review) 04 Mar '19

04 Mar '19

Hello Patrick Rudolph, build bot (Jenkins), Hannah Williams, Michał Żygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29423 to look at the new patch set (#8). Change subject: soc/intel/braswell: Configure IO APIC ...................................................................... soc/intel/braswell: Configure IO APIC IO APIC is not configured. Add sc_enable_ioapic() copied from fsp_baytrail SoC. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/include/soc/lpc.h M src/soc/intel/braswell/southcluster.c 3 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29423/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/29423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d Gerrit-Change-Number: 29423 Gerrit-PatchSet: 8 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: sb/amd/cimx/sb800: Get rid of power button device in coreboot
by Stefan Reinauer (Code Review) 04 Mar '19

04 Mar '19

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27496 ) Change subject: sb/amd/cimx/sb800: Get rid of power button device in coreboot ...................................................................... Patch Set 4: Please cut all the irrelevant pieces out of the commit message. This is way to verbose and hides all the relevant information. Why are you quoting Chrome EC in a change on non-ChromeOS machines? Why all the mention of some HDA audio stuff? What's the meaning of the two journalctl calls? And why do you post them and dmesg and evtest? Also, please only one Signed-off-by: per physical person. -- To view, visit https://review.coreboot.org/c/coreboot/+/27496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cbecb72f7e1bf3d051d3b7656c6af4d6f43b497 Gerrit-Change-Number: 27496 Gerrit-PatchSet: 4 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Mar 2019 05:44:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2019