coreboot-gerrit March 2019

coreboot-gerrit@coreboot.org

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1542 discussions

Change in ...coreboot[master]: drivers/intel/fsp1_0: Use new memory clearing API
by Patrick Rudolph (Code Review) 05 Mar '19

05 Mar '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31551 ) Change subject: drivers/intel/fsp1_0: Use new memory clearing API ...................................................................... Patch Set 6: (2 comments) https://review.coreboot.org/#/c/31551/5/src/soc/intel/fsp_broadwell_de/roms… File src/soc/intel/fsp_broadwell_de/romstage/romstage.c: https://review.coreboot.org/#/c/31551/5/src/soc/intel/fsp_broadwell_de/roms… PS5, Line 112: if (GetUsableHighMemTop(hob_list_ptr) > 4ULL * GiB) : highmem_size = GetUsableHighMemTop(hob_list_ptr) - 4ULL * GiB; : tolm = GetPhysicalLowMemTop(hob_list_ptr); > totally wacky formatting Done https://review.coreboot.org/#/c/31551/5/src/soc/intel/fsp_broadwell_de/roms… PS5, Line 158: if (security_clear_dram_request()) : romstage_clear_mem(hob_list_ptr); > isn't there a more generic piece of code where this could be put in? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/31551 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaac34a9058ee002be71e7089605d80a8b72a3d4 Gerrit-Change-Number: 31551 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 04 Mar 2019 14:54:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/x86: Introduce helper to clear memory using PAE
by Patrick Rudolph (Code Review) 05 Mar '19

05 Mar '19

Hello Kyösti Mälkki, Roy Wen, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Martin Roth, Jens Drenhaus, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31550 to look at the new patch set (#6). Change subject: arch/x86: Introduce helper to clear memory using PAE ...................................................................... arch/x86: Introduce helper to clear memory using PAE * Add Documentation. * Add x86 helper function to clear DRAM on a typical x86 memory map Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/arch/x86/pae.md M src/arch/x86/Makefile.inc A src/arch/x86/include/arch/memory_clear.h A src/arch/x86/memory_clear.c 4 files changed, 163 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31550/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/31550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20 Gerrit-Change-Number: 31550 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: cpu/x86/pae/pgtbl: Add memset with PAE
by Patrick Rudolph (Code Review) 05 Mar '19

05 Mar '19

Hello Kyösti Mälkki, Aaron Durbin, Roy Wen, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Jens Drenhaus, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31549 to look at the new patch set (#6). Change subject: cpu/x86/pae/pgtbl: Add memset with PAE ...................................................................... cpu/x86/pae/pgtbl: Add memset with PAE To clear all DRAM on x86_32, add a new method that uses PAE to access more than 32bit of address space. Add Documentation. Tested on wedge100s. Takes less than 2 seconds to clear 8GiB of DRAM. Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/arch/x86/index.md A Documentation/arch/x86/pae.md M Documentation/security/memory_clearing.md M src/cpu/x86/pae/pgtbl.c M src/include/cpu/x86/pae.h 5 files changed, 148 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31549/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/31549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57 Gerrit-Change-Number: 31549 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: security: Add memory subfolder
by Patrick Rudolph (Code Review) 05 Mar '19

05 Mar '19

Hello Aaron Durbin, Roy Wen, David Hendricks, Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Martin Roth, Jens Drenhaus, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31548 to look at the new patch set (#4). Change subject: security: Add memory subfolder ...................................................................... security: Add memory subfolder Add files to introduce a memory clearing framework. Introduce Kconfig PLATFORM_HAS_DRAM_CLEAR that is to be selected by platforms, that are able to clear all DRAM. Introduce Kconfig SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT that is user selectable to always clear DRAM on non S3 boot. The function security_clear_dram_request tells the calling platform when to wipe all DRAM. Will be extended by TEE frameworks. Add Documentation for the new security API. Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/index.md A Documentation/security/index.md A Documentation/security/memory_clearing.md M src/security/Kconfig M src/security/Makefile.inc A src/security/memory/Kconfig A src/security/memory/Makefile.inc A src/security/memory/memory.c A src/security/memory/memory.h 9 files changed, 132 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31548/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/31548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110 Gerrit-Change-Number: 31548 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: arch/io.h: Drop unnecessary include
by Patrick Georgi (Code Review) 05 Mar '19

05 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31692 ) Change subject: arch/io.h: Drop unnecessary include ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91158452680586ac676ea11c8589062880a31f91 Gerrit-Change-Number: 31692 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 04 Mar 2019 14:42:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: arch/io.h: Drop unnecessary include
by Kyösti Mälkki (Code Review) 05 Mar '19

05 Mar '19

Hello Patrick Rudolph, Piotr Król, Angel Pons, Julius Werner, Tristan Corrick, build bot (Jenkins), Patrick Georgi, Philipp Hug, Alexander Couzens, Werner Zeh, ron minnich, Felix Held, Vanessa Eusebio, Huang Jin, York Yang, Lee Leahy, Jonathan Neuschäfer, Philipp Deppenwiese, Damien Zammit, David Guckian, Michał Żygowski, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31692 to look at the new patch set (#7). Change subject: arch/io.h: Drop unnecessary include ...................................................................... arch/io.h: Drop unnecessary include Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/arm/armv7/mmu.c M src/arch/x86/cpu.c M src/arch/x86/ebda.c M src/console/die.c M src/cpu/amd/family_10h-family_15h/ram_calc.c M src/cpu/amd/smm/smm_init.c M src/cpu/intel/haswell/romstage.c M src/cpu/x86/lapic/apic_timer.c M src/device/device.c M src/device/oprom/realmode/x86_interrupts.c M src/device/pci_device.c M src/drivers/elog/gsmi.c M src/drivers/emulation/qemu/cirrus.c M src/drivers/i2c/at24rf08c/at24rf08c.c M src/drivers/i2c/at24rf08c/lenovo_serials.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/drivers/intel/gma/intel_ddi.c M src/drivers/intel/gma/vbt.c M src/drivers/ricoh/rce822/rce822.c M src/drivers/sil/3114/sil_sata.c M src/drivers/uart/oxpcie_early.c M src/drivers/xgi/common/xgi_coreboot.c M src/drivers/xgi/z9s/z9s.c M src/ec/google/chromeec/crosec_proto.c M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec_i2c.c M src/ec/lenovo/h8/h8.c M src/lib/edid.c M src/mainboard/advansus/a785e-i/mainboard.c M src/mainboard/advansus/a785e-i/resourcemap.c M src/mainboard/amd/bettong/mptable.c M src/mainboard/amd/bimini_fam10/mainboard.c M src/mainboard/amd/bimini_fam10/resourcemap.c M src/mainboard/amd/db-ft3b-lc/mainboard.c M src/mainboard/amd/db-ft3b-lc/mptable.c M src/mainboard/amd/gardenia/mptable.c M src/mainboard/amd/lamar/mainboard.c M src/mainboard/amd/lamar/mptable.c M src/mainboard/amd/mahogany_fam10/mainboard.c M src/mainboard/amd/mahogany_fam10/mptable.c M src/mainboard/amd/mahogany_fam10/resourcemap.c M src/mainboard/amd/olivehillplus/mainboard.c M src/mainboard/amd/parmer/romstage.c M src/mainboard/amd/persimmon/mptable.c M src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c M src/mainboard/amd/tilapia_fam10/mainboard.c M src/mainboard/amd/tilapia_fam10/mptable.c M src/mainboard/amd/tilapia_fam10/resourcemap.c M src/mainboard/amd/torpedo/acpi_tables.c M src/mainboard/aopen/dxplplusu/romstage.c M src/mainboard/apple/macbook21/mainboard.c M src/mainboard/apple/macbook21/smihandler.c M src/mainboard/apple/macbookair4_2/romstage.c M src/mainboard/asus/am1i-a/mptable.c M src/mainboard/asus/kcma-d8/bootblock.c M src/mainboard/asus/kcma-d8/mptable.c M src/mainboard/asus/kcma-d8/resourcemap.c M src/mainboard/asus/kfsn4-dre/acpi_tables.c M src/mainboard/asus/kfsn4-dre/resourcemap.c M src/mainboard/asus/kgpe-d16/bootblock.c M src/mainboard/asus/kgpe-d16/mptable.c M src/mainboard/asus/kgpe-d16/resourcemap.c M src/mainboard/asus/m4a78-em/mainboard.c M src/mainboard/asus/m4a78-em/mptable.c M src/mainboard/asus/m4a78-em/resourcemap.c M src/mainboard/asus/m4a785-m/mainboard.c M src/mainboard/asus/m4a785-m/mptable.c M src/mainboard/asus/m4a785-m/resourcemap.c M src/mainboard/asus/m5a88-v/mainboard.c M src/mainboard/asus/m5a88-v/resourcemap.c M src/mainboard/asus/p5qc/romstage.c M src/mainboard/asus/p8h61-m_lx/romstage.c M src/mainboard/avalue/eax-785e/mainboard.c M src/mainboard/avalue/eax-785e/resourcemap.c M src/mainboard/bap/ode_e20XX/mptable.c M src/mainboard/bap/ode_e21XX/mainboard.c M src/mainboard/biostar/am1ml/mptable.c M src/mainboard/elmex/pcm205400/mptable.c M src/mainboard/emulation/qemu-power8/uart.c M src/mainboard/emulation/qemu-q35/bootblock.c M src/mainboard/emulation/qemu-riscv/uart.c M src/mainboard/emulation/spike-riscv/uart.c M src/mainboard/foxconn/d41s/romstage.c M src/mainboard/getac/p470/mainboard.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/gigabyte/ma785gm/mainboard.c M src/mainboard/gigabyte/ma785gm/mptable.c M src/mainboard/gigabyte/ma785gm/resourcemap.c M src/mainboard/gigabyte/ma785gmt/mainboard.c M src/mainboard/gigabyte/ma785gmt/mptable.c M src/mainboard/gigabyte/ma785gmt/resourcemap.c M src/mainboard/gigabyte/ma78gm/mainboard.c M src/mainboard/gigabyte/ma78gm/mptable.c M src/mainboard/gigabyte/ma78gm/resourcemap.c M src/mainboard/gizmosphere/gizmo2/mptable.c M src/mainboard/google/auron/variant.h M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/beltino/smihandler.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/butterfly/mainboard_smi.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/eve/smihandler.c M src/mainboard/google/foster/mainboard.c M src/mainboard/google/foster/reset.c M src/mainboard/google/glados/smihandler.c M src/mainboard/google/gru/sdram_configs.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/kahlee/mptable.c M src/mainboard/google/link/mainboard_smi.c M src/mainboard/google/link/romstage.c M src/mainboard/google/nyan/romstage.c M src/mainboard/google/nyan_big/romstage.c M src/mainboard/google/nyan_blaze/romstage.c M src/mainboard/google/oak/mainboard.c M src/mainboard/google/octopus/ec.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/parrot/ec.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/google/smaug/reset.c M src/mainboard/google/stout/chromeos.c M src/mainboard/google/stout/ec.c M src/mainboard/google/stout/mainboard.c M src/mainboard/google/stout/mainboard_smi.c M src/mainboard/google/stout/romstage.c M src/mainboard/google/urara/mainboard.c M src/mainboard/google/veyron/sdram_configs.c M src/mainboard/google/veyron_mickey/sdram_configs.c M src/mainboard/google/veyron_rialto/sdram_configs.c M src/mainboard/hp/2570p/romstage.c M src/mainboard/hp/2760p/romstage.c M src/mainboard/hp/8460p/romstage.c M src/mainboard/hp/8470p/romstage.c M src/mainboard/hp/8770w/romstage.c M src/mainboard/hp/compaq_8200_elite_sff/romstage.c M src/mainboard/hp/folio_9470m/romstage.c M src/mainboard/hp/pavilion_m6_1035dx/mainboard.c M src/mainboard/hp/revolve_810_g1/romstage.c M src/mainboard/iei/kino-780am2-fam10/mainboard.c M src/mainboard/iei/kino-780am2-fam10/mptable.c M src/mainboard/iei/kino-780am2-fam10/resourcemap.c M src/mainboard/intel/bayleybay_fsp/mainboard.c M src/mainboard/intel/bayleybay_fsp/romstage.c M src/mainboard/intel/camelbackmountain_fsp/mainboard.c M src/mainboard/intel/cannonlake_rvp/smihandler.c M src/mainboard/intel/d510mo/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dg43gt/romstage.c M src/mainboard/intel/emeraldlake2/mainboard.c M src/mainboard/intel/galileo/gpio.c M src/mainboard/intel/galileo/reg_access.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kblrvp/smihandler.c M src/mainboard/intel/kunimitsu/smihandler.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/jetway/nf81-t56n-lf/mptable.c M src/mainboard/jetway/pa78vm5/mainboard.c M src/mainboard/jetway/pa78vm5/mptable.c M src/mainboard/jetway/pa78vm5/resourcemap.c M src/mainboard/kontron/ktqm77/mainboard.c M src/mainboard/lenovo/l520/romstage.c M src/mainboard/lenovo/s230u/mainboard.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/s230u/smihandler.c M src/mainboard/lenovo/t400/acpi_tables.c M src/mainboard/lenovo/t400/romstage.c M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t430s/variants/t430s/romstage.c M src/mainboard/lenovo/t430s/variants/t431s/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/x131e/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x200/acpi_tables.c M src/mainboard/lenovo/x200/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x230/romstage.c M src/mainboard/msi/ms9652_fam10/resourcemap.c M src/mainboard/pcengines/apu1/mptable.c M src/mainboard/roda/rk9/acpi_tables.c M src/mainboard/roda/rk9/smihandler.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/lumpy/smihandler.c M src/mainboard/samsung/stumpy/chromeos.c M src/mainboard/samsung/stumpy/romstage.c M src/mainboard/samsung/stumpy/smihandler.c M src/mainboard/sapphire/pureplatinumh61/romstage.c M src/mainboard/siemens/mc_tcu3/mainboard.c M src/mainboard/siemens/mc_tcu3/romstage.c M src/mainboard/sifive/hifive-unleashed/mainboard.c M src/mainboard/supermicro/h8dmr_fam10/resourcemap.c M src/mainboard/supermicro/h8qme_fam10/resourcemap.c M src/mainboard/supermicro/h8scm_fam10/mainboard.c M src/mainboard/supermicro/h8scm_fam10/mptable.c M src/mainboard/supermicro/h8scm_fam10/resourcemap.c M src/mainboard/tyan/s2912_fam10/resourcemap.c M src/mainboard/via/epia-m850/romstage.c M src/northbridge/amd/agesa/family12/northbridge.c M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/amdfam10/amdfam10.h M src/northbridge/amd/amdfam10/amdfam10_util.c M src/northbridge/amd/amdfam10/early_ht.c M src/northbridge/amd/amdfam10/ht_config.c M src/northbridge/amd/amdfam10/northbridge.c M src/northbridge/amd/amdfam10/pci.h M src/northbridge/amd/amdfam10/raminit_amdmct.c M src/northbridge/amd/amdk8/reset_test.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/amd/pi/ramtop.c M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/fsp_rangeley/acpi.c M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/fsp_rangeley/port_access.c M src/northbridge/intel/fsp_rangeley/raminit.c M src/northbridge/intel/gm45/bootblock.c M src/northbridge/intel/gm45/early_init.c M src/northbridge/intel/gm45/igd.c M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/gm45/pcie.c M src/northbridge/intel/gm45/pm.c M src/northbridge/intel/gm45/ram_calc.c M src/northbridge/intel/gm45/stage_cache.c M src/northbridge/intel/gm45/thermal.c M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/ram_calc.c M src/northbridge/intel/haswell/report_platform.c M src/northbridge/intel/i440bx/debug.c M src/northbridge/intel/i440bx/northbridge.c M src/northbridge/intel/i440bx/ram_calc.c M src/northbridge/intel/i945/bootblock.c M src/northbridge/intel/i945/debug.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/ram_calc.c M src/northbridge/intel/i945/stage_cache.c M src/northbridge/intel/nehalem/bootblock.c M src/northbridge/intel/nehalem/finalize.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/nehalem/ram_calc.c M src/northbridge/intel/pineview/bootblock.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/pineview/ram_calc.c M src/northbridge/intel/pineview/stage_cache.c M src/northbridge/intel/sandybridge/bootblock.c M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/ram_calc.c M src/northbridge/intel/sandybridge/raminit_ivy.c M src/northbridge/intel/x4x/bootblock.c M src/northbridge/intel/x4x/gma.c M src/northbridge/intel/x4x/northbridge.c M src/northbridge/intel/x4x/ram_calc.c M src/northbridge/intel/x4x/raminit_tables.c M src/northbridge/intel/x4x/stage_cache.c M src/northbridge/via/vx900/bootblock.c M src/northbridge/via/vx900/chrome9hd.c M src/northbridge/via/vx900/early_vx900.c M src/northbridge/via/vx900/early_vx900.h M src/northbridge/via/vx900/lpc.c M src/northbridge/via/vx900/pcie.c M src/northbridge/via/vx900/vx900.h M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/hda.c M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/lpc.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/ramtop.c M src/soc/amd/stoneyridge/romstage.c M src/soc/amd/stoneyridge/sata.c M src/soc/amd/stoneyridge/sm.c M src/soc/amd/stoneyridge/tsc_freq.c M src/soc/amd/stoneyridge/usb.c M src/soc/cavium/cn81xx/bootblock.c M src/soc/cavium/common/bdk-coreboot.c M src/soc/cavium/common/ecam.c M src/soc/imgtec/pistachio/include/soc/spi.h M src/soc/intel/apollolake/include/soc/pci_devs.h M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/apollolake/smihandler.c M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/baytrail/dptf.c M src/soc/intel/baytrail/elog.c M src/soc/intel/baytrail/emmc.c M src/soc/intel/baytrail/hda.c M src/soc/intel/baytrail/lpss.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/baytrail/perf_power.c M src/soc/intel/baytrail/romstage/early_spi.c M src/soc/intel/baytrail/romstage/gfx.c M src/soc/intel/baytrail/romstage/uart.c M src/soc/intel/baytrail/sd.c M src/soc/intel/braswell/bootblock/bootblock.c M src/soc/intel/braswell/elog.c M src/soc/intel/braswell/emmc.c M src/soc/intel/braswell/gfx.c M src/soc/intel/braswell/lpss.c M src/soc/intel/braswell/memmap.c M src/soc/intel/braswell/romstage/early_spi.c M src/soc/intel/braswell/sata.c M src/soc/intel/braswell/sd.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/bootblock/pch.c M src/soc/intel/broadwell/bootblock/systemagent.c M src/soc/intel/broadwell/ehci.c M src/soc/intel/broadwell/include/soc/pci_devs.h M src/soc/intel/broadwell/iobp.c M src/soc/intel/broadwell/me_status.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/pch.c M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/romstage/report_platform.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/broadwell/romstage/smbus.c M src/soc/intel/broadwell/romstage/spi.c M src/soc/intel/broadwell/romstage/uart.c M src/soc/intel/broadwell/systemagent.c M src/soc/intel/broadwell/usb_debug.c M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/include/intelblocks/smihandler.h M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/smbus/smbus_early.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/common/pch/lockdown/lockdown.c M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/denverton_ns/include/soc/pm.h M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/denverton_ns/npk.c M src/soc/intel/denverton_ns/xhci.c M src/soc/intel/fsp_baytrail/gfx.c M src/soc/intel/fsp_baytrail/include/soc/i2c.h M src/soc/intel/fsp_baytrail/lpss.c M src/soc/intel/fsp_baytrail/memmap.c M src/soc/intel/fsp_baytrail/romstage/report_platform.c M src/soc/intel/fsp_baytrail/romstage/uart.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/smihandler.c M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/icelake/bootblock/report_platform.c M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/include/soc/pm.h M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/quark/include/soc/reg_access.h M src/soc/intel/quark/sd.c M src/soc/intel/quark/spi_debug.c M src/soc/intel/quark/storage_test.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/lpc.c M src/soc/intel/skylake/me.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/skylake/vr_config.c M src/soc/mediatek/common/include/soc/pmic_wrap_common.h M src/soc/mediatek/mt8173/memory.c M src/soc/mediatek/mt8173/mt6391.c M src/soc/nvidia/tegra124/dp.c M src/soc/nvidia/tegra124/sdram_lp0.c M src/soc/nvidia/tegra124/soc.c M src/soc/nvidia/tegra124/sor.c M src/soc/nvidia/tegra210/dp.c M src/soc/nvidia/tegra210/funitcfg.c M src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c M src/soc/nvidia/tegra210/mipi-phy.c M src/soc/nvidia/tegra210/mipi_dsi.c M src/soc/nvidia/tegra210/soc.c M src/soc/nvidia/tegra210/sor.c M src/soc/qualcomm/ipq40xx/i2c.c M src/soc/qualcomm/ipq806x/i2c.c M src/soc/rockchip/rk3288/bootblock.c M src/soc/rockchip/rk3288/gpio.c M src/soc/rockchip/rk3399/decompressor.c M src/soc/rockchip/rk3399/gpio.c M src/soc/samsung/exynos5420/dp.c M src/southbridge/amd/agesa/hudson/bootblock.c M src/southbridge/amd/agesa/hudson/hda.c M src/southbridge/amd/agesa/hudson/lpc.c M src/southbridge/amd/agesa/hudson/reset.c M src/southbridge/amd/agesa/hudson/sata.c M src/southbridge/amd/agesa/hudson/sd.c M src/southbridge/amd/agesa/hudson/sm.c M src/southbridge/amd/agesa/hudson/usb.c M src/southbridge/amd/amd8111/bootblock.c M src/southbridge/amd/amd8111/reset.c M src/southbridge/amd/amd8111/smbus.c M src/southbridge/amd/amd8111/usb.c M src/southbridge/amd/cimx/sb800/cfg.c M src/southbridge/amd/cimx/sb800/early.c M src/southbridge/amd/cimx/sb800/lpc.c M src/southbridge/amd/cimx/sb800/reset.c M src/southbridge/amd/cimx/sb900/bootblock.c M src/southbridge/amd/cimx/sb900/reset.c M src/southbridge/amd/pi/hudson/bootblock.c M src/southbridge/amd/pi/hudson/hda.c M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/amd/pi/hudson/reset.c M src/southbridge/amd/pi/hudson/sata.c M src/southbridge/amd/pi/hudson/sd.c M src/southbridge/amd/pi/hudson/sm.c M src/southbridge/amd/pi/hudson/usb.c M src/southbridge/amd/rs780/cmn.c M src/southbridge/amd/rs780/early_setup.c M src/southbridge/amd/rs780/rs780.c M src/southbridge/amd/sb700/bootblock.c M src/southbridge/amd/sb700/fadt.c M src/southbridge/amd/sb700/lpc.c M src/southbridge/amd/sb700/smbus.h M src/southbridge/amd/sb800/bootblock.c M src/southbridge/amd/sb800/fadt.c M src/southbridge/amd/sb800/lpc.c M src/southbridge/amd/sr5650/cmn.h M src/southbridge/broadcom/bcm5785/bootblock.c M src/southbridge/broadcom/bcm5785/lpc.c M src/southbridge/intel/bd82x6x/bootblock.c M src/southbridge/intel/bd82x6x/early_spi.c M src/southbridge/intel/bd82x6x/early_usb_mrc.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/bd82x6x/usb_xhci.c M src/southbridge/intel/bd82x6x/watchdog.c M src/southbridge/intel/common/acpi_pirq_gen.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/usb_debug.c M src/southbridge/intel/fsp_rangeley/early_spi.c M src/southbridge/intel/fsp_rangeley/early_usb.c M src/southbridge/intel/fsp_rangeley/smbus.c M src/southbridge/intel/i82371eb/bootblock.c M src/southbridge/intel/i82371eb/early_pm.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801dx/bootblock.c M src/southbridge/intel/i82801gx/bootblock.c M src/southbridge/intel/i82801gx/smbus.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/bootblock.c M src/southbridge/intel/i82801ix/dmi_setup.c M src/southbridge/intel/i82801ix/smbus.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/bootblock.c M src/southbridge/intel/i82801jx/smbus.c M src/southbridge/intel/i82801jx/smihandler.c M src/southbridge/intel/i82870/pci_parity.c M src/southbridge/intel/ibexpeak/madt.c M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/early_spi.c M src/southbridge/intel/lynxpoint/early_usb.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/rcba.c M src/southbridge/nvidia/ck804/bootblock.c M src/southbridge/nvidia/ck804/ck804.c M src/southbridge/nvidia/ck804/enable_usbdebug.c M src/southbridge/nvidia/ck804/smbus.c M src/southbridge/nvidia/mcp55/bootblock.c M src/southbridge/nvidia/mcp55/enable_usbdebug.c M src/southbridge/nvidia/mcp55/fadt.c M src/southbridge/nvidia/mcp55/mcp55.c M src/southbridge/nvidia/mcp55/smbus.c M src/southbridge/ricoh/rl5c476/rl5c476.c M src/southbridge/ti/pci1x2x/pci1x2x.c M src/southbridge/ti/pci7420/cardbus.c M src/southbridge/ti/pci7420/firewire.c M src/southbridge/ti/pcixx12/pcixx12.c M src/superio/fintek/f71805f/superio.c M src/superio/fintek/f71808a/f71808a_hwm.c M src/superio/fintek/f71808a/f71808a_multifunc.c M src/superio/fintek/f71808a/fintek_internal.h M src/superio/fintek/f71808a/superio.c M src/superio/fintek/f71859/superio.c M src/superio/fintek/f71863fg/superio.c M src/superio/fintek/f71869ad/f71869ad_hwm.c M src/superio/fintek/f71869ad/f71869ad_multifunc.c M src/superio/fintek/f71869ad/fintek_internal.h M src/superio/fintek/f71869ad/superio.c M src/superio/fintek/f71872/superio.c M src/superio/fintek/f81865f/superio.c M src/superio/fintek/f81866d/f81866d_hwm.c M src/superio/fintek/f81866d/f81866d_uart.c M src/superio/fintek/f81866d/fintek_internal.h M src/superio/fintek/f81866d/superio.c M src/superio/ite/it8528e/superio.c M src/superio/ite/it8623e/superio.c M src/superio/ite/it8712f/superio.c M src/superio/ite/it8716f/superio.c M src/superio/ite/it8728f/superio.c M src/superio/ite/it8783ef/it8783ef.h M src/superio/nsc/pc87309/superio.c M src/superio/nsc/pc87360/superio.c M src/superio/nsc/pc87366/superio.c M src/superio/nsc/pc87382/superio.c M src/superio/nsc/pc87384/superio.c M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/superio.c M src/superio/nsc/pc97317/superio.c M src/superio/nuvoton/nct5104d/superio.c M src/superio/nuvoton/nct5572d/superio.c M src/superio/nuvoton/nct6776/superio.c M src/superio/nuvoton/nct6779d/superio.c M src/superio/nuvoton/nct6791d/superio.c M src/superio/nuvoton/wpcm450/superio.c M src/superio/renesas/m3885x/superio.c M src/superio/smsc/dme1737/superio.c M src/superio/smsc/kbc1100/superio.c M src/superio/smsc/lpc47b272/superio.c M src/superio/smsc/lpc47b397/superio.c M src/superio/smsc/lpc47m10x/superio.c M src/superio/smsc/lpc47m15x/superio.c M src/superio/smsc/lpc47n207/lpc47n207.h M src/superio/smsc/lpc47n227/superio.c M src/superio/smsc/mec1308/superio.c M src/superio/smsc/sch4037/superio.c M src/superio/smsc/sio1036/superio.c M src/superio/smsc/smscsuperio/superio.c M src/superio/winbond/w83627dhg/superio.c M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c M src/superio/winbond/w83627thg/superio.c M src/superio/winbond/w83627uhg/superio.c M src/superio/winbond/w83667hg-a/superio.c M src/superio/winbond/w83977tf/superio.c M src/superio/winbond/wpcd376i/superio.c 551 files changed, 0 insertions(+), 551 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/31692/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/31692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91158452680586ac676ea11c8589062880a31f91 Gerrit-Change-Number: 31692 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: arch/io.h: Drop unnecessary include
by Patrick Georgi (Code Review) 05 Mar '19

05 Mar '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31692 ) Change subject: arch/io.h: Drop unnecessary include ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91158452680586ac676ea11c8589062880a31f91 Gerrit-Change-Number: 31692 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 04 Mar 2019 14:08:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: arch/io.h: Add missing includes
by Patrick Georgi (Code Review) 05 Mar '19

05 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31697 ) Change subject: arch/io.h: Add missing includes ...................................................................... arch/io.h: Add missing includes Fixes indirect includes that would break with followup work. Change-Id: I37ca01b904a0b422a4d09475377e755e167a6ab3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/31697 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/include/cpu/amd/vr.h M src/mainboard/asus/kfsn4-dre/bootblock.c M src/mainboard/asus/p3b-f/romstage.c M src/mainboard/google/poppy/variants/nautilus/mainboard.c M src/mainboard/hp/dl165_g6_fam10/bootblock.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/mainboard.c M src/mainboard/lenovo/z61t/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c M src/northbridge/amd/amdfam10/setup_resource_map.c M src/northbridge/amd/amdmct/mct_ddr3/mport_d.c M src/northbridge/intel/pineview/romstage.c M src/soc/amd/stoneyridge/smihandler.c M src/soc/intel/braswell/lpc_init.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/quark/reg_access.c M src/southbridge/amd/agesa/hudson/smihandler.c M src/southbridge/amd/pi/hudson/smihandler.c M src/southbridge/amd/sb700/smbus.c M src/southbridge/amd/sb800/smbus.c 21 files changed, 21 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/include/cpu/amd/vr.h b/src/include/cpu/amd/vr.h index 8c62e44..b5a1fe4 100644 --- a/src/include/cpu/amd/vr.h +++ b/src/include/cpu/amd/vr.h @@ -8,6 +8,7 @@ #define CPU_AMD_VR_H #include <stdint.h> +#include <arch/io.h> #define VRC_INDEX 0xAC1C // Index register #define VRC_DATA 0xAC1E // Data register diff --git a/src/mainboard/asus/kfsn4-dre/bootblock.c b/src/mainboard/asus/kfsn4-dre/bootblock.c index 454443f..ec8b2da 100644 --- a/src/mainboard/asus/kfsn4-dre/bootblock.c +++ b/src/mainboard/asus/kfsn4-dre/bootblock.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <pc80/mc146818rtc.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 4686fb5..387cecb 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <device/pci_def.h> #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> diff --git a/src/mainboard/google/poppy/variants/nautilus/mainboard.c b/src/mainboard/google/poppy/variants/nautilus/mainboard.c index f11bde4..08fb73f 100644 --- a/src/mainboard/google/poppy/variants/nautilus/mainboard.c +++ b/src/mainboard/google/poppy/variants/nautilus/mainboard.c @@ -15,6 +15,7 @@ #include <baseboard/variants.h> #include <chip.h> +#include <arch/io.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c index e1e1a42..7a88566 100644 --- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c +++ b/src/mainboard/hp/dl165_g6_fam10/bootblock.c @@ -11,6 +11,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <device/pnp_def.h> #define SCH4307_CONFIG_PORT 0x162e diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 0777412..8a9fbf1 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -17,6 +17,7 @@ #include <stdint.h> #include <halt.h> +#include <arch/io.h> #include <console/console.h> #include <cpu/intel/romstage.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index df1f174..2d998fb 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -16,6 +16,7 @@ */ #include <device/pci_def.h> +#include <arch/io.h> #include <device/device.h> #include <ec/lenovo/pmh7/pmh7.h> #include <ec/lenovo/h8/h8.h> diff --git a/src/mainboard/lenovo/z61t/mainboard.c b/src/mainboard/lenovo/z61t/mainboard.c index 6616b4a..886b4fb 100644 --- a/src/mainboard/lenovo/z61t/mainboard.c +++ b/src/mainboard/lenovo/z61t/mainboard.c @@ -16,6 +16,7 @@ */ #include <device/pci_def.h> +#include <arch/io.h> #include <device/device.h> #include <ec/lenovo/pmh7/pmh7.h> #include <ec/lenovo/h8/h8.h> diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index c436b02..3e2e7f0 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <bootstate.h> #include <cf9_reset.h> #include <console/console.h> diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c index 38475f3..de2eeac 100644 --- a/src/northbridge/amd/amdfam10/setup_resource_map.c +++ b/src/northbridge/amd/amdfam10/setup_resource_map.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <inttypes.h> #include <console/console.h> #include <device/pci_ops.h> diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c index 76a63b5..3c512ed 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mport_d.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <inttypes.h> #include <string.h> #include "mct_d.h" diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 0d2cc36..757e272 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -17,6 +17,7 @@ * so this one is named with prefix mainboard. */ +#include <arch/io.h> #include <lib.h> #include <timestamp.h> #include <console/console.h> diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 4854e52..657ff49 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <cpu/x86/cache.h> diff --git a/src/soc/intel/braswell/lpc_init.c b/src/soc/intel/braswell/lpc_init.c index a593d30..12ee42c 100644 --- a/src/soc/intel/braswell/lpc_init.c +++ b/src/soc/intel/braswell/lpc_init.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <soc/gpio.h> #include <soc/pm.h> #include <soc/iomap.h> diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 31bcc97..fc22577 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <device/device.h> #include <device/path.h> #include <device/smbus.h> diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 5df8b71..73c8269 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 50a8ff0..df171f5 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -15,6 +15,7 @@ #define __SIMPLE_DEVICE__ +#include <arch/io.h> #include <assert.h> #include <cpu/x86/mtrr.h> #include <console/console.h> diff --git a/src/southbridge/amd/agesa/hudson/smihandler.c b/src/southbridge/amd/agesa/hudson/smihandler.c index 5ef9d6a..a87b75d 100644 --- a/src/southbridge/amd/agesa/hudson/smihandler.c +++ b/src/southbridge/amd/agesa/hudson/smihandler.c @@ -18,6 +18,7 @@ * SMI handler for Hudson southbridges */ +#include <arch/io.h> #include "hudson.h" #include "smi.h" diff --git a/src/southbridge/amd/pi/hudson/smihandler.c b/src/southbridge/amd/pi/hudson/smihandler.c index 5ef9d6a..a87b75d 100644 --- a/src/southbridge/amd/pi/hudson/smihandler.c +++ b/src/southbridge/amd/pi/hudson/smihandler.c @@ -18,6 +18,7 @@ * SMI handler for Hudson southbridges */ +#include <arch/io.h> #include "hudson.h" #include "smi.h" diff --git a/src/southbridge/amd/sb700/smbus.c b/src/southbridge/amd/sb700/smbus.c index 58bbe4c..9b0e8f9 100644 --- a/src/southbridge/amd/sb700/smbus.c +++ b/src/southbridge/amd/sb700/smbus.c @@ -16,6 +16,7 @@ #ifndef _SB700_SMBUS_C_ #define _SB700_SMBUS_C_ +#include <arch/io.h> #include "smbus.h" extern uint8_t amd_sb700_aux_smbus; diff --git a/src/southbridge/amd/sb800/smbus.c b/src/southbridge/amd/sb800/smbus.c index 0803b12..fef6ab8 100644 --- a/src/southbridge/amd/sb800/smbus.c +++ b/src/southbridge/amd/sb800/smbus.c @@ -16,6 +16,7 @@ #ifndef _SB800_SMBUS_C_ #define _SB800_SMBUS_C_ +#include <arch/io.h> #include "smbus.h" static int smbus_wait_until_ready(u32 smbus_io_base) -- To view, visit https://review.coreboot.org/c/coreboot/+/31697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37ca01b904a0b422a4d09475377e755e167a6ab3 Gerrit-Change-Number: 31697 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: arch/io.h: Fix PCI and PNP simple typedefs
by Patrick Georgi (Code Review) 05 Mar '19

05 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31690 ) Change subject: arch/io.h: Fix PCI and PNP simple typedefs ...................................................................... arch/io.h: Fix PCI and PNP simple typedefs Provide clean separation for PCI and PNP headers, followup will also move PNP outside <arch/io.h>. Change-Id: I85db254d50f18ea34a5e95bc517eac4085a5fafa Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/31690 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/arch/x86/include/arch/io.h M src/include/device/pci_ehci.h M src/include/device/pci_ops.h M src/include/device/pci_type.h M src/include/reg_script.h M src/northbridge/amd/amdfam10/pci.h 6 files changed, 6 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index aecf0b6..98cb15a 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -16,7 +16,6 @@ #include <endian.h> #include <stdint.h> -#include <device/pci_type.h> /* * This file contains the definitions for the x86 IO instructions @@ -203,6 +202,8 @@ } #endif +typedef u32 pnp_devfn_t; + #ifdef __SIMPLE_DEVICE__ #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h index 9d18bcc..146946c 100644 --- a/src/include/device/pci_ehci.h +++ b/src/include/device/pci_ehci.h @@ -17,8 +17,8 @@ #ifndef _PCI_EHCI_H_ #define _PCI_EHCI_H_ -#include <arch/io.h> #include <device/device.h> +#include <device/pci_type.h> #define EHCI_BAR_INDEX 0x10 #define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */ diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 6971ce4..f1d50d7 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -3,6 +3,7 @@ #include <stdint.h> #include <device/device.h> +#include <device/pci_type.h> #include <arch/pci_ops.h> #ifdef __SIMPLE_DEVICE__ diff --git a/src/include/device/pci_type.h b/src/include/device/pci_type.h index 0b08e8d..3f72c5f 100644 --- a/src/include/device/pci_type.h +++ b/src/include/device/pci_type.h @@ -17,7 +17,6 @@ #include <stdint.h> typedef u32 pci_devfn_t; -typedef u32 pnp_devfn_t; #define PCI_DEV(SEGBUS, DEV, FN) ( \ (((SEGBUS) & 0xFFF) << 20) | \ diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 28fc82d..7ca457a 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -17,8 +17,8 @@ #define REG_SCRIPT_H #include <stdint.h> -#include <arch/io.h> #include <device/device.h> +#include <device/pci_type.h> #include <device/resource.h> /* diff --git a/src/northbridge/amd/amdfam10/pci.h b/src/northbridge/amd/amdfam10/pci.h index 8fcdbd8..8302582 100644 --- a/src/northbridge/amd/amdfam10/pci.h +++ b/src/northbridge/amd/amdfam10/pci.h @@ -18,6 +18,7 @@ #include <inttypes.h> #include <arch/io.h> +#include <device/pci_type.h> #include <device/pci_def.h> u32 pci_read_config32_index(pci_devfn_t dev, u32 index_reg, u32 index); -- To view, visit https://review.coreboot.org/c/coreboot/+/31690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85db254d50f18ea34a5e95bc517eac4085a5fafa Gerrit-Change-Number: 31690 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: Fix <io.h> includes
by Patrick Georgi (Code Review) 05 Mar '19

05 Mar '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31693 ) Change subject: Fix <io.h> includes ...................................................................... Fix <io.h> includes These resolved to <device/oprom/include/io.h> which included <arch/io.h> that we really wanted. Change-Id: I9aa0bdf34cd1d53e20b4494c7986f0878f4fd840 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/31693 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/stoneyridge/smbus.c M src/soc/intel/denverton_ns/uart_debug.c M src/southbridge/amd/agesa/hudson/smbus.c M src/southbridge/amd/pi/hudson/smbus.c 4 files changed, 3 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c index 21750d8..c4a022a 100644 --- a/src/soc/amd/stoneyridge/smbus.c +++ b/src/soc/amd/stoneyridge/smbus.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include <io.h> +#include <arch/io.h> #include <stdint.h> #include <soc/smbus.h> #include <soc/southbridge.h> diff --git a/src/soc/intel/denverton_ns/uart_debug.c b/src/soc/intel/denverton_ns/uart_debug.c index 5911a45..f7d523e 100644 --- a/src/soc/intel/denverton_ns/uart_debug.c +++ b/src/soc/intel/denverton_ns/uart_debug.c @@ -17,7 +17,6 @@ #include <stdint.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <io.h> #include <soc/uart.h> #define MY_PCI_DEV(SEGBUS, DEV, FN) \ diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c index 33bc917..783c324 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.c +++ b/src/southbridge/amd/agesa/hudson/smbus.c @@ -16,7 +16,7 @@ #ifndef _HUDSON_SMBUS_C_ #define _HUDSON_SMBUS_C_ -#include <io.h> +#include <arch/io.h> #include <stdint.h> #include "smbus.h" diff --git a/src/southbridge/amd/pi/hudson/smbus.c b/src/southbridge/amd/pi/hudson/smbus.c index 33bc917..783c324 100644 --- a/src/southbridge/amd/pi/hudson/smbus.c +++ b/src/southbridge/amd/pi/hudson/smbus.c @@ -16,7 +16,7 @@ #ifndef _HUDSON_SMBUS_C_ #define _HUDSON_SMBUS_C_ -#include <io.h> +#include <arch/io.h> #include <stdint.h> #include "smbus.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/31693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aa0bdf34cd1d53e20b4494c7986f0878f4fd840 Gerrit-Change-Number: 31693 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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