Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31691 )
Change subject: device/mmio.h: Add include file for MMIO ops
......................................................................
Patch Set 6: Code-Review+2
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Hello Werner Zeh, Aaron Durbin, Julius Werner, Patrick Rudolph, Paul Menzel, David Hendricks, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29563
to look at the new patch set (#62).
Change subject: security/tpm: Fix TCPA log feature
......................................................................
security/tpm: Fix TCPA log feature
Until now the TCPA log wasn't working correctly.
* Refactor TCPA log code.
* Add TCPA log dump fucntion.
* Make TCPA log available in bootblock.
* Fix TCPA log formatting.
* Add x86 and Cavium memory for early log.
Change-Id: Ic93133531b84318f48940d34bded48cbae739c44
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
---
A Documentation/security/index.md
M Documentation/security/vboot/measured_boot.md
M src/arch/x86/car.ld
M src/commonlib/include/commonlib/tcpa_log_serialized.h
M src/include/memlayout.h
M src/security/tpm/tspi.h
M src/security/tpm/tspi/log.c
M src/security/tpm/tspi/tspi.c
M src/security/vboot/Kconfig
M src/security/vboot/secdata_tpm.c
M src/security/vboot/symbols.h
M src/security/vboot/vboot_crtm.c
M src/soc/cavium/cn81xx/include/soc/memlayout.ld
M src/soc/imgtec/pistachio/include/soc/memlayout.ld
M src/soc/mediatek/mt8173/include/soc/memlayout.ld
M src/soc/mediatek/mt8183/include/soc/memlayout.ld
M src/soc/nvidia/tegra124/include/soc/memlayout.ld
M src/soc/nvidia/tegra210/include/soc/memlayout.ld
M src/soc/samsung/exynos5250/include/soc/memlayout.ld
M util/cbmem/cbmem.c
20 files changed, 367 insertions(+), 84 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29563/62
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31548 )
Change subject: security: Add memory subfolder
......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/#/c/31548/3/src/security/memory/Kconfig
File src/security/memory/Kconfig:
https://review.coreboot.org/#/c/31548/3/src/security/memory/Kconfig@16
PS3, Line 16: initilization
> typo
Done
https://review.coreboot.org/#/c/31548/3/src/security/memory/Kconfig@23
PS3, Line 23: (as part of FSP or coreboot).
> an x86 specific implementation detail (FSP) that doesn't belong here.
Done
https://review.coreboot.org/#/c/31548/3/src/security/memory/Kconfig@34
PS3, Line 34: endmenu #Memory initilization
> typo
Done
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31549 )
Change subject: cpu/x86/pae/pgtbl: Add memset with PAE
......................................................................
Patch Set 6:
(4 comments)
https://review.coreboot.org/#/c/31549/5/Documentation/security/memory_clear…
File Documentation/security/memory_clearing.md:
https://review.coreboot.org/#/c/31549/5/Documentation/security/memory_clear…
PS5, Line 40: ## Architecture specific implementations
:
: * [x86_32 architecture](../arch/x86/index.md)
> that doesn't look helpful to me as it points to generic x86 docs.
Done
https://review.coreboot.org/#/c/31549/5/src/cpu/x86/pae/pgtbl.c
File src/cpu/x86/pae/pgtbl.c:
https://review.coreboot.org/#/c/31549/5/src/cpu/x86/pae/pgtbl.c@114
PS5, Line 114: scratch2
> vmem_addr?
Done
https://review.coreboot.org/#/c/31549/5/src/cpu/x86/pae/pgtbl.c@117
PS5, Line 117: scratch
> pgtbl_buf? also it's size should be stated somewhere.
Done
https://review.coreboot.org/#/c/31549/5/src/cpu/x86/pae/pgtbl.c@135
PS5, Line 135: assert(scratch);
: assert(IS_ALIGNED((uintptr_t)scratch, 4096));
: assert(IS_ALIGNED((uintptr_t)scratch2, 2 * MiB));
: assert(((uintptr_t)dest > (uintptr_t)scratch2 + 2 * MiB) ||
: ((uintptr_t)dest < (uintptr_t)scratch2));
: assert(((uintptr_t)dest < (uintptr_t)scratch) ||
: ((uintptr_t)dest > (uintptr_t)scratch + sizeof(struct pg_table)));
> we don't always enforce asserts, so this may be unreliable.
Should I just return with an error?
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31713 )
Change subject: drivers/intel/fsp1_0: Deduplicate code
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/31713/1/src/drivers/intel/fsp1_0/fsp_util.c
File src/drivers/intel/fsp1_0/fsp_util.c:
https://review.coreboot.org/#/c/31713/1/src/drivers/intel/fsp1_0/fsp_util.c…
PS1, Line 113: if (Status == 0xFFFFFFFF) {
braces {} are not necessary for single statement blocks
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31550 )
Change subject: arch/x86: Introduce helper to clear memory using PAE
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/31550/6/src/arch/x86/memory_clear.c
File src/arch/x86/memory_clear.c:
https://review.coreboot.org/#/c/31550/6/src/arch/x86/memory_clear.c@79
PS6, Line 79: printk(BIOS_ERR, "%s: CBMEM must reside below 4GiB\n", __func__);
line over 80 characters
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